200942116 六、發明說明： t發明所Λ之技術領域3 發明領域 本發明係有關於一種廣泛用於電腦、行動體通訊用電 5 話、錄像機等各種電子機器之配線板之製造方法及使用於 '該製造方法之壓印片。 【先前技術3 發明背景 參 最近，個人電腦、數位相機、行動電話等移動機器普 10 及，特別是其小型、薄型、輕量、高精細、多功能化等要 求強烈。為因應此，用於機器之半導體元件亦發展封裝之 小型、低背化、三維封裝化。容易實現此種半導體元件封 裝之低背化、半導體元件之三維封裝化之方法之一已知有 使用具有空腔、亦即凹部之基板的方法。 15 第15Α圖及第15Β圖係記載於曰本專利公開公報昭 63-90158號，具有空腔之習知配線板127的製程之截面圖。 ® 如第15Α圖所示，以連接層121位於下側基板122與上侧 基板123間之狀態，一面將電極之位置或窗之位置等對位， 一面重疊上側基板123、連接層12卜下侧基板122，而製作 20 配線板127。之後，將片126載置於上侧基板123。片126由 具有脫模性之解放層124及設置於解放層124上之熱可塑性 樹脂層125構成。熱可塑性樹脂層125由可以熱流動之熱可 塑性樹脂構成。 如第15Β圖所示，一面將片126於上側基板123上加熱， 200942116 一面壓著。當將片126加熱壓著時，連接層121流入至四部 128内之前，片126之熱可塑性樹脂層125流動至凹部128 内，填充凹部128。因而，在連接層121不流動下，層積上 側基板123、連接層121、下側基板122。之後，藉將片I26 5 剝離，完成配線板127。 將片126壓著至配線板127時，如第15B圖所示，變形成 與凹部128相同之形狀。片126在一直維持此形狀下，從配 線板127剝離。因而，片126於凹部128特別深時，不易剝離， 而無法反覆使用，且凹部228之深度深時，不易剝離。 10 在具有熱可塑性樹脂層125之片126方面，需依凹部128 之體積，調整熱可塑性樹脂之量。當熱可塑性樹脂之量不 適合凹部128之體積時，熱可塑性樹脂無法完全填充於凹部 128内，連接層121易流動至凹部128内。 【發明内容3 15 發明揭示 壓印片係用以製造具有形成有凹部之面之配線板。壓 印片包含有彈性變形層，該彈性變形層係於對具有前述凹 部之前述面時加壓時，可沿前述凹部及前述面可逆變形， 且具耐熱性者。 20 藉此壓印片，可以良好效率製造配線密度高之立體配 線板。 圖式簡單說明 第1A圖係本發明實施形態之立體配線板之立體圖。 第1B圖係第1A圖所示之立體配線板之線1B-1B之載面 200942116 r ! 圖。 第1C圖係第1實施形態之立體配線板之連接層之截面 圖。 第2圖係第1實施形態之立體配線板之截面圖。 5 第3A圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第3 B圖係顯示第1實施形態之立體配線板之製程之截 面圖。 〇 第3C圖係顯示第1實施形態之立體配線板之製程之截 10 面圖。 第3D圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第3E圖係顯示第1實施形態之立體配線板之製程之截 面圖。 15 ❹ 第3F圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第4A圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第4B圖係顯示第1實施形態之立體配線板之製程之截 20 面圖。 第4C圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第5 A圖係顯示第1實施形態之立體配線板之製程之截 面圖。 200942116 第5 B圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第5C圖係顯示第1實施形態之立體配線板之製程之截 面圖。 5 第6圖係顯示第1實施形態之立體配線板之製程之截面 圖。 第7圖係顯示第1實施形態之立體配線板之連接層之熔 融黏度。 第8A圖係本發明第2實施形態之立體配線板之立體圖。 10 第8B圖係第8A圖所示之立體配線板之線8B-8B之截面 圖。 第8 C圖係第2實施形態之立體配線板之連接層之截面 圖。 第9圖係第2實施形態之立體配線板之截面圖。 15 第10圖係第2實施形態之立體配線板之截面圖。 第11A圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第11B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 20 第11C圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第11D圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第11E圖係顯示第2實施形態之立體配線板之製程之截 200942116 面圖。 第11F圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第12 A圖係顯示第2實施形態之立體配線板之製程之截 5 面圖。 ' 第12B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第12C圖係顯示第2實施形態之立體配線板之製程之截 ❿ 面圖。 10 第13A圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第13B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第13C圖係顯示第2實施形態之立體配線板之製程之截 15 面圖。 第14圖係顯示第2實施形態之立體配線板之連接層之 © 熔融黏度。 第15A圖係顯示習知配線板之製程之截面圖。 第15B圖係顯示習知配線板之製程之截面圖。 20 【實施方式】 用以實施發明之最佳形態 (第1實施形態） 第1A圖係本發明實施形態之立體配線板116之立體 圖。第1B圖係第1A圖所示之立體配線板116之線1B-1B之截 200942116 面圖。立體配線板116具有下側基板102、設置於下側基板 102之上面102A之連接層103、設置於連接層1〇3之上面 103A之上側基板101。上侧基板1〇1及下側基板1〇2呈相互不 同之形狀。連接層103具有30μιη〜300μηι之厚度。連接層1〇3 5 以使下侧基板1〇2之上面102Α之一部份102C露出之狀態， 設置於上面102Α。因而’於下側基板1〇2之上面ι〇2Α之一 部份102C之正上方形成有以上面l〇2A之一部份102C、連接 層103及上侧基板101包圍之凹部1〇4。於上側基板ιοί之上 面101Α、下面101Β、下側基板1〇2之上面102Α、下面102Β 10 分別形成配線。於凹部104收容零件105，而封裝於立體配 線板116。藉此’可縮小封裝有零件105之立體配線板116之 總厚度。 第1C圖係連接層103之截面圖。連接層1〇3具有具上面 103Α及下面103Β之絕緣層103C、設置於絕緣層103C内之導 15 孔107。絕緣層103C形成連接於上面ι〇3Α及下面103Β之貫 穿孔109。於貫穿孔109填充為導電性材料之導電性膏1〇6， 而形成導孔107。絕緣層103C由環氧樹脂等熱硬化性樹脂 103D、於熱硬化性樹脂103D擴散之無機填料ι〇3Ε構成。連 接層103不包含織布、不織布、薄膜等芯材，從上面103Α 20 至下面103Β實質上以均一之材料構成。當連接層1〇3之厚度 不到30μιη時，配線不易埋入連接層1 〇3。當連接層0103之 厚度超過300μηι時，由於為導孔1〇7之徑對高度之比之寬高 比過大，故導孔107之小徑化不易，不易形成導孔1〇7，而 有損害連接可靠度之情形。此外，導孔107之寬高比宜為1.0 200942116 以下。 5 ❹ 10 15 ❿ 無機填料103E宜以氧化矽、二氧化鋁、鈦酸鋇中之至 少一種以上者構成。無機填料103E之粒徑為1〜15μπι，於絕 緣層103C宜含有7〇重量％〜90重量％。當無機填料103Ε之含 有量不到70重量％時，熱硬化性樹脂i〇3D於加壓當中流動 之際，無機填料103Ε亦流動。當無機填料103Ε之含有量超 過90%時，配線不易埋入絕緣層i〇3C，而有不易與基板 101、102密合之情形。 導電性膏106由銅、銀、金、鈀、鉍、錫及該等合金中 構成，粒徑以1〜20μιη為佳。 第2圖係立體配線板116之截面圖。凹部1044以下側基 板102之上面l〇2A之一部份102C、連接層103之側面103F及 上側基板101之側面101F包圍。即，下側基板102之上面102Α 之一部份102C、連接層103之側面103F、上側基板101之側 面101F與凹部1〇4面對。連接層103之上面103Α之與側面 103F連接之部份i〇3G朝凹部104傾斜至下方，亦即朝凹部 104，於朝向下侧基板1〇2之上面102Α之一部份的102C之方 向104Α傾斜。藉此，形成凹部104之緣之上侧基板101之上 面101Α與側面101F連接之邊緣部101Η呈鈍角。上側基板 101包括傾斜之部份101G，橫亙上面101Α，而具一定厚度。 即，上側基板101之上面101Α之部份101G與連接層103之上 面103Α之部份103G平行。上面101Α、103Α之部份101G、 103G呈平面形狀。 說明第1實施形態之立體配線板116之製造方法。第3Α 20 200942116 圖至第3F圖、第4A圖至第4C圖、第5A圖至第5C圖係顯示立 體配線板116之製程之載面圖。 首先，如第3A圖所示，準備具有第1面i〇3H、第1面103H 之相反側之第2面103J’並含有未硬化之熱硬化性樹脂103D 5 之絕緣層103C。於絕緣層103C之第1面103H及第2面103J分 別貼附樹脂薄膜108A、樹脂薄膜108B。樹脂薄膜108A、108B 由聚對苯二甲酸乙二酯（PET)等強固之樹脂構成。接著，如 第3B圖所示，於絕緣層103C及樹脂薄膜108A、108B形成用 以形成凹部104之孔104B或切斷絕緣層103C、樹脂薄膜 ❹ 10 1〇8Α、108B。接著，如第3C圖所示，剝離樹脂薄膜108A， 將樹脂薄膜108C貼合於第1面103H。樹脂薄膜108C由聚對 苯二甲酸乙二酯（PET)等強固樹脂構成。然後，如第3D圖所 示，通過樹脂薄膜108B、108C，於絕緣層103C形成貫穿孔 109。然後，如第3E圖所示，於貫穿孔109内填充導電性膏 15 106,形成導孔107，製作連接層103。接著，如第3F圖所示， 剝離樹脂薄膜108C。另一方面，樹脂薄膜108B不剝離，而 設於第2面103J。 〇 接著，如第4A圖及第4B圖所示，以絕緣層103C之第1 面103H定位於下側基板102之上面102A之狀態，將連接層 2〇 103配置於下側基板102之上面102A。如此，絕緣層i〇3C之 第1面103H成為連接層103之下面103B，第2面103J成為上面 103A。於下側基板102之上面102A設有配線110。連接層1〇3 配置於下側基板102上時，配線110埋入連接層103。藉此， 由於壓縮導電性膏106，故與配線11〇密合連接。之後，如 10 200942116 第4C圖所示，從連接層103之上面103A、亦即絕緣層i〇3C 之第2面103J剝離樹脂薄膜108B。 接著，如第5A圖所示，以上側基板1〇1之下面ιοιΒ位 於連接層103之上面103A、亦即絕緣層103C之第2面103J之 5 狀態，將上側基板101配置於連接層103上。進一步，於上 側基板101之上面101A上配置壓印片112，以熱加壓將上側 基板101、連接層103、下側基板102加熱加壓而層積。壓印 片112具有抵接上側基板101之上面1〇1 A之下面112B及其 ® 相反側之上面112A。壓印片112具有設置於下面112B之脫膜 10 層115、設置於脫膜層115之上面115A，具有耐熱性之彈性 - 變形層114、設置於彈性變形層114之上面114A上之脫膜層 Π8。脫膜層118設置於壓印片112之上面112A。彈性變形層 114為可逆變形，以矽樹脂等彈性變形之樹脂形成。 當將加壓板112、上側基板101、連接層1〇3、下側基板 15 102加熱壓縮，以使上侧基板101與下側基板102接近時，如 第5B圖所示，將彈性變形層114及脫膜層115壓入至凹部104 内。壓印片112之彈性變形層114抑制連接層1〇3之熱硬化性 樹脂103D之流量，而防止熱硬化性樹脂流入至凹部1〇4内。 藉此’彈性變形層114以沿著上側基板1〇1及凹部丨〇4之狀態 20 覆蓋，而堵住壓縮時之樹脂103D之流動。如此，藉彈性變 形層114，即使凹部104深，亦可將壓印片112以無間隙之狀 態壓入至凹部104内。 如第5B圖所示，彈性變形層114壓入至凹部1〇4内時， 由於可使與連接層103之凹部104面對之侧面i〇3F附近之部 11 200942116 份更壓縮，故可使連接於連接層103之側面i〇3F之上面1〇3Α 之部份103G於方向104A傾斜。此壓縮時，形成於上侧基板 101之下面101B之配線120埋入連接層1〇3之上面103A。藉 此，由於將導電性膏106更壓縮，故可與配線11〇、12〇密合 5 接觸。上側基板1〇ι自身層積成在不壓縮下，仿照連接層 103，故上側基板101之上面i〇iA之部份i〇ig可與連接層 - 103之上面103A之部份103G平行地於方向ι〇4Α傾斜。如 此，上侧基板101之厚度包括部份101G在内，在上面i〇iA 均-。 ❹ 10 之後，將壓印片112、上側基板101、連接層103及下側 基板102冷卻，將壓印片112剝離，如第5C圖所示，完成立 體配線板116。在立體配線板116方面，由於形成凹部1〇4之 緣之上側基板101之上面101A與側面101F連接之邊緣部 101H呈鈍角，故可在不使壓印片112破損下，不於立體配線 15 板116殘留而剝離。壓印片112之彈性變形層1114於冷卻時 要回復加熱前之形狀。因而，剝離壓印片112時，即使凹部 104深，亦可易從凹部1〇4將壓印片112剝離。 〇 此外’在上述製程中，首先，以使絕緣層l〇3C之第1 面103H位於下側基板1〇2之上面102A之狀態下，將連接層 2〇 1〇3配置於下侧基板1〇2之上面102A，之後，將上側基板1〇1 配置於連接層103之上面103A。在第1實施形態中，亦可以 使絕緣層103C之第1面103H位於上側基板1〇1之下面101B 之狀態’將連接層103配置於上側基板101之下面101B，之 後，將連接層103配置於下側基板102之上面102A。 12 200942116 為使壓印片112以無間隙之狀態填充於凹部i〇4内，壓 印片112之彈性變形層114包括壓印片112抵接之面、亦即凹 部104之表面積在内，伸長成上側基板1〇1之上面1〇1A之表 面積以上。藉此，不論凹部1〇4之形狀或深度為何，皆可將 5 彈性變形層U4以無間隙之狀態填充於凹部104内。藉彈性 變形層114伸長，可將上側基板101之上面1〇1A與凹部1〇4 之表面全體以均等之載重加壓。藉此，可防止連接層1〇3之 樹脂103D溢出至凹部1〇4内。 又，為於凹部104内確實填充，以符合ji§ κ 6253之測 10 量之彈性變形層114之硬度以5〜30度為佳。彈性變形層U4 之厚度宜大於上側基板101之上面1〇1 A之凹部1〇4之深度。 如第5B圖所示，由於彈性變形層114伸長至抵接之面之 表面積以上的面積，故壓印片112壓入至凹部1〇4内，同時， 可進一步壓縮連接層103之凹部1〇4附近之部份。因而，可 15 於連接層1〇3之凹部104附近之部份形成傾斜。 連接層103之熱膨脹係數在上側基板1〇1及下側基板 102之熱膨脹係數以下、即65ppm/°C以下，以低於上側基板 101或下侧基板102之熱膨脹係數為佳。 當連接層103之熱膨脹係數超過65ppm/〇c時，或高於上 20 側基板101及下側基板之熱膨脹係數時，因連接層1〇3之 變形，易產生立體配線板116之翹曲或變形。 以動態機械分析(DMA)法測量之連接層1〇3之玻璃轉 移點宜為185 C或宜比上側基板ι01及下側基板1〇2之玻螭 轉移點高10°C以上之差。當連接層13〇之玻璃轉移點不到 13 200942116 185°C或差不到10°C時，在需要如迴焊般高溫之步驟，於基 板產生翹曲或彎曲等複雜形狀之變形，有該變形不可逆之 情形。 連接層103不包含織布、不織布、薄膜等芯材。當連接 5 層103包含芯材時，設置於上側基板101及下側基板102之配 線110、118不易埋入連接層103。 由於壓印片112之彈性變形層1 μ之形狀冷卻後回復至 加熱前之形狀，故可於第5B圖所示之壓印步驟反覆使用。 即，準備另一配線板116，該另一配線板具有另一下側基板 〇 10 102、以露出另一下側基板1〇2上面102A之一部份l〇2C之狀 態，設置於另一下側基板102之上面102A的另一連接層 103、設置於另一連接層1〇3之上面103A之另一上側基板 10卜在另一下側基板102之上面102之一部份102A正上方具 有形成於另一上側基板101之上面101A的凹部104。於配線 15 板116之上側基板101之上面1〇1 A配置壓印片112,將配線板200942116 VI. OBJECTS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a method for manufacturing a wiring board widely used in various electronic devices such as computers, mobile communication, video recorders, and the like. The embossing sheet of the manufacturing method. [Prior Art 3 Background of the Invention Recently, mobile computers such as personal computers, digital cameras, and mobile phones have been intensified in demand, such as small size, thin type, light weight, high definition, and multi-functionality. In response to this, semiconductor components used in machines have also developed small, low-profile, three-dimensional packages for packaging. One of the methods for easily achieving such a low-profile semiconductor element package and three-dimensional packaging of a semiconductor element is known as a method of using a substrate having a cavity, that is, a recess. 15 Fig. 15 and Fig. 15 are cross-sectional views showing the process of the conventional wiring board 127 having a cavity, as described in Japanese Laid-Open Patent Publication No. SHO63-90158. As shown in Fig. 15 , the connection layer 121 is positioned between the lower substrate 122 and the upper substrate 123, and the position of the electrode or the position of the window is aligned, and the upper substrate 123 and the connection layer 12 are overlapped. The side substrate 122 is used to fabricate 20 wiring boards 127. Thereafter, the sheet 126 is placed on the upper substrate 123. The sheet 126 is composed of a release layer 124 having a release property and a thermoplastic resin layer 125 provided on the release layer 124. The thermoplastic resin layer 125 is composed of a thermoplastic resin which can be thermally flowed. As shown in Fig. 15, the sheet 126 is heated on the upper substrate 123, and is pressed against 200942116. When the sheet 126 is heated and pressed, before the connection layer 121 flows into the four portions 128, the thermoplastic resin layer 125 of the sheet 126 flows into the concave portion 128 to fill the concave portion 128. Therefore, the upper substrate 123, the connection layer 121, and the lower substrate 122 are laminated without flowing the connection layer 121. Thereafter, the sheet I 127 is peeled off to complete the wiring board 127. When the sheet 126 is pressed against the wiring board 127, as shown in Fig. 15B, the shape is the same as that of the concave portion 128. The sheet 126 is peeled off from the wiring board 127 while maintaining this shape. Therefore, when the concave portion 128 is particularly deep, the sheet 126 is not easily peeled off, and cannot be used repeatedly, and when the depth of the concave portion 228 is deep, peeling is less likely. 10 In the case of the sheet 126 having the thermoplastic resin layer 125, the amount of the thermoplastic resin is adjusted in accordance with the volume of the concave portion 128. When the amount of the thermoplastic resin is not suitable for the volume of the concave portion 128, the thermoplastic resin cannot be completely filled in the concave portion 128, and the connecting layer 121 easily flows into the concave portion 128. SUMMARY OF THE INVENTION 3 The embossed sheet is used to manufacture a wiring board having a face on which a recess is formed. The embossed sheet comprises an elastically deformable layer which is reversibly deformable along the concave portion and the surface when pressed against the surface having the concave portion, and has heat resistance. 20 With this embossed sheet, a three-dimensional wiring board with high wiring density can be manufactured with good efficiency. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a perspective view of a three-dimensional wiring board according to an embodiment of the present invention. Fig. 1B is a plane of the line 1B-1B of the three-dimensional wiring board shown in Fig. 1A. 200942116 r ! Fig. 1C is a cross-sectional view showing a connection layer of a three-dimensional wiring board of the first embodiment. Fig. 2 is a cross-sectional view showing a three-dimensional wiring board of the first embodiment. 5 Fig. 3A is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. 〇 Fig. 3C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3D is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3E is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. 15 ❹ Fig. 3F is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4A is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 5A is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. 200942116 Fig. 5B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 5C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 6 is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 7 is a view showing the melt viscosity of the connection layer of the three-dimensional wiring board of the first embodiment. Fig. 8A is a perspective view of a three-dimensional wiring board according to a second embodiment of the present invention. 10 Fig. 8B is a cross-sectional view of the line 8B-8B of the three-dimensional wiring board shown in Fig. 8A. Fig. 8C is a cross-sectional view showing the connection layer of the three-dimensional wiring board of the second embodiment. Fig. 9 is a cross-sectional view showing a three-dimensional wiring board of the second embodiment. 15 Fig. 10 is a cross-sectional view showing a three-dimensional wiring board of a second embodiment. Fig. 11A is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11C is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11D is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11E is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11F is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 12A is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 12B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 12C is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13A is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13C is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 14 is a view showing the © melt viscosity of the connection layer of the three-dimensional wiring board of the second embodiment. Fig. 15A is a cross-sectional view showing the process of a conventional wiring board. Fig. 15B is a cross-sectional view showing the process of a conventional wiring board. [Embodiment] The best mode for carrying out the invention (First embodiment) Fig. 1A is a perspective view of a three-dimensional wiring board 116 according to an embodiment of the present invention. Fig. 1B is a cross-sectional view of the line 1B-1B of the three-dimensional wiring board 116 shown in Fig. 1A. The three-dimensional wiring board 116 has a lower substrate 102, a connection layer 103 provided on the upper surface 102A of the lower substrate 102, and an upper substrate 101 provided on the upper surface 103A of the connection layer 1A3. The upper substrate 1〇1 and the lower substrate 1〇2 have mutually different shapes. The connection layer 103 has a thickness of 30 μm to 300 μm. The connection layer 1〇3 5 is disposed on the upper surface 102Α in a state in which one of the upper portions 102C of the upper substrate 1〇2 is exposed. Thus, a recess portion 1〇4 surrounded by a portion 102C of the upper surface 〇2A, the connection layer 103, and the upper substrate 101 is formed right above one of the upper portions 102C of the lower substrate 1〇2. Wiring is formed on the upper surface of the upper substrate ιοί, 101 Α, the lower surface 101 Β, the upper surface 102 Α of the lower substrate 1 〇 2, and the lower surface 102 Β 10 . The component 105 is housed in the recess 104 and packaged in the three-dimensional wiring board 116. Thereby, the total thickness of the three-dimensional wiring board 116 in which the parts 105 are packaged can be reduced. Fig. 1C is a cross-sectional view of the connection layer 103. The connection layer 1〇3 has an insulating layer 103C having an upper surface 103Α and a lower surface 103, and a via hole 107 provided in the insulating layer 103C. The insulating layer 103C forms a through-hole 109 which is connected to the upper surface Α3Α and the lower surface 103Β. The conductive paste 1〇6 of the conductive material is filled in the through hole 109 to form the via hole 107. The insulating layer 103C is composed of a thermosetting resin 103D such as an epoxy resin and an inorganic filler ι〇3Ε diffused from the thermosetting resin 103D. The connecting layer 103 does not contain a core material such as a woven fabric, a non-woven fabric, or a film, and is substantially composed of a uniform material from the upper surface 103Α20 to the lower surface 103Β. When the thickness of the connection layer 1〇3 is less than 30 μm, the wiring is less likely to be buried in the connection layer 1 〇3. When the thickness of the connection layer 0103 exceeds 300 μm, since the aspect ratio of the diameter to the height of the via hole 1〇7 is too large, the diameter of the via hole 107 is not easy to be formed, and the via hole 1〇7 is not easily formed, which is harmful. Connection reliability. In addition, the aspect ratio of the via hole 107 is preferably 1.0 200942116 or less. 5 ❹ 10 15 ❿ The inorganic filler 103E is preferably composed of at least one of cerium oxide, aluminum oxide, and barium titanate. The inorganic filler 103E has a particle diameter of 1 to 15 μm, and the insulating layer 103C preferably contains 7 to 90% by weight. When the content of the inorganic filler 103 is less than 70% by weight, the inorganic filler 103 Ε also flows when the thermosetting resin i〇3D flows during pressurization. When the content of the inorganic filler 103 is more than 90%, the wiring is less likely to be buried in the insulating layer i〇3C, and it is difficult to adhere to the substrates 101 and 102. The conductive paste 106 is composed of copper, silver, gold, palladium, rhodium, tin, and the like, and preferably has a particle diameter of 1 to 20 μm. 2 is a cross-sectional view of the three-dimensional wiring board 116. The concave portion 1044 is surrounded by a portion 102C of the upper surface 102a of the lower substrate 102, a side surface 103F of the connection layer 103, and a side surface 101F of the upper substrate 101. That is, one portion 102C of the upper surface 102 of the lower substrate 102, the side surface 103F of the connection layer 103, and the side surface 101F of the upper substrate 101 face the concave portion 1〇4. The portion 103 of the upper surface 103 of the connection layer 103 which is connected to the side surface 103F is inclined downward toward the concave portion 104, that is, toward the concave portion 104, in the direction 104C of the portion 102C facing the upper surface 102 of the lower substrate 1〇2Α tilt. Thereby, the edge portion 101 of the upper surface 101 of the upper substrate 101 on the side where the concave portion 104 is formed is formed at an obtuse angle with the side surface 101F. The upper substrate 101 includes a slanted portion 101G which is spaced apart from the upper surface and has a certain thickness. That is, the portion 101G of the upper surface 101 of the upper substrate 101 is parallel to the portion 103G of the upper surface 103 of the connection layer 103. The 101G and 103G of the above 101Α, 103Α have a planar shape. A method of manufacturing the three-dimensional wiring board 116 of the first embodiment will be described. 3rd 2009 20 200942116 Figs. 3F, 4A to 4C, and 5A to 5C are plan views showing the process of the vertical wiring board 116. First, as shown in Fig. 3A, an insulating layer 103C having the first surface i〇3H and the second surface 103J' on the opposite side of the first surface 103H and containing the uncured thermosetting resin 103D 5 is prepared. The resin film 108A and the resin film 108B are attached to the first surface 103H and the second surface 103J of the insulating layer 103C, respectively. The resin films 108A and 108B are made of a strong resin such as polyethylene terephthalate (PET). Then, as shown in Fig. 3B, a hole 104B for forming the concave portion 104, a cut insulating layer 103C, and a resin film ❹ 10 1 〇 8 Α, 108B are formed in the insulating layer 103C and the resin films 108A and 108B. Next, as shown in FIG. 3C, the resin film 108A is peeled off, and the resin film 108C is bonded to the first surface 103H. The resin film 108C is made of a strong resin such as polyethylene terephthalate (PET). Then, as shown in Fig. 3D, through holes 109 are formed in the insulating layer 103C by the resin films 108B and 108C. Then, as shown in Fig. 3E, the conductive paste 15 106 is filled in the through hole 109, and the via hole 107 is formed to form the connection layer 103. Next, as shown in Fig. 3F, the resin film 108C is peeled off. On the other hand, the resin film 108B is not peeled off but is provided on the second surface 103J. Then, as shown in FIGS. 4A and 4B, the first layer 103H of the insulating layer 103C is positioned on the upper surface 102A of the lower substrate 102, and the connection layer 2〇103 is disposed on the upper surface 102A of the lower substrate 102. . Thus, the first surface 103H of the insulating layer i3C becomes the lower surface 103B of the connection layer 103, and the second surface 103J becomes the upper surface 103A. Wiring 110 is provided on the upper surface 102A of the lower substrate 102. When the connection layer 1〇3 is disposed on the lower substrate 102, the wiring 110 is buried in the connection layer 103. Thereby, since the conductive paste 106 is compressed, it is closely connected to the wiring 11A. Thereafter, as shown in Fig. 4C of 10 200942116, the resin film 108B is peeled off from the upper surface 103A of the connection layer 103, that is, the second surface 103J of the insulating layer i〇3C. Next, as shown in FIG. 5A, the lower surface of the upper substrate 1〇1 is located on the upper surface 103A of the connection layer 103, that is, the fifth surface 103J of the insulating layer 103C, and the upper substrate 101 is disposed on the connection layer 103. . Further, the embossing sheet 112 is placed on the upper surface 101A of the upper substrate 101, and the upper substrate 101, the connection layer 103, and the lower substrate 102 are heated and pressurized by thermal pressing to be laminated. The embossing sheet 112 has an upper surface 112A which abuts the upper surface 112B of the upper substrate 101 and its opposite side. The embossed sheet 112 has a release film 10 layer 115 disposed on the lower surface 112B, an upper surface 115A disposed on the release layer 115, a heat-resistant elastic-deformation layer 114, and a release layer disposed on the upper surface 114A of the elastic deformation layer 114. Π 8. The release layer 118 is disposed on the upper surface 112A of the stamp 112. The elastically deformable layer 114 is a reversibly deformable shape and is formed of a resin which is elastically deformed such as a resin. When the pressure plate 112, the upper substrate 101, the connection layer 1〇3, and the lower substrate 15102 are heated and compressed so that the upper substrate 101 and the lower substrate 102 are brought close to each other, as shown in FIG. 5B, the elastic deformation layer is formed. 114 and the release layer 115 are pressed into the recess 104. The elastic deformation layer 114 of the embossing sheet 112 suppresses the flow rate of the thermosetting resin 103D of the connection layer 1〇3, and prevents the thermosetting resin from flowing into the concave portion 1〇4. Thereby, the elastic deformation layer 114 is covered in a state 20 along the upper substrate 1〇1 and the recessed portion 4 to block the flow of the resin 103D during compression. Thus, by the elastic deformation layer 114, even if the concave portion 104 is deep, the embossed sheet 112 can be pressed into the concave portion 104 without a gap. As shown in FIG. 5B, when the elastic deformation layer 114 is pressed into the concave portion 1〇4, since the portion 11 200942116 which is adjacent to the side surface i〇3F of the concave portion 104 of the connection layer 103 can be more compressed, A portion 103G connected to the upper side of the side surface i〇3F of the connection layer 103 is inclined in the direction 104A. At the time of this compression, the wiring 120 formed on the lower surface 101B of the upper substrate 101 is buried in the upper surface 103A of the connection layer 1A3. As a result, since the conductive paste 106 is further compressed, it can be brought into close contact with the wirings 11A and 12B. The upper substrate 1〇 itself is laminated so as to be uncompressed, and the connecting layer 103 is formed. Therefore, the portion i〇ig of the upper substrate 101 of the upper substrate 101 can be parallel to the portion 103G of the upper portion 103A of the connection layer 103. The direction ι〇4Α tilts. Thus, the thickness of the upper substrate 101 includes the portion 101G, and i 〇 iA is - above. After ❹ 10, the embossing sheet 112, the upper substrate 101, the connection layer 103, and the lower substrate 102 are cooled, and the embossed sheet 112 is peeled off. As shown in Fig. 5C, the vertical wiring board 116 is completed. In the aspect of the three-dimensional wiring board 116, since the edge portion 101H to which the upper surface 101A of the upper substrate 101 and the side surface 101F are connected at the edge of the recessed portion 1〇4 is obtuse, the three-dimensional wiring 15 can be prevented without breaking the stamping 112. The plate 116 remains and peels off. The elastically deformable layer 1114 of the embossed sheet 112 is returned to the shape before heating upon cooling. Therefore, when the embossed sheet 112 is peeled off, even if the concave portion 104 is deep, the embossed sheet 112 can be easily peeled off from the concave portion 1 〇4. In the above-described process, first, the connection layer 2〇1〇3 is placed on the lower substrate 1 in a state where the first surface 103H of the insulating layer 10C is positioned on the upper surface 102A of the lower substrate 1〇2. After the upper surface 102A of the crucible 2, the upper substrate 1〇1 is disposed on the upper surface 103A of the connection layer 103. In the first embodiment, the first surface 103H of the insulating layer 103C may be placed in the lower surface 101B of the upper substrate 1〇1. The connection layer 103 may be disposed on the lower surface 101B of the upper substrate 101, and then the connection layer 103 may be disposed. On the upper surface 102A of the lower substrate 102. 12 200942116 In order to fill the stamping sheet 112 in the recessed portion i4 without gaps, the elastically deformable layer 114 of the stamping sheet 112 includes the surface on which the stamping sheet 112 abuts, that is, the surface area of the recessed portion 104, and is elongated. It is equal to or larger than the surface area of the upper surface 1〇1A of the upper substrate 1〇1. Thereby, regardless of the shape or depth of the concave portion 1〇4, the elastic deformation layer U4 can be filled in the concave portion 104 without a gap. By the elongation of the elastic deformation layer 114, the entire surfaces of the upper surface 1〇1A and the concave portion 1〇4 of the upper substrate 101 can be pressurized with an equal load. Thereby, the resin 103D of the connection layer 1〇3 can be prevented from overflowing into the concave portion 1〇4. Further, in order to be surely filled in the concave portion 104, the hardness of the elastic deformation layer 114 in accordance with the measurement of ji κ 6253 is preferably 5 to 30 degrees. The thickness of the elastic deformation layer U4 is preferably larger than the depth of the concave portion 1〇4 of the upper surface of the upper substrate 101. As shown in Fig. 5B, since the elastic deformation layer 114 is elongated to an area larger than the surface area of the abutting surface, the embossing sheet 112 is pressed into the concave portion 1〇4, and at the same time, the concave portion 1 of the connection layer 103 can be further compressed. 4 nearby parts. Therefore, the inclination can be formed in a portion near the concave portion 104 of the connection layer 1〇3. The thermal expansion coefficient of the connection layer 103 is lower than the thermal expansion coefficient of the upper substrate 1〇1 and the lower substrate 102, that is, 65 ppm/°C or less, and is preferably lower than the thermal expansion coefficient of the upper substrate 101 or the lower substrate 102. When the thermal expansion coefficient of the connection layer 103 exceeds 65 ppm/〇c, or is higher than the thermal expansion coefficient of the upper 20 side substrate 101 and the lower substrate, warping of the three-dimensional wiring board 116 is liable to occur due to deformation of the connection layer 1〇3. Deformation. The glass transition point of the connection layer 1 〇 3 measured by the dynamic mechanical analysis (DMA) method is preferably 185 C or preferably higher than the glass transition point of the upper substrate ι01 and the lower substrate 1 〇 2 by more than 10 °C. When the glass transition point of the connecting layer 13 is less than 13 200942116 185 ° C or the difference is less than 10 ° C, in the step of requiring high temperature such as reflow, deformation of a complex shape such as warpage or bending occurs on the substrate. The situation of irreversibility of deformation. The connecting layer 103 does not include a core material such as a woven fabric, a non-woven fabric, or a film. When the connection layer 5 includes the core material, the wirings 110 and 118 provided on the upper substrate 101 and the lower substrate 102 are less likely to be buried in the connection layer 103. Since the shape of the elastic deformation layer 1 μ of the stamp 112 is cooled and returned to the shape before heating, it can be used repeatedly in the imprint step shown in Fig. 5B. That is, another wiring board 116 having another lower substrate 〇10 102 to expose one of the upper portions 102A of the lower substrate 1 〇2 is disposed in another lower substrate. Another connection layer 103 of the upper surface 102A of 102, and another upper substrate 10 of the upper surface 103A of the other connection layer 1A are formed directly on one of the portions 102A of the upper surface 102 of the other lower substrate 102. A recess 104 of the upper surface 101A of the upper substrate 101. The embossing sheet 112 is disposed on the upper surface of the upper substrate 101 of the wiring board 15 and the embossing sheet 112.
116加熱加壓後，將壓印板112從上側基板101之上面101A 剝離。在剝離壓印片112後，於另一配線板116之另一上側 G 基板101之上面101A配置壓印片112,將另一配線板116加熱 加壓。 2〇 第7圖顯示連接層103之熔融黏度。連接層之最低熔融 黏度以lOOOPa · s〜lOOOOOPa · s為適當。當最低熔融黏度不 到1000Pa· s時，熱硬化性樹脂103D之流量增大，有產生在 凹部104内熱硬化性樹脂103D之流入之虞。當最低熔融黏度 超過lOOOOOPa · s時，有產生與基板ΗΠ、102之接觸不良或 14 200942116 配線110、118之埋入不良之虞。 連接層103亦可含有著色劑。藉此，提高封裝性、光反 射性。 為抑制熱硬化性樹脂103D之流量，連接層103宜更含有 5 彈性體。 此外，上側基板101及下側基板102只要為通孔配線板 或全層IVH構造之ALIVH配線板等樹脂基板，非特別限定 者，可為兩面基板，亦可為多層基板。亦可將複數個基板 Ο 101、與複數個連接層103交互層積。 10 又，用於上側基板101及下側基板102之絕緣材料由玻 璃織布與環氧系樹脂之複合材料構成。此絕緣材料亦可為 以從醯胺、全芳香族聚酯選出之有機質纖維構成之織布與 熱硬化性樹脂之複合材料形成。又，此絕緣材料亦可以以 從P-醯胺、聚醯亞胺、聚亞苯基苯並二噁唑 15 (P〇1y(P_phenylenebenzobisoxazole)、全芳香族聚醋、PTFE、 聚醚颯、聚醚醯亞胺選擇之有機質纖維構成之不織布與熱 ® 硬化性樹脂之複合材料形成。又，此絕緣材料可以以玻璃 纖維構成之不織布及熱硬化性樹脂之複合材料形成。又， 此絕緣材料亦可以由P-醯胺、聚亞苯基苯並二噁唑、全芳 20 香族聚酯、聚醚醯亞胺、聚醚酮、聚醚醚鲷、聚對苯二甲 酸乙二醇酯、聚四氟乙烯、聚醚砜、聚乙烯對苯二甲酸酯、 聚醯亞胺及聚苯硫醚之至少任一合成樹脂薄膜及設置於此 合成樹脂薄膜兩面之熱硬化性樹脂層構成之複合材料形 成。 15 200942116 連接層103之熱硬化性樹脂l〇3D可使用從環氧樹脂、聚 丁二烯樹脂、苯酚樹脂、聚醯亞胺樹脂、聚醯胺樹脂及氰 酸鹽選擇之至少一個熱硬化性樹脂。 (第2實施形態） 5 第8A圖係本發明第2實施形態之立體配線板216之立體 圖。第8B圖係第8A圖所示之立體配線板216之線8B-8B之截 — 面圖。立體配線板216具有下側基板202、設置於下側基板 202之上面202A之連接層203、設置於連接層203之上面 203A之上側基板201。上側基板201及下側基板202呈不同之 〇 10 形狀。連接層203具有30μιη〜300μηι之厚度。連接層203以使 下側基板202之上面202Α之一部份202C之狀態設置於上面 202A。因而，於下側基板2〇2之上面202A之一部份202C之 正上方形成以上面202A之一部份202C、連接層203及上側 基板201包圍之凹部204。上侧基板201之上面201A、下面 15 201B、下側基板2〇2之上面202A及下面202B形成配線。於 凹部204收容零件205，而封裝於立體配線板216。藉此，可 縮小封裝有零件205之立體配線板216之總厚度。 Θ 第8C圖係連接層2〇3之截面圖。連接層203具有具上面 203A及下面203B之絕緣層203C、設置於絕緣層203C内之導 20孔207。絕緣層203C形成連接於上面203A及下面203B之貫 穿孔2〇9。於貫穿孔2〇9填充導電性膏2〇6，而形成導孔2〇7。 絕緣層203C由環氧樹脂等熱硬化性樹脂2〇3〇、於熱硬化性 树月a203D擴散之無機填料2〇3E構成。連接層2〇3不包含織 布不織布、薄膜等芯材，從上面203A至下面203B實質上 16 200942116 5 ❹ 10 15 ❿ 20 以均一之材料構成。當連接層203之厚度不到30μπι時，配 線不易埋入連接層203。當連接層203之厚度超過300μιη 時’由於導孔2〇7之寬高比過大，故導孔2〇7之小徑化不易， 不易形成導孔207，而有損害連接可靠度之情形。 無機填料203Ε宜以氧化矽、二氧化鋁、鈦酸中之至少 一種以上者構成。無機填料203Ε之粒徑為1〜Ι5μιη，於絕緣 層203C宜含有70重量％〜90重量％。當無機填料203Ε之含有 量不到70重量％時，熱硬化性樹脂203D於加壓當中流動之 際，無機填料203Ε亦流動。當無機填料203Ε之含有量超過 90%時，配線不易埋入絕緣層203C，而有不易與基板201、 202密合之情形。 導電性膏206由銅、銀、金、把、纽、錫及該等合金中 構成’粒控以1〜20μηι為佳。 第9圖係立體配線板216之截面圖。凹部4以下側基板 202之上面202Α之一部份202C、連接層203之側面203F、上 側基板201之側面201F包圍。即，下側基板202之上面202Α 之一部份202C、連接層203之側面203F、上側基板201之側 面201F與凹部204面對。連接層203之上面203Α之與侧面 203F連接之部份203G朝向凹部204傾斜至下方，亦即朝向凹 部204，於朝向下側基板202之上面202Α之一部份的202C之 方向204Α傾斜。因而，設置於連接層203之上面203Α之上 側基板201之上面201Α之與側面20F連接的部份201G朝凹 部204向下傾斜。即，朝向凹部204，於朝向下側基板2〇2之 上面202Α之一部份202C之方向204Α傾斜。連接層203之上 17 200942116 面203A之部份203G形成具圓渾之形狀之曲面狀。同樣地， 上侧基板201之上面201A之部份形成具圓渾之形狀之曲面 狀。藉此，形成凹部204之緣之上側基板201之上面201A及 側面201F連接之邊緣部201H具曲面形狀。上侧基板2〇1包括 5 傾斜而具有曲面形狀之部份201G在内，橫亙上面201A而具 一定厚度。即，上側基板201之上面201A之部份201G與連 接層203之上面203A之部份203G平行。與連接層203之凹部 204面對之側面204F呈曲面形狀。 於上面201A、203A之部份201G、203G形成導孔時， ® 10 有該導孔傾倒之情形。因而，部份201G、203G設置在至距 離凹部204之緣最近之導孔為止之範圍。於連接層203内設 置複數個導孔207。亦於上側基板201内形成由填充於上側 基板内之孔之導電膏構成之複數個導孔219形成。複數個導 孔207、219中導孔207A最接近凹部204、亦即側面203F、 15 201F。上面201A、203A傾斜之部份201G、203G設置在側 面201F、203F至通孔207A間。即，上側基板201之上面201A 之部份201G與連接層203之上面203A之部份203G未形成導 〇 孔。 第10圖係印刷遮罩211插入至凹部204之立體配線板 2〇 116之截面圖。於形成於凹部204之底、亦即下側基板202之 上面202A之一部份202C之焊盤220經由印刷遮罩211而印 刷。由於凹部204具有曲面，故可易將印刷遮罩211插入至 凹部204内。又，在印刷遮罩211插入時及脫離時，可防止 因對準之偏離接觸凹部204之緣而引起之立體配線板116之 18 200942116 破損。 5 Ο 10 15 ❹ 20 由於上側基板201及連接層203之侧面201F、203F之厚 度之和小於封裝於凹部204内之零件205的高度，故封裝零 件205時’易插入零件205及用於封裝之工具，而可以良好 效率封裝零件205。與上側基板201之上面201Α之部份 201G、連接層203之上面203Α之部份203G之侧面201F、侧 面203F呈直角之方向之長度設定成大於用於封裝之工具之 抓取部份的長度，具體言之，設定為1.0mm以下，更佳為 設定在0.3mm以下。 說明第2實施形態之立體配線板216之製造方法。第ι1Α 圖至第11F圖、第12A圖至第12C圖、第13A圖至第13C圖係 顯示立體配線板216之製程之截面圖。 首先，如第11A圖所示，準備具有第1面2〇3H、第1面 203J之相反側之第2面’並含有未硬化之熱硬化性樹脂2〇3D 之絕緣層203C。於絕緣層203C之第1面203H及第2面203J分 別貼有樹脂薄膜208A、樹脂薄膜208B。樹脂薄膜208A、208B 由聚對苯二甲酸乙二酯（PET)等強固之樹脂構成。接著，如 第11B圖所示，於絕緣層203C及樹脂薄膜208A、208B形成 用以形成凹部204之孔204B或切斷絕緣層203C、樹脂薄膜 208A、208B。 接著，如第lie圖所示，剝離樹脂薄膜208A，將樹脂 薄膜208C貼合於第1面203H。樹脂薄膜208C由（PET)等強固 樹脂構成。如第11D圖所示，通過樹脂薄膜2〇8B、208C， 於絕緣層203C形成貫穿孔209。然後，如第he圖所示，於 19 200942116 貫穿孔209内填充導電性膏206，形成導孔207，製作連接層 2〇3。接著，如第uf圖所示，剝離樹脂薄膜208C。另一方 面，樹脂薄膜208B不剝離，而設於第2面203J。 接著，如第12A圖及第12B圖所示，以絕緣層203C之第 5 1面203H定位於下侧基板202之上面202A之狀態，將連接層 203配置於下側基板2〇2之上面202A。如此，絕緣層203C之 第1面203H成為連接層203之下面203B，第2面203J成為上面 203A。於下側基板202之上面202A設有配線210。連接層203 配置於下侧基板202上時，配線210埋入連接層203。藉此， ® 10 由於壓縮導電性膏206，故與配線210密合連接。之後，如 第12C圖所示，從連接層203之上面203A、亦即絕緣層203C 之第2面203J剝離樹脂薄膜208B。 接著，如第13A圖所示，以上側基板201之下面201B位 於連接層203之上面203A、亦即絕緣層203C之第2面203J之 15 狀態，將上側基板201配置於連接層203上。進一步，於上 側基板201之上面201A上配置壓印片212，以熱加壓將上側 基板201、連接層203、下側基板202加熱加壓而層積。壓印 Ο 片212具有抵接上侧基板201之上面201A之下面212B及其 相反側之上面212A。壓印片212具有設置於下面212B之脫 20 模層215、設置於脫模層215之上面215A，具有耐熱性之彈 性變形層214、設置於彈性變形層214之上面214A上之脫模 層218。脫模層218設置於壓印片212之上面212A。彈性變形 層214為可逆變形，以矽樹脂等彈性變形之樹脂形成。 當將加壓板212、上側基板201、連接層203、下側基板 20 200942116 5 Ο 10 15 ❹ 20 202加熱壓縮時，如第13Β圖所示，將彈性變形層214及脫模 層215壓入至凹部204内。壓印片212之彈性變形層214抑制 連接層203之熱硬化性樹脂203D之流量，而防止熱硬化性樹 脂流入至凹部204内。藉此，彈性變形層214以沿著上側基 板201及凹部204之狀態覆蓋，而堵住壓縮時之熱硬化性樹 脂203D之流動。如此，藉彈性變形層214，即使凹部204深， 亦可將壓印片212以無間隙之狀態壓入至凹部204内。 如第13Β圖所示，彈性變形層214壓入至凹部204内時， 由於可使與連接層203之凹部204面對之侧面203F附近之部 份更壓縮，故可使連接於連接層203之侧面203F之上面203Α 之部203G於方向204Α傾斜。此壓縮時，形成於上側基板201 之下面201Β之配線220埋入連接層203之上面203Α。藉此， 由於將導電性膏206更壓縮，故可與配線210、218密合接 觸。上側基板201自身層積成在不壓縮下，仿照連接層203， 故上侧基板201之上面201Α之部份201G可與連接層203之 上面203A之部份203G平行地於方向204A傾斜。如此，上侧 基板201之厚度包括部份201G在内，在上面201A均一。 之後，將壓印片212、上側基板201、連接層203及下側 基板202冷卻’將壓印片212剝離，如第13C圖所示，完成立 體配線板216。在立體配線板216方面，由於形成凹部204之 緣之上側基板201之上面201A與側面201F連接之邊緣部 201H呈鈍角’故可在不使壓印片212破損下，不於立體配線 板216殘留而剝離。壓印片212之彈性變形層214於冷卻時要 回復加熱前之形狀。因而，即使凹部204深，亦可易從凹部 21 200942116 204將壓印片212剝離。 為使壓印片212以無間隙之狀態填充於凹部π#内，壓 印片212之彈性變形層214包括壓印片212抵接之面、亦即凹 部204之表面積在内，伸長成上侧基板2〇1之上面2〇1A之表 5 面積以上。藉此，不論凹部204之形狀或深度為何，皆可將 彈性變形層214以無間隙之狀態填充於凹部2〇4内。藉伸長 彈性變开>層214，可以均等之载重加壓上側基板2〇1之上面 201A與凹部204之表面全體。藉此，可防止連接層2〇3之樹 脂203D溢出至凹部204内。又，彈性變形層214之伸長率為 ❹ 1〇 700%以上，為對反覆之彈性變形確保物理性強度，而具有 15N/mm以上之撕裂強度，為仿照上基板2〇1之形狀，更宜 具有ΙΟΝ/mm以下之抗拉強度。 又，為於凹部204内確實填充，以符合耵8 κ 6253之測 量之彈性變形層214之硬度以5〜30度為佳。彈性變形層214 15 之厚度宜大於上側基板201之上面201A之凹部204之深度。 如第13B圖所示，由於彈性變形層214伸長至抵接之面 之表面積以上的面積’故壓印片212壓入至凹部204内，且 〇 可進一步壓縮連接層203之凹部204附近之部份。因而，可 於連接層203之凹部204附近之部份形成傾斜。 2〇 壓印片212之彈性變形層214在熱加壓步驟中及其前 後’可可逆變形，且具耐熱性。脫模層215設置成在熱加壓 步驟後’以良好效率使壓印片212剝離，非必須形成者。 此外，在上述製程中，首先，以使絕緣層203C之第1 面203H位於下側基板202之上面202A之狀態下，將連接層 22 200942116 203配置於下側基板202之上面202A，之後，將上側基板2〇1 配置於連接層203之上面203A。在第2實施形態中，亦可以 使絕緣層203C之第1面203H位於上侧基板201之下面201B 之狀態，將連接層203配置於上側基板201之下面201B，之 5 後，將連接層203配置於下側基板202之上面202A上。 連接層203之熱膨脹係數在上侧基板201及下側基板 202之熱膨脹係數以下、即65ppm/°C以下，以低於上側基板 201或下側基板202之熱膨脹係數為佳。 ❿ 當連接層203之熱膨脹係數超過65ppm/°C時，或高於上 10 側基板201及下側基板202之熱膨脹係數時，連接層203之變 形’易產生立體配線板216之翹曲或變形。 以動態機械分析(DMA)法測量之連接層203之玻璃轉 移點宜為185°C或宜比上側基板201及下側基板202之玻璃 轉移點咼10 C以上之差。當連接層203之玻璃轉移點不到 15 i85°c或差小於10°C時，在需要如迴焊般高溫之步驟，於基 板產生翹曲或彎曲等複雜形狀之變形，有該變形不可逆之 ❹ 情形。 連接層203不包含織布、不織布、薄膜等芯材。當連接 層203包含芯材時，設置於上側基板2〇丨及下側基板2〇2之配 20 線21〇、218不易埋入連接層203。 由於壓印片212之彈性變形層214之形狀冷卻後回復至 加熱剛之开)狀，故可於第圖所示之壓印步驟反覆使用。 即，準備另一配線板216,該另一配線板具有另一下側基板 202、以露出另—下側基板202上面202A之一部份202C之狀 23 200942116 態，設置於另一下侧基板202之上面202A的另一連接層 203、設置於另一連接層203之上面203A之另一上側基板 2(H，在另一下側基板202之上面202之一部份202A正上方具 有形成於另一上側基板201之上面201A的凹部204。於配線 5 板216之上側基板201之上面201A配置壓印片212,將配線板 216加熱加壓後，將壓印板212從上侧基板201之上面201A 剝離。在剝離壓印片212後，於另一配線板216之另一上側 基板201之上面201A配置壓印片212,將另一配線板216加熱 加壓。 ❿ 1〇 第14圖顯示連接層203之熔融黏度。連接層203之最低 熔融黏度以lOOOPa . s〜lOOOOOPa . s為適當。當最低熔融黏 度不到1000Pa· s時，熱硬化性樹脂203D之流動增大，有產 生在凹部204内熱硬化性樹脂203D之流入之虞。當最低熔融 黏度超過lOOOOOPa . s時，有產生與基板201、202之接觸不 15 良或配線120、128之埋入不良之虞。After heating and pressing 116, the platen 112 is peeled off from the upper surface 101A of the upper substrate 101. After the embossing sheet 112 is peeled off, the embossing sheet 112 is placed on the upper surface 101A of the other upper side G substrate 101 of the other wiring board 116, and the other wiring board 116 is heated and pressurized. 2〇 Fig. 7 shows the melt viscosity of the connection layer 103. The lowest melt viscosity of the tie layer is suitably 100OOa · s~lOOOOOPa · s. When the minimum melt viscosity is less than 1000 Pa·s, the flow rate of the thermosetting resin 103D increases, and the inflow of the thermosetting resin 103D in the concave portion 104 occurs. When the minimum melt viscosity exceeds 100 OOPa · s, there is a problem of poor contact with the substrate ΗΠ, 102 or the burying of the wirings 110, 118 of the 200942116. The connection layer 103 may also contain a colorant. Thereby, the encapsulation and light reflectivity are improved. In order to suppress the flow rate of the thermosetting resin 103D, the connection layer 103 preferably further contains 5 elastomers. In addition, the upper substrate 101 and the lower substrate 102 are not particularly limited as long as they are a via wiring board or a resin substrate such as an ALIVH wiring board having a full-layer IVH structure, and may be a double-sided substrate or a multilayer substrate. A plurality of substrates Ο 101 may be alternately laminated with a plurality of connection layers 103. Further, the insulating material for the upper substrate 101 and the lower substrate 102 is made of a composite material of a glass woven fabric and an epoxy resin. The insulating material may be formed of a composite material of a woven fabric composed of an organic fiber selected from guanamine or a wholly aromatic polyester and a thermosetting resin. Moreover, the insulating material may also be derived from P-amine, polyimine, polyphenylene benzobisoxazole (P〇1y (P_phenylenebenzobisoxazole), wholly aromatic polyacetate, PTFE, polyether oxime, poly A composite material of a non-woven fabric composed of an organic fiber selected from an ether quinone imine and a thermosetting resin, and the insulating material may be formed of a composite material of a non-woven fabric of a glass fiber and a thermosetting resin. It may be composed of P-decylamine, polyphenylene benzobisoxazole, perylene 20 fragrant polyester, polyether quinone imine, polyether ketone, polyether ether oxime, polyethylene terephthalate, At least one of a synthetic resin film of polytetrafluoroethylene, polyether sulfone, polyethylene terephthalate, polyimide, and polyphenylene sulfide, and a thermosetting resin layer provided on both sides of the synthetic resin film The composite material is formed. 15 200942116 The thermosetting resin l〇3D of the connection layer 103 can be selected from at least an epoxy resin, a polybutadiene resin, a phenol resin, a polyimide resin, a polyamide resin, and a cyanate salt. A thermosetting resin. (Second implementation Fig. 8A is a perspective view of a three-dimensional wiring board 216 according to a second embodiment of the present invention. Fig. 8B is a cross-sectional view of a line 8B-8B of the three-dimensional wiring board 216 shown in Fig. 8A. The lower substrate 202, the connection layer 203 provided on the upper surface 202A of the lower substrate 202, and the upper substrate 201 provided on the upper surface 203A of the connection layer 203. The upper substrate 201 and the lower substrate 202 have different shapes of 〇10. 203 has a thickness of 30 μm to 300 μm. The connection layer 203 is disposed on the upper portion 202A in a state of a portion 202C of the upper surface 202 of the lower substrate 202. Thus, a portion 202C of the upper portion 202A of the lower substrate 2〇2 A recess 204 surrounded by a portion 202C of the upper portion 202A, the connection layer 203, and the upper substrate 201 is formed directly above. The upper surface 201A of the upper substrate 201, the lower surface 15 201B, the upper surface 202A of the lower substrate 2〇2, and the lower surface 202B form a wiring. The part 205 is housed in the recess 204, and is packaged in the three-dimensional wiring board 216. Thereby, the total thickness of the three-dimensional wiring board 216 in which the component 205 is packaged can be reduced. Θ Figure 8C is a cross-sectional view of the connection layer 2〇3. 203 has the top The insulating layer 203C of the 203A and the lower surface 203B, and the via hole 207 provided in the insulating layer 203C. The insulating layer 203C forms the through hole 2〇9 connected to the upper surface 203A and the lower surface 203B. The conductive paste 2 is filled in the through hole 2〇9.导6, the via hole 2〇7 is formed. The insulating layer 203C is composed of a thermosetting resin such as epoxy resin 2〇3〇, and an inorganic filler 2〇3E diffused by the thermosetting tree a203D. The connecting layer 2〇3 is not A core material such as a woven non-woven fabric or a film is formed from the upper surface 203A to the lower surface 203B substantially 16 200942116 5 ❹ 10 15 ❿ 20 in a uniform material. When the thickness of the connection layer 203 is less than 30 μm, the wiring is not easily buried in the connection layer 203. When the thickness of the connection layer 203 exceeds 300 μm, the width of the via hole 2〇7 is too large, so that the diameter of the via hole 2〇7 is not easy to be formed, and the via hole 207 is less likely to be formed, which may impair the connection reliability. The inorganic filler 203 is preferably composed of at least one of cerium oxide, aluminum oxide, and titanic acid. The inorganic filler 203 has a particle diameter of 1 to 5 μm, and the insulating layer 203C preferably contains 70% by weight to 90% by weight. When the content of the inorganic filler 203 is less than 70% by weight, the inorganic filler 203 Ε also flows when the thermosetting resin 203D flows during pressurization. When the content of the inorganic filler 203 is more than 90%, the wiring is less likely to be buried in the insulating layer 203C, and it is difficult to adhere to the substrates 201 and 202. The conductive paste 206 is composed of copper, silver, gold, ruthenium, tin, and the like, and the granules are preferably 1 to 20 μm. Fig. 9 is a cross-sectional view of the three-dimensional wiring board 216. The concave portion 4 is surrounded by a portion 202C of the upper surface 202 of the lower substrate 202, a side surface 203F of the connection layer 203, and a side surface 201F of the upper substrate 201. That is, one portion 202C of the upper surface 202 of the lower substrate 202, the side surface 203F of the connection layer 203, and the side surface 201F of the upper substrate 201 face the concave portion 204. The portion 203G of the upper surface 203 of the connection layer 203 which is connected to the side surface 203F is inclined downward toward the concave portion 204, that is, toward the concave portion 204, and is inclined toward the direction 204C of the portion 202C of the upper portion 202 of the lower substrate 202. Therefore, the portion 201G of the upper surface 201 of the side substrate 201 which is disposed above the upper surface 203 of the connection layer 203 and which is connected to the side surface 20F is inclined downward toward the concave portion 204. That is, toward the concave portion 204, it is inclined toward the direction 204 of the portion 202C of the upper surface 202 of the lower substrate 2〇2. The portion 203G of the surface 203A on the connection layer 203 is formed into a curved shape having a rounded shape. Similarly, a portion of the upper surface 201A of the upper substrate 201 is formed into a curved shape having a rounded shape. Thereby, the edge portion 201H to which the upper surface 201A and the side surface 201F of the upper substrate 201 on the edge of the concave portion 204 are formed has a curved shape. The upper substrate 2〇1 includes a portion 61G which is inclined and has a curved shape, and has a thickness corresponding to the upper surface 201A. That is, the portion 201G of the upper surface 201A of the upper substrate 201 is parallel to the portion 203G of the upper surface 203A of the connection layer 203. The side surface 204F facing the concave portion 204 of the connection layer 203 has a curved shape. When the via holes are formed in the portions 201G and 203G of the upper 201A and 203A, the ® 10 has a case where the via hole is dumped. Therefore, the portions 201G, 203G are disposed in a range up to the guide hole closest to the edge of the concave portion 204. A plurality of via holes 207 are provided in the connection layer 203. Further, a plurality of via holes 219 formed of a conductive paste filled in a hole in the upper substrate are formed in the upper substrate 201. The guide holes 207A of the plurality of guide holes 207, 219 are closest to the recess 204, that is, the side faces 203F, 15201F. The inclined portions 201G, 203G of the upper faces 201A, 203A are disposed between the side faces 201F, 203F and the through holes 207A. That is, the portion 201G of the upper surface 201A of the upper substrate 201 and the portion 203G of the upper surface 203A of the connection layer 203 do not form a via hole. Fig. 10 is a cross-sectional view of the three-dimensional wiring board 2〇 116 in which the printing mask 211 is inserted into the recess 204. The pad 220 formed at the bottom of the recess 204, that is, a portion 202C of the upper portion 202A of the lower substrate 202 is printed via the printing mask 211. Since the concave portion 204 has a curved surface, the printed mask 211 can be easily inserted into the concave portion 204. Further, when the printing mask 211 is inserted and detached, it is possible to prevent the damage of the 18139442116 of the three-dimensional wiring board 116 caused by the deviation of the alignment from the contact recess 204. 5 Ο 10 15 ❹ 20 Since the sum of the thicknesses of the side faces 201F, 203F of the upper substrate 201 and the connection layer 203 is smaller than the height of the component 205 enclosed in the recess 204, the component 205 is easily inserted into the component 205 and used for packaging. The tool can be used to package the part 205 with good efficiency. The length of the portion 201G of the upper surface 201 of the upper substrate 201, the side 201F of the upper portion 203G of the upper layer 203 of the connection layer 203, and the side surface 203F are set at a right angle to be larger than the length of the grasping portion of the tool for packaging. Specifically, it is set to 1.0 mm or less, and more preferably set to 0.3 mm or less. A method of manufacturing the three-dimensional wiring board 216 of the second embodiment will be described. Figs. 1 to 11F, 12A to 12C, and 13A to 13C are cross-sectional views showing the process of the three-dimensional wiring board 216. First, as shown in Fig. 11A, an insulating layer 203C having the first surface 2〇3H and the second surface opposite to the first surface 203J and containing the uncured thermosetting resin 2〇3D is prepared. The resin film 208A and the resin film 208B are attached to the first surface 203H and the second surface 203J of the insulating layer 203C, respectively. The resin films 208A and 208B are made of a strong resin such as polyethylene terephthalate (PET). Then, as shown in Fig. 11B, a hole 204B for forming the concave portion 204, a cut insulating layer 203C, and resin films 208A and 208B are formed in the insulating layer 203C and the resin films 208A and 208B. Next, as shown in Fig. lie, the resin film 208A is peeled off, and the resin film 208C is bonded to the first surface 203H. The resin film 208C is made of a strong resin such as (PET). As shown in Fig. 11D, through holes 209 are formed in the insulating layer 203C through the resin films 2A, 8B, and 208C. Then, as shown in Fig. He, the conductive paste 206 is filled in the through hole 209 in 19 200942116 to form the via hole 207, and the connection layer 2〇3 is formed. Next, as shown in Fig. uf, the resin film 208C is peeled off. On the other hand, the resin film 208B is provided on the second surface 203J without being peeled off. Next, as shown in FIGS. 12A and 12B, the fifth layer 203H of the insulating layer 203C is positioned on the upper surface 202A of the lower substrate 202, and the connection layer 203 is disposed on the upper surface 202A of the lower substrate 2〇2. . As described above, the first surface 203H of the insulating layer 203C serves as the lower surface 203B of the connection layer 203, and the second surface 203J serves as the upper surface 203A. Wiring 210 is provided on the upper surface 202A of the lower substrate 202. When the connection layer 203 is disposed on the lower substrate 202, the wiring 210 is buried in the connection layer 203. Thereby, the ® 10 is tightly connected to the wiring 210 by compressing the conductive paste 206. Thereafter, as shown in Fig. 12C, the resin film 208B is peeled off from the upper surface 203A of the connection layer 203, that is, the second surface 203J of the insulating layer 203C. Next, as shown in Fig. 13A, the lower surface 201B of the upper substrate 201 is placed on the upper surface 203A of the connection layer 203, that is, the second surface 203J of the insulating layer 203C, and the upper substrate 201 is placed on the connection layer 203. Further, the embossing sheet 212 is placed on the upper surface 201A of the upper substrate 201, and the upper substrate 201, the connection layer 203, and the lower substrate 202 are heated and pressurized by thermal pressurization to be laminated. The embossed sheet 212 has a lower surface 212B that abuts the upper surface 201A of the upper substrate 201 and an upper surface 212A on the opposite side thereof. The embossing sheet 212 has a delamination layer 215 disposed on the lower surface 212B, an upper surface 215A disposed on the release layer 215, an elastic deformation layer 214 having heat resistance, and a release layer 218 disposed on the upper surface 214A of the elastic deformation layer 214. . The release layer 218 is disposed on the upper surface 212A of the stamp 212. The elastic deformation layer 214 is a reversibly deformable shape and is formed of a resin which is elastically deformed such as a resin. When the pressure plate 212, the upper substrate 201, the connection layer 203, and the lower substrate 20 200942116 5 Ο 10 15 ❹ 20 202 are heated and compressed, as shown in Fig. 13, the elastic deformation layer 214 and the release layer 215 are pressed. Into the recess 204. The elastic deformation layer 214 of the embossed sheet 212 suppresses the flow rate of the thermosetting resin 203D of the connection layer 203, and prevents the thermosetting resin from flowing into the concave portion 204. Thereby, the elastic deformation layer 214 is covered along the state of the upper substrate 201 and the recess 204, and blocks the flow of the thermosetting resin 203D at the time of compression. Thus, by the elastic deformation layer 214, even if the concave portion 204 is deep, the stamp 212 can be pressed into the concave portion 204 without a gap. As shown in FIG. 13 , when the elastic deformation layer 214 is pressed into the concave portion 204, since the portion near the side surface 203F facing the concave portion 204 of the connection layer 203 can be more compressed, it can be connected to the connection layer 203. The portion 203G of the upper surface 203 of the side surface 203F is inclined in the direction 204. At the time of this compression, the wiring 220 formed on the lower surface 201 of the upper substrate 201 is buried in the upper surface 203 of the connection layer 203. Thereby, since the conductive paste 206 is further compressed, it can be brought into close contact with the wirings 210 and 218. The upper substrate 201 itself is laminated so as not to be compressed, and the connecting layer 203 is formed so that the portion 201G of the upper surface 201 of the upper substrate 201 can be inclined in the direction 204A in parallel with the portion 203G of the upper surface 203A of the connection layer 203. Thus, the thickness of the upper substrate 201 includes the portion 201G and is uniform on the upper surface 201A. Thereafter, the embossing sheet 212, the upper substrate 201, the connection layer 203, and the lower substrate 202 are cooled. The embossed sheet 212 is peeled off, and as shown in Fig. 13C, the vertical wiring board 216 is completed. In the aspect of the three-dimensional wiring board 216, since the edge portion 201H to which the upper surface 201A of the upper substrate 201 is formed at the edge of the concave portion 204 and the side surface 201F is at an obtuse angle, the micro-wiring board 216 can be left without being damaged by the stamping sheet 212. And stripped. The elastically deformable layer 214 of the embossed sheet 212 is returned to the shape before heating upon cooling. Therefore, even if the concave portion 204 is deep, the embossed sheet 212 can be easily peeled off from the concave portion 21 200942116 204. In order to fill the stamping 212 in the recess π# with no gap, the elastic deformation layer 214 of the stamp 212 includes the surface abutting the stamp 212, that is, the surface area of the recess 204, and is elongated to the upper side. The area above the surface 2〇1A of the substrate 2〇1 is more than or equal to the area. Thereby, regardless of the shape or depth of the concave portion 204, the elastic deformation layer 214 can be filled in the concave portion 2〇4 without a gap. By the elongation elastic opening layer 214, the surface of the upper surface 201A and the concave portion 204 of the upper substrate 2〇1 can be uniformly pressurized. Thereby, the resin 203D of the connection layer 2〇3 can be prevented from overflowing into the concave portion 204. Further, the elastic deformation layer 214 has an elongation of ❹1〇700% or more, and is a physical strength for reversing elastic deformation, and has a tear strength of 15 N/mm or more, which is a shape imitation of the upper substrate 2〇1, and It is preferable to have a tensile strength of ΙΟΝ/mm or less. Further, in order to be surely filled in the concave portion 204, the hardness of the elastic deformation layer 214 which is measured in accordance with 耵8 κ 6253 is preferably 5 to 30 degrees. The thickness of the elastically deformable layer 214 15 is preferably greater than the depth of the recess 204 of the upper surface 201A of the upper substrate 201. As shown in Fig. 13B, since the elastic deformation layer 214 is elongated to an area larger than the surface area of the abutting surface, the stamp 212 is pressed into the recess 204, and the crucible can further compress the portion near the recess 204 of the connection layer 203. Share. Therefore, the portion adjacent to the concave portion 204 of the connection layer 203 can be inclined. 2) The elastically deformable layer 214 of the embossed sheet 212 is reversibly deformable in the heat pressurization step and before and after it, and has heat resistance. The release layer 215 is disposed to peel the stamp 212 with good efficiency after the hot pressing step, and is not necessarily formed. Further, in the above-described process, first, the connection layer 22 200942116 203 is disposed on the upper surface 202A of the lower substrate 202 in a state where the first surface 203H of the insulating layer 203C is located on the upper surface 202A of the lower substrate 202, and thereafter, The upper substrate 2〇1 is disposed on the upper surface 203A of the connection layer 203. In the second embodiment, the first surface 203H of the insulating layer 203C may be placed on the lower surface 201B of the upper substrate 201, and the connection layer 203 may be disposed on the lower surface 201B of the upper substrate 201, and then the connection layer 203 may be disposed. It is disposed on the upper surface 202A of the lower substrate 202. The thermal expansion coefficient of the connection layer 203 is preferably less than or equal to the thermal expansion coefficient of the upper substrate 201 and the lower substrate 202, i.e., 65 ppm/°C or less, and is preferably lower than the thermal expansion coefficient of the upper substrate 201 or the lower substrate 202. ❿ When the thermal expansion coefficient of the connection layer 203 exceeds 65 ppm/° C. or is higher than the thermal expansion coefficient of the upper 10 side substrate 201 and the lower substrate 202, the deformation of the connection layer 203 easily causes warpage or deformation of the three-dimensional wiring board 216. . The glass transition point of the connection layer 203 measured by the dynamic mechanical analysis (DMA) method is preferably 185 ° C or preferably different from the glass transition point 咼 10 C of the upper substrate 201 and the lower substrate 202. When the glass transition point of the connection layer 203 is less than 15 i85 ° C or the difference is less than 10 ° C, in the step of requiring high temperature such as reflow, deformation of a complex shape such as warpage or bending occurs on the substrate, and the deformation is irreversible. ❹ Situation. The connecting layer 203 does not include a core material such as a woven fabric, a non-woven fabric, or a film. When the connection layer 203 includes a core material, the 20 wires 21, 218 provided on the upper substrate 2A and the lower substrate 2A2 are less likely to be buried in the connection layer 203. Since the shape of the elastic deformation layer 214 of the embossed sheet 212 is cooled and returned to the shape of the heating, it can be used repeatedly in the embossing step shown in the figure. That is, another wiring board 216 having another lower substrate 202 to expose a portion 202C of the upper portion 202A of the lower substrate 202 is in the state of 200942116, and is disposed on the other lower substrate 202. The other connection layer 203 of the upper portion 202A and the other upper substrate 2 (H of the upper surface 203A of the other connection layer 203 are formed on the other upper side directly above the portion 202A of the upper surface 202 of the other lower substrate 202. The concave portion 204 of the upper surface 201A of the substrate 201. The stamping sheet 212 is disposed on the upper surface 201A of the upper substrate 201 of the wiring board 216, and after the wiring board 216 is heated and pressurized, the stamping plate 212 is peeled off from the upper surface 201A of the upper substrate 201. After the embossing sheet 212 is peeled off, the embossing sheet 212 is placed on the upper surface 201A of the other upper substrate 201 of the other wiring board 216, and the other wiring board 216 is heated and pressurized. ❿ 1〇 Figure 14 shows the connection layer 203. The melt viscosity is the lowest melt viscosity of the connection layer 203. The minimum melt viscosity is preferably 100 Å to 100 OO s. When the minimum melt viscosity is less than 1000 Pa·s, the flow of the thermosetting resin 203D is increased, and heat is generated in the concave portion 204. The inflow of the curable resin 203D When the lowest melt viscosity exceeds lOOOOOPa. When the s, there are generated 201, 202 in contact with the substrate 15 is not good or the bad of wires 120, 128 of the embedded risk.
連接層203亦可含有著色劑。藉此，提高封裝性、光反 射性。 G 為抑制熱硬化性樹脂203D之流量，連接層203宜更含有 彈性體。 20 此外，上側基板201及下側基板202只要為通孔配線板 或全層IVH構造之ALIVH配線板等樹脂基板，非特別限定 者’可為兩面基板，亦可為多層基板。亦可將複數個基板 201、202與複數個連接層203交互層積。 又，上側基板201及下側基板202以由玻璃織布與環氧 24 200942116 .緒脂之複合材料構成之絕緣材料形成。此絕緣材料亦可 為以從醯胺、全芳香族聚醋選出之有機質纖維構成之織布 與熱硬化性樹脂之複合材料形成。又，此絕緣材料亦可以 ⑽p_醯胺、親亞胺、聚亞苯基苯並LGiy(p_phen 5 ylenebenZ〇biS〇Xaz〇le)、全芳香族聚酯、PTFE、聚醚砜、聚 賴亞㈣擇之«質_構紅不織布與熱硬化性樹脂 之複合材料形成。又，此絕緣材料可以以玻璃纖維構成之 不織布及熱硬化性樹脂之複合材料形成。又，此絕緣材料 ❿ ’亦可以由P_醯胺、聚亞苯基笨並二㈣、全芳香族聚醋、 10聚醚醯亞胺、聚醚酮、聚醚醚酮、聚對笨二甲酸乙二醇酯、 |四氟乙烯、聚_、聚乙烯對苯二甲酸醋、聚醯亞胺及 鮮綱之至少任-合賴脂薄駭設置於此合成樹脂薄 膜兩面之熱硬化性樹脂層構成之複合材料形成。 熱硬化性樹脂103D可使用從環氧樹脂、聚丁二稀樹 15脂、苯酚樹脂、聚醯亞胺樹脂、聚醯胺樹脂及氰酸鹽選擇 之至少一個熱硬化性樹脂。 〇 此外，在實施形態中，表示「上面」、「下面」、「正上 方」、「下方」等之方向之用語顯示上側基板101、201、下 側基板102、202、連接層103、203等與立體配線板116、216 20 之構成零件相關之相對方向，非顯示上下方向等絕對方向。 【圖式簡單說明】 第1A圖係本發明實施形態之立體配線板之立體圖。 第1B圖係第1A圖所示之立體配線板之線1B-1B之戴面 25 200942116 第1C圖係第1實施形態之立體配線板之連接層之截面 圖。 第2圖係第1實施形態之立體配線板之截面圖。 第3 A圖係顯示第1實施形態之立體配線板之製程之載 5 面圖。 第3B圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第3C圖係顯示第1實施形態之立體配線板之製程之截 面圖。 10 第3D圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第3E圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第3F圖係顯示第1實施形態之立體配線板之製程之截 15 面圖。 第4A圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第4B圖係顯示第1實施形態之立體配線板之製程之截 面圖。 20 第4C圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第5A圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第5B圖係顯示第1實施形態之立體配線板之製程之截 200942116 面圖。 第5C圖係顯示第1實施形態之立體配線板之製程之截 面圖。 第6圖係顯示第1實施形態之立體配線板之製程之截面 5 圖。 ' 第7圖係顯示第1實施形態之立體配線板之連接層之熔 融黏度。 第8A圖係本發明第2實施形態之立體配線板之立體圖。 φ 第8B圖係第8A圖所示之立體配線板之線8B-8B之截面 10 圖。 第8C圖係第2實施形態之立體配線板之連接層之截面 圖。 第9圖係第2實施形態之立體配線板之截面圖。 第10圖係第2實施形態之立體配線板之截面圖。 15 第11A圖係顯示第2實施形態之立體配線板之製程之截 面圖。 Ο 第11B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第11C圖係顯示第2實施形態之立體配線板之製程之截 20 面圖。 第11D圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第11E圖係顯示第2實施形態之立體配線板之製程之截 面圖。 27 200942116 第11F圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第12A圖係顯示第2實施形態之立體配線板之製程之截 面圖。 5 10 15 第12B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第12C圖係顯示第2實施形態之立體配線板之製程之戴 面圖。 第13A圖係顯示第2實施形態之立體配線板之製程之戴 面圖。 第13B圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第13C圖係顯示第2實施形態之立體配線板之製程之截 面圖。 第14圖係顯示第2實施形態之立體配線板之連接層之 熔融黏度。 第15A圖係顯示習知配線板之製程之截面圖。 第15B圖係顯示習知配線板之製程之截面圖。 【主要元件符號說明】 101…上側基板 IOIA. ..上面 IOIB. ..下面 IOIF. ..側面 IOIG. ..部份 101H·.·邊緣部 102…下側基板 102A...上面 102B...下面 102C...— 部份 28 200942116The connection layer 203 may also contain a colorant. Thereby, the encapsulation and light reflectivity are improved. G is for suppressing the flow rate of the thermosetting resin 203D, and the connecting layer 203 preferably further contains an elastomer. In addition, the upper substrate 201 and the lower substrate 202 are resin substrates such as a via wiring board or an ALIVH wiring board having a full-layer IVH structure, and may be a double-sided substrate or a multilayer substrate. A plurality of substrates 201, 202 may be alternately laminated with a plurality of connection layers 203. Further, the upper substrate 201 and the lower substrate 202 are formed of an insulating material made of a composite material of a glass woven fabric and an epoxy resin. The insulating material may be formed of a composite material of a woven fabric and a thermosetting resin composed of organic fibers selected from decylamine or wholly aromatic polyester. Moreover, the insulating material may also be (10) p_ decylamine, pro-imine, polyphenylene benzene LGiy (p_phen 5 ylenebenZ〇biS〇Xaz〇le), wholly aromatic polyester, PTFE, polyether sulfone, poly rya (4) Selecting the composite material of the material_texture non-woven fabric and thermosetting resin. Further, the insulating material may be formed of a composite material of a nonwoven fabric made of glass fiber and a thermosetting resin. Moreover, the insulating material ❿ ' can also be composed of P_ guanamine, polyphenylene stupid (four), wholly aromatic polyacetate, 10 polyether oxime imine, polyether ketone, polyether ether ketone, poly-pair two Ethylene glycol formate, tetrafluoroethylene, poly-, polyethylene terephthalate vinegar, polyimine, and at least any of the lysines, which are provided on both sides of the synthetic resin film, are thermosetting resins. A composite material composed of layers is formed. As the thermosetting resin 103D, at least one thermosetting resin selected from the group consisting of an epoxy resin, a polybutylene resin, a phenol resin, a polyimide resin, a polyamide resin, and a cyanate can be used. In addition, in the embodiment, terms such as "upper", "lower", "upper", and "lower" indicate the upper substrates 101 and 201, the lower substrates 102 and 202, the connection layers 103 and 203, and the like. The relative direction with respect to the components of the three-dimensional wiring boards 116 and 216 20 does not indicate the absolute direction such as the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A is a perspective view of a three-dimensional wiring board according to an embodiment of the present invention. Fig. 1B is a perspective view of a line 1B-1B of a three-dimensional wiring board shown in Fig. 1A. 200942116 Fig. 1C is a cross-sectional view showing a connection layer of a three-dimensional wiring board according to the first embodiment. Fig. 2 is a cross-sectional view showing a three-dimensional wiring board of the first embodiment. Fig. 3A is a plan view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. 10 is a cross-sectional view showing a process of the three-dimensional wiring board of the first embodiment. Fig. 3E is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 3F is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4A is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 4C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 5A is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 5B is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 5C is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 6 is a cross-sectional view showing the process of the three-dimensional wiring board of the first embodiment. Fig. 7 is a view showing the melt viscosity of the connection layer of the three-dimensional wiring board of the first embodiment. Fig. 8A is a perspective view of a three-dimensional wiring board according to a second embodiment of the present invention. φ Fig. 8B is a cross-sectional view of the line 8B-8B of the three-dimensional wiring board shown in Fig. 8A. Fig. 8C is a cross-sectional view showing a connection layer of a three-dimensional wiring board of the second embodiment. Fig. 9 is a cross-sectional view showing a three-dimensional wiring board of the second embodiment. Fig. 10 is a cross-sectional view showing a three-dimensional wiring board of a second embodiment. Fig. 11A is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11C is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11D is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 11E is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. 27 200942116 Fig. 11F is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 12A is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. 5 10 15 Fig. 12B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 12C is a perspective view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13A is a front view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13B is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 13C is a cross-sectional view showing the process of the three-dimensional wiring board of the second embodiment. Fig. 14 is a view showing the melt viscosity of the connection layer of the three-dimensional wiring board of the second embodiment. Fig. 15A is a cross-sectional view showing the process of a conventional wiring board. Fig. 15B is a cross-sectional view showing the process of a conventional wiring board. [Main component symbol description] 101...Upper substrate IOIA... Above IOIB... Below IOIF.....Side IOIG...Part 101H·.·Edge portion 102...Lower substrate 102A...Top 102B.. 102C below... Part 28 200942116
103.. .連接層 103A...上面 103B...下面 103C...絕緣層 103D...熱硬化性樹脂 103E...無機填料 103F...側面 103G...部份 103H...第 1 面 103J···第 2面 104.. .凹部 104A...方向 104B...孔 105.. .零件 106.. .導電性膏 107.. .導孔 107A...導孔 108A...樹脂薄膜 108B...樹脂薄膜 108C...樹脂薄膜 109·.·貫穿孔 110.. .配線 112.. .壓印片 112A...上面 112B...下面 114.. .變形層 114A...上面 115.. .脫模層 115A...上面 116…立體配線板 118.. .脫模層 119…導孔 120.. .配線 121.. .連接層 122.. .下側基板 123.. .上側基板 124.. .解放層 125.. .熱可塑性樹脂層 126…片 127.. .配線板 128…凹部 201.. .上側基板 201A...上面 201B...下面 201F...側面 201G...部份 201H...邊緣部 202.. .下側基板 29 200942116 202A...上面 202B...下面 202C...— 部份 203.. .連接層 203A...上面 203B...下面 203C...絕緣層 203D...熱硬化性樹脂 203E...無機填料 203G...部份 203H...第 1 面 20Ή...第2面 204.. .凹部 204A...方向 204B··.孔 204F...侧面 205.. .零件 206.. .導電性膏 207.. .導孔 207A...導孔 208A...樹脂薄膜 208B...樹脂薄膜 208C...樹脂薄膜 209.. .貫穿孔 210.. .配線 211.. .印刷遮罩 212A...上面 212B...下面 214.. .彈性變形層 215.··脫模層 215A...上面 216.. .立體配線板 218.. .脫模層 220.. .配線103.. Connection layer 103A... Upper surface 103B... Lower 103C... Insulation layer 103D... Thermosetting resin 103E... Inorganic filler 103F... Side 103G... Part 103H.. .1st surface 103J···2nd surface 104.. recessed part 104A... direction 104B... hole 105.. part 106.. conductive paste 107.. guide hole 107A... guide hole 108A...resin film 108B...resin film 108C...resin film 109·.·through hole 110..wiring 112..printing 112A...top 112B...below 114.. Deformed layer 114A... Upper surface 115.. Release layer 115A... Upper surface 116... Three-dimensional wiring board 118.. Release layer 119... Guide hole 120.. Wiring 121.. Connection layer 122.. Lower substrate 123.. Upper substrate 124.. Liberation layer 125.. Thermoplastic resin layer 126... Sheet 127.. Patch panel 128... Recess 201.. Upper substrate 201A... Top 201B... The following 201F... side 201G...part 201H...edge portion 202..lower substrate 29 200942116 202A...top 202B...bottom 202C...-part 203.. 203A...the upper 203B...the lower 203C...the insulating layer 203D...the thermosetting resin 203E...the inorganic filler 203G...the portion 203H...the first surface 20Ή... 2 faces 204.. recesses 204A...direction 204B··. holes 204F... side 205.. parts 206.. conductive paste 207.. guide holes 207A... guide holes 208A... Resin film 208B... Resin film 208C... Resin film 209.. Through-hole 210.. Wiring 211.. Print mask 212A... Top 212B... Below 214.. Elastic deformation layer 215 ..· release layer 215A... above 216.. three-dimensional wiring board 218.. release layer 220.. .
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