TW200935460A - Semiconductor ceramic composition and method for producing the same - Google Patents

Semiconductor ceramic composition and method for producing the same

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Publication number
TW200935460A
TW200935460A TW97104571A TW97104571A TW200935460A TW 200935460 A TW200935460 A TW 200935460A TW 97104571 A TW97104571 A TW 97104571A TW 97104571 A TW97104571 A TW 97104571A TW 200935460 A TW200935460 A TW 200935460A
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Taiwan
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calcined powder
bina
semiconductor
powder
composition
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TW97104571A
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Chinese (zh)
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TWI406303B (en
Inventor
Takeshi Shimada
Kazuya Toji
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Hitachi Metals Ltd
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Priority to TW97104571A priority Critical patent/TWI406303B/en
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Publication of TWI406303B publication Critical patent/TWI406303B/en

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Abstract

This invention provides a semiconductor ceramic composition and a method of producing the same in which a part of Ba in BaTiO3 is substituted with Bi-Na, so as to inhibit the evaporation of Bi during calcinations, and to prevent compositional shift of Bi-Na, which inhibits the formation of out-phases, reduces the resistivity at room temperature and inhibits fluctuation of Curie temperature. The Ba (TiM) O3 calcined powder (where M is a semiconductive element) and (BiNa) TiO3 calcined powders are prepared separately. The Ba(TiM)O3 calcined powder is calcined at a higher temperature, and the (BiNa)TiO3 calcined powder is calcined at a lower temperature, each being calcined at its corresponding optimum temperature respectively, so as to inhibit the evaporation of Bi and prevent compositional shift of Bi-Na and thus inhibit the formation of out-phases. The calined powders are mixed, formed, and sintered to obtain a semiconductor ceramic composition having a reduced resistivity at room temperature and a suppressed fluctuation of Curie temperature.

Description

200935460 九、發明說明: 【發明所屬之技術領域】 本發明係關於PTC熱阻器、PTC加熱器、PTC開關、溫 度檢測器等所使用,並具有正電阻溫度的半導體瓷器組成 - 物和其製造方法。 . 【先前技術】 作為習知顯示PTCR特性(正比電阻溫度係數:p〇sitive ❹ ^mperatUre C〇efficient 〇f Resistivity)的材料,係 提案有在BaTi〇3中添加各種半導體化元素的組成物。該等 組成物的居里溫度係在120。(:左右。另外,該等組成物必 需配合用途而使居里溫度偏移。 例如提案有藉由在BaTi〇3令添加SrTi〇3,而使居里溫度 偏移,但此情況,居里溫度僅朝負方向偏移,在正方向: 並無偏移。目前,已知使居里溫度朝正方向偏移的添加元 素僅有PbTi〇3但疋’因為pbTi〇4有會導致環境污染的 ❹元素,因而近年便渴望不使用PbTi〇3的材料。 針對BaTiM半導體究器,在防止因pb取代而造成的 電阻溫度係數降低以及降低電麗依存性情形,並且提升生 f性與可靠度等目的T,提案有未使用PbTiG3,而是將 - BaTi〇3中的部分 刹田 刀此利用B卜Na進行取代而形成200935460 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor porcelain composition using a PTC thermistor, a PTC heater, a PTC switch, a temperature detector, etc., and having a positive resistance temperature, and a manufacturing thereof method. [Prior Art] As a material which exhibits a PTCR characteristic (proportional resistance temperature coefficient: p〇sitive ❹ ^mperatUre C〇efficient 〇f Resistivity), a composition in which various semiconductor elements are added to BaTi〇3 is proposed. The Curie temperature of these compositions is at 120. (: Left and right. In addition, the composition must be offset by the use of the composition. For example, it is proposed to add the SrTi〇3 in BaTi〇3 to offset the Curie temperature, but in this case, Curie The temperature is only shifted in the negative direction, in the positive direction: there is no offset. At present, it is known that the additive element that shifts the Curie temperature in the positive direction is only PbTi〇3 but 疋' because pbTi〇4 can cause environmental pollution. The bismuth element, in recent years, is eager to not use PbTi〇3 materials. For BaTiM semiconductors, it prevents the temperature coefficient of resistance caused by the replacement of pb and reduces the dependence on the battery, and improves the reliability and reliability. For the purpose of T, it is proposed that PbTiG3 is not used, but some of the brake knives in -BaTi〇3 are replaced by B-sub-Na.

Ba卜2x(BiNa)xTi〇3 構造中,力脸 ^ 在將χ设為〇<χ$0·15範圍内 的組成物中添加Nb、Ta或稀土族元素中之任一種或一種 =上,並在氮巾施行燒結後,再於氧化 理的BaTi〇3系半導體瓷考夕制也士 衣见丁 e叮…処 f㈣U之製造方法(專利獻)。 97104571 5 200935460 專利文獻1:日本專利特開昭56__1693〇1號公報 【發明内容】 ° (發明所欲解決之問題) 專利文獻1 +’於實施射揭*有將作為起始原料的 • BaC〇3、TiO” Bi2〇3、Na2〇3、pb0 等構成組成物的所 _ ϋ ^ .於緞燒前便進行混合,並施行緞燒、成形、燒成、熱處理。 但是’將BaTi〇3的部分Ba利用Bi,進行取代的电成 ❹物:,若如專利文獻!般,將構成組成物的所有元素於锻 燒前便進行混合’㈣燒步驟中,Bi會揮散而導致Βϋ 組成發生偏差,因而促進異相的生成,引發室溫中的電阻 率上升、居里溫度之變動等問題。 為抑制Bi的揮散,雖可考慮依較低溫度施行煅燒,但In the Ba Bu 2x(BiNa)xTi〇3 structure, the force face ^ is added to any one of the Nb, Ta or rare earth elements in the composition in the range of χ<χ$0·15= After the sintering of the nitrogen towel, the BaTi〇3-based semiconductor ceramics of the oxidation process is also used in the manufacturing method (patent offer) of the f (four) U. 97104571 5 200935460 Patent Document 1: Japanese Patent Laid-Open Publication No. SHO 56-_1693 No. 1 [Draft of the Invention] ° (Problems to be Solved by the Invention) Patent Document 1 + 'In the implementation of the shots*, there will be a starting material • BaC〇 3, TiO" Bi2〇3, Na2〇3, pb0 and other constituents of the composition _ ϋ ^. Before satin burning, mixing, and satin burning, forming, firing, heat treatment. But 'BaTi〇3 Partially Ba uses Bi to replace the electroformed mash: If, as in the patent literature, all the elements constituting the composition are mixed before calcination, in the (four) burning step, Bi will volatize and cause Βϋ composition to deviate. Therefore, the generation of heterogeneous phases is promoted, and problems such as an increase in resistivity at room temperature and a change in Curie temperature are caused. In order to suppress the volatilization of Bi, calcination may be considered at a lower temperature, but

Bi的揮散雖被抑制,可是卻有無法形成完全固溶體,: 法獲得所需特性的問題。 …、 本發明之目的在於提供未使用pb,可使居里溫度朝正 〇方向偏移,且可使室溫中的電阻率大幅降低之半導體瓷 組成物和其製造方法。 ° 再者,本發明之目的在於提供在將BaTi〇3的部分⑹利 •用Bi-Na進行取代的半導體瓷器組成物中,抑制煅燒步驟 -中的Bi揮散情形,防止Bi-Na的組成偏差情形俾抑制異 相的生成,並可使室溫中的電阻率更加降低,且能抑制居 里溫度變動的半導體瓷器組成物和其製造方法。 (解決問題之手段) 發明者等為能達成上述目的,經深入鑽研的結果,發現 97104571 6 200935460 當製造將BaTi〇3的部分Ba利用Bi_Na進行取代的半導體 瓷器組成物時,藉由分別準備Ba(TiM)〇3煅燒粉(M係半導 體化元素)和(BiNa)Ti〇3煅燒粉,並將Ba(TiM)〇3鍛燒粉依 較高溫、而將(BiNa)Ti〇3煅燒粉依較低溫,分別依各自對 應的最佳溫度施行煅燒,便可抑制Ba(TiM)〇3烺燒粉的Bi 揮散情形,可防止Bi_Na組成偏差俾抑制異相生成而藉 由將該等煅燒粉施行混合,並施行成形、燒結,便可獲得 至溫中的電阻率低,且經抑制居里溫度變動的半導體瓷器 組成物。 本發月的半導體瓷器組成物之製造方法,係將t〇3 =部分Ba利用Bi-Na進行取代的半導體究器組成物之製 每方法,包括有:準備ga(TiM)〇3煅燒粉(M係半導體化元 素)的步驟;準備(BiNa)Ti〇3煅燒粉的 锻燒粉與⑽a)Ti0邊燒粉進行漏合的步称;以及(將^ 煅燒粉施行成形、燒結的步驟。 ❹再者’本發明係針對上述構成之製造方法,提案如下: 在準備Ba(TiM)04燒粉的步驟中,锻燒溫度係9〇代Although the diffusion of Bi is suppressed, there is a problem that the complete solid solution cannot be formed: the method obtains the desired characteristics. The object of the present invention is to provide a semiconductor ceramic composition which can shift the Curie temperature in the normal direction without using pb, and which can greatly reduce the electrical resistivity at room temperature, and a method for producing the same. Further, an object of the present invention is to provide a semiconductor porcelain composition in which a portion (6) of BaTi〇3 is substituted with Bi-Na, suppressing the V-dispersion in the calcination step, and preventing the compositional deviation of Bi-Na. In the case, the formation of a heterogeneous phase is suppressed, and the resistivity at room temperature is further lowered, and the semiconductor ceramic composition in which the Curie temperature fluctuation is suppressed and the method for producing the same can be suppressed. (Means for Solving the Problem) In order to achieve the above object, the inventors found that 97104571 6 200935460, when fabricating a semiconductor ceramic composition in which a portion Ba of BaTi〇3 is substituted with Bi_Na, is prepared by separately preparing Ba. (TiM) 〇3 calcined powder (M-based semiconductor element) and (BiNa)Ti〇3 calcined powder, and Ba(TiM)〇3 calcined powder is based on higher temperature, and (BiNa)Ti〇3 calcined powder At a lower temperature, the calcination is carried out according to the respective optimum temperatures, thereby suppressing the Bi-dispersion of Ba(TiM)〇3烺-burning powder, preventing Bi_Na composition variation, suppressing heterogeneous formation, and mixing the calcined powders. And forming and sintering, a semiconductor ceramic composition having a low resistivity to a temperature and suppressing a change in the Curie temperature can be obtained. The manufacturing method of the semiconductor porcelain composition of the present month is a method for preparing a semiconductor device composition in which t〇3 = partial Ba is replaced by Bi-Na, and includes: preparing ga(TiM)〇3 calcined powder ( a step of preparing a (Bi-based semiconductor element); a step of preparing a calcined powder of (BiNa) Ti〇3 calcined powder and (10) a) a Ti0 side-fired powder; and a step of forming and sintering the calcined powder. Further, the present invention is directed to the production method of the above configuration, and is proposed as follows: In the step of preparing Ba (TiM) 04 powder, the calcination temperature is 9 generations.

驟中,鍛燒溫度係70(TC 在準備(BiNa)Ti〇3煅燒粉的步 〜950°c ; 煅燒粉進行混合的 在將 Ba(TiM)〇3 煅燒粉與(BiNa)Ti〇3 步驟令’混合係依乾式實施; 在準備Ba(TiM)〇3煅燒粉的 燒粉的步驟、或二項步驟中, 步驟、或準備(BiNa)Ti〇3烺 於锻燒前,添加Si氧化物 97104571 200935460 3. 0莫耳%以下、Ca碳酸鹽或Ca氧化物4. 0莫耳%以下; 在將Ba(TiM)〇3煅燒粉與(BiNa)Ti〇3煅燒粉進行混合的 步驟中,添加Si氧化物3. 0莫耳%以下、Ca碳酸鹽或Ca 氧化物4. 0莫耳%以下; 半導體化元素Μ係Nb、Sb中之至少一種,半導體瓷器 組成物的組成式係依[(訂心)5^1_3[][141_1]〇3表示,又、7 係滿足 0<x$ 〇. 3、〇<y$〇. 〇〇5 ;以及 該構成中,Bi與Na的比係滿足Bi/Na=0· 78〜1的關係。 再者,本發明的半導體瓷器組成物,係將Ba(TiM)〇3锻 燒粉(M係半導體化元素,且為Nb、Sb中之至少一種)與 (BiNa)Ti〇3煅燒粉的混合煅燒粉進行成形、燒結而成的半 導體瓷器組成物,其中,組成式依[(BiNa)xBai χ] [Tii 表示 ’ x、y 滿足 0<x^〇.3、0<y^ 0.005,Bi 與 Na 的 比則滿足Bi/Na=0. 78〜1的關係。 (發明效果) 〇 根據本發明,可提供未使用會造成環境污染的Pb,且 可使居里溫度上升,並能使室溫中的電阻率大幅降低之丰 導體瓷器組成物。 -牛 根據本發明’可提供能夠抑制煅燒步驟+的Bi揮散情 形’防止Bi-Na的組成偏差情形俾抑制含有Na的異二: =成’並可使室溫中的電阻率更加降低’且能抑制居里况 度變動的半導體瓷器組成物。 '皿 【實施方式】 本發明中準備Ba(TiM)Q3炮燒粉(M係半導體化元素)之 97104571 8 200935460 步驟,首先,係將主原料的議3、Ti〇2與半導體化元素 的Nb2〇5或Sb2〇3進行混合,而製成混合原料粉末並施行 .锻燒。锻燒溫度最好設定在_。㈡3崎範圍内,锻燒 時間最好設定在0.5小時以上。若煅燒溫度未滿議。C或 -锻燒時間未滿0.5小時,無法完全形成叫_3,未反 •應的_會與環境中及混合介質的水分產生反應,導致成 為组成偏差的肇目,因而最好避免。此外,錢燒溫度超 ❹過1300Ϊ,烺燒粉中會產生燒結體,妨礙與爾後進行混 合的(BiNa)Ti〇3煅燒粉間之固溶,因而最好避免。 本發明中準備(BlNa)Ti〇3煅燒粉之步驟,係首先將原料 粉末的Na2C〇3、Bi2〇3、Ti〇2進行混合而製作混合原料粉末, 並施行烺燒。煅燒溫度最好設定在7〇(rc〜95(rCi圍内, 炮燒時間最好設定在0.5小時〜1〇小時。若鍛燒溫度未滿 7〇〇 C或煅燒時間未滿〇· 5小時,未反應的Ν&〇會與環境 之水分或進行濕式混合時之溶劑產生反應,導致發生組成 ❹偏差、特性變動等情形,因而最好避免。此外,若煅燒溫 度超過9501:或煅燒時間超過1〇小時,會促進Bi揮散, 引發組成偏差情形’且促進異相生成,因而最好避免。 另外,準備上述Ba(TiM)〇3煅燒粉的步驟中之較佳煅燒 溫度(900。〇1300。〇,與準備(BiNa)Ti〇3緞燒粉的步驟中 之較佳煅燒溫度(7〇〇 t〜950。〇,最好配合用途等適當地 進行最佳溫度選擇。例如(β i Na ) T i 〇3的煅燒溫度係為了能 在抑制Bi揮散的情況下充分進行反應,最好施行經調整 锻燒時間等並依較低溫實施。此外,(BiNa)Ti〇3的烺燒溫 97104571 9 200935460 度最好設定為低於Ba(TiM)〇3的煅燒溫度。 上述分別執行準備Ba(TiM)〇3的步驟、與準備 (BiNa)Ti〇3煅燒粉的步驟,係本發明的主要特徵,藉此, 可提供經抑制緞燒步驟中之(BiNa)Ti〇3的Bi θ -防止Bi-Na組成偏差俾抑制異相生成,進一步降低=溫中 •的電阻率’且抑制居里溫度變動的半導體瓷器組成物。 上述各自準備煅燒粉的步驟中,當進行原料粉末混合之 ❹際,亦可配合原料粉末的粒度施行粉碎。此外,混合、粉 碎係可採取使用純水或乙醇的濕式混合·粉碎或^ 合•粉碎等任何方式,最好施行乾式混合•粉碎,可更加 防止組成偏差。另外,上述中,作為原料粉末係舉BaC〇3、 NaAOs、Ti(h等為例,但即便使用其他的Ba化合物、 化合物等,仍不致損及本發明的效果。 如上述,當分別準備Ba(TiM)〇3烺燒粉與(BiNa)Ti〇3緞 燒粉之後,將各緞燒粉調配既定量之後便施行混合。混合 ❹係可採取使用純水或乙醇的濕式混合或乾式混合等任; 方式’最好施行乾式混合,因可更加防止組成偏差情形。 此外,亦可配合烺燒粉的粒度,經混合後再施行粉碎、或 -者同時施行混合與粉碎。混合、粉碎後的混合锻燒粉平均 粒度最好為0.6/zm~1.5/zin。 上述準備Ba(TiM)〇3煅燒粉的步驟及/或準備 (B’TiG3煅燒粉的步驟、或將各烺燒粉進行混合的步驟 中,若添加Si氧化物3.0莫耳%以下、以氧化物或以碳 酸鹽4.0料%以下,Si氧化物會抑制結晶粒的異常成 97104571 200935460 長,且可輕易地進行電阻率之控制,而CaA化物或c 酸鹽可提升在低溫下的燒結性,並可控制還原性,因而屬 較佳狀況。若任一者添加超過上述限定量,則組成物無法 顯示半導體化,因而最好避免。添加最好在各步驟中 混合前便實施^ 订 • 藉由將Ba(TiM)〇3煅燒粉與(BiNa)Ti〇3煅燒粉進行混合 的步驟而獲得的混合烺燒粉予以成形、燒結,便可獲得: ❹發明的半導體瓷器組成物。以下舉出煅燒粉混合步驟以後 的較佳步驟之一例,惟並不僅侷限於此,亦可採用公知之 任何方法。 利用Ba(TiM)〇3緞燒粉與(BiNa)Ti〇3烺燒粉進行混合的 步驟而獲得的混合烺燒粉,係利用所需成形手段進行成 形。在成形前,視需要亦可將粉碎粉利用造粒裝置而施行 造粒。經成形後的成形體密度最好為2〜3g/cm3。 燒結係可在大氣中或還原環境中、或低氧濃度的惰性氣 ❹體環境中’且依燒結溫度1200°C〜1400。(:、燒結時間2小 時〜6小時的條件實施,此外’採用以下所示燒結步驟亦 屬較佳一例。另外,當在成形前便施行造粒的情況,最好 於燒結前便依3 0 0 °C〜7 0 0 °C施行脫黏結劑處理。 -燒結步驟係在溫度1290°C〜135(TC、氧濃度未滿1%的環 境中,(1)依未滿4小時的燒結時間實施,或者(2)依滿足 式:△ T2 25t(t=燒結時間(hr),△ T=燒結後的冷卻速度 (°C/hr))之燒結時間實施,接著,依滿足上式的冷卻速度 施行燒結後的冷卻。 97104571 200935460 上述任一燒結步驟,亦即縮短燒結時間或延長燒結時 =由依配合該燒結時間的適當急冷速度施行急冷,便 可,侍如利用BaTiCh系材料施行,於未在大氣中施行熱處 里等的If况下’仍保持低的室溫比電阻,且於高溫區域(居 里溫度以上)中提升電阻溫度係數的半導體究器組成物。 匕上述燒結步驟中,所謂「氧濃度未滿U的環境t」,係 指氧濃度未滿U的真空中或惰性氣體環境中。較佳 性氣體環境巾’最好在例如氮氣、氬氣環境巾實施。另外, 燒結後進行冷卻時的環境亦是最好設定為上述環境,但是 亦可未必如此。 上述燒結步驟中,當施行上述(1)之方法時,經燒结 的冷卻條件係可任意選擇。另—方面,當施行上述&之 方法時,冷卻速度△价加)係依照燒結時間t的長 決定。例如當燒結時間U !小時的情況,冷卻速产又 便設為25xl=25°C/hr以上,當燒結時間t為4小時又 ❹況,冷卻速度ΔΤ便設為25x4=10(rc/hr以上。即,♦二 結時間t增長的情況’便配合燒結時間,加速冷卻速^ T。該方法係在燒結時間t增長的情況為有效,但二 • 燒結時間t較短(例如未滿4小時)仍可適用。 疋In the middle of the step, the calcination temperature is 70 (TC in the step of preparing (BiNa) Ti〇3 calcined powder ~ 950 ° C; the calcined powder is mixed in the Ba (TiM) 〇 3 calcined powder and (BiNa) Ti 〇 3 step Let the 'mixed system be dry-type; in the step of preparing the calcined powder of Ba(TiM)〇3 calcined powder, or in two steps, or prepare (BiNa)Ti〇3烺 before calcination, add Si oxide 97104571 200935460 3. 0 mol% or less, Ca carbonate or Ca oxide 4. 0 mol% or less; in the step of mixing Ba(TiM)〇3 calcined powder with (BiNa)Ti〇3 calcined powder, Addition of Si oxide of 3.0% or less, Ca carbonate or Ca oxide of 4.0% by mole or less; at least one of the semiconductor elements lanthanides Nb and Sb, and the composition of the semiconductor porcelain composition is dependent on [ (Order) 5^1_3[][141_1]〇3 indicates that the 7 series satisfies 0 <x$ 〇. 3, 〇<y$〇. 〇〇5 ; and the ratio of Bi to Na in the composition The semiconductor porcelain composition of the present invention is a Ba (TiM) 〇3 calcined powder (M-based semiconductor element, and is Nb, Sb). At least one) and (BiNa a semiconductor ceramic composition obtained by forming and sintering a mixed calcined powder of Ti〇3 calcined powder, wherein the composition formula is [(BiNa)xBai χ] [Tii means 'x, y satisfies 0 < x^〇.3, 0<y^ 0.005, the ratio of Bi to Na satisfies the relationship of Bi/Na=0.78~1. (Effect of the invention) 〇 According to the present invention, Pb which does not cause environmental pollution can be provided, and Curie can be provided. According to the present invention, the temperature rises and the electrical resistivity at room temperature is greatly reduced. - The cow can provide a Bi-voke condition capable of suppressing the calcination step + to prevent the compositional deviation of Bi-Na. The difference of Na: = is 'and can make the resistivity at room temperature more lower' and can inhibit the variation of the state of the semiconductor ceramic composition. 'Dishes】In the present invention, the Ba(TiM) Q3 gun is prepared. Burning powder (M-based semiconductor element) 97104571 8 200935460 The first step is to mix the main raw material, 3, Ti〇2, with the semiconductor element Nb2〇5 or Sb2〇3 to form a mixed raw material powder. Execution. Calcination. The calcination temperature is preferably set at _. (b) 3 Saki range The calcination time is preferably set to 0.5 hours or more. If the calcination temperature is not fully satisfied, C or - calcination time is less than 0.5 hours, and it cannot be completely formed as _3, which is not reversed and should be mixed with the environment and the medium. The moisture produces a reaction that leads to a component deviation and is therefore best avoided. Further, since the temperature of the calcination is over 1300 Torr, a sintered body is formed in the sinter-burning powder, which hinders the solid solution between the (BiNa)Ti〇3 calcined powder which is mixed with the sinter, and thus is preferably avoided. In the present invention, a step of preparing (BlNa) Ti〇3 calcined powder is carried out by first mixing Na2C〇3, Bi2〇3, and Ti〇2 of the raw material powder to prepare a mixed raw material powder, and performing calcination. The calcination temperature is preferably set at 7 〇 (rc~95 (rCi circumference), and the firing time is preferably set at 0.5 hour to 1 hour. If the calcination temperature is less than 7 〇〇C or the calcination time is less than 〇·5 hours The unreacted Ν& 〇 will react with the moisture of the environment or the solvent in the wet mixing, resulting in composition enthalpy deviation, characteristic variation, etc., and thus preferably avoided. In addition, if the calcination temperature exceeds 9501: or calcination time If it exceeds 1 hour, it will promote Bi volatilization, cause composition deviation, and promote heterogeneous formation, so it is best to avoid it. In addition, the preferred calcination temperature in the step of preparing the above Ba(TiM)〇3 calcined powder (900.〇1300) 〇, and the preferred calcination temperature in the step of preparing (BiNa) Ti〇3 satin powder (7〇〇t~950. 〇, preferably in combination with the use, etc., the optimum temperature is appropriately selected. For example (β i Na The calcination temperature of T i 〇 3 is preferably carried out at a lower temperature in order to sufficiently carry out the reaction while suppressing the dispersion of Bi, and the calcination temperature of (BiNa)Ti〇3 is further reduced to 97104571. 9 200935460 degrees is best set to The calcination temperature of Ba(TiM)〇3. The steps of preparing Ba(TiM)〇3 and preparing the (BiNa)Ti〇3 calcined powder, respectively, are the main features of the present invention, whereby Bi θ of (BiNa)Ti〇3 in the satin burning step is prevented—Bi-Na composition is prevented from deviating 俾, and heterogeneous phase generation is suppressed, and the resistivity of the temperature of the medium is further reduced and the semiconductor ceramic composition is suppressed from changing in the Curie temperature. In the step of preparing the calcined powder, the raw material powder may be mixed, and the powder may be pulverized in accordance with the particle size of the raw material powder. In addition, the mixing and pulverizing may be carried out by wet mixing, pulverization or blending using pure water or ethanol. In any of the methods such as pulverization, it is preferable to carry out dry mixing and pulverization to further prevent composition variation. In the above, BaC〇3, NaAOs, Ti (h, etc.) are exemplified as the raw material powder, but other Ba compounds are used. The compound or the like does not impair the effects of the present invention. As described above, after preparing Ba(TiM)〇3烺-burning powder and (BiNa)Ti〇3 satin-fired powder separately, each satin-fired powder is prepared and quantified. Mixing It can adopt wet mixing or dry mixing using pure water or ethanol; the method 'prefers to dry mixing, because it can prevent the composition deviation. In addition, it can also be combined with the particle size of the smoldering powder. The pulverization or the simultaneous mixing and pulverization is carried out. The average particle size of the mixed calcined powder after mixing and pulverization is preferably from 0.6/zm to 1.5/zin. The above steps and/or preparation for preparing Ba(TiM) 〇3 calcined powder ( In the step of calcining the B'TiG3 powder or the step of mixing the calcined powders, if the Si oxide is 3.0 mol% or less, and the oxide or the carbonate is 4.0% by mass or less, the Si oxide suppresses the crystal grains. The abnormality is 97104571 200935460 long, and the resistivity can be easily controlled, and the CaA compound or the c acid salt can improve the sinterability at a low temperature and can control the reducing property, which is a preferable condition. If any of the above-mentioned limited amounts is added, the composition cannot be semiconductorized, and thus it is preferable to avoid it. The addition is preferably carried out before mixing in each step. The mixed calcined powder obtained by the step of mixing Ba(TiM)〇3 calcined powder with (BiNa)Ti〇3 calcined powder is shaped and sintered. You can get: ❹ Invented semiconductor porcelain composition. An example of a preferred step after the calcining powder mixing step is exemplified below, but it is not limited thereto, and any known method can be employed. The mixed calcined powder obtained by the step of mixing Ba(TiM)〇3 satin powder and (BiNa)Ti〇3烺 powder is formed by a desired forming means. Before the forming, the pulverized powder may be granulated by a granulator as needed. The density of the formed body after molding is preferably 2 to 3 g/cm3. The sintering system can be in the atmosphere or in a reducing environment, or in an inert gas atmosphere of low oxygen concentration, and at a sintering temperature of 1200 ° C to 1400. (: The sintering time is carried out under conditions of 2 hours to 6 hours, and 'the sintering step shown below is also a preferred example. In addition, when granulation is performed before forming, it is preferable to use 3 0 before sintering. Debonding treatment is carried out at 0 °C to 7 0 °C. - The sintering step is carried out at a temperature of 1290 ° C to 135 (TC, oxygen concentration less than 1% in the environment, (1) sintering time less than 4 hours Implementation, or (2) according to the satisfaction formula: Δ T2 25t (t = sintering time (hr), Δ T = cooling rate after sintering (°C / hr)) sintering time, followed by cooling according to the above formula Speed is performed after sintering. 97104571 200935460 Any of the above sintering steps, that is, shortening the sintering time or prolonging the sintering = quenching by the appropriate quenching speed according to the sintering time, can be performed by using BaTiCh-based materials, In the atmosphere where heat is applied, etc., the semiconductor material composition that maintains a low room temperature specific resistance and raises the temperature coefficient of resistance in a high temperature region (above the Curie temperature) is used in the above sintering step. The so-called "oxygen concentration is not full U ring t" means a vacuum or an inert gas atmosphere in which the oxygen concentration is less than U. The preferred gas environment towel is preferably carried out, for example, in a nitrogen or argon atmosphere. In addition, the environment after cooling is also the most In the above sintering step, when the method of the above (1) is carried out, the sintering conditions for sintering can be arbitrarily selected. On the other hand, when the method of the above & The cooling rate Δ valence is determined according to the length of the sintering time t. For example, when the sintering time is U hr, the cooling rate is set to 25xl=25°C/hr or more, and when the sintering time t is 4 hours, In other cases, the cooling rate ΔΤ is set to 25x4=10 (rc/hr or more. That is, ♦ the case where the two junction time t increases) is matched with the sintering time, and the cooling rate is accelerated. This method is the case where the sintering time t increases. Effective, but two • Sintering time t is short (for example, less than 4 hours) is still applicable.

-本發明中作為對象的半導體究器組成物係將B 部分Ba利用BtNa進行取代,如上述,分備 ㈣則瓜锻燒粉(M係半導體化元幻的步驟丁 = (BiNa)Ti〇3煅燒粉的步驟,並將該等進 ' 心1 丁屁合,®娘士、 形、燒結便可獲得。 丹,、工成 97104571 12 200935460 將部分BaTi(h利用Bi-Na進行取代的組成物,係藉由添 加半導體化元素並施行原子價控制,而成為半導體曼器組 成物。本發明中’半導體化元素係添加於BaT i 〇3中,而成 為Ba(TiM)〇3烺燒粉(M係半導體化元素),所獲得半導體 竟器組成物的組成式係依[(BiNa)xBai-x] [Tii-yMy ]〇3表示, 且 X、y 滿足 0<xS0.3、〇<y$〇.〇〇5。 [(BiNa)xBai-x][Tii-yMy]〇3 組成物中,x 係指(BiNa)的成 分範圍,0<χ$0·3係較佳範圍。若χ為〇,則無法將居 里溫度朝高溫側偏移,反之,若超過0 3,則室溫的電阻 率會接近104Ωαη’較難應用於PTC加熱器等’因而最好 避免。 再者’ Μ係Nb、Sb中之至少 具宁最好為Nb ^式中,y係指Μ的成分範圍,0<yg〇 〇〇5係較佳範圍。 右y為0’便無法進行原子價控制,組成物無法半導體化, ❹ 反之,若超過0.005,則室溫的電阻率超過1〇3〇cm,因 而最好避免。另外,上述G<⑻篇依莫耳%表示係為 0 0.5莫耳%(未含〇)。 上述[(BiNahBahHTn-yMy;^組成物的情況,為執行原 子價控制’係將Ti利用M元素進行取代,但是此情況下, π素的添加(添加量G<y錢⑽5)係以4價元素的^位 之原子價控制為目的,因而且古可分.„ 劍,具有依少量進行原子價控 並可減輕所獲得半導體莞器組成物的内應變等優點。 為 t,rLNl)xBai_x][Ti,_爲]03 組成物中,Bi * Na 係設 為ι:ι,即組成式最好成為[(Bi〇5Na〇5)』ai x][TiiyMy]〇3。 97104571 13 200935460 ===中亦有記載般,若將構成組成物的所有元 散導致二-心=T燒步驟中,發生Bi揮 -令的… 而促進異相生成,導致室 ’皿’的電率上升,引發居里溫度變動的問題。 ❹ 制居里溫产二 溫中的電阻率,並可抑 X變動。右Bi/Na超過1,則對(BiNa)Ti〇3生 作用的Bi會殘留於材射,導致在燒結時容易生 成異相,造成室溫中的電阻率上升,反之, 則燒結階段中容易生成異相,造成室溫中的電阻率上:, 因而最好避免。 依照上述奥;iL古、、土 ^ . 义表&方法,可獲得組成式依 [(BiNaXJBahnTibMy^w 係 Nb、Sb 中之至少一種)表 ❹ 示,而 X、y 滿足 〇<U〇.3、〇<0〇 〇〇5,且 Bi 與 Μ 的比滿足Bi/Na=0.78〜l之關係的半導體莞器組成物,該 等半導體竟器、组成物係具有在未使用會造成環境污㈣- The composition of the semiconductor device to be used in the present invention is to replace B part B with BtNa, as described above, and to divide (4) the melon forging powder (the step of M-system semiconductorization phantom = (BiNa) Ti〇3 The step of calcining the powder, and the same as the 'heart 1 butt, the maiden, shape, and sintering can be obtained. Dan,, Gongcheng 97104571 12 200935460 Partial BaTi (h composition substituted with Bi-Na) By adding a semiconductor element and performing valence control, it becomes a semiconductor device composition. In the present invention, a 'semiconductor element is added to BaT i 〇 3 to become Ba(TiM) 〇3 烺 burnt powder ( M system semiconductor element), the composition formula of the semiconductor semiconductor composition obtained is expressed by [(BiNa)xBai-x] [Tii-yMy ] 〇3, and X, y satisfies 0 < xS0.3, 〇 < Y$〇.〇〇5. [(BiNa)xBai-x][Tii-yMy]〇3 In the composition, x is the range of the composition of (BiNa), and 00<χ$0·3 is the preferred range. For 〇, the Curie temperature cannot be shifted toward the high temperature side. On the other hand, if it exceeds 0 3, the room temperature resistivity will be close to 104 Ωαη, which is difficult to apply to PTC heaters, etc. Therefore, it is best to avoid. In addition, at least N of Nb and Sb are preferably Nb ^, where y is the range of ingredients, and 0 yg 〇〇〇 5 is preferred. Right y is 0. 'The valence control cannot be performed, and the composition cannot be semiconductorized. 反之 On the other hand, if it exceeds 0.005, the room temperature resistivity exceeds 1〇3〇cm, so it is best to avoid it. In addition, the above G<(8) Emol%% The expression is 0 0.5 mol% (excluding 〇). The above [(BiNahBahHTn-yMy;^ composition, in order to perform valence control] is to replace Ti with M element, but in this case, π The addition (addition amount G < y money (10) 5) is for the purpose of controlling the atomic price of the tetravalent element, and it can be divided into several parts. The sword has a small amount of atomic price control and can reduce the composition of the obtained semiconductor valve. The internal strain of the object is such that the composition of t, rLNl)xBai_x][Ti,_ is ]03, Bi * Na is set to ι:ι, that is, the composition formula is preferably [(Bi〇5Na〇5)" Ai x][TiiyMy]〇3. 97104571 13 200935460 === It is also recorded that if all the elements constituting the composition are scattered, the two-heart = T burnt step In the case of Bi-swings, it promotes the generation of heterogeneous phases, which leads to an increase in the electric rate of the chamber's dish, which causes a problem of fluctuations in the Curie temperature. ❹ Resistivity in the second temperature of the Curie temperature, and can suppress X changes. When the right Bi/Na exceeds 1, Bi which acts on (BiNa)Ti〇3 will remain in the material, which causes a heterogeneous phase to be easily formed during sintering, resulting in an increase in resistivity at room temperature, and conversely, it is easy in the sintering stage. Heterogeneous is generated, resulting in a resistivity at room temperature: and thus is best avoided. According to the above-mentioned Austrian; iL ancient, soil ^. table & method, the composition formula can be obtained according to [(BiNaXJBahnTibMy^w is at least one of Nb, Sb), and X, y meets 〇 <U〇 .3, 〇 <0〇〇〇5, and the ratio of Bi to Μ satisfies the relationship of Bi/Na=0.78~l, and the semiconductor device and composition have no effect on unused Environmental pollution (4)

Pb之情況下’能使居里溫度上升,且能使室溫中的電阻 率大幅降低之效果。 [實施例] [實施例1] 準備作為主原料的BaC〇3、Ti〇2以及作為半導體化元素 的Nb2〇s等原料粉末,依成為BaCTio.mNbuWO3之方式進 行調配,並在純水中進行混合。將所獲得的混合原料粉末 97104571 14 200935460 於1000°C下施行4小時煅燒,而準備^(1^仙)〇3煅燒粉。 準備Na2C〇3、Bi2〇3、Ti〇2的原料粉末,依成為 (BiuNao.OTiO3的方式進行調配,並在乙醇中進行混合。 將所獲得的混合原料粉末,於大氣中依6〇〇〇c〜9〇〇。〇施行 -4小時緞燒,獲得(BiNa)Ti〇3煅燒粉。所獲得之 -(Bi°.5Na°.5)Ti〇3煅燒粉在600t〜90(TC中的每個煅燒溫度 之X射線繞射圖案係如圖1所示。 ❹將上述Ba(TiNb)〇3煅燒粉及依80(rc施行煅燒的 (BiNa)Ti〇3煅燒粉,依成為莫耳比73:7的方式進行調配, 進步添加作為燒結助劑的Si〇2(〇.4莫耳%)、CaC〇3(1 4 莫耳/〇,以純水為介質且利用球磨機施行混合、粉碎,直 到混合煅燒粉的中心粒徑成為〇Am為止,然後 施行乾燥。在s亥混合锻燒粉的粉碎粉中添加PVA並經混合 後,再利用造粒裝置施行造粒。將所獲得的造粒粉利用單 軸壓製裝置施行成形,然後將上述成形體依5〇(rc施行脫 ❾黏結劑後,於大氣中,依燒結溫度13〇(rc 〜138{rc施行4 小時燒結,便獲得燒結體。 將所獲得的燒結體加工成1 〇mmx 1 〇mmxl随的板狀,製成 •試驗片,經形成歐姆電極後,將各試驗片利用電阻測定器 -依室溫至270°c之範圍内進行比電阻值的溫度變化測定。 測定結果如表1所示。另外’施行Bi與Na的成分分析, 並求取Bi /Na比。結果如表1所示。另外,表1中的試料 No.5係在準備(BiNa)Ti〇3烺燒粉的步驟中,於大氣中施行 乾式混合的例子’其餘則屬於在乙醇中進行混合的例子。 97104571 15 200935460 此外’試料No.旁的「*」記號係指比較例。 [比較例1 ] 準備作為主原料的BaCCh、T i 〇2 ;作為半導體化元素的 Nb2〇5 ;作為居里溫度偏移劑的Na2C〇3、Bi2〇3、Ti〇2,並將 - 構成組成物的所有元素在最初便進行調配,添加作為燒結 •助劑的Si〇2(0.9莫耳%)、CaC〇3(1.9莫耳%),再於乙醇中 進行混合。將所獲得的混合原料粉末在大氣中依2〇〇 ❹〜1200 °C施行4小時煅燒,獲得煅燒粉。所獲得之 [(81。.也。.5)』8卜31][1^卜1]〇3(叉=0.06,7 = 0.005)烺燒粉, 在200X:〜90(TC中的每個烺燒溫度之X射線繞射圖案係如 圖2所示。 在依1 0 0 0 C施行锻燒的锻燒粉中添加pva,經混合後, 再利用造粒裝置施行造粒。將所獲得造粒粉利用單軸壓製 裝置施行成形,並將上述成形體依5〇〇〇c施行脫黏結劑 後,於大氣中依燒結溫度丨32〇t施行4小時燒結,獲得 燒結體。 將所獲知的燒結體加工成1 〇mmxl 〇mmxlmin的板狀,製成 試驗片’經形成歐姆電極後,將各試驗片利用電阻測定器 依至溫至2 7 0 C之範圍内進行比電阻值的溫度變化測定。 /則定結果如表1中的試料N〇. 6所示。另外,施行βi與In the case of Pb, the Curie temperature can be increased and the electrical resistivity at room temperature can be greatly reduced. [Examples] [Example 1] Raw material powders such as BaC〇3 and Ti〇2 as main raw materials and Nb2〇s as a semiconductor element were prepared and formulated in the form of BaCTio.mNbuWO3, and were carried out in pure water. mixing. The obtained mixed raw material powder 97104571 14 200935460 was calcined at 1000 ° C for 4 hours to prepare a calcined powder of 〇 3 . The raw material powders of Na2C〇3, Bi2〇3, and Ti〇2 are prepared, and are mixed in the form of (BiuNao.OTiO3) and mixed in ethanol. The obtained mixed raw material powder is immersed in the atmosphere. c~9〇〇.〇4 hours of satin burning to obtain (BiNa)Ti〇3 calcined powder. The obtained (Bi°.5Na°.5) Ti〇3 calcined powder in 600t~90 (TC The X-ray diffraction pattern of each calcination temperature is as shown in Fig. 1. The Ba(TiNb)〇3 calcined powder and the calcined (BiNa) Ti〇3 calcined powder according to 80 (rc) are used as the molar ratio. In the way of 73:7, it is possible to add Si〇2 (〇.4 mol%) and CaC〇3 (1 4 mol/〇) as a sintering aid, and mix and pulverize with a ball mill using pure water as a medium. Until the center particle diameter of the mixed calcined powder is 〇Am, and then dried. PVA is added to the pulverized powder of the shai mixed calcined powder and mixed, and then granulated by a granulator. The granules are formed by a uniaxial pressing device, and then the above-mentioned formed body is subjected to a bismuth (the rc is subjected to a debonding adhesive agent in the atmosphere, depending on the sintering temperature 13 〇 (rc ~ 138{rc) is sintered for 4 hours to obtain a sintered body. The obtained sintered body is processed into a plate shape of 1 〇mmx 1 〇mmxl to prepare a test piece, and after forming an ohmic electrode, each will be formed. The test piece was measured by a resistance measuring device - the temperature change of the specific resistance value was performed in the range of room temperature to 270 ° C. The measurement results are shown in Table 1. In addition, the composition analysis of Bi and Na was performed, and Bi / Na was determined. The results are shown in Table 1. In addition, sample No. 5 in Table 1 is an example in which dry mixing is carried out in the atmosphere in the step of preparing (BiNa)Ti〇3烺-fired powder, and the rest belongs to ethanol. Example of mixing. 97104571 15 200935460 In addition, the "*" mark next to the sample No. refers to a comparative example. [Comparative Example 1] BaCCh and T i 〇2 as main raw materials; Nb2〇5 as a semiconductor element; As a Curie temperature shifting agent, Na2C〇3, Bi2〇3, Ti〇2, and all the elements constituting the composition were initially formulated, and Si〇2 (0.9 mol%) as a sintering aid was added. ), CaC〇3 (1.9 mol%), and then mixed in ethanol. The raw material powder is calcined in the atmosphere at 2 to 1200 ° C for 4 hours to obtain a calcined powder. The obtained [(81.. also .5)" 8b 31][1^卜1]〇3 ( Fork = 0.06, 7 = 0.005) 烺 粉 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Pva was added to the calcined powder, and after mixing, granulation was carried out by means of a granulation apparatus. The obtained granulated powder was molded by a uniaxial pressing apparatus, and the above-mentioned formed body was subjected to debonding agent according to 5 〇〇〇c, and then sintered in the atmosphere at a sintering temperature of 〇32 〇t for 4 hours to obtain a sintered body. The obtained sintered body is processed into a plate shape of 1 〇mmxl 〇mmxlmin to prepare a test piece. After forming an ohmic electrode, each test piece is subjected to a specific resistance by using a resistance measuring device to a temperature of 270 C. The temperature change of the value is determined. / The results are shown in Table 1 in the sample N〇. In addition, the implementation of βi and

Na的成分分析,並求取Bi/Na比。結果如表j的試料N〇. 6 所示。 由圖1與圖2中得知,實施例1的(BiNa)Ti〇3煅燒粉係 在70(TC時完全成為單相。另一方面,比較例丨中係將構 97104571 16 200935460 成組成物的所有元素在最初便進行調配,此情況,若未達 900 c以上則無法m容,可知無法充分成為锻燒粉。 再者,由表i中得知,實施例的本發明半導體莞器組成 係可使居里溫度上升,且能使室溫中的電阻率大幅降 / 卜藉由刀別執行準備Ba(TiNb)〇3锻燒粉的步驟與 •準備(B_i〇3锻燒粉的步驟,可抑制Bi揮散,即使經 燒結後,仍具有高的Bi/Natb,故可抑制異相之生成,可 ❹更加降低至溫中的電阻率,並能抑制居里溫度之變動。 相對於此’比較例的半導體瓷器組成物雖可達成居里溫 又之上升但疋電阻溫度係數低。且,在煅燒步驟、燒結 步驟中,因為有大量的Bi揮散,故燒結後的Bi/Na比係 在0. 77以下。 另外,所有實施例中,電阻溫度係數係依下式進行求取。 TCR=(InRi-InRc)xl〇〇/(T1-T〇) R1係最大比電阻,R r T ~1 I .T- 电I Kc保1C下的比電阻,Τι係表示Ri的溫度, ❾Tc係居里溫度。The composition of Na was analyzed and the ratio of Bi/Na was determined. The results are shown in the sample N〇. 6 of Table j. 1 and 2, the (BiNa)Ti〇3 calcined powder of Example 1 completely became a single phase at 70 (TC). On the other hand, in the comparative example, the structure was 97104571 16 200935460. All of the elements are initially formulated. In this case, if it is less than 900 c or more, it is impossible to obtain a calcined powder. Further, as seen from Table i, the semiconductor valve of the present invention of the embodiment is composed. The Curie temperature can be raised, and the resistivity at room temperature can be greatly reduced. Steps and preparation for preparing Ba(TiNb)〇3 calcined powder by means of a knife (B_i〇3 calcined powder step) It can suppress Bi volatilization and has a high Bi/Natb even after sintering, so that generation of heterophase can be suppressed, and the resistivity to the temperature can be further lowered, and the variation of the Curie temperature can be suppressed. The semiconductor porcelain composition of the comparative example can achieve a rise in Curie temperature but a low temperature coefficient of yttrium resistance. Moreover, in the calcination step and the sintering step, since a large amount of Bi is volatilized, the Bi/Na ratio after sintering is 0. 77 or less. In addition, in all of the examples, the temperature coefficient of resistance Calculate according to the following formula: TCR=(InRi-InRc)xl〇〇/(T1-T〇) R1 is the maximum specific resistance, R r T ~1 I .T- Electric I Kc is the specific resistance under 1C, Τι It is the temperature of Ri, and the temperature of ❾Tc is the Curie temperature.

Bi/Na 比 -iiL) ι〇30 (Ω cm) Tc (°C) 電阻溫度係數 (%/°〇 199 138 149 22. 6 84 158 19. 9 _i94__ 72 155 19. 5 -Λ91_ 96 161 17.8 -Α97_ 81 157 20. 3 73 160 16. 9 [表1 ]Bi/Na ratio -iiL) ι〇30 (Ω cm) Tc (°C) Temperature coefficient of resistance (%/°〇199 138 149 22. 6 84 158 19. 9 _i94__ 72 155 19. 5 -Λ91_ 96 161 17.8 - Α97_ 81 157 20. 3 73 160 16. 9 [Table 1]

;十诚令照砰細的特定實施例進行說明,作 在不脫逸本發明精神與範_之前提下,可進行各種變化輿 97104571 17 200935460 修正’此係熟習此技術者均可明白。 本申請案係以2006年11月1日申請的日本專利申請案 (特願2006-298304)為基礎,參照其内容並爰引於本案中^ (產業上之可利用性) 依本發明所獲得的半導體瓷器組成物係適用為pTC熱 阻器、PTC加熱器、PTC開關、溫度檢測器等的材料。 【圖式簡單說明】 圖1為本發明的半導體瓷器組成物依每個煅燒溫度的X 射線繞射圖案圖。 圖2為比較例的半導體瓷器組成物依每個煅燒溫度的χ 射線繞射圖案圖。 97104571The descriptions of the specific embodiments are described in detail, and various changes can be made without departing from the spirit and scope of the present invention. 97104571 17 200935460 The amendments can be understood by those skilled in the art. This application is based on the Japanese Patent Application (Japanese Patent Application No. 2006-298304) filed on Nov. 1, 2006, the content of which is hereby incorporated by reference in The semiconductor porcelain composition is suitable for materials such as pTC thermistors, PTC heaters, PTC switches, temperature detectors, and the like. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an X-ray diffraction pattern of a semiconductor ceramic composition of the present invention at each calcination temperature. Fig. 2 is a ray diffraction pattern of the semiconductor ceramic composition of the comparative example at each calcination temperature. 97104571

Claims (1)

200935460 十、申請專利範圍: 1 · 一種半導體瓷器組成物之製造方法,係用以製造將 BaTi〇3的部分Ba利用Bi_Na進行取代的半導體瓷器組成 物者,其特徵為包括有:準備Ba(TiM)〇3煅燒粉(M係半導 ,體化元素)的步驟;準備(BiNa)Ti(h煅燒粉的步驟;將 .Ba(TiM)〇3煅燒粉與(BiNa)Ti〇3煅燒粉混合的步驟;以及 將混合烺燒粉予以成形、燒結的步驟。 ❹2.如申請專利範圍第1項之半導體瓷器組成物之製造 方法,其中,在準備Ba(TiM)〇3烺燒粉的步驟中,緞燒溫 度係 900°C 〜1300°C。 3. 如申請專利範圍第1項之半導體瓷器組成物之製造 方法,其中,在準備(BiNa)Ti〇3煅燒粉的步驟中,锻燒溫 度係 700°C 〜950°C。 4. 如申請專利範圍第1項之半導體瓷器組成物之製造 方法,其中,在將Ba(TiM)〇3鍛燒粉與(BiNa)Ti〇3锻燒粉 ❹混合的步驟中,混合係依乾式實施。 5. 如申請專利範圍第1項之半導體瓷器組成物之製造 方法’其中’在準備Ba(TiM)〇3锻燒粉的步驟、或準備 1 (BiNa)Ti〇3緞燒粉的步驟、或該二項步驟中,於锻燒前係 添加Si乳化物3.0莫耳%以下、Ca碳酸鹽或Ca氧化物4 0 莫耳%以下。 6. 如申請專利範圍第1項之半導體瓷器組成物之製造 方法,其中,在將Ba(TiM)〇3煅燒粉與(BiNa)Ti〇3烺燒粉 混合的步驟中’係添加Si氧化物3.0莫耳%以下、Ca破 97104571 200935460 酸鹽或Ca氡化物4. 〇莫耳%以下。 7.如申請專利範圍第1項之半導體瓷器組成物之製造 方法’其中’半導體化元素Μ係Nb、Sb中之至少一種, 半導體瓷器組成物的組成式係依[(BiNa)xBai-x] [Tii-yMy]〇3 表示,x、y 係滿足 〇< 〇. 3、〇< 〇. 〇〇5。 8_如申請專利範圍第7項之半導體瓷器組成物之製造 方法,其中,Bi與Na的比係滿足Bi/Na=〇. 78〜丨的關係。 9· 一種半導體瓷器組成物 ❹ -…你將仙UiM)〇3煅燒粉(M係 半導體化元素,且為Nb、Sb中之至少一種)與(_Ti〇3 煅燒粉的混合煅燒粉進行成形、燒結而成的半導體瓷器組 成物,組成式係依[(BiNa)xBai_x][Til_yMy]〇3表示,X、y滿 足 〇<x^0.3、0<y$ 0.005,Bi 與 Ν& 的比係滿足 Bi/Na=0.78〜1的關係。200935460 X. Patent application scope: 1 . A method for manufacturing a semiconductor porcelain composition, which is used for manufacturing a semiconductor porcelain composition in which a part of Ba of BaTi〇3 is replaced by Bi_Na, and is characterized by comprising: preparing Ba (TiM) 〇3 calcined powder (M system semiconducting, body element) step; preparation of (BiNa)Ti (h calcined powder step; mixing .Ba(TiM)〇3 calcined powder with (BiNa)Ti〇3 calcined powder And a step of forming and sintering the mixed calcined powder. The method for producing a semiconductor ceramic composition according to claim 1, wherein in the step of preparing Ba(TiM)〇3烺 calcined powder The satin-sintering temperature is 900 ° C to 1300 ° C. 3. The method for producing a semiconductor ceramic composition according to claim 1, wherein the calcining temperature is in the step of preparing (BiNa)Ti〇3 calcined powder 700 ° C ~ 950 ° C. 4. The method for manufacturing a semiconductor porcelain composition according to claim 1, wherein the Ba (TiM) 〇 3 calcined powder and the (BiNa) Ti 〇 3 calcined powder In the mixing step, the mixing system is implemented in a dry manner. The method for producing a semiconductor ceramic composition according to item 1 of the first aspect, wherein the step of preparing Ba(TiM)〇3 calcined powder, or the step of preparing 1 (BiNa)Ti〇3 satin powder, or the two steps In the method of manufacturing a semiconductor ceramic composition according to claim 1, wherein the Si emulsion is 3.0 mol% or less, and the Ca carbonate or the Ca oxide is 40% or less. In the step of mixing Ba (TiM) 〇 3 calcined powder with (BiNa) Ti 〇 3 烺 烺 powder, 'addition of Si oxide 3.0 mol% or less, Ca broken 97104571 200935460 acid salt or Ca 氡 4 4. 〇 The molar composition is less than or equal to 7. The manufacturing method of the semiconductor ceramic composition of the first aspect of the patent application, wherein at least one of the semiconductor elements lanthanides Nb and Sb, the composition of the semiconductor porcelain composition is [[BiNa] )xBai-x] [Tii-yMy]〇3 means that x and y are satisfied by 〇< 〇. 3, 〇< 〇. 〇〇5. 8_The semiconductor ceramic composition of claim 7 The manufacturing method, wherein the ratio of Bi to Na satisfies the relationship of Bi/Na=〇.78~丨. 9. A semiconductor porcelain Composition ❹ -...You will be a semiconductor made of sinter calcined powder (M-based semiconductor element and at least one of Nb and Sb) and (_Ti〇3 calcined powder mixed calcined powder for forming and sintering) The composition of the porcelain is composed of [(BiNa)xBai_x][Til_yMy]〇3, X and y satisfy 〇<x^0.3, 0 <y$ 0.005, and the ratio of Bi to Ν& satisfies Bi/Na= The relationship of 0.78~1. 97104571 2097104571 20
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