200929867 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種電位移轉電路(Level Shift arcuit)， 特別是指一種能以較少的元件來將正供應電壓轉為負供應 電壓的電位移轉電路’以及相關聯的方法。 【先前技術】 電位移轉電路為電子電路中所經常使用到的電路，其 目的在於提供電子訊號之位準轉換。當必須將工作電壓的 高低位準自VDD/0V轉換為0V/-VDD時，先前技術作法都 必須使用相當多的元件才能達成。例如請參閱第丨圖之先 前技術，此種作法是先將高/低位準由YQD/0V轉換成 1/2 VDD/0V，再轉換成 1/2 VDD/-1/2 VDD，再轉換成 0V/-1/2 VDD，再轉換成0V/—VDD。顯然此種作法不論 是能量運用效率、轉換速度、元件數目等都並不經濟。在 某些設計中將五級轉換改為三級轉換，省略了第丨圖中轉 換至1/2 VDD/0V與〇V/_i/2 VDD的步驟，但仍然不夠 理想。 第2圖示出先前技術的另一種作法，此電路雖然在轉 換速度上比第1圖理想，但所使用的元件數目仍然报高， 仍然不夠經濟。 有鑑於上述先前技術之缺點’本發明乃提出一種較佳 之電位移轉電路以及相關方法，以大幅降低元件數目，並 提高電路輸出的變換速度。 5 200929867 【發明内容】 ▲本發明之第-目的在提供—種電位移轉電路，其中使 用U數目的7〇件，來達紅貞供應電壓的減位準轉換。 本發明之第二目的在提供—種對應的方法。 β為達上述之目的，就在本發明的其中一個觀點而言， 提供了種電位移轉電路，包含：一個輸入級驅動電路； 個電谷’其第一端電連接於該輸入級驅動電路之輸出 端；一個輸出級驅動電路，電連接於該電容之第二端；以 及個反饋栓鎖電路’電連接於該輸出級驅動電路之輸出 端與該電容第二端之間’以轉該電容第二端的電壓位準。 上述電路中之反饋拴鎖電路可為全拴鎖電路（fUU latch)或半拴鎖電路（halflaich)。 此外，根據本發明的另一個觀點，也提供了一種電位 移轉方法，包含：提供一輸入訊號，此輸入訊號在第一工 作高/低電壓間變換；提供—電容，並在該電容上產生一 跨壓；根據該跨壓，驅動一輸出電路產生輸出訊號，此輸 出訊號對應於輸入訊號而在第二工作高/低電壓間變換； 以及根據該輸出訊號而反饋控制電容一端的電位。 底下藉由具體實施例詳加說明，當更容易瞭解本發明 之目的、技術内容、特點及其所達成之功效。 【實施方式】 請參考第3圖’首先以示意電路圖的方式說明本發明 的概念。如圖所示’本發明的作法是提供一個工作高/低 6 200929867 位準為VDD/0V的輸入級驅動電路10，其輸出與電容15 連接，利用該電容15來儲存電位差；此外並提供一個輸出 級電路20，與電容15連接，此電路2〇中包含一個工作高 /低位準為〇V /-VDD的輸出級驅動電路24，以及一個 反饋栓鎖電路22’利用該反饋栓鎖電路22將輸出級驅動電 路24的輸入節點a保持在正確的位準。 上述電路概念可有多種具體實施型態，舉一例如第4 圖’在本實施例的電位移轉電路中，係由pM〇s電晶體MU 與NMOS電晶體M12構成輸入級驅動電路1〇，並由pM〇s 電晶體M2卜M22與NM0S電晶體M23、腿構成輸出 級電路20。PMOS電晶體M22與NMOS電晶體M24構成 輸出級驅動電路24，PMOS電晶體M21與NMOS；電晶體 =3則構成反饋栓鎖電路22，其為全拾鎖電路（触他也， 思即^輸㈣訊齡何鱗的情況下都進行反饋拾鎖）。 詳《之，藉由從輸出端OUT反饋控制電晶體M2i與 M23的閘極’可確保節點A在正確的位準；當輸出為高位 f (〇V)時，節點A為低位準（.娜），*當輸出為低位 準（-VDD)時，節點A為高位準㈣。確保節點A在正 準，其侧是轉電容15兩端的跨壓，使訊號不致 隨時間而失準。 〜第4圖實施例的操作情形，請參考第5圖與第6圖。 假設VDD為5V，當整體電位移轉電路的輸入為〇 PMOS =晶體M11導通、應〇8電晶體觀關閉，故電容 I5左端祕B的電縣sv，右端節點A的初始電壓為〇v， 7 200929867 因此電容15上產生了 5V的跨壓。因節點A為〇v，因此 NMOS電晶體M24導通、PM〇s電晶體M22關閉，使輸出 端電壓為-5V。此外，自輸出端反饋控制電晶體與M23 的閘極，將節點A保持在0V，故如圖中箭號所示，自 VDD(5V)-M11—B—電容 15—A—M21—_ 構成一個 對電容15充電的迴路，使電容15的跨壓維持為5V。 另-方面’當整體電位移轉電路的輸人為5V時，pM〇s 電晶體Mil關閉、NMOS電晶體M12導通，故電容15左 端節點B的電壓為GV ’因電容之跨壓，使右端節點a的電 壓成為-5V ’而使PMOS電晶體]導通、麵〇8電晶體 M24關閉，於是輸出端電壓成為，自輸出端反饋控制電 晶體M21與M23的閘極，將節點A保持在_5V，故如圖中 箭號所示，自GND —M12 —B —電容15—A_M23_ _VDD(_5V)構成一個對電容15充電的迴路，使電容15的 跨壓維持為5V。 第4圖實施例所示為較保守的作法，事實上反饋检鎖 電路22不必使用全拾鎖電路，可更節省元件請參考第7 圖的第一個實施例，在此實施例中，僅以電晶體⑽構成 之半拴鎖電路(half latch)來作為反饋栓鎖電路22，此電 路僅在輸_為低辦時才反馳卿點A的位準，又例 如第8圖所示的第三個實施例，在此實施射，僅以電晶 體M23構成之半拾鎖電路來作献饋检鎖電路22，此電路 僅在輸出端為高位準時才反饋控制節點A的位準。第7圖 與第8圖實施例，亦為可行之作法。 8 200929867 以上已針對較佳實施例來說明本發明’唯以上所述 者，僅係為使熟悉本技術者易於了解本發明的内容而已， 並非用來限定本㈣之侧額。對於熟悉本技術者，當 可在本發明概念之内，立即思及各種等效變化。例如，^ 饋控制節點A的方式，可使用其他拾鎖電路；又如，本發 明不限於應用在正供應電壓轉負供應電壓等等。故凡依本 舞 鲁 發明之概念與精神所為之均等變化或修飾，均應包括於本 發明之申請專利範圍内。 〜 、 【圖式簡單說明】 圖式說明： 第1圖與第2騎先驗術之正電顯貞 電路的電職。 〈％位移轉 第3圖說明本發明的概念。 第4圖為本發明第一實施例之電位移轉電路的電路圖。 第5圖與第6 ®說明第4 _實施例的操作情形。 第7圖與第8圖示出本發明的另兩實施例。 【主要元件符號說明】 1〇輸入級驅動電路 15電容 20輸出級電路 22反饋栓鎖電路 24輸出級驅動電路 9 200929867 Α,Β節點 GND接地 IN輸入 M11,M12,M21，M22，M23，M24 電晶體 OUT輸出 VDD供應電壓200929867 IX. Description of the Invention: [Technical Field] The present invention relates to a level shifting circuit, and more particularly to an electric power capable of converting a positive supply voltage to a negative supply voltage with fewer components. Displacement to circuit 'and associated methods. [Prior Art] The electric displacement circuit is a circuit which is often used in electronic circuits, and its purpose is to provide level conversion of electronic signals. When it is necessary to convert the high and low levels of the operating voltage from VDD/0V to 0V/-VDD, prior art practices must use quite a few components to achieve. For example, please refer to the prior art of the figure, which is to convert the high/low level from YQD/0V to 1/2 VDD/0V, then convert to 1/2 VDD/-1/2 VDD, and then convert it into 0V/-1/2 VDD, then convert to 0V/-VDD. Obviously, this method is not economical, regardless of energy use efficiency, conversion speed, number of components, and so on. In some designs, the five-level conversion was changed to the third-level conversion, omitting the steps in the figure to convert to 1/2 VDD/0V and 〇V/_i/2 VDD, but it is still not ideal. Fig. 2 shows another practice of the prior art. Although this circuit is more desirable than the first figure in the conversion speed, the number of components used is still high, which is still not economical. In view of the above disadvantages of the prior art, the present invention proposes a preferred electric displacement circuit and related method for drastically reducing the number of components and increasing the conversion speed of the circuit output. 5 200929867 [Disclosed Summary] The first object of the present invention is to provide an electric displacement circuit in which a U number of 7 turns is used to achieve a reduced level conversion of a red 贞 supply voltage. A second object of the present invention is to provide a corresponding method. β is for the above purpose, and in one aspect of the present invention, an electric displacement circuit is provided, comprising: an input stage driving circuit; and a first end electrically connected to the input stage driving circuit An output stage driving circuit electrically connected to the second end of the capacitor; and a feedback latch circuit 'electrically connected between the output end of the output stage driving circuit and the second end of the capacitor The voltage level at the second end of the capacitor. The feedback shackle circuit in the above circuit may be a full-lock circuit (fUU latch) or a half-lock circuit (halflaich). In addition, according to another aspect of the present invention, an electrical displacement method is also provided, comprising: providing an input signal, the input signal is converted between a first operating high/low voltage; providing a capacitance, and generating on the capacitor a voltage across the voltage; driving an output circuit to generate an output signal, the output signal is converted between the second operating high/low voltage corresponding to the input signal; and feedbackting the potential of one end of the control capacitor according to the output signal. The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments. [Embodiment] Referring to Figure 3, the concept of the present invention will first be described in a schematic circuit diagram. As shown in the figure, the present invention provides an input stage driving circuit 10 with a high/low 6 200929867 level of VDD/0V, the output of which is connected to the capacitor 15, and the capacitor 15 is used to store the potential difference; The output stage circuit 20 is connected to a capacitor 15 which includes an output stage drive circuit 24 having a high/low level of 〇V / -VDD, and a feedback latch circuit 22' utilizing the feedback latch circuit 22 The input node a of the output stage drive circuit 24 is maintained at the correct level. The above circuit concept can be implemented in various embodiments. For example, in the electric displacement circuit of the present embodiment, the input stage driving circuit 1 is composed of the pM〇s transistor MU and the NMOS transistor M12. And the output stage circuit 20 is constituted by the pM〇s transistor M2, the M22, and the NM0S transistor M23, and the legs. The PMOS transistor M22 and the NMOS transistor M24 constitute an output stage driving circuit 24, a PMOS transistor M21 and an NMOS; and a transistor=3 constitutes a feedback latch circuit 22, which is a full-stack circuit (touch him, think and lose) (4) In the case of the age of the scale, feedback locks are carried out). In detail, by controlling the gates of the control transistors M2i and M23 from the output terminal OUT, it is ensured that the node A is at the correct level; when the output is the high level f (〇V), the node A is at a low level (. ), * When the output is low (-VDD), node A is high (four). Make sure that node A is on the positive side and that the side is the voltage across the transcapacitor 15 so that the signal does not misalign with time. ~ For the operation of the embodiment of Fig. 4, please refer to Fig. 5 and Fig. 6. Assuming VDD is 5V, when the input of the overall electric displacement circuit is 〇 PMOS = crystal M11 is turned on, and 电 8 transistor is turned off, so the capacitance of the left end of the capacitor I5 is the electric county sv, and the initial voltage of the right end node A is 〇v, 7 200929867 Therefore, a 5V crossover voltage is generated on the capacitor 15. Since the node A is 〇v, the NMOS transistor M24 is turned on, and the PM〇s transistor M22 is turned off, so that the output terminal voltage is -5V. In addition, the output control terminal feedback control transistor and M23 gate, keep node A at 0V, so as shown by the arrow in the figure, from VDD (5V)-M11-B-capacitor 15-A-M21-_ A circuit that charges capacitor 15 maintains the voltage across capacitor 15 at 5V. On the other hand, when the input of the overall electric displacement circuit is 5V, the pM〇s transistor Mil is turned off and the NMOS transistor M12 is turned on, so the voltage at the left end node B of the capacitor 15 is GV 'because of the voltage across the capacitor, the right end node The voltage of a becomes -5V', and the PMOS transistor is turned on, and the surface 电8 transistor M24 is turned off, so that the output terminal voltage becomes, the gate of the control transistors M21 and M23 is fed back from the output terminal, and the node A is kept at _5V. Therefore, as shown by the arrow in the figure, from GND — M12 — B — Capacitor 15-A_M23_ _VDD (_5V) constitutes a loop for charging capacitor 15, so that the voltage across capacitor 15 is maintained at 5V. The embodiment of Figure 4 shows a more conservative approach. In fact, the feedback lockout circuit 22 does not have to use a full pick-up circuit, which saves components. Please refer to the first embodiment of Figure 7, in this embodiment, only The half latch of the transistor (10) is used as the feedback latch circuit 22, and the circuit only reverses the level of the point A when the input_low is low, for example, as shown in FIG. In the third embodiment, the half-lock circuit formed by the transistor M23 is used for the feedback check circuit 22, and the circuit only feeds back the level of the control node A when the output terminal is at a high level. The figures in Figures 7 and 8 are also feasible. 8 200929867 The present invention has been described above with respect to preferred embodiments, and the above description is only for the purpose of facilitating the understanding of the present invention by those skilled in the art, and is not intended to limit the amount of the present invention. For those skilled in the art, various equivalent variations can be immediately considered within the inventive concept. For example, other means of controlling the node A may be used, and as another example, the present invention is not limited to application to a positive supply voltage to a negative supply voltage or the like. Any change or modification of the concept and spirit of the invention in accordance with this dance should be included in the scope of the patent application of the present invention. ~ , [Simple description of the schema] Schematic description: Figure 1 and the 2nd riding a priori positive electric circuit. <% Displacement Turning Fig. 3 illustrates the concept of the present invention. Fig. 4 is a circuit diagram of an electric displacement to circuit of the first embodiment of the present invention. Fig. 5 and Fig. 6 illustrate the operation of the fourth embodiment. Figures 7 and 8 show two further embodiments of the invention. [Main component symbol description] 1〇 input stage drive circuit 15 capacitor 20 output stage circuit 22 feedback latch circuit 24 output stage drive circuit 9 200929867 Α, Β node GND ground IN input M11, M12, M21, M22, M23, M24 Crystal OUT output VDD supply voltage
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