200929532 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種影像感測器。 【先前技術】 一互補式金氧半導體（Complementary Metal Oxide Semiconductor, CMOS )影像感測器可具有形成於一畫素單元中的 一光電二極體及一金氧半導體（Metal Oxide Semiconductor, MOS ) ❿ 電晶體。互補式金氧半導體（CMOS)影像感測器通過切換可順次 偵測各個單元晝素中的電訊號用以產生一影像。 習知技術之互補式金氧半導體（CM0S )影像感測器可具有一 水平配設之光電二極體及電晶體。習知技術之水平配設的互補式 金氧半導體（CMOS )影像感測器可克服電荷結合器 (Charge-Ccmpled Device，CCD )影像感測器之不同的限制。然而， 習知技術的水平互補式金氧半導體（CM〇s )影像感測器依然具有 ❹ 缺點。 舉例而言，習知技術的水平互補式金氧半導體（CMOS)影像 感測器可使用水平位置及相鄰近的光電二極體及電晶體製造。因 此，當需要-光電二極體的額外空間之時，應該減少一填充因子 區，並且可產生對解析度電勢的限制。 此外1賴知技術的水平互補式金氧半導體⑽⑻影像 ’難謂得同時製造光電二極體及電晶體的理想條件。 200929532 、 在1知技術的水平互補式金氧半導體（CMOS、 影像感測器中，當一金去P* π丄 ) 、Α“ 旦素尺寸增加時，可減少影像感測器的解析 度’並且當光電二極體的面積減少時，可減少影像感測器的 度。 【發明内容】 鑒於上述問題，本發明之實施例關於一種影像感測器及1製 造方法’本翻之影像感·及其製造方法可提供_ © 電路及光電二極體。 σ % 本發明之影像感測器及其製造方法能夠提高解析度及靈敏 度。根據本發明之實_，—影··可包含有垂直配設的光 電二極體，並且在光電二極體與電路之間具有改善的物理及電接 觸。 本發明之實闕綱於—雖㈣歧設的光電二極體的影 像感·及其製造方法。這樣可減少或防止光電二極财的缺陷。 ❹ 根據本發狀實補，—影像_||可包含有以下元件至少 之一。-第-基板’其上形成有電路。一光電二極體，係與第一 基板相結合且該電路電連接。一接觸插塞，係位於一畫素邊界且 與電路及光電二極體電連接。光電二極體包含有一第一導電型離 子注入區及-第二導電型離子注人區，第—導電型離子注入區可 選擇地配設於-縣半賴射，並且第二導電養子注入區係 與第一導電型離子注入區之一側表面相接觸。 6 200929532 根據本發明之實施例，一種影像感測器之製造方法包含以下 步驟至少之-。準備-第-基板，此第—基板具有電路及接線。 準備一第二基板，第二基板具有一光電二極體。結合第一基板及 第二基板，用以將光電二極體與—第—介電層相接觸。透過去除 第二基板之一底侧用以暴露光電二極體。在一畫素邊界提供一接 觸插塞用以電連接接線與光電二極體，光電二極體可包含有一第 一導電型離子注入區及一第二導電型離子注入區，第一導電型離 © 子注入區可選擇地配設於一結晶半導體層中，並且第二導電型離 子注入區與第一導電型離子注入區之一側表面相接觸。 【實施方式】 以下，將結合圖式部份描述本發明實施例之影像感測器及其 製造方法。「第1B圖」係為本發明之實施例之影像感測器之平面 圖’並且「第1A圖」係為沿「第1B圖」之u，線的影像感測器 之截面圖。 Ο 本發明實施例之影像感測器可包含有第一基板1〇〇及光電二 極體210，第一基板1〇〇之上形成有電路，並且光電二極體21〇 與第一基板100相結合且與該電路電連接。本發明之實施例之影 像感測器還包含有形成於一晝素邊界的接觸插塞240，接觸插塞 240與電路及光電一極體210電連接。光電二極體21〇可包含有第 一導電型離子注入區214及第二導電型離子注入區216,第一導電 型離子注入區214選擇性地形成於一結晶半導體層中，並且第二 200929532 導電型離子注入區216與第― 接觸形成。 導電型離子注入區214之側表面相 第1A圖」所示’根據本發明之實施例，接觸插塞240 之一側表面可與光電二極體的第一導電型離子注入區214電接 觸並且接觸插塞240的另一側表面可透過第二介電層挪絕緣。 根據本發明之實施例，阻擋層22〇可更形成於第二介電層23〇 之-侧表面之上與/或上方。根據本發明之實施例，第二介電層 © 230可為-氧化層’並且阻擒層22〇可為一氮化層。然而，還可使 用習知技術所知悉的其他材料代替。 根據本發明之實施例，第—介電層m可形成大約％埃（a) 至大約麵埃⑷之間的厚度且可形成於第一基板卿與光電 :極體210之間。第一介電層12〇功能上可用作第一基板廳與 第二基板200 (如「第5圖」所示）的結合層。 ❿且’根據本發明之實施例，高濃度第-導f雜子注入區 罾212可更形成於光電二極體的第一導電型離子注入區214與接觸 插塞240之間。 、 睛參閱「第1B目」，根據本發明之實施例，了頁電極μ2可與 光電二極體的第二導電型離子注入區216電連接。 、 根據本發明之實施例，半導體層210a (如「第3圖」所示） 可為-單晶半導體層’但是可由習知技術知悉触何材料形成。 根據本發明之實施例，半導體層210a可為一多晶半導體層。 8 200929532 根據本發明之實施例，互補式金氧半導體（CM〇s)影像感測 器（CMOS Image Sensor，CIS)的第—基板1〇〇之電路可為4電晶 體互補式金氧半導體（CMOS)影像感湘（4TrCIS)。根據本發 明之實施例，第一基板100之電路可為一〗TrCIS、一 3、 一 5 Tr CIS、一共用電晶體CIS ( u Tr as)、或者習知技術所知 悉的其他任何結構。200929532 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to an image sensor. [Previous Technology] A Complementary Metal Oxide Semiconductor (CMOS) image sensor may have a photodiode formed in a pixel unit and a metal oxide semiconductor (MOS). Transistor. A complementary metal oxide semiconductor (CMOS) image sensor can sequentially detect the electrical signals in the individual cells to generate an image. A complementary metal oxide semiconductor (CMOS) image sensor of the prior art may have a horizontally disposed photodiode and a transistor. The complementary metal-oxide semiconductor (CMOS) image sensor at the level of the prior art overcomes the different limitations of Charge-Ccmpled Device (CCD) image sensors. However, the horizontal complementary metal oxide semiconductor (CM〇s) image sensor of the prior art still has the disadvantages. For example, horizontal complementary metal oxide semiconductor (CMOS) image sensors of the prior art can be fabricated using horizontal locations and adjacent photodiodes and transistors. Therefore, when an extra space of the photodiode is required, a fill factor area should be reduced and a limit on the resolution potential can be generated. In addition, the horizontal complementary metal-oxide semiconductor (10) (8) image of the technology is difficult to achieve the ideal conditions for the simultaneous fabrication of photodiodes and transistors. 200929532, in the level-complementary MOS semiconductor (in CMOS, image sensor, when a gold goes to P* π丄), Α" when the size of the element increases, the resolution of the image sensor can be reduced. In addition, when the area of the photodiode is reduced, the degree of the image sensor can be reduced. SUMMARY OF THE INVENTION In view of the above problems, embodiments of the present invention relate to an image sensor and a method of manufacturing the image of the image. And the manufacturing method thereof can provide _ © circuit and photodiode. σ % The image sensor of the present invention and the method of manufacturing the same can improve the resolution and sensitivity. According to the present invention, the image can include vertical The photodiode is provided with improved physical and electrical contact between the photodiode and the circuit. The invention is based on the image sensing of the photodiode and its manufacture. The method can reduce or prevent the defects of the photodiode. ❹ According to the present invention, the image_|| can include at least one of the following components: - the first substrate - has a circuit formed thereon. Polar body, system and first The plates are combined and the circuit is electrically connected. A contact plug is located at a pixel boundary and is electrically connected to the circuit and the photodiode. The photodiode includes a first conductivity type ion implantation region and a second conductivity type. In the ion implantation region, the first conductivity type ion implantation region is selectively disposed in the -semi-subject, and the second conductive nut implantation region is in contact with one side surface of the first conductivity type ion implantation region. 6 200929532 In an embodiment of the present invention, a method for manufacturing an image sensor includes at least the following steps: preparing a first substrate, the first substrate having a circuit and a wiring. Preparing a second substrate, the second substrate having a photodiode The first substrate and the second substrate are combined to contact the photodiode with the first dielectric layer, and the bottom side of the second substrate is removed to expose the photodiode. Providing a contact plug for electrically connecting the wiring and the photodiode, the photodiode may include a first conductivity type ion implantation region and a second conductivity type ion implantation region, and the first conductivity type may be separated from the electron injection region selected The second conductivity type ion implantation region is in contact with one side surface of the first conductivity type ion implantation region. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The image sensor and the method of manufacturing the same. "1B" is a plan view of the image sensor of the embodiment of the present invention, and "1A" is an image of the line along the u of "1B". A cross-sectional view of the sensor. The image sensor of the embodiment of the present invention may include a first substrate 1 and a photodiode 210. The first substrate 1 is formed with a circuit thereon, and the photodiode 21 is coupled to the first substrate 100. Combined and electrically connected to the circuit. The image sensor of the embodiment of the present invention further includes a contact plug 240 formed at a pixel boundary, and the contact plug 240 is electrically connected to the circuit and the photodiode 210. The photodiode 21A may include a first conductivity type ion implantation region 214 and a second conductivity type ion implantation region 216, and the first conductivity type ion implantation region 214 is selectively formed in a crystalline semiconductor layer, and the second 200929532 The conductive ion implantation region 216 is formed in contact with the first contact. The side surface phase of the conductive ion implantation region 214 is shown in FIG. 1A". According to an embodiment of the present invention, one side surface of the contact plug 240 may be in electrical contact with the first conductivity type ion implantation region 214 of the photodiode and The other side surface of the contact plug 240 can be insulated through the second dielectric layer. According to an embodiment of the present invention, the barrier layer 22 may be formed over and/or over the side surface of the second dielectric layer 23A. According to an embodiment of the present invention, the second dielectric layer © 230 may be an - oxide layer and the barrier layer 22 may be a nitride layer. However, other materials known to the prior art may be substituted. According to an embodiment of the present invention, the first dielectric layer m may form a thickness between about angstroms (a) and about angstroms (4) and may be formed between the first substrate and the photo-electric body 210. The first dielectric layer 12 is functionally used as a bonding layer between the first substrate chamber and the second substrate 200 (as shown in Fig. 5). Further, according to an embodiment of the present invention, the high concentration first-conducting impurity region 212 may be formed between the first conductivity type ion implantation region 214 of the photodiode and the contact plug 240. Referring to "1B", according to an embodiment of the present invention, the page electrode μ2 can be electrically connected to the second conductivity type ion implantation region 216 of the photodiode. According to an embodiment of the present invention, the semiconductor layer 210a (as shown in "Fig. 3") may be a - single crystal semiconductor layer' but may be formed by any of the materials known in the art. According to an embodiment of the present invention, the semiconductor layer 210a may be a polycrystalline semiconductor layer. 8 200929532 According to an embodiment of the present invention, a circuit of a first substrate of a complementary CMOS image sensor (CIS) may be a 4-cell complementary metal oxide semiconductor ( CMOS) Image Sensation (4TrCIS). In accordance with an embodiment of the present invention, the circuitry of the first substrate 100 can be a TrCIS, a 3, a 5 Tr CIS, a shared transistor CIS (u Tr as), or any other structure known in the art.
Ο 根據本發明之實施例，形成於第一基板1〇〇之上與/或上方 之接線110可包含有金屬及插塞。接線110之最頂部份功能上可 作為光線二極體的底部電極。 根據本發明之實施例，如「第1A圖」及「第1B圖」所示， 透過在-晝素邊界形成-接觸插塞及頂電極可增加填充因子。 而且’根據本發明之實施例，透過在畫素電極邊界形成一介 電層可最小化或防止晝素的串擾。另外，根據本發明之實施例， 通過保證晝素電極邊界的接糖塞與底部接線之間的接觸可增加 歐姆接觸。本發明之實_還提供有H極體，此光電二極 體形成於該電路之上的結晶半導财之侧表面上。 圖」係為本發明之實施例的影像感測器 「第2圖」至「第13 之製造方法之截面圖。 请參閱「第2圖」，準備第一基板1〇〇，第一基板⑽之上盥 或上方可形成具有接線m的電路。根據本發明之實施例，此 路可為f知技術所知悉之任何結構。舉例而言，此電路可為一 4 9 200929532 之上與/或上方的接線110可包含有According to an embodiment of the present invention, the wiring 110 formed on and/or over the first substrate 1 may include metal and a plug. The topmost portion of the wiring 110 functions as the bottom electrode of the light diode. According to an embodiment of the present invention, as shown in "1A" and "1B", the fill factor can be increased by forming a contact plug and a top electrode at the -cell boundary. Moreover, according to an embodiment of the present invention, crosstalk of halogen can be minimized or prevented by forming a dielectric layer at the boundary of the pixel electrode. Further, according to an embodiment of the present invention, the ohmic contact can be increased by ensuring contact between the sugar plug and the bottom wiring of the boundary of the halogen electrode. The present invention also provides an H pole body formed on the side surface of the crystal semiconducting material above the circuit. FIG. 2 is a cross-sectional view showing a manufacturing method of the image sensor "2nd" to "13th embodiment of the present invention. Please refer to FIG. 2, preparing a first substrate 1", a first substrate (10) A circuit having a wire m can be formed on or above the top. In accordance with an embodiment of the present invention, this path can be any structure known to the art. For example, the circuit 110 can be a wiring above and/or over a 4 9 200929532
TrCIS。形成於第一基板1〇〇 金屬及插塞。 第一介電層m可形成於第一基板100之上與/或上方用以 選擇性地與魏11G相接觸。根縣㈣之魏例，形 ㈣㈣不是必需之過程。第一介電㈣可為一氧化層，例如 虱化石夕s1〇2)，但是並不限制於此。可在第一介電層⑽之上執 ❹ 行一平坦化過程，例如-化學機械研磨⑽咖Meehanieal Polishing, CMP)過程。 根據本發明之實施例，—介電層可配設於光電二極體與電路 之間。這可提高光電二極體與垂直結構光電二極體中的電路之間 的連接性。而且’根據本㈣之實施例，在—介電剌成於電路 之上與/或上方且執行平坦化過程例如化學機械研磨（。則之 後’可執行結合過程。這樣可最小化疊蓋錯誤且提高結合及分離 之狀態。 請參閱「第3圖」，可為結晶體的半導體層耻形成於第二 土板200之上與/或上方。透過形成一光電二極體於一結晶半導 體層施之上’可最小化或防止光電二極體巾的缺陷。 根據本發明之實施例，結晶半導體層21⑽可外卿成於第二 基板200之上與/或上方。然後氫離子可在第二基板厕與結晶 半導體層21Ga之間的邊界注人。這樣可形錢離子注入層 207a。 光電二極體210可通過對結晶半導體層耻的離子注入過程 200929532 形成。根據本發明之實施例’結晶半導體層2i〇a可形成為一第一 導電型層。在形成結晶半導體層210a之後’可在全部表面之上與 /或上方執行第一導電型離子注入。根據本發明之實施例，在形 成結晶半導體層21〇a之後，一光罩可用以選擇性地形成第一導電 型離子注入區214。根據本發明之實施例，第一導電型離子注入區 214可為N-型區，但是並不限制於此。 第一感光層圖案310可用作一光罩用以在第一導電型離子注 〇 入區214之一侧的畫素邊界上形成一高濃度第一導電型離子注入 區212。根據本發明之實施例，透過在該畫素邊界形成一 N+區能 夠感應歐姆接觸。 請參閱「第4圖」，可去除第一感光層圖案31〇,並且第二感 光層圖案320可用作一光罩用以在第一導電型離子注入區214之 另一側表面上形成第二導電型離子注入層216。 叫參閱「第5圖」，第一基板100與第二基板200可相結合以 © θ 4得光電二極體210與第一介電層12〇相接觸。根據本發明之實 施例，在第一基板與第二基板200相結合之前，可使用電漿 激活用以增加待結合之表面的表面能量。 请參閱「第6圖」，可熱處理第二基板200。這樣可將氫離子 庄入層207a (如「第5圖」所示）轉化為氫氣層2〇7。接下來， °月參閱「第7圖」’透過去除氫氣層207之上的第二基板200之一 底部可暴露光電二極體21〇。 11 200929532 請參閱「第8圖」’可執行姓刻用以將光電二極體2i〇定義為 單獨的晝素。根據本發明之實施例，可去除晝素邊界的光電二極 體210及第一介電層120用以可選擇地暴露接線11〇且形成一第 一接觸孔H1。根據本發明之實施例，可選擇且部份地去除畫素邊 界的高濃度第一導電型離子注入區212及第二導電型離子注入區 216，用以可選擇地暴露接線11〇。 請參閱「第9圖」，阻擋層220可形成於第一接觸孔H1及光 〇 電二極體210之上與/或上方。阻擋層220可為一氮化層，例如 一氮化矽（SiN) ’但是並不限制於此。 請參閱「第10 ®」，第二介電層230可形成為用以填充第一 接觸孔H1且形成於阻擋層220之上與/或上方。第二介電層2邓 可為-氧化層，例如二氧化石夕（Si02)，但是並不限制於此。 請參閱「第11圖」，可去除第二介電層23〇帛以暴露第一接 觸孔H1之一側的侧表面及絲面的阻擋層220且形成第二接觸孔 H2。根據本㈣之實_，制具有高侧選擇性_刻劑對第 二介電層230及該阻擋層執行第一濕蝕刻。 請參閱「第12圖」，可去除暴露的阻擋層22〇。這樣可形成第 二接觸孔H3用以選擇性地暴露光電二極體21〇的一側表 11〇。根據本發明之實施例，制具有高爛選擇性醜刻劑對第 -介電層23〇及該阻檔層執行第二涵刻。根據本發明之實施例， 可去除暴露的輯層22G職形成第三接觸孔H3，第三接觸孔 12 200929532 H3可選擇地暴露高濃度第一導電型離子注入區212之一侧表面及 接線110。 根據本發明之實施例，當形成此接觸孔時，透過使用一濕# 刻能夠最小化或者防止在乾蝕刻中可能產生的電漿損壞。相比較 於習知技術可產生光電二極體的更多的有益特性。 請參閱「第13圖」，一接觸插塞240可形成為用以填充第三 接觸孔H3。根據本發明之貫施例’接觸插塞24〇可由·鶴（AV)、 ® 一單鈦（Ti)層、或者一鈦/氮化鈦（Ti/TiN)多層形成，但是並 不限制於此。然後可形成一與第二導電型離子注入區216電接觸 的頂電極242。根據本發明之實施例，在選擇性地去除該晝素邊界 用以暴露第二導電型離子注入區216之一侧表面之後，頂電極242 可形成為與第二導電型離子注入區216相接觸。 形成頂電極242的蝕刻過程可與形成接觸插塞24〇的蝕刻過 程一起執行。根據本發明之實施例，用以形成接觸插塞240之材 料與形成頂電極242之材料可為相同之材料。根據本發明之實施 例，可形成一第四接觸孔。在形成用以暴露高濃度第一導電型離 子注入區212的第三接觸孔H3期間，第四接觸孔可暴露第二導電 t離子/主人區216,接觸減及頂電極可同時形成用以填充第三接 觸孔H3及第四接觸孔。 本領域之技術人員應當意識到在不脫離本發明所附之申請專 利範圍所揭不之本㈣之精神和範圍的情況下，所作之更動與潤 13 200929532 飾’均屬本發明之專利保護範圍之内。關於本發明所界定之保護 範圍請參照所附之申請專利範圍。 【圖式簡單說明】 第1A圖及第1B圖係為本發明之實施例的一影像感測器之截 面圖及平面圖；以及 第2圖至第13圖係為本發明之實施例的一影像感測器之製 方法之截面圖。 ©【4要元件符號說明】 100 110 120 200 207 207a 〇 ^ w 210 210a 212 214 216 220 第一基板 接線 第一介電層 弟二基板 氮氣層 氫離子注入層 光電二極體 半導體層 尚濃度第一導電型離子注入區 第一導電型離子注入區 第二導電型離子注入區 阻擋層 第二介電層 230 200929532 240 接觸插塞 242 頂電極 310 第一感光層圖案 320 第二感光層圖案 HI 第一接觸孔 H2 第二接觸孔 H3 第三接觸孔 〇 ❿ 15TrCIS. Formed on the first substrate 1 〇〇 metal and plug. The first dielectric layer m may be formed on and/or over the first substrate 100 for selectively contacting the Wei 11G. The Wei case of the county (4), the form (4) (4) is not a necessary process. The first dielectric (4) may be an oxide layer, such as strontium fossil s1 〇 2), but is not limited thereto. A planarization process, such as a chemical mechanical polishing (10) process, can be performed on the first dielectric layer (10). According to an embodiment of the invention, a dielectric layer can be disposed between the photodiode and the circuit. This improves the connectivity between the photodiode and the circuitry in the vertical structure photodiode. Moreover, 'in accordance with the embodiment of the present invention, the dielectric is formed on and/or over the circuit and a planarization process such as chemical mechanical polishing is performed (and then the 'binding process' can be performed. This minimizes overlay errors and The state of bonding and separation is improved. Referring to FIG. 3, the semiconductor layer of the crystal may be formed on and/or over the second earth plate 200. The photodiode is formed in a crystalline semiconductor layer by forming a photodiode. The above can minimize or prevent defects of the photodiode towel. According to an embodiment of the present invention, the crystalline semiconductor layer 21 (10) can be externally formed on and/or over the second substrate 200. Then hydrogen ions can be on the second substrate The boundary between the toilet and the crystalline semiconductor layer 21Ga is injected. Thus, the ion implantation layer 207a can be formed. The photodiode 210 can be formed by an ion implantation process 200929532 on the crystalline semiconductor layer. According to an embodiment of the present invention, a crystalline semiconductor The layer 2i〇a may be formed as a first conductivity type layer. After the formation of the crystalline semiconductor layer 210a, the first conductivity type ion implantation may be performed over and/or over the entire surface. In an embodiment of the present invention, after forming the crystalline semiconductor layer 21A, a photomask may be used to selectively form the first conductivity type ion implantation region 214. According to an embodiment of the present invention, the first conductivity type ion implantation region 214 may be It is an N-type region, but is not limited thereto. The first photosensitive layer pattern 310 can be used as a mask for forming a high concentration on a pixel boundary on one side of the first conductivity type ion implantation intrusion region 214. a first conductivity type ion implantation region 212. According to an embodiment of the present invention, an ohmic contact can be induced by forming an N+ region at the pixel boundary. Referring to FIG. 4, the first photosensitive layer pattern 31〇 can be removed, and The second photosensitive layer pattern 320 can be used as a mask for forming the second conductive type ion implantation layer 216 on the other side surface of the first conductive type ion implantation region 214. Referring to "Fig. 5", the first substrate 100 and the second substrate 200 may be combined with the photodiode 210 to be in contact with the first dielectric layer 12A. According to an embodiment of the present invention, before the first substrate is combined with the second substrate 200, Plasma activation can be used to increase the amount to be combined Surface energy of the surface. Please refer to Fig. 6 to heat treat the second substrate 200. This converts the hydrogen ion enrichment layer 207a (as shown in Fig. 5) into a hydrogen layer 2〇7. Next, For the month of the month, refer to "Fig. 7". The photodiode 21〇 can be exposed by removing the bottom of the second substrate 200 above the hydrogen layer 207. 11 200929532 Please refer to "Fig. 8" The photodiode 2i is defined as a separate halogen. According to an embodiment of the invention, the photodiode 210 and the first dielectric layer 120, which can remove the halogen boundary, are used to selectively expose the wiring 11 and form a First contact hole H1. According to an embodiment of the present invention, the high concentration first conductivity type ion implantation region 212 and the second conductivity type ion implantation region 216 of the pixel boundary may be selectively and partially removed for selectively exposing Wiring 11〇. Referring to FIG. 9, the barrier layer 220 may be formed on and/or over the first contact hole H1 and the photodiode 210. The barrier layer 220 may be a nitride layer such as a tantalum nitride (SiN)' but is not limited thereto. Referring to "10th", the second dielectric layer 230 may be formed to fill the first contact hole H1 and formed on and/or over the barrier layer 220. The second dielectric layer 2 may be an oxide layer such as SiO 2 (SiO 2 ), but is not limited thereto. Referring to Fig. 11, the second dielectric layer 23 is removed to expose the side surface of one side of the first contact hole H1 and the barrier layer 220 of the silk surface and form a second contact hole H2. According to the fourth aspect of the present invention, the first wet etching is performed on the second dielectric layer 230 and the barrier layer with a high side selectivity. Please refer to Figure 12 to remove the exposed barrier layer 22〇. This forms the second contact hole H3 for selectively exposing the side surface 11 of the photodiode 21''. In accordance with an embodiment of the present invention, a second etch is performed on the first dielectric layer 23A and the barrier layer with a high etch selectivity etchant. According to an embodiment of the present invention, the exposed layer 22G can be removed to form a third contact hole H3, and the third contact hole 12 200929532 H3 can selectively expose one side surface of the high concentration first conductivity type ion implantation region 212 and the wiring 110. . According to an embodiment of the present invention, when such a contact hole is formed, it is possible to minimize or prevent plasma damage which may occur in dry etching by using a wet etching. More beneficial properties of the photodiode can be produced compared to conventional techniques. Referring to Fig. 13, a contact plug 240 may be formed to fill the third contact hole H3. According to the embodiment of the present invention, the contact plug 24 can be formed of a plurality of layers of a crane (AV), a single titanium (Ti) layer, or a titanium/titanium nitride (Ti/TiN) layer, but is not limited thereto. . A top electrode 242 in electrical contact with the second conductivity type ion implantation region 216 can then be formed. According to an embodiment of the present invention, after selectively removing the halogen boundary to expose one side surface of the second conductivity type ion implantation region 216, the top electrode 242 may be formed in contact with the second conductivity type ion implantation region 216. . The etching process for forming the top electrode 242 can be performed together with the etching process for forming the contact plug 24A. According to an embodiment of the present invention, the material used to form the contact plug 240 and the material forming the top electrode 242 may be the same material. According to an embodiment of the present invention, a fourth contact hole can be formed. During formation of the third contact hole H3 for exposing the high concentration first conductivity type ion implantation region 212, the fourth contact hole may expose the second conductive t ion/master region 216, and the contact subtraction top electrode may be simultaneously formed for filling The third contact hole H3 and the fourth contact hole. It will be appreciated by those skilled in the art that, without departing from the spirit and scope of the invention as set forth in the appended claims. within. Please refer to the attached patent application for the scope of protection defined by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A and 1B are a cross-sectional view and a plan view of an image sensor according to an embodiment of the present invention; and FIGS. 2 to 13 are an image of an embodiment of the present invention. A cross-sectional view of the method of making the sensor. ©【4Required Symbol Description】 100 110 120 200 207 207a 〇^ w 210 210a 212 214 216 220 First substrate wiring First dielectric layer Di substrate Nitrogen layer Hydrogen ion implantation layer Photodiode semiconductor layer concentration One conductivity type ion implantation region first conductivity type ion implantation region second conductivity type ion implantation region barrier layer second dielectric layer 230 200929532 240 contact plug 242 top electrode 310 first photosensitive layer pattern 320 second photosensitive layer pattern HI One contact hole H2 second contact hole H3 third contact hole 〇❿ 15