KR101038809B1

KR101038809B1 - image sensor and fabricating method thereof

Info

Publication number: KR101038809B1
Application number: KR1020080109559A
Authority: KR
Inventors: 신종훈
Original assignee: 주식회사 동부하이텍
Priority date: 2008-11-05
Filing date: 2008-11-05
Publication date: 2011-06-03
Also published as: KR20100050328A

Abstract

Embodiments relate to an image sensor and a method of manufacturing the same. In another embodiment, a method of manufacturing an image sensor includes: forming a wiring and an interlayer insulating layer on a semiconductor substrate, bonding an image sensing unit including a first doping layer and a second doping layer on the interlayer insulating layer, and the image. Forming a via hole through the sensing unit and the interlayer insulating layer to expose the wiring, forming an insulating layer pattern covering at least a portion of sidewalls of the second doped layer and the first doped layer in the via hole; Forming a barrier layer and a contact plug in the via hole to be insulated from the second doped layer. In the embodiment, while employing the vertical image sensing unit, the first doping layer and the second doping layer of the image sensing unit may be electrically separated to prevent generation of leakage current.

Image sensor, image sensor

Description

Image sensor and fabrication method thereof

Embodiments relate to an image sensor and a method of manufacturing the same.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is classified into a charge coupled device (CCD) image sensor and a complementary metal oxide silicon (CMOS) image sensor (CIS). do.

The CMOS image sensor is a structure in which a photo diode area for receiving a light signal and converting it into an electric signal and a transistor area for processing the electric signal are horizontally disposed.

Such a horizontal image sensor is limited in that the photodiode region and the transistor region are horizontally disposed on the semiconductor substrate to extend the light sensing portion (commonly referred to as "Fill Factor") under a limited area.

As an alternative to overcome this problem, the circuitry is formed on a silicon substrate by depositing a photodiode with amorphous silicon or by using wafer-to-wafer bonding. Attempts have been made to form photodiodes on the lead-out circuit (hereinafter referred to as "three-dimensional image sensor"). The photodiode and the circuit area are connected through a metal line.

The silicon substrate on which the photodiode is formed is formed by vertically stacking a P layer, an intrinsic layer, and an N layer, and the P layer serves to ground the electrons in the pixel to ground by receiving light to retake an image. The layer takes an image, ie receives light and sends electrons to the lower lead-out circuit to image the electrons in the pixel. If the P layer and the N layer are not electrically separated from each other, and electrons remaining in the P layer are transferred to the N layer to generate a leakage current, there is a problem of poor image quality of the CMOS image sensor.

The embodiment provides a method of manufacturing an image sensor that employs a vertical image sensing unit and electrically separates a first doping layer and a second doping layer from an image sensing unit to prevent leakage current.

In an embodiment, the first and second doped layers may be electrically insulated from each other by forming an image sensing unit on the readout circuit and forming vias of the image sensing unit for electrically connecting the image sensing unit and the readout circuit. An image sensor having a via structure is provided.

The image sensor according to the embodiment, an image sensing unit including a wiring and an interlayer insulating layer formed on a semiconductor substrate, an ohmic contact layer bonded on the interlayer insulating layer, a first doped layer and a second doped layer, the image sensing And a contact plug formed in the via hole formed through the interlayer and interlayer insulating layers, and an insulating layer pattern formed between at least a portion of sidewalls of the second doped layer and the first doped layer and the contact plug.

In another embodiment, a method of manufacturing an image sensor includes: forming a wiring and an interlayer insulating layer on a semiconductor substrate, bonding an image sensing unit including a first doping layer and a second doping layer on the interlayer insulating layer, and the image. Forming a via hole through the sensing unit and the interlayer insulating layer to expose the wiring, forming an insulating layer pattern covering at least a portion of sidewalls of the second doped layer and the first doped layer in the via hole; Forming a barrier layer and a contact plug in the via hole to be insulated from the second doped layer.

According to the method of manufacturing the image sensor according to the embodiment, the fill factor may be approached to 100% by employing a circuitry and a vertical integration of the image sensing unit.

The image sensor according to the embodiment employs a deep via hole and a metal plug in which the first doping layer and the second doping layer of the image sensing unit are electrically separated, thereby transferring the electrons of the image sensing unit to the readout circuit to output the signal of the photodiode. (Signal Out Put) can be made normally. That is, since the metal plug is electrically connected only to the n-type layer of the image sensing unit, the n-type layer and the p-type layer are electrically separated, thereby preventing leakage current and improving image quality.

A method of manufacturing an image sensor according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or via another layer. (indirectly) includes everything formed.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

The embodiment is not limited to the CMOS image sensor, and may be applied to all image sensors requiring a photodiode such as a CCD image sensor.

1 to 3 are cross-sectional views illustrating a method of manufacturing a semiconductor substrate including a readout circuit unit of an image sensor according to an embodiment.

Referring to FIG. 1, a wiring 150 and an interlayer insulating layer 160 are formed on a semiconductor substrate 100 including a readout circuit 120.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type impurities or n-type impurities. An isolation region 110 is formed on the semiconductor substrate 100 to define an active region, and a readout circuit 120 including a transistor is formed in the active region. For example, the readout circuit 120 may include a transfer transistor (Tx) 121, a reset transistor (Rx) 123, a drive transistor (Dx) 125, and a select transistor (Sx) 127. can do. Thereafter, an ion implantation region 130 including a floating diffusion region (FD) 131 and source / drain regions 133, 135, and 137 for each transistor may be formed. Meanwhile, the readout circuit 120 may be applied to a 3Tr or 5Tr structure.

The forming of the lead-out circuit 120 on the semiconductor substrate 100 may include forming an electrical junction region 140 on the semiconductor substrate 100 and the wiring 150 on the electrical junction region 140. ) May include forming a first conductivity type connection region 147.

For example, the electrical junction region 140 may be a PN junction 140, but is not limited thereto. For example, the electrical junction region 140 may include a first conductive ion implantation layer 143 and a first conductive ion implantation layer (143) formed on the second conductive well 141 or the second conductive epitaxial layer. 143 may include a second conductivity type ion implantation layer 145. For example, the PN junction 140 may be a P0 145 / N- 143 / P-141 junction as shown in FIG. 1, but is not limited thereto. In addition, the semiconductor substrate 100 may be conductive in a second conductivity type, but is not limited thereto.

According to the embodiment, the device can be designed such that there is a voltage difference between the source / drain across the transfer transistor Tx, thereby enabling full dumping of the photo charge. Accordingly, as the photo charge generated in the photodiode is dumped into the floating diffusion region, the output image sensitivity may be increased.

That is, by forming an electrical junction region 140 in the semiconductor substrate 100 on which the readout circuit 120 is formed, there is a voltage difference between the source / drain across the transfer transistor (Tx) 121 so as to completely dump the photocharge. This can be made possible.

Hereinafter, the dumping structure of the photocharge of the embodiment will be described in detail with reference to FIGS. 1 and 2.

Unlike the floating diffusion (FD) 131 node, which is an N + function in the embodiment, the P / N / P section 140, which is an electrical junction region 140, does not transmit all of the applied voltage and pinches at a constant voltage. It is off (Pinch-off). This voltage is called a pinning voltage and the pinning voltage depends on the P0 145 and N- (143) doping concentrations.

Specifically, the electrons generated by the photodiode 205 are moved to the PNP caption 140 and are transferred to the FD 131 node when the transfer transistor (Tx) 121 is turned on and converted into voltage.

Since the maximum voltage value of the P0 / N- / P- caption 140 becomes pinning voltage and the maximum voltage value of the node FD 131 becomes Vdd-Rx Vth, as shown in FIG. 2, the potential difference between both ends of the Tx 131 is shown. Due to this, electrons generated from the photodiode on the chip may be completely dumped to the FD 131 node without charge sharing.

That is, in the embodiment, the reason why the P0 / N- / Pwell junction is formed instead of the N + / Pwell junction in the silicon sub, which is the semiconductor substrate 100, is P0 / N- / Pwell during the 4-Tr APS Reset operation. In the junction, + voltage is applied to N- (143) and ground voltage is applied to P0 (145) and Pwell (141). Therefore, P0 / N- / Pwell double junction is more than Pinch-Off as in BJT structure. Will occur. This is called pinning voltage. Therefore, a voltage difference is generated in the source / drain at both ends of the Tx 121, and thus the photocharge is completely dumped from the N-well to the FD through the Tx at the Tx On / Off operation to prevent the charge sharing phenomenon.

Therefore, unlike the case where the photodiode is simply connected with N + junction in the technology of a general image sensor, according to the embodiment, problems such as degradation of saturation and degradation of sensitivity can be avoided.

Next, according to the embodiment, the first conductive connection region 147 is formed between the photodiode and the lead-out circuit 120 to minimize the dark current source by creating a smooth movement path of the photo charge. Deterioration of saturation and degradation of sensitivity can be prevented.

To this end, the embodiment may form an N + doped region as the first conductive connection region 147 for ohmic contact on the surface of the P0 / N− / P− junction 140. The N + region 147 may be formed to contact the N− 143 through the P0 145.

Meanwhile, in order to minimize the first conductive connection region 147 from becoming a leakage source, the width of the first conductive connection region 147 may be minimized.

To this end, the embodiment may proceed with a plug implant after etching the second metal contact 151a, but is not limited thereto. For example, the first conductive connection region 147 may be formed by forming an ion implantation pattern (not shown) and using the ion implantation mask as an ion implantation mask.

That is, the reason for N + doping locally only in the contact forming part as in the embodiment is to facilitate the formation of ohmic contact while minimizing the dark signal. As in the prior art, when N + Doping the entire Tx Source part, the dark signal may increase due to the substrate surface dangling bond.

3 shows another structure for the readout circuit. As shown in FIG. 3, a first conductive connection region 148 may be formed on one side of the electrical junction region 140.

Referring to FIG. 3, an N + connection region 148 for ohmic contact may be formed in the P0 / N− / P− junction 140, wherein the process of forming the N + connection region 148 and the M1C contact 151a is performed. It can be a Leakage Source. This is because the electric field EF may be generated on the Si surface of the substrate because the reverse bias is applied to the P0 / N− / P− junction 140. Crystal defects that occur during the contact formation process inside these electric fields become a source of liquidity.

In addition, when the N + connection region 148 is formed on the surface of the P0 / N- / P- junction 140, an E-Field by the N + / P0 junction 148/145 is added, which is also a leakage source. Can be

That is, the first contact plug 151a is formed in an active region formed of the N + connection region 148 without being doped with the P0 layer, and a layout for connecting the first contact plug 151a with the N-junction 143 is presented.

Then, the E-Field of the surface of the semiconductor substrate 100 does not occur, which may contribute to the reduction of dark current of the 3-D integrated CIS.

Referring back to FIG. 1, an interlayer insulating layer 160 and a wiring 150 may be formed on the semiconductor substrate 100. The wiring 150 may include a second metal contact 151a, a first metal M1 151, a second metal M2 152, and a third metal M3 153. It is not decided. In an embodiment, after forming the third metal 153, an insulating film may be deposited to prevent the third metal 153 from being exposed, and then an interlayer insulating layer 160 may be formed by performing a planarization process. Therefore, the surface of the interlayer insulating layer 160 having a uniform surface profile may be exposed on the semiconductor substrate 100.

4 to 11 are cross-sectional views illustrating a method of manufacturing a semiconductor substrate including an image sensing unit of an image sensor according to an embodiment.

Referring to FIG. 4, an image sensing unit 200 is formed on the interlayer insulating layer 160 of the semiconductor substrate 100. The image sensing unit 200 may include a first doped layer (N−) 210 and a second doped layer (P +) 220 to have a photodiode structure of a PN junction. In addition, the image sensing unit 200 may include an ohmic contact layer (N +) 230 under the first doped layer 210.

For reference, the third metal 153 and the interlayer insulating layer 160 of the wiring 150 illustrated in FIG. 4 represent portions of the wiring 150 and the interlayer insulating layer 160 illustrated in FIG. 1. For convenience, some of the readout circuit 120 and the wiring 150 are omitted.

For example, the image sensing unit 200 ion-implants N-type impurities (N−) and P-type impurities (P +) in order into the p-type carrier substrate (not shown) having a crystalline structure, and thus the first doped layer 210. ) And the second doped layer 220 may be formed in a stacked structure. In addition, an ohmic contact layer 230 may be formed by ion implanting a high concentration of N-type impurities (N +) under the first doped layer 210. The ohmic contact layer 230 may lower the contact resistance between the image sensing unit 200 and the wiring 150.

In an embodiment, the first doped layer 210 may be formed to have a wider area than the second doped layer 220. The depletion region can then be expanded to increase the production of photoelectrons.

Next, the ohmic contact layer 230 of the carrier substrate (not shown) is positioned on the interlayer insulating layer 160, and a bonding process is performed to bond the semiconductor substrate 100 and the carrier substrate. Thereafter, the carrier substrate on which the hydrogen layer is formed is exposed by the cleaving process so that the image sensing unit 200 bonded on the interlayer insulating layer 160 is exposed to expose the surface of the second doped layer 220. . For example, the height of the image detection unit 200 may be about 1.0 ~ 1.5㎛.

That is, since the semiconductor substrate 100 and the image sensing unit 200 having the readout circuit 120 are formed by wafer-to-wafer bonding, defects may be prevented.

In addition, the image sensing unit 200 may be formed above the readout circuit 120 to increase the fill factor. In addition, since the image sensing unit 200 is bonded on the interlayer insulating layer 160 having a uniform surface profile, the bonding force may be physically improved.

Referring to FIG. 5, a via hole 240 penetrating the image sensing unit 200 and the interlayer insulating layer 160 is formed. The via hole 240 may expose a surface of the third metal 153 inside the interlayer insulating layer 160 as a deep via hole.

Although not shown, the via hole 240 may form a hard mask (not shown) and a photoresist pattern (not shown) on the image sensing unit 200, and then the image sensing unit 200 and the interlayer insulating layer ( 160 may be formed by selectively etching. In this case, the opening of the hard mask and the photoresist pattern may expose the surface of the image sensing unit 200 corresponding to the third metal 153. Thereafter, the photoresist pattern may be removed by an ashing process, and the hard mask may remain on the image sensing unit 200. In the embodiment, the hard mask is removed.

The via hole 240 may have a depth of about 8000 to 15000 μs, and a width of about 3000 to 6000 μm.

Referring to FIG. 6, the photoresist layer 250 is formed on the entire surface of the image sensing unit while filling the via hole 240.

Referring to FIG. 7, the sacrificial pattern 251 is formed in the via hole 240 by etching the entire surface of the photoresist layer 250 using Reactive Ion Etching (RIE).

Here, the sacrificial pattern 251 in the via hole 240 may remain at least to the height of the ohmic contact layer 230. That is, the sacrificial pattern 251 in the via hole 240 covers the side surface of the ohmic contact layer 230 exposed by the via hole 240. The sacrificial pattern 251 may be formed from the bottom of the ohmic contact layer 230 to the height of the first doped layer 210.

When the photoresist layer 250 is etched using the reactive ion etching method, an upper surface of the second doped layer 220 of the image sensing unit 200 may be exposed, and a first surface of the via hole 240 may be exposed. And sidewalls of the second doped layers 210 and 220 may be exposed.

For example, when the depth of the via hole 240 is 1.2 μm, the depth of the next via hole 240 having the sacrificial pattern 251 formed in the via hole 240 may be 0.5 to 0.7 μm.

Referring to FIG. 8, an insulating film 260 is deposited on the entire surface of the image sensing unit 200. The insulating layer 260 may be an oxide layer. It is important to set the thickness of the insulating film 260 appropriately. If the insulating layer 260 is too thick, it may be difficult to form a contact plug in the via hole 240. If the insulating layer 260 is too thin, an electrical field is formed between the second doped layer 220 and the contact plug. Electrical isolation may not be complete. In addition, when the insulating layer 260 is later etched at the corner of the via hole 240 to expose the second doped layer 220, a leakage current may be generated between the second doped layer 220 and the contact plug. The insulating film 260 is deposited to an appropriate thickness.

The insulating film 260 may be formed to a thickness of 50 ~ 500Å.

The insulating layer 260 is a low temperature oxide (LTO) film and may be formed by a plasma enhanced chemical vapor deposition (PE-CVD) method. In order to carry out the PE-CVD method, the gas was prepared using SiH _{4 of} 300-600 sccm, N ₂ O of 6000-8000 sccm, process temperature of 150-220 ° C., chamber pressure of 0.5torr-1.5torr, and RF power of 300-500w. Has a condition.

The insulating layer 260 covers an upper surface of the second doped layer 220 and covers sidewalls of the first and second doped layers 210 and 220 exposed in the via hole 240 and an upper surface of the sacrificial pattern 251. Covered and formed.

The insulating layer 260 electrically insulates the second doped layer 220 from the contact plug and prevents the first doped layer 210 and the second doped layer 220 from shorting. That is, the photoelectrons generated in the first doped layer 210 leak to the second doped layer 220 through the contact plug, or the remaining electrons of the second doped layer 220 pass through the first contact plug. It is prevented from being transferred to the doped layer 210 or the third metal 153.

9, a photoresist pattern 255 is formed on the insulating layer 260 on the second doped layer 220.

The photoresist pattern 255 forms an opening in a portion corresponding to the via hole 240. That is, the via hole 240 is exposed by the photoresist pattern 255.

The photoresist pattern 255 may be aligned with the insulating layer 260 at the corner of the via hole 240 to correspond to the via hole 240.

Thereafter, reactive ion etching is performed using the photoresist pattern 255 as a mask to remove the insulating layer 260 on the sacrificial pattern 251.

The reactive ion etching is anisotropic etching, the etching of the insulating film 260 formed on the sidewall in the via hole 240 is hardly etched and the sacrificial pattern 251 is exposed by actively etching the insulating film 260 on the bottom surface. .

Referring to FIG. 10, the sacrificial pattern 251 and the photoresist pattern 255 are removed together. Since the sacrificial pattern 251 is made of a photoresist, the sacrificial pattern 251 may be removed together in one step by a strip process of the photoresist pattern 255 or an ashing process using oxygen.

Accordingly, an insulating layer pattern 261 covering the top surface of the second doped layer 220, the sidewalls of the second doped layer 220 in the via hole 240, and at least a portion of the first doped layer 210 is formed.

The insulating layer pattern 261 may expose at least a sidewall of the ohmic contact layer 230 and a third metal 153 in the via hole 240, and may expose a portion of the first doped layer 210.

Thereafter, the contact plug 280 is formed in the via hole 240 in which the insulating layer pattern 261 is formed. The contact plug 280 may be formed in the via hole 240 to be electrically connected to the third metal 153. In addition, a barrier layer 270 may be formed between the contact plug 280 and the via hole 240.

For example, the contact plug 280 may be formed of any one of metal materials such as copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and tungsten (W).

The barrier layer 270 may be formed in a structure in which titanium / titanium nitride (Ti / TiN) 250 and 260 are stacked. For example, the Ti layer 260 of the barrier layer 270 may be formed to a thickness of 200 ~ 400Å, the TiN layer 250 may be formed of a thickness of 50 ~ 150Å.

The barrier layer 270 may be formed by PVD (Physical Vapor Deposition) method so that the barrier layer 270 may be uniformly formed well at the end of the insulating layer pattern 261. For example, the barrier layer 270 may be formed by an atom layer deposition (ALD) method.

The contact plug 280 may be formed by a chemical vapor deposition (CVD) method.

The barrier layer 270 and the contact plug 280 form a thin Ti layer and a TiN layer in the via hole 240, and gap fill a metal material on the barrier layer 270 so that the via hole 240 is gap-filled. Afterwards, the planarization process may be performed to form the contact plug 280.

During the planarization process, the insulating layer pattern 261 on the upper surface of the second doped layer 220 is left.

In this case, the contact plug 280 may be electrically insulated from the second doping layer 220 in the via hole 240 and may be electrically connected to the first doping layer 210 and the ohmic contact layer 230 at the same time. Can be. If the first doped layer 210 and the second doped layer 220 are electrically connected to each other by the contact plug 280, the device may be shorted and the image sensor may not output a normal signal. That is, the contact plug 280 is a signal transfer wiring for transferring the photoelectrons generated by the image sensing unit 200 to the readout circuit 120 to be electrically separated from the second doped layer 220 to provide a normal signal. You can print

Since the contact plug 280 is electrically connected only to the first doped layer 210 and the ohmic contact layer 230, the first doped layer 210 and the second doped layer 220 may be electrically separated. .

Subsequently, although not described, a pixel trench isolation forming process may be further performed to classify the photodiode region for each pixel.

In addition, the second doped layer 220 of the image sensing unit 200 may be selectively connected to an upper electrode (not shown) to receive a ground voltage. Alternatively, a transparent electrode (not shown) may be selectively connected only to the second doped layer 220 to receive a ground voltage.

In addition, a color filter (not shown) and a micro lens (not shown) may be formed on the image detector 200.

As described above, in the image sensor according to the exemplary embodiment, since the first doped layer 210 and the ohmic contact layer of the image sensing unit 200 generating photocharges are connected to the contact plug 280, the first doped layer 210 may be used. The second doping layer 220 may be electrically separated to prevent the device from malfunctioning.

Therefore, since the contact plug for transferring the photoelectrons generated by the image sensing unit 200 to the readout circuit 120 is electrically connected only to the first doped layer 210, the image sensor may signal a normal signal. ) Can be printed.

The above-described embodiments are not limited to the above-described embodiments and drawings, and it is common in the technical field to which the present embodiments belong that various changes, modifications, and changes can be made without departing from the technical spirit of the present embodiments. It will be obvious to those who have

Claims

A wiring and an interlayer insulating layer formed on the semiconductor substrate;

An image sensing unit bonded on the interlayer insulating layer and formed in an order of an ohmic contact layer, a first doping layer, and a second doping layer;

A contact plug formed in the via hole formed through the image sensing unit and the interlayer insulating layer; And

And an insulating layer pattern formed between the second doped layer and at least a portion of the sidewall of the first doped layer and the contact plug.

The method of claim 1,

The insulating film pattern is an image sensor, characterized in that formed in 50 ~ 500Å thickness.

The method of claim 1,

And the first doped layer includes N-type impurities, and the second doped layer includes P-type impurities.

The method of claim 1,

The insulating film pattern is an image sensor, characterized in that the low temperature oxide (LTO) film.

Forming a wiring and an interlayer insulating film on the semiconductor substrate;

Bonding an image sensing unit formed on the interlayer insulating layer in order of a first doped layer and a second doped layer;

Forming a via hole through the image sensing unit and the interlayer insulating layer to expose the wiring;

Forming an insulating layer pattern covering the second doped layer sidewall and at least a portion of the first doped layer sidewall and covering the upper surface of the second doped layer in the via hole; And

Forming a barrier layer and a contact plug in the via hole to be insulated from the second doped layer.

The method of claim 5,

In the step of forming the insulating film pattern,

Forming a photoresist film on the entire surface of the image sensing unit in which the via holes are formed;

Reactive ion etching the photoresist layer to form a sacrificial pattern only in a portion of the via hole;

Forming an insulating layer on the image sensing unit and in the via hole;

Selectively etching the insulating film to remove the insulating film on the sacrificial pattern; And

Removing the sacrificial pattern.

The method of claim 5,

The insulating film is formed by Plasma Enhanced Chemical Vapor Deposition (PE-CVD) method, and the gas is 300 to 600 sccm of SiH ₄ , 6000 to 8000 sccm of N ₂ O, a process temperature of 150 to 220 ° C., and a chamber of 0.5 tor to 1.5 tor. It is an LTO film formed on the conditions of pressure and RF power of 300-500w, The manufacturing method of the image sensor characterized by the above-mentioned.

The method of claim 5,

The barrier layer may be formed by a physical vapor deposition (PVD) method or an atom layer deposition (ALD) method.

The method of claim 6,

Selectively etching the insulating film to remove the insulating film on the sacrificial pattern;

Forming a photoresist pattern having an opening on the insulating layer to correspond to the via hole; And

And anisotropically etching the insulating film using the photoresist pattern as a mask, thereby removing the insulating film on the sacrificial pattern and leaving the insulating film on the sidewall.

The method of claim 5,

The thickness of the insulating film pattern is a manufacturing method of the image sensor, characterized in that formed in 50 ~ 500Å thickness.

The method of claim 5,

In forming the contact plug,

And forming a contact plug to form a contact plug by forming a metal material on the barrier layer and the insulating layer pattern so as to gap fill the via hole, and then planarizing the exposed insulating layer pattern on the upper surface of the second doped layer. Method of preparation.