TW200929455A - Wafer level stacked die packaging - Google Patents

Wafer level stacked die packaging Download PDF

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Publication number
TW200929455A
TW200929455A TW097139680A TW97139680A TW200929455A TW 200929455 A TW200929455 A TW 200929455A TW 097139680 A TW097139680 A TW 097139680A TW 97139680 A TW97139680 A TW 97139680A TW 200929455 A TW200929455 A TW 200929455A
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Taiwan
Prior art keywords
adhesive
semiconductor
die
viscous
microelectronic
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Application number
TW097139680A
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English (en)
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TWI400779B (zh
Inventor
Thomas M Goida
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Analog Devices Inc
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Publication of TWI400779B publication Critical patent/TWI400779B/zh

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Description

200929455 九、發明說明： 【發明所屬^技術領域】 發明領域 本發明係有關堆疊的微電子裝置，及其製造方法。 5 【先前技術】 發明背景 堆疊的晶粒封裝典型會有三種形式的任一種：角錐構 形，倒反的角錐構形，及同尺寸晶粒構形。在一角錐構形 _ 中’其頂部晶粒係小於底部晶粒。而在倒反的角錐構形中 10則為相反的情況。或者，該等晶粒可為相同的尺寸。在所 有的堆疊晶粒構形中黏劑典型會被塗佈來將該等頂部 和底部晶粒附接在一起。當有一較大晶粒在頂部之倒反角 錐的情況下，時常需要包含一間隔物，其會在封裝體組合 製程中帶來二分開且添加的晶粒附接步驟。間隔物係由數 15種不同類型的材料所製成，包括以石夕和聚合物為基礎的預 _ s界定帶等。電連接則係藉將晶粒上的電極接結於用以連 接該基座的導線而來提供。 t 明内j 發明概要 2〇 依據本發明的實施例，一堆疊晶粒封裝體包含至少二 個微電子半導體晶粒，一個固定在另一個頂上。一在底部 曰曰粒頂上的黏性壁會在一底部和頂部晶粒之間形成一空氣 隙。在一實施例中，該黏性壁係呈一矩形的形狀，並形成 環繞一位在該晶粒上方中央之中空區域的周緣。在另一實 5 200929455 施例中，該黏性壁可為c形’ v形，H形成x形等等諸多構形。 該頂部晶粒係被固定在該黏性壁上來造成堆疊晶粒。在一 特定實施例中’該純壁會在該二晶粒之間提供一與該壁 的寬度之比為至少1 : 1的厚度。該等堆疊晶粒係被安裝在 5 -基座上。結線會將該各晶粒_面連接於該基座。該堆 疊晶粒封裝體能被包封在一成型於該第一和第二半導體晶 粒上之非導電性材料中。該封裝體更可包含導電焊球等附 接於該基壁之一底面以便電連接。 依據一製造方法’ 一黏性墊的圖案會被沈積在一半導 10體晶圓的主動表面上。可能的黏劑圖案係為一黏劑環的陣 列’或-黏劑的幾何形狀實心塊之陣列。然後該晶圓會被 切割來將其分開成個別的第一半導體晶粒，各晶粒上皆具 有一黏性墊。各第一半導體晶粒的背面可被附接於—基 座。一第二半導體晶粒會被附接於該第一半導體晶粒上的 15黏性整頂上來形成一堆疊晶粒封裳體。導線接結蜗可被進 行來將該第二半導體晶粒電附接於該基座。以非導電材料 來覆蓋成型該第-和第二半導體晶粒的疊塊會包封該等個 別的封裝體。在一較佳實施例中，於沈積一黏劑圖案之前 該晶圓可被背磨。該方法可更包括在切割該晶圓之前先部 20 份地固化該黏劑。 典型會被該黏劑層所賦予之該底部晶粒的晶粒表面上 之應力係可藉僅使用一黏性壁而保留一沒有黏劑的空氣隙 區來被減小。對該半導體晶圓的主動表面塗敷該黏劑會提 供一種有效率的製造方法。本發明的其它目的和優點將可 200929455 2…圖式參閱以下本發明之目前較佳實施例的描述時更 易瞭解。 圖式簡單說明 5 Ο 10 15 ❹ 20 本發明的上述特徵將可配合所附圖式參閱以下詳細說 明而更容易瞭解，其中： " 第Α考1Β圖為依據本發明實施例之一中間半 品的平面圖。 良 _第2圖係為第1 A圖之產品在切割成個別 晶粒之後的平 面示意圖。 第3圖為|獨晶粒附接於—基座之後的側視示意圖。 第4圖為第3圖之晶粒在導線接結之後的側視示意圖。 第5圖為第4圖之晶粒在頂部晶粒附接之後的側視示意圖。 第6圖為第5圖之堆疊晶粒在頂部晶粒導線接結之後的 侧視不意圖。 第7圖為第6圖的堆疊晶粒在覆蓋成型之後的側視示意圖。 第8圖為第7圖的堆疊晶粒在焊球附接之後的侧視示意圖。 第9圖為本發明之一實施例的用以製造堆疊晶粒的方 法之流程圖。 【Λ 較佳實施例之詳細說明 為能以一量產方法來製造一堆疊晶粒封裝體，一起始 材料可為一如誘領域中所泛知的半導體晶圓。該典型的半 導體晶圓是由矽所製成。一微電子電路的陣列會被形成於 該半導體晶圓上。典型地，該電路陣列係被以多數橫排和 7 200929455 直列之個別的微電子電路來形成。該半導體晶圓包含一主 動表面其上可被製成導線連接物，並有一背面可供安裝。 當厚度會造成問題時，一背磨製程可被進行於該載有電路 的晶圓上，以使其和所製成的晶粒更薄些。 5 依據本發明之一態樣，如第9圖所示，黏性墊Ua、ub 等會被沈積100在該半導體晶圓的主動表面上，其中每一黏 性墊11a、lib會與該等個別的微電子電路之一者對準。該 等黏性墊lla、llb係為一定量的黏劑而具有一厚度使其能 有利地作為一封裝體的底部晶粒和頂部晶粒之間的間隔物。 1〇 該黏性墊可被以多種方法之任一者來佈設於該晶圓 Λ等方法包括網幕印刷或光微影法。該黏性材料可被 選自許多適用於製造微電子構件的黏劑之任一種。該等黏 劑可包含例如聚醯亞胺或苯環丁烯(BCB)。該要被用作一間 隔物之黏劑的厚度乃取決於一特定封裝用途之石夕晶粒的幾 何特徵就—堆疊晶粒其中較小的晶粒係被置於頂上者而 言，—較小厚度的間隔物是可接受的，例如，在5至2〇^1111 範圍内在一較大晶粒係被置於較小晶粒頂上來形成一堆 叠封裝體的實施例中，則該黏劑的厚度可例如在50至75μιη 之^。此一厚黏性塾可較適合藉由網幕印刷法來敷設。本 2發月的方法和產品可使用任何厚度的黏性塾其能被用來製 造一可用的裝置。 依據一如第1Α圖中所示的實施例，該等黏性墊Ua係為 1劑裒或黏劑會形成一壁而留下—中空區域⑶立於各晶 粒上方的中央，如第1A圖所示。此中空的中央部份13會留 200929455 下-空氣隙，其將不會以一正常係與該黏劑有關連的方式 來造成該底部晶粒的應力。以有機材料為基礎的間隔物會 在-堆疊晶粒封裝體中的底部石夕晶粒之頂面上致生熱機械 剪切應力。此剪切應力的大小將取決於該材料性質，間隔 5物的形狀和介面黏著面積。此剪切應力可能會使該石夕晶粒 内4的内層結構及/或晶粒純化層造成剝離及/或破裂。該等 黏劑環會減少其黏著面積，故乃被設計來減少此等剪切應 力。該黏劑似如一壁其會形成圍繞該中空中央部份的周 緣。在第1A圖的實施例中，該黏劑環係呈矩形的形狀。可 10以推知在特定實施例中，該壁之厚度（高度)對寬度之一標定 的高寬比應為1比1。該黏性壁的實際高寬比將取決於該底 部晶粒的幾何特徵和用途的類型。此等壁亦可被用來造成 形狀不同於環的接墊，其仍會造成一空氣隙並得到類似之 減少應力的優點。該等形狀係不可勝數，包括C形、η形、 15 V形、或X等及其它者。 依據一變化實施例譬如第1Β圖中所示者，該等黏性墊 lib係被幾何地成形為實心的黏劑塊。示於第1Β圖中的形狀 係為一矩形的黏劑塊。顯然地，一卵形或其它形狀亦可同 樣被使用。 20 依據一較佳實施例，各黏性墊係被設在一微電子電路 上但在被接墊15等所設定的邊界内，該等接墊15係沿一晶 粒的周緣來被使用。故，用於該微電子電路的接墊15會曝 露而可由該黏性墊的周緣外部接近。當該等黏性墊被沈積 後，一中間半導體產品即告完成可供進一步用於堆疊晶粒 9 200929455 封裝體的製造。 該製造方法的後續步驟係部份地固化1〇2該黏劑來將 ' 之帶至其B階段。該B階段係為在一熱固性樹脂反應中之一 中間階段’其中該塑體會保持在一柔軟狀態。該中間半導 5 體產品嗣會準備個體化。該個體化製程1〇4典型包括將該晶 圓鋸切成個別的晶粒20，如第2圖所示。每一晶粒2〇包含一 微電子電路及已被沈積其上的黏性墊11&、Ub。 - 該等個別的晶粒㈣可被檢取並置於一基座3〇上^ 一適 當的吸取喷嘴會被用來容納該有黏性墊設於其上的電路。 ❹ 10在該基座30上之一急促固化或低溫固化黏劑32會將該晶粒 20的底部附接106於該基座。該基座30可為一基材或引線框 或其它用以支樓一堆疊晶粒封裝體的適當底座。該急促固 化或低溫固化黏劑32嗣可被固化，而不會完全固化該晶粒 20上的黏性墊11a，lib。該固化可在一比固化該黏性墊更 15 低的溫度進行’或該固化能在一很短的時間内進行而使該 黏性墊不會固化。標準的晶粒附接材料譬如ABLESTIK 84-1會在一比完全固化例如聚醯亞胺或bcb等黏劑更低甚 〇 多的溫度下被固化。例如，一晶粒附接材料若在125。〇至150 C的溫度下大約1小時可被固化。另·一方面，用於該黏性塾 20 的BCB或聚醯亞胺乃可在300°C以上超過30分鐘至1小時才 被固化。 在將該底部晶粒附接於基座之後，將該晶粒附接於該 基座的黏劑會被固化108而不會固化該黏性墊。即，於此低 溫或快速固化時，該黏性墊可保留在其B階段。在此時，導 10 200929455 線接結110可被進行來將底部晶粒上的接墊連接於該基 座，如第4圖所示。 5 e 10 15 ❹ 20 一頂部晶粒50嗣會準備附接12於後底部晶粒20上。該 頂部晶粒50係被置於該黏性墊11a、lib上，如第5圖所示。 該B階段的黏性墊之完全固化114嗣會進行來固接該堆疊晶 粒封裝體的底部和頂部晶粒。由該頂部晶粒50至該基座30 的導線接結lib嗣可被完成，如第6圖所示。覆蓋成型118會 以一非導電性材料來包封該堆疊晶粒封裝體，如第7圖所 示。覆蓋成型係可例如使用一標準的轉移成型製法來進 行。視該封裝體的類型及所用的基座而定，在此時係可進 行焊球附接於該基座的底部’而來提供用以進入該等微電 子裝置的傳導點，如第8圖所示。 依據本發明的實施例，當一黏性壁被用來形成該黏性 墊時，一空氣隙80會保留在該底部晶粒和頂部晶粒之間。 尤其是，當一黏劑環11a被形成時，該空氣隙8〇會位於其中 央。此乃可釋除該中央區域之會與—黏劑連接有關連的應力。 當然，應請瞭解對前述較佳實施例的各種變化和修正 將可為精習於該技術者輕易得知。例如，依據本發明的堆 昼晶粒封裝舰被以-相對於底部晶粒較小或較大的頂部 晶粒來製成。i，該封裝體的基座可為—半導體基材或一 引線框，乃視所需的封裝體而^。又，添加的晶粒層亦可 被含括而使多數個晶粒被使用上述方法來堆叠。這些及其 它的變化將能被實施而不超出本發明的精神與範圍，且不 減損其_帶的優點。因此該等變化和修正應要被以下申 11 200929455 請專利範圍所涵蓋。 c圖式簡單說明3 第1A和1B圖為依據本發明實施例之一中間半導體產 品的平面圖。 5 第2圖係為第1A圖之產品在切割成個別晶粒之後的平 面示意圖。
第3圖為一單獨晶粒附接於一基座之後的側視示意圖。 第4圖為第3圖之晶粒在導線接結之後的側視示意圖。 第5圖為第4圖之晶粒在頂部晶粒附接之後的側視不意圖。 10 第6圖為第5圖之堆疊晶粒在頂部晶粒導線接結之後的 側視示意圖。 第7圖為第6圖的堆疊晶粒在覆蓋成型之後的側視示意圖。 第8圖為第7圖的堆疊晶粒在焊球附接之後的側視示意圖。 第9圖為本發明之一實施例的用以製造堆疊晶粒的方 15 法之流程圖。 【主要元件符號說明】 32.. .黏劑 70.. .非傳導性材料 80.. .空氣隙 100〜120...各步驟
Q 11a，b...黏性墊 13.. .中空區域 15…接墊 20，50...晶粒 30.. .基座 12

Claims (1)

  1. 200929455 十、申請專利範圍： 1. 一種堆疊晶粒封裝體，包含： 一第一微電子半導體晶粒； 一黏性壁設在該晶粒頂上而形成一周緣圍繞該晶 粒上方之一位於中央的中空區域；及 一第二微電子半導體晶粒固定在該黏性壁頂上。
    10
    20 2. 如申請專利範圍第1項之堆疊晶粒封裝體，更包含一基 座其上係以一黏劑來附接該第一微電子半導體，而該黏 劑會在該黏性壁中的黏劑固化之前先固化。 3. 如申請專利範圍第2項之堆疊晶粒封裝體，更包含結線 等連接於該第一微電子半導體晶粒之一頂部表面與該 基座之間。 4. 如申請專利範圍第3項之堆疊晶粒封裝體，更包含結線 等連接於該第二微電子半導體晶粒之一頂部表面與該 基座之間。 5. 如申請專利範圍第4項之堆疊晶粒封裝體，更包含非傳 導性材料成型覆蓋於該’第一和第二半導體晶粒上。 6. 如申請專利範圍第5項之堆疊晶粒封裝體，更包含傳導 性球體附接於該基座之一底部表面。 7. 如申請專利範圍第1項之堆疊晶粒封裝體，其中該黏性 壁係呈一矩形壁的形狀。 8. —種用以製造堆疊晶粒的方法，包含： 提供一半導體晶圓其具有一主動表面與一背後表面； 沈積一黏性墊的圖案於該半導體晶圓之主動表面 13 200929455 上；及 將該晶粒個體化成個別的第一半導體晶粒，各晶粒 上具有一黏性墊。 9. 如申請專利範圍第8項之方法，更包含將多數個該第— 5 半導體晶粒之每—者的該背後表面附接於一基座。 10. 如申請專利範圍第9項之方法，其中有一低温黏劑將該 各第一半導體晶粒附接於其基座，並更包含以一不足以 完全固化該黏性墊的溫度來固化該低溫黏劑。 11·如申請專利範圍第9項之方法，其中有—急促固化點劑 10 將該各第一半導體晶粒附接於其基座，並更包含固化該 急促固化黏劑而不固化該黏性塾。 12.如申請專利範圍第1〇項之方法，更包含將一第二半導體 晶粒附接於該各第一半導體晶粒上的黏性墊頂上並完 全地固化該黏性墊。 15丨3.如申請專利範圍第12項之方法，更包含將各第二半導體 晶粒以導線接結於在其各自的第一半導體晶粒底下之 該基座。 14.如申請專利範圍第13項之方法，更包含覆蓋成型一非傳 導性材料於該各第一與第二半導體晶粒疊塊上。 20 I5.如申請專利範園第8項之方法，更包含在個體化該晶圓 之前先部份地固化該等黏性墊。 16. 如申請專利範園第8項之方法，更包含在沈積黏劑圖案 之前先背磨該晶圓。 17. 如申請專利範園第8項之方法，其中該各黏性墊包含一 200929455 黏劑形成的環。 18. 如申請專利範圍第8項之方法，其中該各黏性墊係被幾 何狀地成形為一實心塊體。 19. 一種中間半導體產品，包含： 5 —半導體晶圓具有一背後表面與一主動表面，該半 ' 導體晶圓含有一由互相隔開之個別微電子電路等所形 * 成的陣列；及 一黏性墊的圖案設在該半導體晶圓的主動表面 〇 上，而被對準成使各微電子電路位於一該黏性墊的底下。 10 20.如申請專利範圍第19項之中間半導體產品，其中該黏劑 J系被部份地固化至B階段。 21. 如申請專利範圍第19項之中間半導體產品，其中該各黏 性墊包含一黏劑形成的環。 22. 如申請專利範圍第19項之中間半導體產品，其中該各黏 15 性墊係被幾何狀地成形為一實心塊體。 23. 如申請專利範圍第19項之中間半導體產品，其中該各黏 ® 性墊包含一黏性壁在該主動表面上具有一寬度，且由該 主動表面至該壁之一頂部具有一厚度，而該厚度對該寬 度之比係為至少1 : 1。 20 24. —種堆疊晶粒封裝體，包含： 一第一微電子半導體晶粒； 一黏性壁設在該晶粒頂上而在該晶粒上具有一寬 度且由該晶粒至該壁之一頂部具有一厚度，其中該厚度 對該寬度之比係為至少1 : 1 ;及 15 200929455 一第二微電子半導體晶粒固定在該黏性壁頂上，而 以該壁厚度來與該第一半導體晶粒分開。 25.如申請專利範圍第24項之堆疊晶粒封裝體，更包今一基 座其上係以一黏劑來附接該第一微電子半導體，而該黏 5 劑會在一比該黏性壁中之黏劑更低的溫度固化。
    16
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