TW200924133A - Multichip package structure and the forming method thereof - Google Patents

Multichip package structure and the forming method thereof Download PDF

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Publication number
TW200924133A
TW200924133A TW096145579A TW96145579A TW200924133A TW 200924133 A TW200924133 A TW 200924133A TW 096145579 A TW096145579 A TW 096145579A TW 96145579 A TW96145579 A TW 96145579A TW 200924133 A TW200924133 A TW 200924133A
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package
light
patterned
die
layer
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TW096145579A
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Chinese (zh)
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TWI358804B (en
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Wen-Yung Fu
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Chipmos Technologies Inc
Chipmos Technologies Bermuda
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Publication of TWI358804B publication Critical patent/TWI358804B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A multichip package structure is provided, which includes a plurality of chips, each chips have a plurality of pads on an active surface thereon; a package body is covered around the five sides of the chips and the active surface and the pads of the chip is to be exposed; a plurality of patterned metal traces, the two ends of the portion of the patterned metal traces are electrically connected to the plurality of pads of the chips, one end of the other portion of the metal traces is electrically connected to the pads of the chips; a patterned protective layer is covered on the patterned metal traces and another end of the patterned metal traces is to be exposed; a plurality of conductive elements is electrically connected to one end of the exposed portion of the patterned metal traces; and a heat sink is provided on the backside of the package body.

Description

200924133 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體封裝方法，特別是將不同尺寸大小及功能 之晶粒進行重新配置之封裝封方法。 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒(Dice) fί 必須具有多樣化的功能的需求，使得半導體晶粒必須要在很小的區域中配 置更多的輸入/輸出墊(I/O pads)，因而使得金屬接腳(pins)的密度也快速的 尚了。因此，早期的導線架封裝技術已經不適合高密度之金屬接腳；故 發展出一種球陣列(Ball Grid Array: BGA)的封裝技術，球陣列封裝除了有比 導線架封裝更高密度之優點外，其錫球也比較不容易損害與變形。 15¾•著3C產品的流行’例如：行動電話(Cell Phone)、個人數位助理(pda) 或疋iPod等’都必須要將許多複雜的系統晶片放入一個非常小的空間中， 因此為解決此一問題，一種稱為「晶圓級封裝（wafer level package ; wlp)」 I, 之封裝技術已經發展出來，其可以在切割晶圓成為一顆顆的晶粒之前，就 先對晶圓進行封裝。美國專利公告第5,323,051號專利即揭露了這種「晶圓 級封裝」技術。然而，這種r晶圓級封裝」技術隨著晶粒主動面上的焊塾(pads) 數目的加，使得焊墊(pads)之間距過小，除了會導致訊號耦合或訊號干擾 =外也會因為谭墊間距過小而造成封裝之可靠度降低等問題。因此， * aa粒再更進—步的縮小後’使得前述的封裝技術都無法滿足。 導^解決此_問題，類專利公告第7，19_號已揭露了—種將完成半 重製程之晶圓，經過測試及切割後，將測試結果為良好的晶粒（gooddie) 新放置於個基板之上，紐再進行封裝製程，如此，使得這些被重 放置的阳粒間具有較寬的間距，故可以將晶粒上的焊墊適當的分配，例 6 200924133 如使用向外延伸（fanout)技術，因此可以有效解決因間距過小，除了會導 致訊號耦合或訊號干擾的問題。 然而，為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶圓切 割前，會先對晶圓進行薄化處理，例如以背磨㈤咖也㈣呢）方式將晶 圓薄化至2 2Gmil豸後再切割成顆的n此—經過薄化處理之晶 粒’經過重新配置在另一基板上，再以注模方式將複數個晶粒形成一封裝 體；由於晶粒很薄，使得封裝體也是非常的薄，故當封裝體脫離基板之後， 封裝體本身的應力會使得難體產絲曲，增加後續進行切難程的困難。 另外，在晶圓切割之後，重新配置在另一個基板時，聽新的基板的 尺寸較原㈣尺寸為大，錢幢球製程中，會無法鮮，其封裝结 構可靠度降低。為此，本發明提供—種在進行晶圓切割之前，在晶圓背面 形成對準標諸(alignmentmark^可以有效地解決植球時無法對準以及封裝 體產生翹曲的問題。 此外’在整個封裝的過程中，還會產生植球時，製造設備會對晶粒產 生局部過大的壓力，而可能損傷晶粒的問題；同時，也可能因為植球的材 料造成與晶粒上的焊之電阻值敎，而影響晶粒之性能等問題。 【發明内容】 有鑒於發明背景巾所述之姆對準以及職馳曲關題，本發明提 供-種利解概之晶㈣新配置之封裝結構及其方法，來將複數 個3曰粒重新進行配置並進行封裝之方法。故本發明之主要目的在提供一種 在曰曰圓切#]之則先形成解觀，綠藉由解銳進行晶粒重新配置之 封裝方法’使得在植球之製程中可輯準之外，封裝體本身可以克服應力 而會使得封裝體在脫縣域，㈣平整，可有效提高製造之良率及可靠 度。 200924133 本發明之[主要目的在提供_種在晶粒重娜置之封裝方法，係將 不同尺寸大小及功能之晶粒重新配置在一基板上之封裝方法。 此外本明還有―主要目的在提供—種晶粒重新配置之封裝方法， 其可以將12叶晶圓所切割出來的晶粒重新配置於8忖晶圓之基板上，如此 可以有效賴8㈣圓之即有之封裝設備，而減重新設立12咐圓之封 裝設備，可以降低12吋晶圓之封裝成本。 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使得進 行封裝的晶片都是，，已知是功能正常之晶片，，（KnQwn gGQd也），可以節省 封裝材料，故也可以降低製程之成本 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使得進 行封裝的晶片都是，’已知是功能正常之晶片，，（Kn〇wn g〇〇d die)，可以節省 封裝材料，故也可以降低製程之成本。 根據以上所述，本發明提供一種模組化之多晶粒封裝方法，包括:提供 複數個晶粒，每一晶粒具有一主動面且主動面上配置有複數個焊墊；取放 複數個晶粒至一基板上，每一晶粒係以覆晶方式將主動面與一配置於基板 上的黏著層連接；形成一高分子材料層在基板及部份晶粒之一下表面上； 脫離基板，以曝露出母一晶粒之主動面及每一焊墊，以形成一封裝體；形 成複數個圖案化之金屬線段，部份複數個圖案化之金屬線段之兩端電性連 接複數個晶粒之主動面上的複數個焊墊，部份複數個圖案化之金屬線段之 端電性連接複數個晶粒之主動面上的複數個焊墊；形成圖案化之保護層 以覆蓋複數個圖案化之金屬線段，並曝露部份複數個圖案化之金屬線段之 另一端；形成複數個導電元件，係將複數個導電元件電性連接在已曝露之 每—圖案化之金屬線段之另一端上；及切割封裝體，以形成複數個模組化 之多晶粒封裝結構。 本發明揭露另一種發光二極體重新配置之封裝方法，包括:提供複數個 200924133 發光二極體’每一發光二極體具有一主動面且主動面上具有一 P電極及一 N 電極；取放複數個發光二極體至一基板上，每一發光二極體係以覆晶方式 將主動面與一配置於基板上的黏著層連接；形成一高分子材料層於基板及 部份發光二極體之一下表面上；平坦化高分子材料層，使高分子材料層充 滿於複數個發光二極體之間並包覆每一發光二極體之一下表面；脫離模具 裝置，以曝露出每一發光二極體之主動面以及每一電極以形成一封裝體； 形成複數個圖案化之金屬線段，複數個圖案猾之金屬線段之一端分別電性 連接每一發光二極體之主動面上之每一 p電極及每一 N電極，而另一端分 別共接於一向外延伸之金屬線段；形成一圖案化之保護層以覆蓋複數個圖 案化之金屬線段，並曝露出複數個圖案化之金屬線段之向外延伸之的兩端 之部份表面；形成複數個導電元件，係將複數個導電元件電性連接在已曝 露之向外延伸之金屬線段之表面上；及切割封裝體，以形成複數個模組化 之之發光二極體封裝結構。 本發明揭露-種發光二極體重新配置之封裝結構，包括:複數個發光二 極體’每—發光二極體具有—主動面且主動面上配置有-P電極及一 N電 極，-封裝體，係環覆於每-發光二極體之五個面且曝露出每—發光二極 體之主動面及每-P電極及每—N電極；複數個圖案化之金屬線段，係盆 —端分別電性連接每-發光二極體之主動面上之每_ p電極及n電極，^ 另了端則分別共接於-向外延伸之金屬線段；—圖案化之保護層，用以覆 蓋複數個圖案化之金屬線段’且曝露出向外延伸之金屬線段的部份表面； 及複數個導電元件’係形成在已曝露之向外延伸之表面上，以形成電 接。 曰本發明另揭露-種模組化之多晶粒封裝、结構，包括:複數個晶粒，每一 j具有-主動面且主動面上配置體複數個焊墊；—封裝體，係環覆於每 金屬紅，部份Μ化之金屬線段之兩端電性連接複數減粒之主動面上 200924133 的複數個烊墊，而也 動面上之複數二圖=之金屬線段之一端電性連接_^^ 段並曝露部份_化之^ 保護層，係覆蓋複數侧案化之金屬線 '、 金屬線段之另一端；形成複數個導電元件，俜將複 散鮮置，做/ 每—職化之金屬線段之另-端上及一 、聚置細成於封裝體之-背面上。 ’茲配合圖示作最佳實施例詳細說明如下。 、特徵、及其功能有進一步的瞭解，茲配合 有關本發明的特徵與實作 (為使對本發明的目的、構造 實施例詳細說明如下。） 【實施方式】 粒討的方向為一種晶粒重新配置之封裝方法，將複數個晶 明 ；—基板上’然後進行封裝的方法。為了能徹底地瞭解本發 二將在下觸描射提出詳錢步驟及該成。麵地，本發明的施行 並未限定w堆疊的方式之技藝者職制特殊細節。另—方面，眾所周 =的晶片形成方式収w薄化科段_之詳細步縣未贿於細節 怜以避免造成本發明不必要之限制。然而，對於本發明的較佳實施例， 則會詳細描述如下’細除了這些詳細描述之外，本發明還可以廣泛地施 行在其他的實_中，且本發_範圍不纽定，其狀後的專利 準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程喊制 p_ss)之晶圓（wafer)先進行薄化處理（Thinningpr_s)，例如將晶片 的厚度研磨至2〜20 mil之間；然後，進行晶圓的切割（隱吨p職ss)以 形成-顆顆的晶粒11G ;然後，使用取放裝置（piekandplaee)將—顆顆的 晶粒逐-放置於另-個基板上，如第i圖所示。很明顯地，基板满 上的晶粒間隔區域比晶粒11G大，因此，可以使得這些被錢放置的晶粒 110間具有較寬的間距’故可以將晶粒11〇上的焊墊適當的分配。此外，本 200924133 所使姆齡法，可謂12叶晶__來_⑽重新配 置於‘圓之基板上，如此可以有效· 8他社即有之封裝設備， 而無需重新設立12咐圓之封裝設備，可以降低12㈣圓之封裝成本。 然後要強觸是，本發明之實補並未限讀“㈣社小之基板，立 嫌= 她觸，齡··補、辟、嘱金屬薄板 )等，均可作為本實施例之基板⑽，因此基板_雜也未 加以限制。 請參考第2圖，係表示一基板其背面具有對準標諸俯視圖。如第2圖， 係表不在晶·板的上表面上之麵的x_y方向上，設置有複數個對準標總 (alg_t ma_h由先前陳述所知，當—晶圓(未在圖中㈣，例如具 有f數個微處理晶粒(mic零〇cess〇r)之晶圓'具有複數個記，_ 或是具杨數個記湖晶粒之晶31經過_之後形成複數個晶粒，再 重新將廷些晶粒逐-配置在新的基板1G冑，其中在新的基板上的晶粒因 .在，的基板上可以是複數個綱功能及尺寸的晶粒，例如—記憶體模 組；或是由不同功能及尺寸之晶粒_成之—晶粒模組，例如由微處理晶 粒(mlcroprocessor)、記憶體晶粒(m_^或是記憶體控制晶粒(mem〇w r)所、.且成之Ba粒模組。由於新的基板1()之間的晶粒間隔區域比重新 配置的晶粒大，在後續封裝製㈣植球步驟(baii_nt)會無法對準，而將導 電讀(未在W巾表示)準摘形成在晶粒的背面上所需陳置，而造成封裝 結構的可靠度降低。，在本發_具體實施财，軸鮮標諸3〇2 的方式可以利用光侧(photo_etching)製程，其係在基板的背面且在π方 ^上形成複數個對準標諸302，且其形狀為十字之標誌、。另外，形成對準標 〜3〇2的方式還包括利用雷射標籤(1織贿幻製程，以形成複數個對準標總 302在基板的背面上。 接著’第3圖至第6圖係表示本發明所揭露之晶粒重新配置之實施例之 各步驟不_。首先’如第3騎示，先提供—基板⑴，並在基板1〇上配 200924133 置有-黏著層2G’此黏著層2G為-具有彈性之黏著材料，例如秒橡膠卿〇n 滿er)、矽樹脂(础c〇nresin)、彈性pu、多孔pu、丙稀酸橡膠(吻^ 或晶粒切割膠等。接著，使用取放裝置(未在圖中表示)將複數個好的晶粒· 逐-放置並貼附至基板1G上的黏著層2〇，其中晶粒⑽係以覆晶(flip chip) 方式將其主動面上的焊墊312與基板1G上的黏著層2()連接。此外，要強 調的是，在此取放過程中，取放裝置(未在圖中表示)會根據每_顆晶粒31〇 的背面上的對準標諸3〇2以及參考基板1〇上的複數個鱗標諸(未在圖中表 示)的位置後’準確地將每一顆晶粒310與基板1〇上的黏著層2〇連接。因 此’每-顆晶粒31G之主動面上的焊墊312位置均為已知，故可解決後續 進行金屬線連接時的對準問題。 接下來’請繼續參考第3圖，當複數個好的晶粒31〇已被準確地放置並 貼附至基板10上義著層2G之後，接著，於基板⑴及部份晶粒上3ι〇上 塗佈高分刊騎4G，其巾此高好材料層4G可以切膠 烯酸（aciylic)、及苯環丁烯（BCB)等材料；然後，使用一模具裝置曰 將高分子材料層⑽壓平，使得高分子材㈣*形成—平坦制表面，並 且使得高分子材料層4G填滿於晶粒31G之間並且每-顆晶粒3ω的五個面 均由高分子材料層40所包覆。 然後，可以選擇性地對平坦化的高分子材料層4〇進行一烘烤程序，以 使高分子材料層40固化。再接著，進行脫模程序，將模具裝置5⑻與固化 後的高分子材料層40分離，以裸露出平坦化的高分子材料層4〇的表面， 如第4圖所示。接著’將高分子材料層4〇與黏著層2〇分離，例如將高分 子材料層40與基板1〇 -起放入去鮮水的槽中，使高分子材料層4〇無 著層2〇分離’形成一個封裝體；此封裝體包覆每一顆晶粒训，並且只曝 露出每一晶粒310之主動面上的焊墊312。再接著，可以選擇性地使用切割 刀（未顯示於圖中）在高分子材料層40的表面上形成複數條切割道仙， 如第4圖所示；每一切割道41〇的深度為MM密爾（mU)，而切割道41〇 12 200924133 之寬度則為5至25微米。在一較佳實施例中，此切割道41〇可以是相互垂 ^父錯’並且可以作騎際蝴晶㈣的參考線。由於在封裝體之相對於 b曰粒31G之主動面之背面形成有複數條切割道仙，因此當高分子材料層 與土板10剝離後，封裝體上的應力會被這些切割道41〇所形成的區域所 抵消，故可有效地解決封裝體翹曲的問題。 接著’參考第5圖至第6 κ，係表示在複數個晶粒⑽上形成複數個圖 案化之金屬線段之俯_。在本實施财，已先以轉體製程將封農體上 的複數個日日粒310之主動面上的每一個焊墊312都曝露出來。接著，即可 在曰曰粒310的主動面的焊墊312上形成複數個圖案化之金屬線段％，每一 條金屬線& 5〇之向外延伸之兩端係以串聯的方式分別電性連接相鄰之每— β曰粒310 _L之焊^* 312 ,而形成複數個圖案化之金屬線段之步驟包含：首 先’形成-金屬層50A在每-晶粒31〇之主動面之每—焊塾312上，如第$ 圖所不’接著’侧半導體製程技術，例如：以塗佈、顯影及_等方式， 先形成-®案化光阻層(未細巾表示)在金屬層氣之上丨然後贿刻方式 來移除部份金麟5GA之後，·_案化之光阻層；因此，可以依據所 需要，電性連接方式來形成複數個圖案化之金屬線段％;而在本實施例 :’每-圖案化之金屬線段5〇之向外延伸之兩端係電性連接至相鄰之每— 晶粒310上之複數個焊墊312，使得相鄰的每一晶粒31〇彼此係以_聯的方 式電性連接；然而’此串聯的電性連接方式僅為本發明之—實施例，盆目 的僅在揭露制_化的金屬製程，可以將複數個晶粒依據所要的電性連 接方式完舰接。由上所述，可靖複數個晶粒31()財截並聯方式形 成一模組(mo·)，例如：Dram模組，如第6圖所示。此外，金屬線段 5〇可以是由銅、金或銅合金等材料所形成，同時，金屬線段％也可以是由 -UBM金屬層來形成，此麵金屬層之材料可以是職或是挪心。 在此要強調的是’本發明在將複數個好的晶粒31〇重新配置在另一基板 1〇的過程中，由於每-晶粒31G的背面上都有對準標誌屬同時可以ς一 13 200924133 步參考基板ω上的複數個對準標諸的錄後，每一顆晶粒之主動面上 的焊墊312位置均為已知，故可解決後續進行金屬線連接時的對準問題。 因在使用回刀子材料40形成封裝體後，由於每-晶粒3ι〇的5個面都 被高分子材料層4G所包覆，僅有晶粒310之主動面上的焊墊3!2曝露出來， 而此主動面上的焊墊312位置是可以確定的故可以依據本發明所揭露之 方式’將複數個相同或是不相同的好的晶粒31()封裝在―起，#遭以半導 =裝程來域®案化的金屬線％將所餘合賴組（购臟的複數個 曰曰粒310電座連接在一起。例如：將4顆25脱的服施曰曰曰粒以串連或並 連的方式難在-起’軸-個域容量為1(}之記賴組；献，將複數 個發光一極體（LED)串接成—個柱狀絲或是並連成—面狀杨；或是， 將不同魏、柯大小之晶粒封裝成—綠等，都可藉由本實施例來達成。 以下將會進一步的說明。 此外在上述實_巾’形成平坦化的高好材㈣⑻的方式可以選 擇使用注模方式（祕ngproeess)來形成。此時，將一模具裝置$⑻覆蓋 ^板10上，並且使模具裝置500與晶粒31〇間保持一空間，因此可以將 咼分子材料層4G，例如環氧細旨模珊料(Ep()xy Mdding CGmp_d ; EMC), /主入模具裝置5〇〇與晶粒31〇的空間中’使得高分子材料層形 成平坦化的表面並且使得高分子材料層4〇充滿於晶粒31〇之間並包覆每 曰曰才：310由於，使用注模方式來包覆每一晶粒Μ。之後，其製造過程與 前述方式相同，故不再贅述之。 接著’請參考第7圖’係為上述第6圖之—俯視圖（即第6圖為第7 圖在AA剖面的不意圖第7圖係表示每一晶粒31〇之間係利用金屬線段 5〇以串聯的方式電性連接以形成―模組，其巾可使用四個姻尺寸大小及 ^能之晶粒31G (例如：DRAM)形成晶粒模組或是兩個晶粒形成一模組。 當然，也可以將兩兩並排之晶粒以串聯及並聯之方式連接成一模組。然而， 將複數個晶粒串聯及並聯連接在—起之方式，即可軸歧第3圖至第6 200924133 圖的過程中完成。 接著’請參考第8圖，係表示形成一 LED發光模組之示意圖。如第8 圖所示，晶粒320係為發光二極體(LED)’每一發光二極體320的P電極322 與相鄰的發光二極體320的P電極322電性連接；而發光二極體320的N 電極321係與相鄰的發光二極體32〇的n電極321電性連接，且每一發光 二極體320之N電極321及p電極322係藉由金屬線段50分別與焊塾70 電性連接。同樣地，本發明也不限定發光二極體320之數量或是其電性連 接之方式，例如：將複數個發光二極體（LED)串接成一個柱狀光源或是並 連成一面狀光源；同時，本發明也不限定發光二極體320之發光顏色，即 發光二極體320可以是紅光發光二極體或綠光發光二極體或藍光發光二極 體或其他顏色之發光二極體（例如：白光）或是前述發光二極體之組合等。 另外，如第9圖所示，係將不同功能或不同大小之晶粒封完成封裝之上視 圖。很明顯地，這些晶粒模組係由複數個晶粒所構成之系統級封裝 (System-In-Package; SIP)，這些晶粒至少包含微處理裝置 3〇5(micr〇prOeessOT means)、記憶體裝置310(mem〇ry means)或是記憶體控制裝置 controller means);其中每一晶粒之主動面上具有複數個焊墊，且在每一晶 粒的焊墊上形成複數條金屬線段，以串聯或是並聯的方式電性連接相鄰之 晶粒並與導電元件電性連接。 在刖述將每一顆晶粒完成模組化的封裝及電性連接後，緊接著，要進 打對外連接元件的配置。如第10A圖所示，在完成模組化的電性連接後， 隨即在封裝體之具有金屬線段的面上，形成一圖案化之保護層6〇 (例如. Pdyimide)以覆蓋複數侧案化之金屬線段5G，並在金屬線段％之向外延 伸之兩端之部份表面上形賴口 62，以便曝露出魏個圖案化之金屬線段 5〇的另-端。此形成圖案化之保護層6〇的步驟包括:形成一保護層= 數個圖案化之金祕段50上轉體餘，例如顯影，絲成—圖案 化之光阻層(未在圖中表示)在保護=60上；接著，在進行顯影後，移除相 200924133 對於複數個圖案化之金屬線段50之向外延伸之兩端上之保護層以形成開口 62，即可曝露出位於開口 62下之複數個圖案化之金屬線段5〇之向外延伸 之兩端之部份表面。 緊接著，如第10B圖所示，係在保護層60之複數個開口 62處形成複 數個導電元件7G，其中導電元件7〇可以是錫球(sdder ba戦是金屬凸塊 (metal bump)。最後’即可切割封裝體，以形成複數個完成封裝之模組。很 明顯地’第10A圖及第10B暇相對第7圖之封裝形式。此外，如第u圖 所示’係顯示第8圖沿BB線段之剖式圖及第9圖沿CC線段之剖式圖。 ^第11圖所示為第9圖之系統級封裝(System_；[n_package ; Sip)時，在 本發明的另—較佳實關巾，可以在封裝體之背面上獅-散熱片，如第 12A圖所示；或是選擇先藉由薄化製程，使得被封裝體包覆之晶粒之背面曝 露出來後，再於已曝露之晶粒之背面上黏貼-散熱片，如f 12B圖所示。 此外’要強調的是’這種黏貼散熱片的實施方式，也適用在第7圖之實施 例中同時’黏貼散熱片的時間’可以選擇在封裝體進行切之前或是選 擇在封裝體進彳了_之後’都為本個之實施方式，本發明並未加以限制。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發 明，任何熟習相像技藝者，在不脫離本發明之精神和範圍Θ，當可作些許 此本她糊纖嶋糊細之申料利 【圖式簡單說明】 第1圖係表示先前技術之示意圖； 在具有對準標§志之基板之背面之 第2圖係根據本發明所揭露之技術 封裝結構之俯視圖；及 200924133 粒重係根據本發明所揭露之技術，晶圓對準標誌、之晶 裝方法形成之封裝結構之各步驟示意圖； 第7圖係根據本發明所揭露之技術，係絲第6圖之俯視圖； 成雷露之技術’絲示在複數個發光二極體上形 成電性連接之示意圖； 第圖係根據本發明所揭露之技術，表示在複數個晶粒上形成電性連 接之不意圖； 第10A圖係根據本發明所揭露之技術，係表示在複數個金屬線段上形 成保護層之示意圖； 第10B圖係根據本發明所揭露之技術，係表示在封裝結構上形成複數 個導電元件之示意圖； 第11圖係根據本發明所揭露之技術，係表示第8圖沿BB線段之剖式 圖及第9圖沿cc線段之剖式圖；及 第12A圖係根據本發明所揭露之技術，表示具有散熱裝置之封裴結構 之示意圖；及 第12B圖係根據本發明所揭露之技術’表示經薄化之封裝結構之示魚 圖。 【主要元件符號說明】 10基板 20黏著層 100 基板 17 200924133 110 晶粒 302對準標誌 305 微處理裝置 310晶粒/記憶體裝置 312焊墊 315 記憶體控制裝置 320 發光二極體 40高分子材料層 410切割道 50金屬線段 60保護層 70導電元件 500模具裝置200924133 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor packaging method, and more particularly to a package sealing method for reconfiguring die of different sizes and functions. [Prior Art] The technology of semiconductors has been developed quite rapidly, so the miniaturized semiconductor die (Dice) must have a variety of functions, so that the semiconductor die must be configured in a small area. The input/output pads (I/O pads) thus make the density of the metal pins fast. Therefore, the early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. In addition to the higher density than the lead frame package, the ball array package has the advantages of higher density than the lead frame package. Its tin ball is also less susceptible to damage and deformation. 153⁄4• The popularity of 3C products, such as: Cell Phone, Personal Digital Assistant (PDA) or 疋iPod, etc., must put many complicated system chips into a very small space, so to solve this One problem, a kind of packaging technology called "wafer level package (wlp)" I, has been developed to encapsulate wafers before they are diced into individual dies. . This "wafer level packaging" technique is disclosed in U.S. Patent No. 5,323,051. However, this r-wafer-level package technology increases the number of pads between the pads on the active side of the die, so that the distance between the pads is too small, in addition to signal coupling or signal interference. Because the pitch of the tan pad is too small, the reliability of the package is reduced. Therefore, the *aa grain is further advanced and the step-down is reduced, so that the aforementioned packaging technique cannot be satisfied. To solve this problem, the patent publication No. 7, 19_ has revealed that the wafer will be completed in a semi-heavy process. After testing and cutting, the test result is a good good die. On the substrate, the button is then packaged, so that the repositioned anodes have a wider spacing, so that the pads on the die can be properly distributed. Example 6 200924133 Fanout) technology can effectively solve the problem that the spacing is too small, except for signal coupling or signal interference. However, in order to enable the semiconductor wafer to have a smaller and thinner package structure, the wafer is thinned before wafer dicing, for example, by back grinding (five) (4) After 2 2Gmil 豸 and then cut into pieces of n - the thinned film 're-disposed on another substrate, and then injection molding a plurality of grains into a package; because the grain is very thin Therefore, the package body is also very thin, so after the package body is separated from the substrate, the stress of the package body itself makes it difficult to produce a filament, which increases the difficulty of subsequent cutting difficulties. In addition, after the wafer is diced and re-arranged on another substrate, the size of the new substrate is larger than the original (four) size, and it is not possible in the process of the money ball process, and the reliability of the package structure is lowered. To this end, the present invention provides an alignment mark on the back surface of the wafer before wafer dicing (alignment mark can effectively solve the problem of misalignment and warpage of the package when the ball is implanted. During the process of encapsulation, when the ball is implanted, the manufacturing equipment will locally exert excessive pressure on the crystal grains, which may damage the crystal grains. At the same time, it may also cause resistance to the solder on the crystal grains due to the material of the ball. The value of 敎, which affects the performance of the grain, etc. [Invention] In view of the invention of the background towel and the title of the game, the present invention provides a package structure for the new configuration of the crystal (4) And the method thereof, the method of reconfiguring and encapsulating a plurality of 3 granules. Therefore, the main object of the present invention is to provide a solution in the case of 曰曰圆切#], and the crystallization is performed by the solution The packaging method of particle reconfiguration makes the package itself overcome the stress, which can make the package in the county, and (4) leveling, which can effectively improve the manufacturing yield and reliability. 200924133 The main purpose of the present invention is to provide a packaging method for re-distributing different sizes and functions of a die on a substrate. The purpose of the invention is to provide a packaging method for re-disposing a crystal grain, which can reconfigure the die cut by the 12-leaf wafer on the substrate of the 8 忖 wafer, so that it can effectively rely on the packaging equipment of the 8 (four) circle. The reduction of the packaging cost of the 12-inch wafer can reduce the packaging cost of the 12-inch wafer. Another main object of the present invention is to provide a package method for die re-configuration, so that the packaged wafers are all known. It is a functioning chip, (KnQwn gGQd also), which can save packaging materials, so it can also reduce the cost of the process. Another main object of the present invention is to provide a chip reconfiguration packaging method, so that the packaged wafers are , 'Kn〇wn g〇〇d die, which is known to be a functioning chip, can save packaging materials, so it can also reduce the cost of the process. The present invention provides a modular multi-die package method, comprising: providing a plurality of dies, each die having an active surface and having a plurality of pads disposed on the active surface; picking and placing a plurality of dies to On a substrate, each of the crystal grains is connected to an adhesive layer disposed on the substrate by flip chip bonding; a polymer material layer is formed on the lower surface of one of the substrate and the partial crystal grains; and the substrate is separated from the substrate to expose The active surface of each die and each pad are formed to form a package; a plurality of patterned metal segments are formed, and the active ends of the plurality of patterned metal segments are electrically connected to the plurality of die a plurality of pads on the surface, the ends of the plurality of patterned metal segments being electrically connected to the plurality of pads on the active faces of the plurality of crystal grains; forming a patterned protective layer to cover the plurality of patterned metals a line segment and exposing a portion of the plurality of patterned metal line segments; forming a plurality of conductive elements electrically connecting the plurality of conductive elements to the other end of each of the exposed metal line segments; and Cut package body to form a plurality of modular die package structure as much. The present invention discloses another method for packaging a light-emitting diode reconfiguration, comprising: providing a plurality of 200924133 light-emitting diodes each having an active surface and having a P electrode and an N electrode on the active surface; The plurality of light emitting diodes are stacked on a substrate, and each of the light emitting diodes is connected to the adhesive layer disposed on the substrate by flip chip bonding; forming a polymer material layer on the substrate and a part of the light emitting diode a lower surface of the body; planarizing the polymer material layer such that the polymer material layer is filled between the plurality of light emitting diodes and covering a lower surface of each of the light emitting diodes; and the mold device is removed to expose each An active surface of the light-emitting diode and each of the electrodes to form a package; forming a plurality of patterned metal line segments, one of the ends of the plurality of metal lines of the pattern is electrically connected to the active surface of each of the light-emitting diodes Each of the p-electrodes and each of the N-electrodes are connected to an outwardly extending metal line segment; and a patterned protective layer is formed to cover the plurality of patterned metal segments. Exposing a portion of the surface of the outwardly extending ends of the plurality of patterned metal segments; forming a plurality of conductive members electrically connecting the plurality of conductive members to the surface of the exposed outwardly extending metal segments And cutting the package to form a plurality of modular LED package structures. The invention discloses a package structure for reconfiguring a light-emitting diode, comprising: a plurality of light-emitting diodes each of the light-emitting diodes having an active surface and having a -P electrode and an N electrode on the active surface, - packaging The body is covered on each of the five faces of each of the light-emitting diodes and exposes the active surface of each of the light-emitting diodes and each of the -P electrodes and each of the N-electrodes; a plurality of patterned metal line segments, and a basin - The terminals are electrically connected to each of the _p electrodes and the n electrodes of the active surface of each of the light emitting diodes, and the other ends are respectively connected to the outwardly extending metal line segments; the patterned protective layer is used for Covering a plurality of patterned metal segments 'and exposing a portion of the surface of the outwardly extending metal segment; and a plurality of conductive elements' are formed on the exposed outwardly extending surface to form an electrical connection. The present invention further discloses a modular multi-die package and structure, comprising: a plurality of dies, each j having an active surface and a plurality of pads on the active surface; - a package, a ring In each metal red, the two ends of the metallized wire segment are electrically connected to a plurality of cymbal pads of the active surface of the plurality of granules 200924133, and the plurality of wires of the metal wire segment of the second surface of the moving surface are also electrically connected. Connect the _^^ section and expose part of the _化^protective layer, covering the metal wire of the complex side, and the other end of the metal wire segment; forming a plurality of conductive elements, which will be re-distributed fresh, do / per- On the other end of the metal segment of the service, and on the back side of the package. The following is a detailed description of the preferred embodiment in conjunction with the drawings. Further understanding of the features, functions, and functions thereof is provided in conjunction with the features and implementations of the present invention (for the purpose of the present invention, the structural embodiments are described in detail below.) [Embodiment] The orientation of the grain is a grain re- The package method of the configuration will be a plurality of crystal clears; the method on the substrate is then packaged. In order to thoroughly understand the hair, the second step will be to present the detailed money steps and the completion. In particular, the practice of the present invention does not define the specific details of the skill of the art in the manner of w-stacking. On the other hand, the wafer formation method of the public is reduced. The detailed step counts are not bribed in detail to avoid unnecessary restrictions on the invention. However, for the preferred embodiment of the present invention, the following detailed description will be described in detail. In addition to the detailed description, the present invention may be widely practiced in other embodiments, and the present invention is not limited in scope. After the patent is approved. In the modern semiconductor packaging process, a wafer (wafer) that has completed the pre-process p_ss) is first thinned (Thinningpr_s), for example, the thickness of the wafer is ground to between 2 and 20 mils; Cutting the wafer (his ss) to form a grain 11G; then, using a picking device (piekandplaee) to place the grains on the other substrate, such as Figure i shows. Obviously, the die-spaced area of the substrate is larger than that of the die 11G, so that a wide pitch between the deposited crystal grains 110 can be made, so that the pads on the die 11 can be appropriately formed. distribution. In addition, this 200924133 method of the ageing method can be described as 12 leaf crystal __来_(10) reconfigured on the 'round substrate, so it can be effective. 8 The company has its packaging equipment, without having to re-establish the 12-inch packaging equipment. Can reduce the packaging cost of 12 (four) round. Then, the strong touch is that the actual compensation of the present invention is not limited to "(4) the small substrate of the society, the suspect = her touch, the age, the complement, the thin, the thin metal sheet), etc., can be used as the substrate of the embodiment (10) Therefore, the substrate_hetero is also not limited. Please refer to Fig. 2, which shows a substrate having a back surface with an alignment plan. As shown in Fig. 2, the surface is not in the x_y direction of the surface on the upper surface of the crystal plate. , set with a plurality of alignment targets (alg_t ma_h known from the previous statement, when - wafer (not in the figure (four), for example, wafers with f micro-processed grains (mic zero 〇cess〇r)' With a plurality of records, _ or a number of crystal grains 31 with a number of lakes, after forming a plurality of crystal grains, the crystal grains are again arranged on the new substrate 1G, in which a new substrate is formed. The upper die may be a plurality of die and size die, for example, a memory module; or a die of different functions and sizes - for example, a die module, for example From the micro-processor (mlcroprocessor), the memory grain (m_^ or the memory control grain (mem〇wr), and the Ba grain mode Since the die spacing area between the new substrates 1() is larger than the reconfigured grains, the subsequent packaging (4) ball implantation step (baii_nt) may not be aligned, and the conductive reading will be performed (not indicated in the W towel). The quasi-pickup is formed on the back side of the die, which results in a decrease in the reliability of the package structure. In the present invention, the method of photo-etching can be utilized by the method of photo-etching. It is formed on the back surface of the substrate and forms a plurality of alignment marks 302 on the π square, and the shape thereof is a mark of the cross. In addition, the manner of forming the alignment marks 〜3〇2 further includes using the laser label ( 1 woven bribery process to form a plurality of alignment labels 302 on the back side of the substrate. Next, 'Fig. 3 through 6 show the steps of the embodiment of the crystal reconfiguration disclosed in the present invention. First, as shown in the third riding, the substrate (1) is provided first, and the substrate 1 is equipped with 200924133 with the adhesive layer 2G'. The adhesive layer 2G is an elastic adhesive material, such as a second rubber 〇n full er) , 矽 resin (basic c〇nresin), elastic pu, porous pu, acrylic rubber (kiss ^ or grain cutting) Glue, etc. Next, a plurality of good dies are placed and attached to the adhesive layer 2 on the substrate 1G using a pick-and-place device (not shown), wherein the crystal grains (10) are flipped (flip) Chip) is to connect the pad 312 on the active surface to the adhesive layer 2 () on the substrate 1G. In addition, it should be emphasized that during the pick and place process, the pick-and-place device (not shown) will be The alignment on the back side of each of the 31 dies 31 marks 3 〇 2 and the position of a plurality of scales on the reference substrate 1 ( (not shown in the figure) 'accurately each of the dies 310 It is connected to the adhesive layer 2〇 on the substrate 1〇. Therefore, the position of the pad 312 on the active surface of each of the die 31G is known, so that the alignment problem in the subsequent connection of the metal wires can be solved. Next, please continue to refer to Figure 3, after a plurality of good dies 31〇 have been accurately placed and attached to the substrate 2G on the substrate 10, and then on the substrate (1) and part of the die 3 〇 The coated high-grade magazine rides 4G, and the high-quality material layer 4G can cut materials such as aciylic and benzocyclobutene (BCB); then, a polymer device layer is used to form a polymer material layer (10). The flattening causes the polymer material (4)* to form a flat surface, and the polymer material layer 4G is filled between the crystal grains 31G and the five faces of each of the crystal grains 3ω are covered by the polymer material layer 40. cover. Then, the planarized polymer material layer 4 can be selectively subjected to a baking process to cure the polymer material layer 40. Next, a mold release process is performed to separate the mold device 5 (8) from the cured polymer material layer 40 to expose the surface of the planarized polymer material layer 4, as shown in Fig. 4. Then, 'the polymer material layer 4〇 is separated from the adhesive layer 2〇, for example, the polymer material layer 40 and the substrate 1 are placed in a groove for fresh water, so that the polymer material layer 4 has no layer 2〇. Separating 'forms a package; this package covers each die and exposes only pads 312 on the active side of each die 310. Then, a plurality of dicing streets can be selectively formed on the surface of the polymer material layer 40 by using a dicing blade (not shown), as shown in FIG. 4; the depth of each scribe line 41 为 is MM dense (mU), while the cutting path 41〇12 200924133 has a width of 5 to 25 microns. In a preferred embodiment, the scribe lines 41 〇 may be mutually offset and may be used as reference lines for the rider (four). Since a plurality of dicing streets are formed on the back surface of the active surface of the package relative to the b-grain 31G, when the polymer material layer is detached from the soil plate 10, the stress on the package is formed by the scribe lines 41. The area is offset, so the problem of package warpage can be effectively solved. Next, referring to Figs. 5 to 6 κ, it is shown that a plurality of patterned metal line segments are formed on a plurality of crystal grains (10). In the implementation of the present invention, each of the pads 312 on the active surface of the plurality of solar particles 310 on the agricultural body is exposed first. Then, a plurality of patterned metal line segments % can be formed on the pads 312 of the active surface of the enamel particles 310, and the outwardly extending ends of each of the metal wires & amps are electrically connected in series. The step of connecting a plurality of adjacent 曰 310 310 310 310 310 310 310 312 , , , , , , 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接 连接On the soldering pad 312, as shown in Figure #, the 'semiconductor' side-side semiconductor process technology, for example, coating, developing, and the like, first forming a --case photoresist layer (not shown by the thin film) in the metal layer gas On top of the 丨 and then bribes to remove some of the Jinlin 5GA, _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In this embodiment, the two ends of each of the outwardly extending metal segments 5 are electrically connected to a plurality of pads 312 adjacent to each of the die 310 so that each adjacent die 31〇 are electrically connected to each other in a _ way; however, the electrical connection of the series is only the present invention. In the embodiment, the metal substrate of the basin can be connected to the metal system according to the desired electrical connection. From the above, a plurality of crystal grains 31 () can be formed in parallel to form a module (mo·), for example, a Dram module, as shown in Fig. 6. In addition, the metal wire segment 5〇 may be formed of a material such as copper, gold or a copper alloy, and at the same time, the metal wire segment % may also be formed of a -UBM metal layer, and the material of the metal layer may be a job or a heart. It should be emphasized here that the present invention is in the process of reconfiguring a plurality of good crystal grains 31〇 on another substrate, since the alignment marks on the back surface of each of the crystal grains 31G can be simultaneously 13 200924133 After the reference number of alignment marks on the reference substrate ω, the position of the pad 312 on the active surface of each die is known, so the alignment problem in the subsequent metal wire connection can be solved. . Since the five faces of each of the grains 3 〇 are covered by the polymer material layer 4G after the package body 40 is formed by using the backing material 40, only the pads 3! 2 on the active surface of the die 310 are exposed. And the position of the pad 312 on the active surface is determinable, so that a plurality of identical or different good dies 31() can be packaged in the manner disclosed in the present invention. The semi-conductor = process-to-domain ® case of the metal wire % will be connected to the remaining group (the dirty number of 曰曰 310 310 310 110 110 110 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 310 It is difficult to connect or connect in parallel with the axis-domain capacity of 1 (} in the group; to provide a plurality of light-emitting diodes (LED) in series as a columnar wire or in parallel - planar poplar; or, encapsulation of different Wei and Ke size grains into - green, etc., can be achieved by this embodiment. It will be further explained below. In addition, the above-mentioned real towel is flattened. High-quality materials (4) (8) can be formed by using injection molding methods (secret ngproeess). At this time, a mold device $(8) is covered on the board 10 Moreover, the mold device 500 and the die 31 are kept in a space, so that the molecular material layer 4G, for example, epoxy resin (Ep()xy Mdding CGmp_d; EMC), / main mold device 5〇 can be used. The space between the crucible and the 31 〇 of the crystal grains is such that the polymer material layer forms a flattened surface and the polymer material layer 4 〇 is filled between the crystal grains 31 并 and covers each 曰曰: 310 due to the use of injection molding The method is to cover each of the die Μ. After that, the manufacturing process is the same as that described above, and therefore will not be described again. Then, please refer to FIG. 7 for the above-mentioned FIG. 6 - top view (ie, FIG. 6 is the first 7 is not intended to be in the AA section. Figure 7 shows that each of the 31 〇 is electrically connected in series by a metal wire segment 5 以 to form a module, which can use four sizes and ^Energy die 31G (for example: DRAM) forms a die module or two die forms a module. Of course, it is also possible to connect two or two side-by-side die in series and parallel to form a module. , the plurality of dies are connected in series and in parallel, and the axis is 3rd. The figure is completed in the process of Figure 6 200924133. Next, please refer to Figure 8 for a schematic diagram of forming an LED lighting module. As shown in Figure 8, the die 320 is a light emitting diode (LED). The P electrode 322 of each of the LEDs 320 is electrically connected to the P electrode 322 of the adjacent LED 320; and the N electrode 321 of the LED 320 is connected to the adjacent LED 32 The n-electrode 321 is electrically connected to each other, and the N-electrode 321 and the p-electrode 322 of each of the light-emitting diodes 320 are electrically connected to the soldering wire 70 by the metal wire segment 50. Similarly, the present invention is not limited to the light-emitting diode. The number of 320 or the way of its electrical connection, for example, a plurality of light-emitting diodes (LEDs) are connected in series to form a columnar light source or connected into a one-sided light source; meanwhile, the present invention is not limited to the light-emitting diodes. The illuminating color of the body 320, that is, the illuminating diode 320 may be a red illuminating diode or a green illuminating diode or a blue illuminating diode or a light emitting diode of other colors (for example, white light) or the foregoing illuminating A combination of diodes, etc. In addition, as shown in Fig. 9, the die seals of different functions or different sizes are packaged. Obviously, these die modules are system-in-package (SIP) composed of a plurality of dies, which include at least a micro-processing device 3〇5 (micr〇prOeessOT means), memory The device (mem〇ry means) or the memory control device); wherein each of the die has a plurality of pads on the active surface, and a plurality of metal segments are formed on the pads of each die to The adjacent crystal grains are electrically connected in series or in parallel and electrically connected to the conductive elements. After the module is packaged and electrically connected to each of the dies, the configuration of the external connection components is followed. As shown in FIG. 10A, after the modular electrical connection is completed, a patterned protective layer 6 (eg, Pdyimide) is formed on the surface of the package having the metal line segments to cover the multiple side cases. The metal wire segment 5G and the surface 62 are formed on a portion of the surface of the metal wire segment % extending outward to expose the other end of the patterned metal wire segment 5〇. The step of forming the patterned protective layer 6〇 includes: forming a protective layer = a plurality of patterned gold secret segments 50, such as a developed, silk-patterned photoresist layer (not shown in the figure) At a protection = 60; then, after development, the phase 200924133 is removed from the protective layer on the outwardly extending ends of the plurality of patterned metal segments 50 to form an opening 62, which is exposed to the opening 62. a portion of the surface of the plurality of patterned metal segments 5 向外 extending outwardly. Next, as shown in FIG. 10B, a plurality of conductive elements 7G are formed at a plurality of openings 62 of the protective layer 60, wherein the conductive elements 7〇 may be tin balls (strip ba戦 is a metal bump). Finally, the package can be cut to form a plurality of modules that complete the package. It is obvious that the package forms of the 10A and 10B are compared with the 7th. In addition, as shown in the figure u, the system displays the 8th. The cross-sectional view along the line BB and the cross-sectional view along line CC in Figure 9. ^ Figure 11 shows the system-level package of Figure 9 (System_;[n_package; Sip), in the other part of the present invention. Preferably, the lion-heat sink can be placed on the back side of the package, as shown in FIG. 12A; or the thin film process is used to expose the back surface of the crystallized body covered by the package body. Then attach the heat sink to the back side of the exposed die, as shown in Figure f 12B. In addition, 'the emphasis is on the implementation of this adhesive heat sink, which is also applicable in the embodiment of Figure 7. The time to stick the heat sink can be selected before the package is cut or selected in the package. The present invention is not limited thereto. The present invention is not limited by the foregoing preferred embodiments, but it is not intended to limit the present invention. The spirit and scope of the present invention, when a little bit of this can be made, she is succinct and succinct. [Simplified description of the drawing] Fig. 1 shows a schematic diagram of the prior art; 2 is a top view of a package structure according to the present invention; and 200924133 grain weight is a schematic diagram of steps of a package structure formed by a wafer alignment mark and a crystal mounting method according to the technology disclosed in the present invention; Figure 7 is a plan view of the wire according to the technique disclosed in the present invention; Figure 6 is a schematic view showing the electrical connection of a plurality of light-emitting diodes according to the technique of the wire; The disclosed technology is not intended to form an electrical connection on a plurality of crystal grains; FIG. 10A is a technique for forming a protective layer on a plurality of metal line segments according to the disclosed technology. 10B is a schematic diagram showing the formation of a plurality of conductive elements on a package structure according to the technology disclosed in the present invention; FIG. 11 is a cross-sectional view taken along line BB of FIG. 8 according to the technique disclosed in the present invention. FIG. 12A is a cross-sectional view along line cc; and FIG. 12A is a schematic view showing a sealing structure having a heat sink according to the technology disclosed in the present invention; and FIG. 12B is a diagram according to the present invention. ' indicates the fish chart of the thinned package structure. [Main component symbol description] 10 substrate 20 adhesive layer 100 substrate 17 200924133 110 die 302 alignment mark 305 microprocessing device 310 die / memory device 312 pad 315 Memory control device 320 light-emitting diode 40 polymer material layer 410 cutting channel 50 metal line segment 60 protective layer 70 conductive element 500 mold device

Claims (1)

200924133 十、申請專利範圍： - L一種模組化之多晶粒封裝方法，包括： 提供複數個離，每-雜粒具有—絲自雌主裝德置有複數個焊塾； 取放該些晶粒至-基板上，每_該晶粒係以覆晶方式職主動面與一配置於 該基板上的黏著層連接； 形成一咼分子材料層在該基板及部份該些晶粒之一下表面上； 平坦化該面分子材料層，使該高分子材料層充滿於該些晶粒之間並包覆每一 該晶粒； 脫離該基板，以曝露出每一該晶粒之該主動面及每一該焊墊，以形成一封裝 體； 、 形成複數個fflt化之金線段，部份該卵雜之金舰段之_電性連接 該些晶粒之該主動面上的該些焊墊，而部份該些圖案化之金屬線段之一端電 性連接該些晶粒之該主動面上的該些焊墊； 形成-圖案化之保遵層以覆蓋該些圖案化之金屬線段，並曝露部份該些圖案 化之金屬線段之另一端； 、 形成複數個導電元件，係將該些導電元件電性連接在已曝露之每一該圖案化 之金屬線段之另一端上；及 切割該封裝體，以形成複數個模組化之多晶粒封裝結構。 2·如申請專利範圍第}項所述之晶粒重新配置之封裝方法，#中該些晶粒為 具有相同尺寸大小之記憶體。 3. 如申請專利範圍第1項所述之晶粒重新配置之封裝方法，其中該些晶粒為 發光二極體。 4. 如申請專利範圍第3項所述之封裝方法，其中該發光二極體係由下列組 中選出：紅光、綠光、藍光或是白光。 5. 如申請專利範圍帛1項所述之封裝方法，其中該些晶粒可以是由大小尺寸 19 200924133 不同之晶粒所組成。 6. 如申請專利範圍第5項所述之封裝方法’其中該些大小尺寸不同之晶粒可 以為一微處理裝置、一記憶體裝置或一記憶體控制裝置。 7. 如申請專利範圍第1項所述之封裴方法，其中該高分子材料層係由下列組 中選出.石夕膠、環氧樹脂、丙烯酸（acrylic)、及苯環丁烯（BCB)等材料。 8'如申請專利範圍第1項所述之封裝方法，其中形成該些圖案化之金屬線 段包括： ' 形成一金屬層以覆蓋在該每一該晶粒之該主動面之該些焊墊上； 形成一圖案化之光阻層在該金屬層上；及 移除部份該金屬層，以移除部份該些焊墊上之金屬層，以形成該些 圖案化之金屬線段，其中部份該些圖案化之金I線段之兩端電性連接複數個 晶粒之該主動面上的複數個焊墊，部份該些圖案化之金屬線段之 接該些晶粒之該主動面上之該些焊墊。 9.如申明專利範圍第i項所述之封農方法其中該些圖案化之金屬線一 UBM金屬層。 ’ 1〇.如申物咖第丨項所述之封裝方法，其中細案化之保護層之材 Polyimide。 ，其中每一該晶粒之一背面具有 其中該些導電元件係為金屬凸 ，其中每一該模組化之多晶粒封 lh如申請專利範圍第1項所述之封裝方法 一對對準標誌。 12·如申請專利範圍第1項所述之封裝方法 ，其中該些導電元件係為錫球。 ’更包含於該封襞體上形成有複 13. 如申請專利範圍第1項所述之封裝方法200924133 X. Patent application scope: - L A modular multi-die packaging method, including: providing a plurality of separations, each-heavy particles having a plurality of wires from the female main assembly, and having a plurality of welding pads; a die-to-substrate, each of which is connected to an adhesive layer disposed on the substrate by a flip-chip active surface; forming a layer of germanium molecular material under the substrate and a portion of the plurality of crystal grains Surface-planning; planarizing the surface molecular material layer such that the polymer material layer is filled between the crystal grains and covering each of the crystal grains; and is detached from the substrate to expose the active surface of each of the crystal grains And each of the pads to form a package; forming a plurality of ffltized gold segments, and the portion of the gold segment is electrically connected to the pads on the active faces of the die a pad, and one of the patterned metal segments is electrically connected to the pads on the active surface of the die; forming a patterned layer to cover the patterned metal segments, And exposing at least the other end of the patterned metal line segments; a plurality of conductive elements electrically connected to the other end of each of the patterned metal line segments exposed; and cutting the package to form a plurality of modularized multi-die package structures . 2. The method of encapsulating a die for re-arrangement as described in the scope of the patent application, wherein the grains are memory having the same size. 3. The method of encapsulating a die reconfiguring according to claim 1, wherein the plurality of crystal grains are light emitting diodes. 4. The packaging method of claim 3, wherein the light emitting diode system is selected from the group consisting of red light, green light, blue light, or white light. 5. The encapsulation method of claim 1, wherein the dies may be composed of different dies of size 19 200924133. 6. The packaging method according to claim 5, wherein the different sizes of the crystal grains may be a micro processing device, a memory device or a memory control device. 7. The method of sealing according to claim 1, wherein the polymer material layer is selected from the group consisting of: diabase gum, epoxy resin, acrylic, and benzocyclobutene (BCB). And other materials. The packaging method of claim 1, wherein the forming the patterned metal line segments comprises: forming a metal layer to cover the pads on the active surface of each of the crystal grains; Forming a patterned photoresist layer on the metal layer; and removing a portion of the metal layer to remove portions of the metal layer on the pads to form the patterned metal line segments, wherein the portion The two ends of the patterned gold I line segments are electrically connected to the plurality of pads on the active surface of the plurality of crystal grains, and the patterned metal line segments are connected to the active surface of the plurality of crystal grains Some pads. 9. The method of agricultural closure according to claim i, wherein the patterned metal wires are a UBM metal layer. </ RTI> </ RTI> As described in the application of the food item, the packaging method of the fine layer of the protective layer of Polyimide. One of the back sides of each of the dies has a conductive protrusion, wherein each of the plurality of patterned dies is a pair of alignments as described in claim 1 Sign. 12. The packaging method of claim 1, wherein the conductive elements are solder balls. </ RTI> further comprising a package formed on the package body. 13. The package method as described in claim 1 14, 如申請專利範圍第1項所述之封裝方法 15·如申請專利範圍第i項所述之封裝方法 裝結構之一背面上更包括一散熱片。 20 200924133 16.如申請專纖圍第丨項所述之封裝方法，其中於切難封裝 執行一薄化程序，以將該封裝體之背面薄化。 别无 薄化後封裝體之該背 17.如申請專利範圍第16項所述之封裝方法，其中於該 面上黏貼一散熱片。 18.—種發光二極體重新配置之封裝方法，包括： 主動面且該主動面上具有 提供複數個發光二極體，每一該發光二極體具有一 一 P電極及一 N電極；14. The packaging method as described in claim 1 of the patent application. 15. The packaging method as described in claim i. The mounting structure further includes a heat sink on the back surface. 20 200924133 16. The packaging method of claim 1, wherein the thinning process is performed on the hard-to-package to thin the back side of the package. The package of the package of claim 16, wherein a heat sink is adhered to the surface. 18. A method of packaging a light-emitting diode reconfiguration, comprising: an active surface having a plurality of light emitting diodes, each of the light emitting diodes having a P electrode and an N electrode; 取放該些發光三滅至-級上’每-該發光二_係哺晶方式將該主動 面與一配置於該基板上的黏著層連接； 形成一高分子材料層於該基板及部份該些發光二極體之一下表面上. 平坦化該高分子材·，使職分子材料層充滿於職魏二鋪之間並包 覆每一該發光二極體之一下表面； 脫離該基板，以曝露出每一該發光二極體之該主動面以及每一該電極以形成 一封裝體； V 形成複數個圖案化之金屬線段，該些圖案化之金屬線段之一端分別電性連接 母該發光一極體之該主動面上之每一該P電極及每一該N電極，而另一端 則分別共接於一向外延之金屬線段； 形成一圖案化之保護層以覆蓋該些圖案化之金屬線段且曝露出該向外延伸之 金屬線段的部份表面； 形成複數個導電元件’係將該些導電元件電性連接在已曝露之該向外延伸之 金屬線段之表面上；及 切割該封裝體’以形複數個模組化之發光二極體封裝結構。 19·如申請專利範圍第18項所述之封裝方法，其中每一該發光二極體之一背 面具有一對對準標誌。 20.如申請專利範圍第18項所述之封裝方法，其中該些發光二極體係由下列 組中選出：紅光、綠光、藍光或是白光》 21 200924133 21. 如申請專利範圍第18項所述之封裝方法，其中該高分子材料層係由下列 組中選出.石夕膠、環氧樹脂、丙烯酸（acrylic)、及苯環丁烯（BCB)等材料。 22. 如申請專利範圍第18項所述之封裝方法，其中更包含於該封裝體上形成 有複數個切割道。 V 23. 如申請專利範圍第18項所述之封裝方法，其中該些導電元件係為金 塊。 ，、 24. 如申請專利範圍第1S項所述之封裝方法，其中該些導電元件係為錫球。 25. —種發光二極體重新配置之封裝結構，包括：Placing and arranging the light-emitting three-off-level-on-the-light-emitting mode to connect the active surface to an adhesive layer disposed on the substrate; forming a polymer material layer on the substrate and the portion On the lower surface of one of the light-emitting diodes, the polymer material is planarized, and the layer of the molecular material is filled between the two parts of the service and coated on the lower surface of each of the light-emitting diodes; Exposing the active surface of each of the light-emitting diodes and each of the electrodes to form a package; V forming a plurality of patterned metal line segments, and one of the patterned metal line segments is electrically connected to the mother Each of the P electrodes and each of the N electrodes on the active surface of the light-emitting body and the other end are respectively connected to the respectively extended metal line segments; forming a patterned protective layer to cover the patterned patterns a metal wire segment exposing a portion of the surface of the outwardly extending metal wire segment; forming a plurality of electrically conductive elements ' electrically connecting the electrically conductive elements to the surface of the outwardly extending metal wire segment; and cutting Package To form a plurality of modular light emitting diode package structure. The encapsulation method of claim 18, wherein each of the light-emitting diodes has a pair of alignment marks on the back side. 20. The packaging method of claim 18, wherein the light emitting diode systems are selected from the group consisting of: red, green, blue, or white. 21 200924133 21. The encapsulation method, wherein the polymer material layer is selected from the group consisting of: stone enamel, epoxy resin, acrylic, and benzocyclobutene (BCB). 22. The method of packaging of claim 18, further comprising forming a plurality of dicing streets on the package. V 23. The method of packaging of claim 18, wherein the conductive elements are gold nuggets. 24. The method of claim 1, wherein the conductive elements are solder balls. 25. A package structure for light-emitting diode reconfiguration, comprising: 複數個發光二極體’每—紐光二極體具有—絲面且触動面上配置有一 P電極及一 N電極； -封裝體，係環覆於每—該發光二極體之五個面且曝露出每—該發光二極體 之該主動面及每一該p電極及每一該N電極； 複數個圖案化之金屬線段，係其—端分別電性連絲—該發光二極體之該主 動面上之每=該P電極及每—該N電極，而另—端則分別共接於—⑽延伸 之金屬線段； 夕：保護層’用以覆蓋該些圖案化之金屬線段，且曝露出該向外延伸 之金屬線段的部份表面；及 元件’係形成在已曝露之該向外延伸之金屬線段之表面上， 帛Μ項所^封雜構，料每-該魏二鋪之一背 Μ撕切_，Μ軸陳極體係由下列 、’且中選出·紅光、綠光、藍光或是白光。 層。申4她圍第25項所述之封裝結構，其中該封裝體為—高分子材料 29.如申請__ 28撕辦姻，_繪刪係由下列 22 200924133 组中選出.矽膠、環氧樹脂、丙烯酸（acrylie)、及苯環丁烯（BCB)等材料。 30. 如申請專利範圍帛25項所述之封裝結構，其中該些圖案化之金屬線段為 一 UBM金屬層。 31. 如申請專利範圍第Μ項所述之封裝結構，其中該些導電元件可以是锡球 (solder ball)。 32·如中π專她圍第25顿述之雖結構，其中該些導電元件可以是金屬 凸塊(metal bump)。 33.a plurality of light-emitting diodes each of the neo-light diodes have a silk surface and a P electrode and an N electrode are disposed on the touch surface; and a package body is attached to each of the five sides of the light emitting diode And exposing the active surface of each of the light-emitting diodes and each of the p-electrodes and each of the N-electrodes; the plurality of patterned metal line segments are respectively electrically connected to the ends - the light-emitting diodes Each of the active surfaces has a respective one of the P electrodes and each of the N electrodes, and the other ends are respectively connected to the (10) extended metal line segments; and the protective layer 'is used to cover the patterned metal line segments, And exposing a portion of the surface of the outwardly extending metal line segment; and the component 'is formed on the surface of the outwardly extending metal line segment that has been exposed, and the material is sealed, and the material is each One of the paving backs and tears _, the Μ axis Chen pole system is selected from the following, 'and selected · red, green, blue or white light. Floor. Shen 4 her package structure as described in item 25, wherein the package is a polymer material 29. If the application is __28, the _ picture is selected from the following 22 200924133 group. Silicone, epoxy resin , acrylie, and benzocyclobutene (BCB) and other materials. 30. The package structure of claim 25, wherein the patterned metal segments are a UBM metal layer. 31. The package structure of claim 2, wherein the conductive elements are solder balls. 32. For example, in the case of π, she is surrounded by the structure of the 25th, wherein the conductive elements may be metal bumps. 33. 種模組化之多晶粒封裝結構，包括. 複數個晶粒’每-該晶粒具有—主動面且該主動面上配置有複數個焊塾； 封裝體’係喊於母-該晶粒之五個面且曝露出每—該晶粒之該主動面及 每一該焊墊 ，數個圖案化之金屬線段，部份該些圖案化之金屬線段之兩端電性連接該些 動面上的該些焊墊’㈣份該些圖案化之金屬線段之一端電性連接 s 亥些晶粒之主動面上的該些焊塾； 一圖案化之保s蒦層，係覆蓋該些圖案^ ^ 金屬線段之男一端·, 魏之金屬私並曝露部份該些圖案化之 形成複數個導電元件， 之金屬線段之另一端上 係將該些導電元件紐連接在已《之每 一該圖案化 :及 一散熱裝置，係形成於該封裝體之—背面上 34.如申請專利範圍第33項所述之封裝結構， 能及尺寸大小之晶粒。 其中該些晶粒可以是相同功 35.如申請專利範圍第33項所述之封裝結構， 粒0 其中該些晶粒可以是記憶體晶 36.如申請專利範圍第 及尺寸大小之晶粒。 33項所述之封裝結構’其巾該些晶粒可以是不同功能 37.如申請專利細第33項所述之封裝結構， 其中該些晶粒可以是由一微處 23 200924133 理裝置、一記憶體裝置及一記憶體控制裝置所組成。 38. 如申請專利範圍第33項所述之封裝結構，其中每一該晶粒之一背面具有 一對對準標誌。 ~ 39. 如申請專利範圍第33項所述之封裝結構，其中該封裝體為一高分子材料 層。 40. 如申凊專利範圍第39項所述之封襄結構，其中該高分子材料層係由下列 組中選出：石夕膠、環氧樹脂、丙稀酸（aciylic)、及苯環丁稀（bcb)等材料。 礼如申請專利範圍第％項所述之封裝結構，其中該些圖案化之金屬線段為 一 UBM金屬層。 42. 如申請專利範圍第33項所述之封裝結構，其中該些導電元件可以是锡球 (solder ball) ° 43. 如申咕專利圍第33項所述之封裝結構，其中該些導電元件可以是金屬 凸塊(metal bump) 〇 24The modular multi-die package structure includes: a plurality of dies each of the dies having an active surface and a plurality of solder pads disposed on the active surface; the package is shrouded in the mother-the dies The five sides of the die are exposed to each of the active faces of the die and each of the pads, a plurality of patterned metal segments, and the two ends of the patterned metal segments are electrically connected to the movable faces The solder pads of the (4) portions of the patterned metal line segments are electrically connected to the solder pads on the active faces of the plurality of crystal grains; a patterned protective layer covers the patterns ^ ^ The male end of the metal segment, Wei Zhi Metal privately exposes some of the patterned ones to form a plurality of conductive elements, and the other end of the metal line segment connects the conductive elements to each of the Patterning: and a heat dissipating device formed on the back surface of the package 34. The package structure as described in claim 33, and the size and size of the crystal grains. The granules may be the same work. The package structure as described in claim 33, wherein the granules may be memory crystals. 36. The granules of the size and size of the patent application. The package structure of the above-mentioned item 33 may have different functions. 37. The package structure as described in claim 33, wherein the plurality of crystal grains may be a micro-location 23 200924133 device, The memory device and a memory control device are composed. 38. The package structure of claim 33, wherein one of the back sides of each of the dies has a pair of alignment marks. The package structure of claim 33, wherein the package is a polymer material layer. 40. The sealing structure according to claim 39, wherein the polymer material layer is selected from the group consisting of: shiqi gum, epoxy resin, aciylic, and benzocycline. (bcb) and other materials. The package structure of claim 100, wherein the patterned metal segments are a UBM metal layer. 42. The package structure of claim 33, wherein the conductive elements may be solder balls. 43. The package structure of claim 33, wherein the conductive elements Can be metal bump 〇24
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Publication number Priority date Publication date Assignee Title
TWI456143B (en) * 2012-04-26 2014-10-11 新世紀光電股份有限公司 Light emitting module
TWI672832B (en) * 2018-10-23 2019-09-21 聯嘉光電股份有限公司 Wafer level light emitting diode packaging method and structure thereof

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KR102185706B1 (en) * 2017-11-08 2020-12-02 삼성전자주식회사 Fan-out semiconductor package
KR102004243B1 (en) * 2017-12-14 2019-07-26 삼성전자주식회사 Fan-out semiconductor package

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI456143B (en) * 2012-04-26 2014-10-11 新世紀光電股份有限公司 Light emitting module
TWI672832B (en) * 2018-10-23 2019-09-21 聯嘉光電股份有限公司 Wafer level light emitting diode packaging method and structure thereof

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