TWI672832B - Wafer level light emitting diode packaging method and structure thereof - Google Patents

Wafer level light emitting diode packaging method and structure thereof Download PDF

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TWI672832B
TWI672832B TW107137355A TW107137355A TWI672832B TW I672832 B TWI672832 B TW I672832B TW 107137355 A TW107137355 A TW 107137355A TW 107137355 A TW107137355 A TW 107137355A TW I672832 B TWI672832 B TW I672832B
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package
emitting diode
light emitting
wafer
electrodes
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TW107137355A
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TW202017210A (en
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黃國欣
周充祐
蔡增光
趙永祥
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聯嘉光電股份有限公司
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Abstract

本發明方法為用於封裝一晶圓保護膜上的複數發光二極體晶片,其主要是先於該些發光二極體晶片的第一電極上形成一封裝表層,再於該封裝表層形成電性連接該第一電極的一導出電極,再切割該些發光二極體晶片並分選測試、重組該些發光二極體晶片,並藉由一封裝層來覆蓋該些發光二極體晶片的側邊,再於該封裝層上鑽孔與填充導電材來形成複數共電極,接著印刷複數共電線路,並讓每一該共電線路電性連接一個該共電極與多個該導出電極,最後覆蓋線路保護層即完成製程;據此,本發明直接於晶圓保護膜上進行封裝,無需使用封裝基板,且藉由印刷線路的方式,可以降低成本並改善製程生產的速度。 The method of the present invention is for packaging a plurality of light-emitting diode chips on a wafer protective film, which mainly forms a package surface layer on the first electrodes of the light-emitting diode chips, and then forms a surface on the package surface layer. Connecting a lead electrode of the first electrode, cutting the light emitting diode chips, sorting and testing the light emitting diode chips, and covering the light emitting diode wafers with an encapsulation layer Forming a plurality of common electrodes on the side of the package layer by drilling and filling the conductive material, and then printing the plurality of common lines, and electrically connecting each of the common lines to the common electrode and the plurality of the lead electrodes. Finally, the circuit protection layer is covered, and the process is completed. According to the invention, the package is directly packaged on the wafer protection film, and the package substrate is not required, and the cost can be reduced and the speed of the process production can be improved by means of the printed circuit.

Description

晶圓級發光二極體封裝方法及其結構 Wafer level light emitting diode packaging method and structure thereof

本發明有關於發光二極體,尤其有關於發光二極體封裝結構與方法。 The invention relates to a light-emitting diode, in particular to a light-emitting diode package structure and method.

傳統發光二極體的封裝方式,為以打線接合(wire bond)來連接發光二極體的電極與封裝基板,由於其需要一粒一粒的進行打線接合,對於多晶片的應用需求,會有生產速度與良率無法滿足要求的問題;且打線接合的方式,在體積上難以縮小化,且阻抗高,亦難滿足輕、薄、小與高亮度的應用需求。 The conventional LED package is a wire bond to connect the electrodes of the LED and the package substrate. Since it needs to be bonded one by one, the application requirements for the multi-chip will be The production speed and yield cannot meet the requirements; and the way of wire bonding is difficult to reduce in volume, and the impedance is high, and it is difficult to meet the application requirements of light, thin, small and high brightness.

而覆晶(Flip chip)封裝技術的出現,解決了體積難以縮小的問題,其可大幅縮小封裝後的體積,滿足輕、薄、小與高亮度的使用需求。然而在覆晶封裝製程中,需要對晶片進行精準的定位取放而放置於封裝基板的指定位置,然而由於發光二極體的晶片尺寸越來越小,其導致吸取晶片移載的穩定性不佳,容易會有晶片旋轉、偏移、掉料等等異常,並且吸嘴的尺寸為了符合晶片尺寸的大小,其孔隙相當的微小,容易有吸嘴阻塞而造成吸力不足的問題,其導致生產效率的浪費以及生產成本增加。 The emergence of Flip chip packaging technology solves the problem that the volume is difficult to shrink, which can greatly reduce the volume after packaging, and meet the needs of light, thin, small and high brightness. However, in the flip chip packaging process, the wafer needs to be accurately positioned and placed and placed at a specified position on the package substrate. However, since the size of the wafer of the light-emitting diode is smaller, the stability of the wafer transfer is not improved. It is easy to have abnormalities such as wafer rotation, offset, material drop, etc., and the size of the nozzle is small in size in order to conform to the size of the wafer, and the nozzle is clogged and the suction is insufficient, resulting in insufficient suction. Waste of efficiency and increased production costs.

爰此,本發明之主要目的在於揭露一種於晶圓保護膜上進行封裝製程的發光二極體晶片封裝方法。 Accordingly, the main object of the present invention is to disclose a method of packaging a light-emitting diode chip on a wafer protective film.

而本發明之次要目的在於揭露一種直接於晶圓保護膜上進行發光二極體晶片封裝而形成的封裝結構。 A secondary object of the present invention is to disclose a package structure formed by directly performing a light emitting diode package on a wafer protective film.

本發明為一種晶圓級發光二極體封裝方法,用於封裝複數發光二極體晶片,該些發光二極體晶片尚未分離而集合形成一晶圓,且該晶圓黏貼於一晶圓保護膜上,並該些發光二極體晶片具有位於上下兩面的一第一電極與一第二電極,其封裝方法包含:步驟S1:覆蓋封裝膠材、步驟S2:鑽盲孔、步驟S3:形成導出電極、步驟S4:切割、步驟S5:分選測試、步驟S6:建構封裝主體、步驟S7:形成共電極、步驟S8:形成共電線路與步驟S9:形成線路保護層。 The present invention is a wafer level light emitting diode package method for packaging a plurality of light emitting diode chips. The light emitting diode chips are not separated and assembled to form a wafer, and the wafer is adhered to a wafer protection. On the film, the LED chips have a first electrode and a second electrode on the upper and lower sides, and the packaging method comprises the following steps: Step S1: covering the encapsulant, step S2: drilling the blind hole, step S3: forming Deriving the electrode, step S4: cutting, step S5: sorting test, step S6: constructing the package body, step S7: forming a common electrode, step S8: forming a common line and step S9: forming a line protection layer.

其中步驟S1為於該晶圓的上面覆蓋一封裝表層,該封裝表層覆蓋該些發光二極體晶片的該第一電極;步驟S2為於該封裝表層對應該些發光二極體晶片的位置進行鑽孔而形成複數盲孔,該些盲孔顯露該些發光二極體晶片的該第一電極;步驟S3為於該些盲孔上分別填充導電材而形成複數導出電極,該些導出電極分別電性連接該些發光二極體晶片的該第一電極;步驟S4為對該晶圓進行切割,讓該些發光二極體晶片分離為單一個體;步驟S5為對該些發光二極體晶片進行測試,剔除損壞的該發光二極體晶片,並將剩餘的該些發光二極體晶片分組重新排列於該晶圓保護膜上,又該晶圓保護膜定義出複數封裝區域,且相同分組的該些發光二極體晶片位於相同的該封裝區域;步驟S6為於該晶圓保護膜上形成一封裝層,該封裝層覆蓋該些發光二極體晶片的側邊,且該封裝層與該封裝表層等高而形成共平面;步驟S7為於每一該封裝區域的該封裝層上鑽孔,而於該封裝層上形成複數貫孔,並於該些貫孔填充導電材而形成複數共電極;步驟S8為於該封裝層與該封裝表層上同時印刷複數共電線路,且每一該封裝區域對應設置一個該共電線路,且一個該共電線路電性連接該封裝區域內的該共電極與該導出電極;步驟S9為於該封裝層與該封裝表層上形成一線路保護 層,該線路保護層覆蓋該封裝層與該封裝表層上的該些導出電極、該些共電極與該些共電線路。 Step S1 is to cover a surface of the package with a package surface layer covering the first electrode of the LED chip; and step S2 is for the position of the package surface corresponding to the LED chip. Drilling to form a plurality of blind holes, the blind holes revealing the first electrodes of the LED chips; step S3 is to fill the blind holes with conductive materials to form a plurality of lead electrodes, respectively Electrically connecting the first electrodes of the LED chips; step S4 is to cut the wafers to separate the LED chips into a single body; and Step S5 is to process the LED chips. Performing a test to remove the damaged LED chip and rearranging the remaining LED sub-groups on the wafer protection film, and the wafer protection film defines a plurality of package regions, and the same grouping The light emitting diode chips are located in the same package area; step S6 is to form an encapsulation layer on the wafer protection film, the package layer covers the side edges of the light emitting diode chips, and the package Forming a coplanar surface with the package surface layer; step S7 is to drill holes in the package layer of each package region, and forming a plurality of through holes on the package layer, and filling the conductive holes to fill the conductive holes a plurality of common electrodes; step S8 is to simultaneously print a plurality of common electric lines on the package layer and the package surface layer, and each of the package areas is correspondingly disposed with one of the common lines, and one of the common lines is electrically connected to the package area The common electrode and the derivation electrode; step S9 is to form a line protection on the encapsulation layer and the package surface layer a layer, the circuit protection layer covering the encapsulation layer and the derivation electrodes on the package surface layer, the common electrodes, and the common electric lines.

而依據上述方法,其在切割後,可以形成一種晶圓級發光二極體封裝結構,其包含至少二發光二極體晶片、封裝表層、至少二導出電極、封裝層、共電極、共電線路與線路保護層,其中該些發光二極體晶片具有位於上下兩面的第一電極與第二電極,該封裝表層覆蓋該些發光二極體晶片的第一電極;該封裝表層具有至少二盲孔,該些盲孔於對應該些發光二極體晶片的位置穿過該封裝表層,並顯露該些發光二極體晶片的第一電極;該些導出電極填充於該些盲孔內,且該些導出電極分別電性連接該些發光二極體晶片的第一電極;該封裝層覆蓋該些發光二極體晶片的側邊,且該封裝層與該封裝表層等高而形成共平面,並該封裝層具有貫穿兩側的貫孔;該共電極填充於該貫孔內;該共電線路設置於該封裝層與該封裝表層上,且該共電線路電性連接該共電極與該些導出電極;該線路保護層覆蓋該封裝層與該封裝表層上的該些導出電極、該共電極與該共電線路。 According to the above method, after the dicing, a wafer level light emitting diode package structure can be formed, which comprises at least two light emitting diode chips, a package surface layer, at least two lead electrodes, an encapsulation layer, a common electrode, and a common line. And a circuit protection layer, wherein the light-emitting diode wafers have first and second electrodes on the upper and lower sides, the package surface covers the first electrodes of the light-emitting diode wafers; the package surface layer has at least two blind holes The blind holes pass through the surface of the package at positions corresponding to the light-emitting diode chips, and expose the first electrodes of the light-emitting diode chips; the lead-out electrodes are filled in the blind holes, and the The lead electrodes are electrically connected to the first electrodes of the LED chips; the encapsulation layer covers the sides of the LED chips, and the encapsulation layer is coplanar with the package surface layer, and The encapsulation layer has a through hole extending through the two sides; the common electrode is filled in the through hole; the common electric line is disposed on the encapsulation layer and the package surface layer, and the common electric line is electrically connected to the common electrode and These leading-out electrode; the circuit protective layer covering the plurality of the encapsulation layer on the surface of the package deriving electrode, the common electrode and the common electrical line.

如上所述,本發明為直接於晶圓保護膜上進行封裝製程,因而無需使用封裝基板,且藉由印刷線路的方式,可以降低成本並改善製程生產的速度,滿足製造上的需求。 As described above, the present invention performs a packaging process directly on the wafer protective film, thereby eliminating the need for a package substrate, and by means of a printed circuit, the cost can be reduced and the speed of process production can be improved to meet the manufacturing requirements.

步驟S1‧‧‧覆蓋封裝膠材 Step S1‧‧‧ Covering the package adhesive

步驟S2‧‧‧鑽盲孔 Step S2‧‧‧Drilling blind holes

步驟S3‧‧‧形成導出電極 Step S3‧‧‧ Forming the derivation electrode

步驟S4‧‧‧切割 Step S4‧‧‧ cutting

步驟S5‧‧‧分選測試 Step S5‧‧‧ Sorting test

步驟S6‧‧‧建構封裝主體 Step S6‧‧‧Constructing the package body

步驟S7‧‧‧形成共電極 Step S7‧‧‧ forming a common electrode

步驟S8‧‧‧形成共電線路 Step S8‧‧‧ forming a common line

步驟S9‧‧‧形成線路保護層 Step S9‧‧‧ forming a line protection layer

步驟S10‧‧‧成品切割 Step S10‧‧‧ Finished cutting

10‧‧‧晶圓 10‧‧‧ wafer

11‧‧‧發光二極體晶片 11‧‧‧Light Emitting Diode Wafer

12‧‧‧晶圓保護膜 12‧‧‧ wafer protective film

13‧‧‧第一電極 13‧‧‧First electrode

14‧‧‧第二電極 14‧‧‧second electrode

15‧‧‧切割區 15‧‧‧Cutting area

20‧‧‧封裝表層 20‧‧‧Package surface

21‧‧‧盲孔 21‧‧‧Blind holes

22‧‧‧導出電極 22‧‧‧Derived electrode

30‧‧‧封裝區域 30‧‧‧Package area

40‧‧‧封裝層 40‧‧‧Encapsulation layer

41‧‧‧貫孔 41‧‧‧through holes

42‧‧‧共電極 42‧‧‧Common electrode

50‧‧‧共電線路 50‧‧‧Communication lines

60‧‧‧線路保護層 60‧‧‧Line protection layer

圖1,為本發明封裝方法步驟圖。 FIG. 1 is a step diagram of a packaging method of the present invention.

圖2A~圖2K,為本發明封裝方法的圖面結構示意圖。 2A-2K are schematic structural views of a packaging method of the present invention.

圖3,為本發明封裝結構俯視圖。 3 is a top plan view of the package structure of the present invention.

圖4,為本發明封裝結構底視圖。 Figure 4 is a bottom plan view of the package structure of the present invention.

圖5,為本發明圖3之A-A處剖視圖。 Figure 5 is a cross-sectional view taken along line A-A of Figure 3 of the present invention.

為俾使貴委員對本發明之特徵、目的及功效,有著更加深入之瞭解與認同,茲列舉一較佳實施例並配合圖式說明如後:請參閱圖1與圖2A~圖2K所示,本發明為一種晶圓級發光二極體封裝方法,用於封裝複數發光二極體晶片11,如圖2A所示,該些發光二極體晶片11尚未分離而集合形成一晶圓10,且該晶圓10黏貼於一晶圓保護膜12上,並該些發光二極體晶片11具有位於上下兩面的一第一電極13與一第二電極14,且該些發光二極體晶片11之間具有一切割區15。 In order to give your members a better understanding and recognition of the features, objects and effects of the present invention, a preferred embodiment will be described with reference to the following figures: Please refer to FIG. 1 and FIG. 2A to FIG. 2K. The present invention is a wafer level light emitting diode package method for packaging a plurality of light emitting diode chips 11. As shown in FIG. 2A, the light emitting diode chips 11 are not separated and assembled to form a wafer 10, and The wafer 10 is adhered to a wafer protective film 12, and the LEDs 11 have a first electrode 13 and a second electrode 14 on the upper and lower sides, and the LEDs 11 There is a cutting zone 15 therebetween.

如圖1所示,本發明封裝方法包含步驟S1:覆蓋封裝膠材、步驟S2:鑽盲孔、步驟S3:形成導出電極、步驟S4:切割、步驟S5:分選測試、步驟S6:建構封裝主體、步驟S7:形成共電極、步驟S8:形成共電線路與步驟S9:形成線路保護層。 As shown in FIG. 1, the packaging method of the present invention comprises the step S1: covering the encapsulant, step S2: drilling a blind hole, step S3: forming a derivation electrode, step S4: cutting, step S5: sorting test, step S6: constructing the package Main body, step S7: forming a common electrode, step S8: forming a common electric line and step S9: forming a line protective layer.

如圖2B所示,步驟S1為於該晶圓10的上面覆蓋一封裝表層20,該封裝表層20覆蓋該些發光二極體晶片11的該第一電極13,該封裝表層20可以選自環氧樹脂(Epoxy)與矽基樹脂(Silicone)的任一種,且該封裝表層20為選用壓模、點膠等等作業方式,形成於該晶圓10的上面。 As shown in FIG. 2B, the upper surface of the wafer 10 is covered with a package surface layer 20, and the package surface layer 20 covers the first electrode 13 of the light-emitting diode wafers 11. The package surface layer 20 may be selected from the ring. Any one of an epoxy resin and a silicone resin, and the package skin 20 is formed on the wafer 10 by using a stamper, a dispensing, or the like.

如圖2C所示,步驟S2為於該封裝表層20對應該些發光二極體晶片11的位置進行鑽孔而形成複數盲孔21,該些盲孔21顯露該些發光二極體晶片11的該第一電極13,鑽孔的方式可以選自雷射與鑽頭的任一種皆可,其只要可以形成該些盲孔21,就滿足使用上的需求。 As shown in FIG. 2C, in step S2, a plurality of blind holes 21 are formed by drilling the positions of the package surface layer 20 corresponding to the light-emitting diode chips 11, and the blind holes 21 expose the light-emitting diode chips 11. The first electrode 13 may be drilled in any manner selected from the group consisting of a laser and a drill. As long as the blind holes 21 can be formed, the requirements for use are satisfied.

如圖2D所示,步驟S3為於該些盲孔21上分別填充導電材而形成複數導出電極22,該些導出電極22分別電性連接該些發光二極體晶片11的該 第一電極13;導電材為導電銀膠(Conductive Silver Adhesive)或導電奈米銀膠(Conductive Nano Silver Adhesive)。 As shown in FIG. 2D, in step S3, the blind holes 21 are respectively filled with a conductive material to form a plurality of lead-out electrodes 22, and the lead-out electrodes 22 are electrically connected to the light-emitting diode wafers 11, respectively. The first electrode 13; the conductive material is Conductive Silver Adhesive or Conductive Nano Silver Adhesive.

如圖2E所示,步驟S4為對該晶圓10進行切割,其為沿著該切割區15進行切割,讓該些發光二極體晶片11分離為單一個體,其可以使用雷線切割等技術進行切割。 As shown in FIG. 2E, step S4 is to cut the wafer 10, and cut along the cutting area 15 to separate the light-emitting diode wafers 11 into a single individual, which can use techniques such as lightning cutting. Cut.

如圖2F所示,步驟S5為對該些發光二極體晶片11進行測試,剔除損壞的該發光二極體晶片11,此過程與傳統的晶片測試並無不同,目的在於剔除不良品;又本發明並將剩餘的該發光二極體晶片11分組重新排列於該晶圓保護膜12上,又該晶圓保護膜12定義出複數封裝區域30(如圖2H所示),且相同分組的該些發光二極體晶片11位於相同的該封裝區域30;在此一步驟中,該些發光二極體晶片11的分組排列方式與數量為依據後續需求而建置,如圖2F所示,該封裝區域30內的該些發光二極體晶片11為三個,並預留出封裝時所需的佈線區域。 As shown in FIG. 2F, in step S5, the LEDs 11 are tested to remove the damaged LEDs 11. This process is no different from the conventional wafer test, and the purpose is to eliminate defective products; The present invention re-arranges the remaining light-emitting diode wafers 11 on the wafer protective film 12, and the wafer protective film 12 defines a plurality of package regions 30 (as shown in FIG. 2H), and the same grouping The LED arrays 11 are located in the same package area 30. In this step, the grouping and quantity of the LED chips 11 are set according to subsequent requirements, as shown in FIG. 2F. The plurality of light-emitting diode chips 11 in the package region 30 are three, and a wiring area required for packaging is reserved.

如圖2G所示,步驟S6為於該晶圓保護膜12上形成一封裝層40,該封裝層40覆蓋該些發光二極體晶片11的側邊,且該封裝層40與該封裝表層20等高而形成共平面;該封裝層40的材質同樣可以選自環氧樹脂(Epoxy)與矽基樹脂(Silicone)的任一種,且該封裝層40可選用壓模、點膠等等作業方式製成。 As shown in FIG. 2G, in step S6, an encapsulation layer 40 is formed on the wafer protection film 12. The encapsulation layer 40 covers the side edges of the LED sub-die 11, and the encapsulation layer 40 and the package surface layer 20 are formed. The material of the encapsulation layer 40 can also be selected from any one of epoxy resin (Epoxy) and Silicone resin, and the encapsulation layer 40 can be selected by using a stamper, a dispensing method, or the like. production.

如圖2H所示,步驟S7為於每一該封裝區域30的該封裝層40上鑽孔,而於該封裝層40上形成複數貫孔41,該些貫孔41的鑽孔方法為選自雷射與鑽頭的任一種,並於該些貫孔41填充導電材而形成複數共電極42,導電材同樣為導電銀膠(Conductive Silver Adhesive)或導電奈米銀膠(Conductive Nano Silver Adhesive)。 As shown in FIG. 2H, step S7 is to drill holes in the encapsulation layer 40 of each of the package regions 30, and a plurality of through holes 41 are formed on the encapsulation layer 40. The drilling method of the through holes 41 is selected from the following steps. Any one of a laser and a drill bit, and the conductive holes are filled in the through holes 41 to form a plurality of common electrodes 42. The conductive materials are also Conductive Silver Adhesive or Conductive Nano Silver Adhesive.

如圖2I所示,步驟S8為於該封裝層40與該封裝表層20上同時印刷複數共電線路50,且每一該封裝區域30對應設置一個該共電線路50,並該共電線路50電性連接該封裝區域30內的該共電極42與該導出電極22。 As shown in FIG. 2I, step S8 is to simultaneously print a plurality of common electric lines 50 on the package layer 40 and the package surface layer 20, and each of the package areas 30 is correspondingly provided with the common electric line 50, and the common electric line 50 is disposed. The common electrode 42 and the lead-out electrode 22 in the package region 30 are electrically connected.

如圖2J所示,步驟S9為於該封裝層40與該封裝表層20上形成一線路保護層60,該線路保護層60覆蓋該封裝層40與該封裝表層20上的該些導出電極22、該些共電極42與該些共電線路50。 As shown in FIG. 2J, a circuit protection layer 60 is formed on the package layer 40 and the package surface layer 20, and the circuit protection layer 60 covers the package layer 40 and the lead-out electrodes 22 on the package surface layer 20, The common electrodes 42 and the common electric lines 50.

如圖2K所示,此外,本發明更可包含一步驟S10:成品切割,步驟S10為讓該封裝區域30作為切割單位,對該封裝層40進行切割。 As shown in FIG. 2K, in addition, the present invention may further comprise a step S10: cutting the finished product, and step S10 is to cut the encapsulating layer 40 by using the encapsulating area 30 as a cutting unit.

又當該些發光二極體晶片11的發光顏色為單一色時,此時只要讓更多數量的該發光二極體晶片11在一個該封裝區域30,即可以提供較大的亮度。而當該些發光二極體晶片11的發光顏色分別為選自紅、綠與藍的任一種時,可以讓相同分組的該些發光二極體晶片11為三個,且該三發光二極體晶片11的發光顏色分別為紅、綠與藍,其可混光而形成白色光源。 Moreover, when the illuminating color of the illuminating diode chips 11 is a single color, at this time, a larger number of the illuminating diode chips 11 may be provided in one of the package regions 30, that is, a larger brightness can be provided. When the illuminating colors of the illuminating diodes 11 are respectively selected from the group consisting of red, green, and blue, the LEDs 11 of the same group can be three, and the three LEDs are The color of the body wafer 11 is red, green, and blue, respectively, which can be mixed to form a white light source.

請再一併參閱圖3、圖4與圖5所示,其為依據上述方法步驟S1-S10所製成的晶圓級發光二極體封裝結構,如圖所示,其包含至少二發光二極體晶片11、封裝表層20、至少二導出電極22、封裝層40、共電極42、共電線路50與線路保護層60。該些發光二極體晶片11具有位於上下兩面的第一電極13與第二電極14,該封裝表層20覆蓋該些發光二極體晶片11的第一電極13;該封裝表層20具有至少二盲孔21,該些盲孔21於對應該些發光二極體晶片11的位置穿過該封裝表層20,並顯露該些發光二極體晶片11的第一電極13;該些導出電極22填充於該些盲孔21內,且該些導出電極22分別電性連接該些發光二極體晶片11的第一電極13,其中該些發光二極體晶片11、該些導出電極22與該些盲孔21,於圖式中為繪製三個代表之。 Please refer to FIG. 3, FIG. 4 and FIG. 5 together, which is a wafer level light emitting diode package structure formed according to the above method steps S1-S10, as shown in the figure, which comprises at least two light emitting two. The polar body wafer 11, the package surface layer 20, the at least two lead-out electrodes 22, the encapsulation layer 40, the common electrode 42, the common electric line 50, and the line protection layer 60. The LEDs 11 have a first electrode 13 and a second electrode 14 on the upper and lower sides. The package surface 20 covers the first electrodes 13 of the LEDs 11; the package surface 20 has at least two blinds. Holes 21 passing through the package surface layer 20 at positions corresponding to the LED chips 11 and exposing the first electrodes 13 of the LED chips 11; the lead electrodes 22 are filled in The plurality of lead electrodes 21 are electrically connected to the first electrodes 13 of the LED chips 11 , wherein the light emitting diode chips 11 , the lead electrodes 22 and the blind electrodes Hole 21, in the figure, draws three representations.

又該封裝層40覆蓋該些發光二極體晶片11的側邊,且該封裝層40與該封裝表層20等高而形成共平面,並該封裝層40具有貫穿兩側的貫孔41;該共電極42填充於該貫孔41內;該共電線路50設置於該封裝層40與該封裝表層20上,且該共電線路50電性連接該共電極42與該些導出電極22;該線路保護層60覆蓋該封裝層40與該封裝表層20上的該些導出電極22、該共電極42與該共電線路50。 The encapsulation layer 40 covers the sides of the LED array 11 , and the encapsulation layer 40 is coplanar with the package surface layer 20 , and the encapsulation layer 40 has a through hole 41 extending through the two sides; The common electrode 42 is filled in the through hole 41; the common line 50 is disposed on the package layer 40 and the package surface layer 20, and the common line 50 is electrically connected to the common electrode 42 and the lead electrodes 22; The line protection layer 60 covers the encapsulation layer 40 and the derivation electrode 22 on the encapsulation surface layer 20, the common electrode 42 and the common electric line 50.

如上所述的結構,本發明的優點至少包含: With the structure as described above, the advantages of the present invention include at least:

1.利用晶圓保護膜12作為封裝的載體,無需使用封裝基板,可節省成本。 1. Using the wafer protective film 12 as a package carrier, it is possible to save costs without using a package substrate.

2.為利用印刷技術,同時印刷複數共電線路50,可改善製程生產的速度。 2. In order to utilize the printing technology and simultaneously print a plurality of common electric lines 50, the speed of the process production can be improved.

3.製成的封裝結構,可藉由SMT方式直接上件(on board),藉以提升生產效率。 3. The manufactured package structure can be directly on the board by SMT method, thereby improving production efficiency.

綜上所述僅為本發明之較佳實施例而已,並非用來限定本發明之實施範圍,即凡依本發明申請專利範圍所做的均等變化與修飾,皆為本發明申請專利範圍所涵蓋。 The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, that is, the equivalent variations and modifications made by the scope of the present invention are covered by the scope of the patent application of the present invention. .

Claims (10)

一種晶圓級發光二極體封裝方法,用於封裝複數發光二極體晶片,該些發光二極體晶片尚未分離而集合形成一晶圓,且該晶圓黏貼於一晶圓保護膜上,並該些發光二極體晶片具有位於上下兩面的一第一電極與一第二電極,其封裝方法包含:步驟S1:覆蓋封裝膠材,步驟S1為於該晶圓的上面覆蓋一封裝表層,該封裝表層覆蓋該些發光二極體晶片的該第一電極;步驟S2:鑽盲孔,步驟S2為於該封裝表層對應該些發光二極體晶片的位置進行鑽孔而形成複數盲孔,該些盲孔顯露該些發光二極體晶片的該第一電極;步驟S3:形成導出電極,步驟S3為於該些盲孔上分別填充導電材而形成複數導出電極,該些導出電極分別電性連接該些發光二極體晶片的該第一電極;步驟S4:切割;步驟S4為對該晶圓進行切割,讓該些發光二極體晶片分離為單一個體;步驟S5:分選測試,步驟S5為對該些發光二極體晶片進行測試,剔除損壞的該發光二極體晶片,並將剩餘的該些發光二極體晶片分組重新排列於該晶圓保護膜上,又該晶圓保護膜定義出複數封裝區域,且相同分組的該些發光二極體晶片位於相同的該封裝區域;步驟S6:建構封裝主體,步驟S6為於該晶圓保護膜上形成一封裝層,該封裝層覆蓋該些發光二極體晶片的側邊,且該封裝層與該封裝表層等高而形成共平面;步驟S7:形成共電極,步驟S7為於每一該封裝區域的該封裝層上鑽孔,而於該封裝層上形成複數貫孔,並於該些貫孔填充導電材而形成複數共電極; 步驟S8:形成共電線路,步驟S8為於該封裝層與該封裝表層上同時印刷複數共電線路,且每一該封裝區域對應設置一個該共電線路,並該共電線路電性連接該封裝區域內的該共電極與該導出電極;步驟S9:形成線路保護層,步驟S9為於該封裝層與該封裝表層上形成一線路保護層,該線路保護層覆蓋該封裝層與該封裝表層上的該些導出電極、該些共電極與該些共電線路。 A wafer level light emitting diode package method for packaging a plurality of light emitting diode chips, wherein the light emitting diode chips are not separated and assembled to form a wafer, and the wafer is adhered to a wafer protective film, The light-emitting diode chip has a first electrode and a second electrode on the upper and lower sides, and the package method includes: step S1: covering the package adhesive, and step S1 is to cover a surface of the package on the upper surface of the wafer. The package surface layer covers the first electrodes of the LED chips; Step S2: drilling blind holes, and step S2 is to drill a plurality of blind holes in the package surface layer corresponding to the positions of the LED chips. The blind holes expose the first electrodes of the LED chips; Step S3: forming the derivation electrodes, and step S3 is to fill the blind holes with conductive materials to form a plurality of derivation electrodes, and the derivation electrodes are respectively electrically The first electrode of the light emitting diode chip is connected; step S4: cutting; step S4 is to cut the wafer to separate the light emitting diode wafers into a single individual; step S5: sorting test Step S5 is to test the LED chips, reject the damaged LED chip, and rearrange the remaining LED chips on the wafer protection film, and the wafer The protective film defines a plurality of package regions, and the same group of the LED chips are located in the same package region; Step S6: constructing the package body, and step S6 is to form an encapsulation layer on the wafer protection film, the package The layer covers the sides of the LED chips, and the encapsulation layer is equal to the package surface layer to form a coplanar surface; step S7: forming a common electrode, and step S7 is drilling the encapsulation layer of each of the package regions a plurality of through holes are formed in the encapsulation layer, and the plurality of through holes are filled in the through holes to form a plurality of common electrodes; Step S8: forming a common electric circuit, step S8 is to simultaneously print a plurality of common electric lines on the encapsulation layer and the package surface layer, and each of the package areas is correspondingly disposed with one common electric line, and the common electric line is electrically connected to the The common electrode and the lead-out electrode in the package area; step S9: forming a line protection layer, step S9 is to form a line protection layer on the package layer and the package surface layer, the line protection layer covering the package layer and the package surface layer The lead-out electrodes, the common electrodes, and the common lines. 如申請專利範圍第1項所述之晶圓級發光二極體封裝方法,其中更包含一步驟S10:成品切割,步驟S10為讓該封裝區域作為切割單位,對該封裝層進行切割。 The wafer level LED package method according to claim 1, further comprising a step S10: finalizing the cutting, and step S10 is to cut the encapsulation layer by using the encapsulation area as a cutting unit. 如申請專利範圍第1項所述之晶圓級發光二極體封裝方法,其中該些發光二極體晶片的發光顏色為單一色。 The wafer level light emitting diode package method of claim 1, wherein the light emitting color of the light emitting diode chips is a single color. 如申請專利範圍第1項所述之晶圓級發光二極體封裝方法,其中該些發光二極體晶片的發光顏色分別為選自紅、綠與藍的任一種。 The wafer level light emitting diode package method according to claim 1, wherein the light emitting color of the light emitting diode chips is any one selected from the group consisting of red, green and blue. 如申請專利範圍第4項所述之晶圓級發光二極體封裝方法,其中相同分組的該些發光二極體晶片為三個,且該三發光二極體晶片的發光顏色分別為紅、綠與藍。 The wafer-level light-emitting diode package method of claim 4, wherein the plurality of light-emitting diode chips of the same group are three, and the color of the three-light-emitting diode chip is red, respectively. Green and blue. 如申請專利範圍第1項所述之晶圓級發光二極體封裝方法,其中步驟S2與步驟S7的鑽孔方法為選自雷射與鑽頭的任一種。 The wafer level light emitting diode packaging method according to claim 1, wherein the drilling method of step S2 and step S7 is any one selected from the group consisting of a laser and a drill. 一種晶圓級發光二極體封裝結構,其結構包含:至少二發光二極體晶片,該些發光二極體晶片具有位於上下兩面的一第一電極與一第二電極; 一封裝表層,該封裝表層覆蓋該些發光二極體晶片的該第一電極,該封裝表層具有至少二盲孔,該些盲孔於對應該些發光二極體晶片的位置穿過該封裝表層,並顯露該些發光二極體晶片的該第一電極;至少二導出電極,該些導出電極填充於該些盲孔內,且該些導出電極分別電性連接該些發光二極體晶片的該第一電極;一封裝層,該封裝層覆蓋該些發光二極體晶片的側邊,且該封裝層與該封裝表層等高而形成共平面,並該封裝層具有貫穿兩側的一貫孔;一共電極,該共電極填充於該貫孔內;一共電線路,該共電線路設置於該封裝層與該封裝表層上,且該共電線路電性連接該共電極與該些導出電極;以及一線路保護層,該線路保護層覆蓋該封裝層與該封裝表層上的該些導出電極、該共電極與該共電線路。 A wafer-level light-emitting diode package structure comprising: at least two light-emitting diode chips, wherein the light-emitting diode chips have a first electrode and a second electrode on the upper and lower sides; a package surface layer covering the first electrode of the light emitting diode chip, the package surface layer having at least two blind holes, the blind holes passing through the package surface at positions corresponding to the light emitting diode wafers And exposing the first electrodes of the LED chips; at least two deriving electrodes, the deriving electrodes are filled in the blind holes, and the deriving electrodes are electrically connected to the LED chips respectively The first electrode; an encapsulation layer covering the side edges of the LED chips, and the encapsulation layer is coplanar with the package surface layer, and the encapsulation layer has a consistent hole penetrating the two sides a common electrode, the common electrode is filled in the through hole; a common electric circuit, the common electric line is disposed on the encapsulation layer and the package surface layer, and the common electric line is electrically connected to the common electrode and the derivation electrodes; And a line protection layer covering the encapsulation layer and the derivation electrodes, the common electrode and the common electric line on the encapsulation surface layer. 如申請專利範圍第7項所述之晶圓級發光二極體封裝結構,其中該些發光二極體晶片的發光顏色為單一色。 The wafer-level light emitting diode package structure according to claim 7, wherein the light emitting color of the light emitting diode chips is a single color. 如申請專利範圍第7項所述之晶圓級發光二極體封裝結構,其中該些發光二極體晶片的發光顏色為選自紅、綠與藍的任一種。 The wafer level light emitting diode package structure according to claim 7, wherein the light emitting color of the light emitting diode chips is any one selected from the group consisting of red, green and blue. 如申請專利範圍第9項所述之晶圓級發光二極體封裝結構,其中該些發光二極體晶片具有三個,且該三發光二極體晶片的發光顏色分別為紅、綠與藍。 The wafer-level light-emitting diode package structure according to claim 9, wherein the light-emitting diode chips have three colors, and the three-light-emitting diode chips have red, green and blue colors respectively. .
TW107137355A 2018-10-23 2018-10-23 Wafer level light emitting diode packaging method and structure thereof TWI672832B (en)

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