200922429 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種多層電路板結構及製造方法，特別是關於一 種具有内埋元件的多層電路板結構及製造方法。 、 【先前技術】 單一可攜式電子產品上運用了愈來愈多的被動元件。早期被動 元件以晶片型分離式元件(Discrete Components)為發展重心。不 過’由+於這一類的元件仍有其發展限制，例如元件的切割及相關表 面黏著設備之搭配，致使内埋元件電路板技術(Em]3eddedPassiveQi> Intergral Substrates)逐漸受到青睞。 ^内埋元件電路板技術能提高被動元件效能、減少被動元件數 量，並且降低被動元件佔用的電路板面積。因此，利用内埋元件電 路板技術的構裝整合，可以用來取代傳統分離式被動元件，例如電 谷器、電阻及電感專，其優點為減少分離式被動元件的使用數量， 進而降低產品的相關製作與檢測成本，減少被動元件的 提高產品構裝密度與可靠度等。 在内埋元件電路板技術中，為了增加佈線面積，多層電路板用 上了更多的導電層及埋設被動元件用的孔洞，例如導孔(via)、埋孔 (Buried vias)或盲孔(Blind vias)等。導孔通常打穿整個多層電路板， 因此可能會浪費一些導電層的線路空間。埋孔和盲孔技術可以避免 這個問題，因為它們只穿透其中幾個導電層。 圖1顯示一習知的多層電路板100，其包括一絕緣基板1〇2、 二個圖案化的内層線路1〇4及1〇6、二圖案化的外層線路1〇8及 110’以及一内埋的被動元件112。製造多層電路板的流程係先製作 内層線路104及106於絕緣基板1〇2上，此步驟包括前處理，上光 阻劑、曝光、顯影、飯刻及去光阻等細部財，接著使用機械或雷 射鑽孔挖出一埋孔(未標號)貫穿二内層線路1〇4及應及絕緣基板 102。然後，將被動元件112埋入埋孔中，再將二絕緣樹脂114及 116壓合於二内層線路1〇4及1〇6及被動元件112上。接著，將兩 106 200922429 外層線路108及no壓合於 技術仍有改良郎。 的佈線需求，上述内埋元件電路板 【發明内容】 ή如，明之目的在於提供—齡層電路板結構及製造方法以改 得到進—步的ϋ。的和優點可樣本㈣所揭露的技術特徵中 $達上述之-或部份或全部目的或是其他目的，本發明之一實 施^樣的多層電路板製造方法，包括提供i緣基板；形成一凹穴 凹陷於絕緣基板之上表面，但未穿透絕緣基板，使凹穴具有一底 面:形成複數通孔自凹穴之底面貫穿絕緣基板之下表面；埋設一電 子元件於凹穴中，其中電子元件具有複數接點對準通孔；形成一第 一導電層於絕緣基板之上表面，並覆蓋凹穴；以及形成一第二導電 層於絕緣基板之下表面，並覆蓋通孔。 上述提供絕緣基板之步驟包括：提供一多層板包括絕緣基板以 及兩金屬層分別形成於絕緣基板之上表面及下表面；全面移除兩金 屬層以曝露絕緣基板之上表面及下表面。上述全面移除兩金屬層之 步驟包括姓刻兩金屬層。上述形成凹穴之步驟包括以雷射鑽孔或機 械鑽孔技術形成凹穴。上述形成通孔之步驟包括以雷射鑽孔或機械 鑽孔技術形成通孔。上述形成第一導電層及第二導電層之步驟包括 以雙面電鍍技術同時形成第一導電層及第二導電層。 上述多層電路板製造方法更包括形成一第二通孔於凹穴之一 側，藉由第二通孔使第一導電層電性連接於第二導電層，再圖案化 第一導電層及第二導電層。在埋設電子元件之前，填充一黏著膠於 凹穴底面。在埋設電子元件之後，以及在形成第二導電層之前，清 200922429 ‘術清、(去除黏者膠。上述清潔通孔内部之步驟係以雷射鑽孔 電子實if、樣係提供多層f路板，包括—絕緣基板、一 ίΐϊί二ί電層以及一第二導電層。絕緣基板具有一凹穴 凹穴之底® 未ί穿其τ表面，以及複數通孔貫穿其下表面及 第-ίΐΐ位設於凹穴中，並且具有複數接點對準通孔。 層位於絕i魅，€、·彖基板之上表面，並覆蓋於凹穴之上。第二導電 i元件及並覆蓋於通孔之上’並且電性連接於電 第二包括—第—介電層位於第—導電層之上，以及一 上;及上 三導電層位於第一介電層之 -莫雷導電層第二介電層之上。上述第-導電層與第 V電層鋼層。電子元件係為—主動元件或 【實施方式】 i去ί，本發明之前述及其他技_容、特點與功效，在以下配合 it較佳實施例的詳細說明中，將可清楚的呈現。以下實 方向用語’例如：上、下、左、右、前或後等，僅 來限Ϊ本=的方向°因此，使用的方向用語是用來說明並非用 圖2之多層電路板200至少包括一絕緣基板202、一電子元件 有=ϋ(Μ20Λ以及一第二導電層208。絕緣基板202具 =，八210貝穿其上表面2m，但未貫穿其下表面2〇3 ,並且具 f複數通孔212貫穿其下表面2G3及凹穴21()之底面214。電子元 ==04没於凹穴21〇中，並且具有複數接點216對準通孔212。第 ¥電層206位於絕緣基板202之上表面2〇1，並覆蓋於凹穴21〇 =上。、第二導電層識位於絕緣基板2G2之下表面203以覆蓋通孔 212，並且電性連接於電子元件204及第一導電層206。 ，2結構之製造方法如下。首先，提供絕緣基板202，並且形 1凹八210其凹陷於絕緣基板202之上表面2〇1，但未穿透絕緣 基板202，而使凹穴21〇形成底面214 ;形成複數通孔212自凹穴 200922429 210之底面214貫穿絕緣基板202之下表面；埋設電子元件204於 凹穴210中，並以其複數接點216對準通孔；形成第一導電層2〇6 於絕緣基板202之上表面2〇1，並覆蓋凹穴21〇 ;以及形成第二導 電層=08於絕緣基板2〇2之下表面203 ,並覆蓋通孔212。 、清f照圖3A至圖3G，較詳細地說明多層電路板製造方法。 首先，提供一如圖3A所示的多層板3〇〇包括絕緣基板2〇2以及兩 金屬層3^2及304分別形成於絕緣基板2〇2之上表面2〇1及下表面 203。接著，全面移除兩金屬層3〇2及3〇4以曝露絕緣基板2〇2之 上表面201及下表面2〇3 ’其結果如圖3]B。全面移除兩金屬層3〇2 及304之方法包括|虫刻兩金屬層及304。 .再參照圖3C ’係以雷射鑽孔或機械鑽孔技術形成凹穴21〇及 通孔=12。特別地，若以機械鑽孔技術形成凹穴21〇或通孔212， 則凹穴210_或通孔212的側壁與底面之夾角較接近直角，其側剖面 如圖3C所示的矩形凹穴21〇。若以雷射鑽孔技術形成凹穴或通孔， 則凹或通孔的側壁與底面之夾角通常並非直角，其侧剖面如圖 3C；所示的梯形通孔212。另外，形成一通孔3〇6於凹穴21〇之一側 以便於後續製程中填入導電材料。 接著:如圖3D所示，先於凹穴21〇底面填充一黏著膠3〇8， 再將電子元件204埋入凹& 210中，並藉由黏著膠3〇8 g]定於凹穴 中 210。 少圖3E ^+不在埋設電子元件2〇4之後，清潔通孔212内部以去 除多巧之黏著膠308，例如：以雷射鑽孔技術清潔通孔212。接著 再將第-★導電層206及第二導電層2〇8分別形成於圖3D結構之上 表面。第了導電層206及第二導電層208可以雙面電鍍技術同時 形成。在此過程中，同時將導電材料填入通孔3〇6中以使第一導電 層206及第二導電層208能夠電性連接。在形成第二導電層2〇8的 同時，也將導電材料填充於通孔212中，使第二導電層208與電子 元件204電性連接。 圖3F顯示圖案化後的第一導電層2〇6及第二導電層2〇8。 圖3G顯示，在一較佳實施方式中，可更進一步形成一第一介 200922429 電於第一導電層206之上，以及形成一第二介電層312於第 了導電層208之上。接著，於第一及第二介電層31〇、312上挖】 孔洞314、316,再形成-第三導電層318於第一介電層31〇之上， ^及形成-第四導電層32。位於第二介電層312之上。如此 ί =藉由孔洞314與第—導電層206電性連接，並 f德真楚2可藉由孔洞316與第二導電層208電性連接。 板= 第四導電層318、320即可製作完成-多層 在上述所有實施例中，電子元件可為一主動元件，例如：精 電路晶片（1C 主動元件具有一接觸塾322位於一主動^ 上，主動表面係藉由接觸塾322對準通孔212 :電容、電感，紐器。若以機械鑽^貝 =0或通孔212之孔控範圍為3〜5inm。若以雷射鑽孔，咖穴 =通孔212之孔徑範圍為70〜100^m。第、 層观、第三導電層训、第四導電層32〇皆可電為曰銅層。 二介電層310及312可為絕緣膠層β自湖盾第及第 Ϊ 2〇2之材料可為玻纖布、絕緣紙等加上含浸樹腊，例 雔祕樹脂、聚亞酿胺樹脂等。絕緣基板202經裁片 ίί板又面附加銅箱，經過熱壓成型後，即為圖3a所示銅 元成畦路製程後的多層電路板外層，再塗、^ ^ ^ 至相鄰線路造成短：二： =======賴峨板，再作表BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board structure and a manufacturing method thereof, and more particularly to a multilayer circuit board structure and a manufacturing method having embedded components. [Prior Art] More and more passive components are used in single portable electronic products. Early passive components were focused on Discrete Components. However, the components of this type are still subject to development limitations, such as the cutting of components and the matching of surface bonding equipment, resulting in the gradual popularization of embedded component board technology (Em]3eddedPassiveQi> Intergral Substrates). ^ Buried component board technology can improve passive component performance, reduce the number of passive components, and reduce the board area occupied by passive components. Therefore, the integration of the embedded component board technology can be used to replace the traditional discrete passive components, such as electric grids, resistors and inductors. The advantage is to reduce the number of separate passive components, thereby reducing the product. Related production and testing costs, reducing passive components to improve product density and reliability. In the buried component circuit board technology, in order to increase the wiring area, the multilayer circuit board uses more conductive layers and holes for embedding passive components, such as vias, buried vias, or blind vias ( Blind vias) and so on. The vias typically break through the entire multilayer board, which may waste some of the wiring space of the conductive layer. Buried and blind via techniques can avoid this problem because they only penetrate several of the conductive layers. 1 shows a conventional multilayer circuit board 100 comprising an insulative substrate 1 2, two patterned inner layer lines 1〇4 and 1〇6, two patterned outer layer lines 1〇8 and 110′, and a Buried passive component 112. The process of manufacturing the multi-layer circuit board is to first fabricate the inner layer lines 104 and 106 on the insulating substrate 1〇2. This step includes pre-processing, upper photoresist, exposure, development, rice etching and photoresist removal, and then using machinery. Or a laser hole is drilled to dig a buried hole (not labeled) through the two inner layer lines 1 and 4 and the insulating substrate 102. Then, the passive component 112 is buried in the buried via, and the two insulating resins 114 and 116 are bonded to the two inner wirings 1〇4 and 1〇6 and the passive component 112. Next, the two 106 200922429 outer lines 108 and no are pressed into the technology. The wiring requirement, the above-mentioned embedded component circuit board [Summary of the Invention] For example, the purpose of the invention is to provide an age-old layer circuit board structure and a manufacturing method to obtain a further step. And the advantages of the method disclosed in the fourth aspect of the present invention, which may be the above-mentioned or some or all of the objectives or other objects, the method for manufacturing a multilayer circuit board according to one embodiment of the present invention, comprising providing an i-edge substrate; forming a The recess is recessed on the upper surface of the insulating substrate, but does not penetrate the insulating substrate, so that the recess has a bottom surface: a plurality of through holes are formed from the bottom surface of the recess through the lower surface of the insulating substrate; an electronic component is embedded in the recess, wherein the electronic component Having a plurality of contacts aligned with the vias; forming a first conductive layer on the upper surface of the insulating substrate and covering the recesses; and forming a second conductive layer on the lower surface of the insulating substrate and covering the through holes. The step of providing the insulating substrate comprises: providing a multilayer board comprising an insulating substrate and two metal layers respectively formed on the upper surface and the lower surface of the insulating substrate; and removing the two metal layers to expose the upper surface and the lower surface of the insulating substrate. The above steps of completely removing the two metal layers include the first two metal layers. The step of forming the recesses described above includes forming the pockets by laser drilling or mechanical drilling techniques. The step of forming the through holes described above includes forming the through holes by laser drilling or mechanical drilling techniques. The step of forming the first conductive layer and the second conductive layer includes simultaneously forming the first conductive layer and the second conductive layer by double-sided plating. The method for fabricating a multilayer circuit board further includes forming a second via hole on one side of the recess, electrically connecting the first conductive layer to the second conductive layer through the second via hole, and then patterning the first conductive layer and the first conductive layer Two conductive layers. An adhesive is applied to the underside of the recess prior to embedding the electronic component. After embedding the electronic components, and before forming the second conductive layer, clear 200922429 'clearing, (removing the adhesive. The above steps of cleaning the through-holes are provided by the laser drilling electrons, the sample system provides multiple layers of f The board includes an insulating substrate, an electric layer, and a second conductive layer. The insulating substrate has a bottom of the recessed hole, the bottom surface of the recessed hole is not worn, and the plurality of through holes penetrate the lower surface thereof and the first layer The position is set in the cavity, and has a plurality of contacts aligned with the through hole. The layer is located on the upper surface of the substrate, and covers the upper surface of the substrate, and covers the second hole. Above the hole 'and electrically connected to the second second-first dielectric layer on the first conductive layer, and one upper; and the upper three conductive layer is located on the first dielectric layer - the second conductive layer Above the dielectric layer, the first conductive layer and the fifth electrical layer steel layer. The electronic component is an active component or an embodiment, and the foregoing and other techniques, features, and functions of the present invention are In the following detailed description of the preferred embodiment, it will be clear Present. The following real-directional terms 'for example: up, down, left, right, front or back, etc., only limit the direction of the = =. Therefore, the directional term used is used to illustrate that the multi-layer circuit board 200 is not used in FIG. The method includes at least one insulating substrate 202, an electronic component having a ϋ20Μ and a second conductive layer 208. The insulating substrate 202 has ???, the octa 210 is penetrated through the upper surface thereof by 2m, but does not penetrate the lower surface thereof 2〇3, and has The plurality of through holes 212 extend through the lower surface 2G3 and the bottom surface 214 of the recess 21 (). The electron element = =0 is not in the recess 21, and has a plurality of contacts 216 aligned with the through holes 212. The electric layer 206 The second surface of the insulating substrate 202 is located on the lower surface 203 of the insulating substrate 2G2 to cover the through hole 212, and is electrically connected to the electronic component 204 and The manufacturing method of the first conductive layer 206, 2 structure is as follows. First, the insulating substrate 202 is provided, and the concave portion 210 is recessed on the upper surface 2〇1 of the insulating substrate 202, but does not penetrate the insulating substrate 202, thereby making The recess 21〇 forms a bottom surface 214; the plurality of through holes 212 are formed from the bottom surface of the recess 200922429 210 The 214 is inserted through the lower surface of the insulating substrate 202; the electronic component 204 is embedded in the recess 210, and the plurality of contacts 216 are aligned with the through holes; the first conductive layer 2 is formed on the upper surface of the insulating substrate 202, And covering the recess 21〇; and forming a second conductive layer=08 on the lower surface 203 of the insulating substrate 2〇2, and covering the through hole 212. Clearly, according to FIG. 3A to FIG. 3G, the multilayer circuit board manufacturing is described in more detail. First, a multi-layer board 3 shown in FIG. 3A is provided, including an insulating substrate 2〇2, and two metal layers 3^2 and 304 are respectively formed on the upper surface 2〇1 and the lower surface 203 of the insulating substrate 2〇2. . Next, the two metal layers 3〇2 and 3〇4 are completely removed to expose the upper surface 201 and the lower surface 2〇3' of the insulating substrate 2〇2. The result is shown in Fig. 3]B. The method of completely removing the two metal layers 3〇2 and 304 includes etching the two metal layers and 304. Referring again to Figure 3C, the recess 21 and the through hole = 12 are formed by laser drilling or mechanical drilling techniques. In particular, if the recess 21 〇 or the through hole 212 is formed by a mechanical drilling technique, the angle between the side wall of the recess 210_ or the through hole 212 and the bottom surface is closer to a right angle, and the side cross section is a rectangular recess as shown in FIG. 3C. 21〇. If a recess or a through hole is formed by a laser drilling technique, the angle between the side wall of the recess or the through hole and the bottom surface is usually not a right angle, and the side cross section is as shown in Fig. 3C; the trapezoidal through hole 212 is shown. Further, a through hole 3〇6 is formed on one side of the recess 21〇 to facilitate filling of a conductive material in a subsequent process. Next, as shown in FIG. 3D, an adhesive 3〇8 is filled on the bottom surface of the recess 21, and the electronic component 204 is buried in the concave & 210, and is fixed in the recess by the adhesive 3〇8 g]. In 210. Less Figure 3E ^+ After the electronic component 2〇4 is buried, the inside of the through hole 212 is cleaned to remove the adhesive 308, for example, the through hole 212 is cleaned by a laser drilling technique. Next, the first conductive layer 206 and the second conductive layer 2 are formed on the upper surface of the structure of Fig. 3D. The first conductive layer 206 and the second conductive layer 208 can be formed simultaneously by double-sided plating. During this process, a conductive material is simultaneously filled into the via holes 3〇6 to electrically connect the first conductive layer 206 and the second conductive layer 208. While the second conductive layer 2 is formed, the conductive material is also filled in the via hole 212 to electrically connect the second conductive layer 208 with the electronic component 204. FIG. 3F shows the patterned first conductive layer 2〇6 and second conductive layer 2〇8. FIG. 3G shows that, in a preferred embodiment, a first dielectric layer 200922429 can be further formed over the first conductive layer 206, and a second dielectric layer 312 is formed over the first conductive layer 208. Then, holes 314 and 316 are formed on the first and second dielectric layers 31, 312, and a third conductive layer 318 is formed on the first dielectric layer 31, and a fourth conductive layer is formed. 32. Located above the second dielectric layer 312. Thus, the hole 314 is electrically connected to the first conductive layer 206, and the ground electrode 316 is electrically connected to the second conductive layer 208 by the hole 316. Plate = fourth conductive layer 318, 320 can be completed - multi-layer in all of the above embodiments, the electronic component can be an active component, such as a precision circuit chip (1C active component has a contact 322 located on an active ^ The active surface is aligned with the through hole 212 by the contact 塾 322: a capacitor, an inductor, and a new device. If the mechanical drill is used, the hole control range is 3 to 5 inm. The hole diameter of the hole = through hole 212 is 70~100^m. The first layer, the third layer, and the fourth layer 32 can be electrically formed of a beryllium copper layer. The second dielectric layers 310 and 312 can be insulated. The material of the rubber layer β from the lake shield and the second layer 2〇2 may be a fiberglass cloth, an insulating paper or the like, and an impregnated tree wax, such as a secret resin, a polyamidamine resin, etc. The insulating substrate 202 is cut into pieces ίί板After adding the copper box, after hot pressing, it is the outer layer of the multilayer circuit board after the copper element forming process shown in Fig. 3a, and then coated, ^ ^ ^ to the adjacent line to cause short: two: ==== ===Lie 峨 board, then make a table
^ PTHf^pZV trough Hole ； W 刹躺的方々，舰電路板主要的製造方法’可利用通孔電鍍與蝕 h +式將基板表面局部無用的銅箔除掉，而形成電路的減 成法(Substractive Process)以及在盔導體的其奴类而里 減 學銅進行局部導體線路的)加成另加阻劑以化 顺的減成法中又可分為全板電錄(pand piating)法與線路電 200922429 種方式。前者以鏡金、鑛錫紹再經侧方式 i解銅彳是在絕緣基板上，全面進行無€解銅層，再以 線「成。加成法主要可分為在無銅狀基板表面以化學 二“如之产加成法（FuU_Additive)」，以及採用超薄銅皮(UCF) 二二且y進負片法線路鍍銅與錫鉛，再經剝膜、蝕刻成之厂部 伤加成法(Partial-Additive)」。 - 士 T以士所述者’僅為本發明之較佳實施例而已’當不能以此限 =本發明實施之範圍’即大凡鉢發明申請判顧及發明說明内 各所作之簡單的等效變化與修飾，皆仍屬本發料利涵蓋之範圍 内。另外本發明的任-實關或申請專利範圍不織成本發明所揭 露之全部目的或優點或特點。此外，摘要部分和標題僅是用來辅助 專利文件搜尋之用，並非甩來限制本發明之權利範圍。 【圖式簡單說明】 圖1為一習知的多層電路板不意圖。 圖2為依據本發明之一實施例之多層電路板的示意圖。 圖3A至圖3G為依據本發明之多層電路板的製造方法示意圖。 【主要元件符號說明】 100 多層電路板 102 絕緣基板 104 、 106 内層線路 108、110 外層線路 112 被動元件 114 、 116 f絕緣樹脂 200 多層電路板 201 上表面 202 絕緣基板 203 下表面 200922429 204 電子元件 206 第一導電層 208 第二導電層 210 凹穴 212 通孔 214 底面 216 接點 300 多層板 302、304 金屬層 306 通孔 308 黏著膠 310 第一介電層 312 第二介電層 314、316 孔洞 318 第三導電層 320 第四導電層 322 接觸墊 330 多層電路板^ PTHf^pZV trough Hole ; W The square of the brakes, the main manufacturing method of the ship's circuit board can use the through-hole plating and etching h + type to remove the copper foil which is partially useless on the surface of the substrate, and form a circuit subtractive method ( Substractive Process) and the addition of copper to the slave conductors to reduce the copper for the local conductor circuit. Addition of a resist to the smoothing reduction method can be divided into a full-panel piating method and Line electricity 200922429 ways. The former uses the mirror gold, the tin-salt and the side-by-side method to solve the copper enamel on the insulating substrate, and the copper layer is completely uncoated, and then the wire is formed. The addition method can be mainly divided into the surface of the copper-free substrate. Chemistry II "FuU_Additive", and the use of ultra-thin copper (UCF) 22 and y into the negative film line copper and tin-lead, and then stripped, etched into the factory damage bonus Partial-Additive. - 士 士 士 者 者 者 者 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' And modifications are still within the scope of this release. In addition, the scope of the invention is not limited to the full scope or advantages or features of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional multilayer circuit board. 2 is a schematic diagram of a multilayer circuit board in accordance with an embodiment of the present invention. 3A to 3G are schematic views showing a method of manufacturing a multilayer circuit board according to the present invention. [Main component symbol description] 100 multilayer circuit board 102 Insulating substrate 104, 106 Inner layer wiring 108, 110 Outer wiring 112 Passive element 114, 116 f Insulating resin 200 Multi-layer circuit board 201 Upper surface 202 Insulating substrate 203 Lower surface 200922429 204 Electronic component 206 First conductive layer 208 second conductive layer 210 recess 212 through hole 214 bottom surface 216 contact 300 multilayer board 302, 304 metal layer 306 through hole 308 adhesive 310 first dielectric layer 312 second dielectric layer 314, 316 hole 318 third conductive layer 320 fourth conductive layer 322 contact pad 330 multilayer circuit board