200919669 九、發明說明： 【發明所屬之技術領域】 本發明係有關於-種半導體之封裝方法，特別是有關於在晶粒上形成 金屬層(UBM)以電性連接焊墊，且取代錫球以做為導電元件，而進行晶粒重 新配置之封裝方法。 & 【先前技術】 半導體的技術已經發展的相當的迅速，因此微型化的半導體晶粒(以⑶) 必須具有多樣化的功能的需求，使得半導體晶粒必須要在很小的區域中配 置更多的輸入/輸出墊(I/O pads)，因而使得金屬接腳❻丨把)的密度也快速的 提南了。因此’早期的導線架封裝技術已經不適合高密度之金屬接腳；故 發展出一種球陣列(BallGridArray:BGA)的封裝技術，球陣列封裝除了有比 導線架封裝更面密度之優點外，其錫球也比較不容易損害與變形。 隨著3C產品的流行，例如：行動電話(CeU ph〇ne )、個人數位助理(pDA ) 或疋iPod等，都必須要將許多複雜的系統晶片放入一個非常小的空間中， 因此為解决此問通，一種稱為「晶圓級封裝（職知；wlp)」 之封裝技舰姆展出來’其可以在洲晶圓成為—麵的晶粒之前，就 先對晶圓進行封裝。美國專利公告第5,323，G51號即揭露了這種「晶圓級封 裝」技術。然而’這種「晶圓級封裝」技術隨著晶粒主動面上的焊塾①油) 數目的增加’使得焊塾(pads)之間距過小，除了會導致訊號耗合或訊號干擾 的問題外，也會因為焊墊間距過小而造成封裝之可靠度降低等問題。因此， 當晶粒再更進一步的縮小後’使得前述的封裝技術都無法滿足。 為解决此問題’美國專利公告第7,196,4〇8號已揭露了 一種將完成半 導體製程之晶圓，經過測試及切割後，將測試結果為良好的晶粒（㈣㈣ 重新放置於另彳U基板之上，然後再進行封裝製程，如此，使得這些被重 新放置的晶粒間具有較寬關距，故可以將晶粒上的科適當的分配，例 200919669 如使用橫向延伸（fanQut)技術，因此可財效解決關距過小，除 致訊號柄合或訊號干擾的問題。 然而，為使半導體晶片能夠有較小及較薄的封裝結構，在進行晶圓切 割前，會先對晶圓進行薄化處理，例如以背磨卿㈣方=將晶 圓薄化至2〜2(Μ ’然後再切誠—麵的晶粒。此—經過薄化處^之曰曰曰 粒，經過重新配置料—基板上，私注财切複數㈣細彡成一封^ 體’由於晶粒㈣’使得封膠體也是非常的薄，故當封膠體脫離基板之後， 封膠體本身的應力錢得封縣產生麟，增加賴進行_製程的困難。 另外，在晶_割之後，重新配置在另—個基板時，由於新的基板的 尺寸較原來的尺寸為大，因此在後續植球製程_，會無法對準，其封裝結 【發明内容】 有鑒於發明背景中所述之植球對準以及娜_曲的問題，本發明提 供-種糊晶粒背面之對準標誌，且在晶粒上形成金麟(刪)做為導電元 件與焊墊之雜連接之晶粒重新配置之封裝結構及其方法，將複數個晶粒 重新進桃置並断封裝之方法。故本發明之主要目的係在紐上配置黏 著層，且將晶粒·基板麵所配置之複數個對準標糾可準確的置放在 基板的黏著層上，且金騎(UBM)分聰鱗電元件且與焊触彡成電性 ，接，以進行晶粒重新配置之封裝方法’使得在後續製程中，進行植球之 製程可以解之外，娜體本身可以克服應力騎使得_體在脫離基板 後，保持平整’可有效提高製造之良率及可靠度且可以制於低壓元件， 例如記憶體元件，如RAM。 本發明之又-主要目的在提供—種晶粒重新配置之封裝方法，其可以 將,12时晶圓所切割出來的晶粒重新配置於8忖晶圓之基板上，如料以有 效運用8吋晶圓之即有之封裝設備，而無需重新設立丨2吋晶圓之封裝設 7 200919669 備’可以降低12吋晶圓之封裝成本。 本發明之還有一主要目的在提供一種晶粒重新配置之封裝方法，使得 進行封裝的晶片都是，，已知是功能正常之晶片’，（Known good die)，可以節 省封裝材料，故也可以降低製程之成本 本發明之再一主要目的在提供一種晶粒重新配置之封裝方法，使得進 行封裝的晶片都是”已知是功能正常之晶片’’（Known good die)，可以節省 封裝材料，故也可以降低製程之成本。 Γ 根據以上所述’本發明提供一種晶粒重新配置之封裝方法，包括：提供 複數個晶粒，每一晶粒具有主動面且主動面上配置有複數個焊墊；取放複 數個晶粒至一基板上，每一晶粒係以覆晶方式將主動面與一配置於基板上 的黏著層連接；形成一高分子材料層於基板及部份晶粒上；覆蓋模具裝置 在兩分子材料層上，以平坦化高分子材料層，並使高分子材料層充滿於複 數個晶粒之間且包覆每一晶粒；脫離模具裝置，以曝露出高分子材料層之 表面，脫離基板，以曝露出每一晶粒之主動面及每一焊墊，以形成一封膠 體，形成一第一犧牲層以覆蓋每一晶粒之主動面以及每一焊塾；形成一第 ，二犧牲層於第—犧牲層之上；移除部份第二犧牲層及第—犧牲層以形成一 ί _結構’且在娜於每—晶粒之絲面之紐轉塾處形成複數個孔 洞，以曝露出每一烊墊；形成複數個圖案化之金屬線段在第二犧牲層及第 犧牲層之上’且與每-晶粒之主動面上之複數個焊墊形成電性連接；形 成圖案化之保護層，以覆蓋複數個圖案化之金屬線段，並曝露出位於第 -犧牲層上之部份瞧化之金屬線段；及切割封膠體，以形成複數個各自 獨立之完成封裝之晶粒，其中每一晶粒之五個面均由高分子材料層所包覆。 根據上述之晶《新配置之封裝方法，本發鴨揭露—種晶圓級晶片 封裝結構’包括:-晶粒其主動面上配置有複數個焊塾，一封膠體包覆晶粒 之五個面、―圖案化之高分子採料層以及複數侧案化之金屬線段覆蓋部 8 200919669 份圖案化之高分子材料層，藉由複數個圖案化之金屬線段電性連接至每一 晶粒之主動面上之複數個，其特徵在於：圖案化之高分子材料層 於晶粒之主動面上及其外侧—部份區域形成—向外延伸（f则⑷之 狀結構，其巾向外延伸之端鱗其階梯結射具有較高之結構且在相對於 晶粒之主動面之複數個焊墊處形成—孔洞，以曝露出每―焊塾；複數個圖 案化之金屬線段係形成於圖案化之高分子材料層上，以使每一晶粒之 面上之複油㈣無餘結狀高分子材觸上之複油酵化之 線段電性連接；及-保護層，以覆蓋複數個_化之金祕段及部份圖案 r 化之两分子材料層，並曝露出階梯結構中位於較高處之圖案化之高分子材 料層上之複數個圖案化之金屬線段之一表面。 有關本發_特徵與實作，紐合圖示作最佳實施辦細說明如下。 (為使對本發_目的、構造、特徵、及其魏有進—步的瞭解，兹配合 實施例詳細說明如下。） β 【實施方式】 本發明在此所探討的方向為__種晶粒重新配置之封I方法，將複數個 晶粒重新配置於另-基板上，然後進行封裝的方法。為了能徹底地瞭解本 Μ，將在下顺财巾提出詳㈣轉及其减。雜地，本發明的施 行並未限定晶牌疊的方式之技藝者所熟⑽特殊細n方面，眾所 周知的晶片形成方式以及晶0化等後段製程之詳細步驟並未描述於細節 中，以避免造成本發明不必要之限制。然而，對於本發明的較佳實施例， 則會詳細描壯L除了這些詳細描述之外，本㈣财以廣泛地施 行在其他的實施财’且本發_顧不受蚊，其以之後的專利範圍為 準。 在現代的半導體封裝製程中，均是將一個已經完成前段製程（加扯咖 Process)之晶圓（wafer)先進行薄化處理（Thinningp聰⑷，例如將晶片 200919669 的厚度研磨至2〜20 mil之間；然後，進行晶圓的切割（sawing pr〇cess)以 形成一顆顆的晶粒；然後，使用取放裝置（pickandplace)將一顆顆的晶粒 逐一放置於另一個基板100上，如第i圖所示。很明顯地，基板1〇〇上的 晶粒間隔區域比晶粒11G大，因此，可以使得這些被重新放置的晶粒110 間具有較寬的間距’故可崎晶粒11G上的焊㈣當的分配。此外，本實施 例所使用的封裝方法’可以將12忖晶圓所切割出來的晶粒11G重新配置於 8吋晶圓之基板100上，如此可以有效運用8吋晶圓之即有之封裝設備，而 無需重新设立12吋晶圓之封裝設備，可以降低12吋晶圓之封裝成本。然 後要強調的是，本發明之實施例並未限定使用8吋晶圓大小之基板1〇〇，其 只要能提供承載的魏者’例如：玻璃、石m電路板或金屬薄板 (metal foil)等，均可作為本實施例之基板1〇〇，因此基板1〇〇的形狀也未 加以限制。 請參考第2圖，絲示-基板其背面具有對準標諸俯視圖。如第2圖， 係表不在晶ffl基板社表面上之背面的x_y方向上，設置有複數個對準標該 (alignment mark)202。由先前陳述所知，當一晶圓(未在圖中表示)經過切割 之後形成複數個晶粒’再重新將這些晶粒逐—配置在新的基板2G時，由於 新的基板20之間的晶粒間隔區域比重新配置的晶粒大，在後續封裝製程的 植球步驟(ball_nt)會無法對準，而將導電元件(未在圖中表示)準確的形成 在晶粒的背面上所需的位置’而造成封裝結構的可#度降低。因此，在本 發明的具體實施例中’形成對準標總2〇2的方式可以利用光钱刻 (^o-etching)製程’其係在基板2〇的背面且在巧方向上形成複數個對準 m〇2 ’且其形狀為十字之標諸。另外，形成對準標誌2G2的方式還包括 利用雷射標蕺(laser mark)製程，以形成複數個對準標諸2〇2在基板2〇的背 面上。 接著’第3A圖至第3G圖係表示本發明所揭露之晶粒重新配置之實施 例之各步驟示意圖。首先，如第3A圖所示，係將配置有複數個晶粒之一晶 200919669 圓(未在圖中表示)進行切割，以形成複數個晶粒，，每—晶粒加具有一 主動面且於主動面上配置有複數個焊塾212然後再將複數個晶粒训重新 配置在新的基板2〇上；其巾，在基板Μ上配置有—黏㈣Μ，此點著層 3〇為-具有彈性之黏著材料，例如石夕橡膠(silk〇n灿⑹）、石夕樹脂(咖⑽ “）彈性PU多孔PU、丙烯酸橡膠(acrylic祕㈣或晶粒切割膠等。接 者’使用取放裝置(未在圖中表示)將晶粒21()逐一放置並貼附至基板上 的黏著層3〇，其中_加係以覆晶(flip卿方式並根據基板Μ背面之複 數個對準標誌、，將其主動面上的焊塾212與基板2()上的黏著層％連接。 接著’同樣參考第3A圖，於基板2〇及部份晶粒上21〇上塗佈高分子材料 層40 ’例如polyimide，並且使用一模具裝置將高分子材料層4〇壓平， 使得高分子材料層40形成一平坦化的表面，並且使得高分子材料層40填 滿於晶粒210之間並且每一顆晶粒21〇的五個面均由高分子材料層4〇所包 覆。 接著’可以選擇性地對平坦化的高分子材料層4〇進行一烘烤程序，以 使高分子材料層40卽卜再接著，進行脫模程序，將模具裝置與固化 後的高分子材料層40分離，以裸露出平坦化的高分子材料層4〇的表面； 然後’使用切割刀（未顯示於圖中）在高分子材料層4()的表面上形成複數 條切割道·，如第3B圖所示；每—條切割道的深度為0.^密爾 (mU)，而_道之寬度縣5至25微米。在—較佳得實施例中，此 切割道41G可岐相互垂直交錯’並且可以作為實際切割晶粒時的參考線。 最後’將高分子漏層4G與基板2〇分離，修}將高分子材料層4〇與 ^板20 -械人去軒水的射(未在圖巾絲），使高分子材㈣4〇與黏 著層3〇及基板2G相互分離，以形成-個封·;此封賴包覆每一晶粒 210的五個面，並且只曝露出每一晶粒之主動面上的焊塾犯。由於封 膠體之相對於晶粒2H)之主動面之背面上有複數條切割道仙，因此當第一 高分子材料層40與基板2G _後，娜體上的應力會被這些_道41〇 11 200919669 所形成的Μ所抵消’故可有效祕決娜馳曲的問題。 接著’如第3C圖所示，在每一晶粒21〇之主動面上的複數個焊塾加 上形成第-犧牲層(dummy layer)5G及第二犧牲層52，其中第—犧牲層5〇 及第-犧牲層52的材料可以是p()lyimide或是高分？材料。接著，移除部 份第二犧牲層52及部份第—犧牲層5G以形成-階梯狀結構，且在相^於 每-晶粒’之主動面之複數個焊墊M2處形成複數個孔洞的，以曝露出 每一焊塾212 ;在此’移除部份第二犧牲層52及部份第-犧牲層5〇以形成 -P皆梯狀結構之步驟包含:在第二犧牲@ %上形成一圖案化之光阻層(未在 圖中表示）；接著，進行-蝴步驟，例如濕式蝴，以第—犧牲層％作為 蝕刻終止層(etchstoplayer) ’蝕刻以移除部份的第二犧牲層52 ;接著，再以 殘留的第二難層52做為侧遮罩’伽m移除部份第-犧牲層5〇，在相 對於複數個焊墊2丨2處形成複數個孔洞⑼，並曝露出複數個焊塾212。在 此’圖案化之第二犧牲層52及第一犧牲層％位於每一個晶粒2ι〇之主動 面及其外側-部份區域形成—向外延伸(fan㈣之—階梯狀結構，其中外側 部份具有較高之結構係為第二犧牲層52，如第3D圖所示。八 接著，如第3E圖，係形成複數個圖案化之金屬線段7〇在第二犧牲層 52及第-犧牲層5〇之上，且每一圖案化之金屬線段％係與每一晶粒別 之主動面上之複數個焊墊212形成電性連接；其中形成圖案化之金屬線段 7〇之步驟包含:形成一金屬層(未在圖中表示)以覆蓋在第二犧牲層η及第一 犧牲層50之上；觀半導體製程麟，利如顯影及侧，首先，形成一圖 案化光阻層(未在圖中表示)在金屬層之上；钱刻以移除部份金屬層，保留在 第犧牲層52及複數個焊塾212上之金屬層，以形成複數個圖案化之金屬 線奴70，及剠除圖案化之光阻層。另外，金屬線段可以是金屬層， 其材料可以Tl/Cu或是Tiw/Cu;且形成相案化n牲層η上的 UBM金屬層7〇的厚度約為$微米。 接著，如第3F圖所示’形成一保護層8〇卩覆蓋如第3E圖所緣示之結 12 200919669 構；接下來，利用半導體製程技術，例如顯影及蝕刻，先形成一圖案化之 光阻層(未在圖中表示)在保護層80上；蝕刻以移除部份的保護層8〇以曝露 出在第二犧牲層52上之複數個圖案化之金屬線段7〇 ;及剝除圖案化之光阻 層。在此，位於第二犧牲層52上之圖案化金屬線段7〇與第二犧牲層52可 以視為一錫球，然而藉由圖案化之金屬線段70可以與焊墊212電性連接， 其省略了在一般重佈線製程(RDL)中，於金屬線段形成之後，還必需於金屬 線段上進行植球之一步驟，因此，在此晶粒重新配置之封裝結構中，位於 第二犧牲層52上之圖案化之金屬線段70可以取代錫球做為導電元件。最 後’進行切割封膠體，以形成複數個各自獨立之完成封裝之晶粒，如第犯 圖所示。 此外，形成複數個圖案化之金屬線段7〇的方法還可以在形成階梯狀結 構之後’於第二犧牲層52、第一犧牲層50及複數個孔洞60的表面上，先 形成-晶種層(seed layei〇(未在财表示），織再以電賴方式在晶種層上 形成金屬層，然後再半導體製織術，例如顯影及_，絲成一圖 案化之光阻層(未在圖中表示）’侧以移除部份金屬層及晶種層；剝除圖案 化之光阻層，以形成複數個圖案化之金屬線段7〇在第二犧牲層％之表面 上，以作為導電元件。 雖然本發明以前述之較佳實施例揭露如上，然其並非用以限定本發 明’任何Μ相像技藝者’在不脫離本發明之精神和範_，當可作些許 之更動與潤飾’因此本發明之專·護範關視本·之中請專利 範圍所界定者為準。 【圖式簡單說明】 第1圖係表示先前技術之示意圖； 第2圖係Μ本酬所财之觀，在具有解標狄級之背面之 封裝結構之俯視圖；及 13 200919669 第3A圖至第3G圖係根據本發明所揭露之技術，利用晶圓對準標誌之 晶粒重新配置之封裝方法形成之封裝結構之各步驟示意圖。 【主要元件符號說明】 100基板 110 晶粒 20基板 210 晶粒 202對準標誌 212焊墊 30黏著層 40 高分子材料層 410切割道 50 第一犧牲層 52 第二犧牲層 60 孔洞 70 圖案化之金屬線段 80 圖案化之保護層 500 模具裝置 14200919669 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor packaging method, and more particularly to forming a metal layer (UBM) on a die to electrically connect a solder pad and replace the solder ball As a conductive element, a method of encapsulating the die is performed. & [Prior Art] Semiconductor technology has been developed quite rapidly, so miniaturized semiconductor dies (by (3)) must have diverse functional requirements, so that semiconductor dies must be configured in a small area. A large number of input/output pads (I/O pads), thus making the density of metal pins) quickly increase. Therefore, 'early lead frame packaging technology is not suitable for high-density metal pins; therefore, a ball grid array (BGA) packaging technology has been developed. In addition to the advantages of ball density of the ball array package, the ball array package has tin. The ball is also less susceptible to damage and deformation. With the popularity of 3C products, such as: mobile phones (CeU ph〇ne), personal digital assistants (pDA) or 疋iPod, etc., many complex system chips must be placed in a very small space, so to solve In this connection, a package called "wafer-level packaging (WLC)" was exhibited. It can package the wafer before it becomes a wafer. This "wafer level packaging" technique is disclosed in U.S. Patent Publication No. 5,323, G51. However, 'this kind of wafer-level packaging technology' increases with the number of soldering irons on the active side of the die', so that the distance between the pads is too small, in addition to the problem of signal consumption or signal interference. Also, problems such as reduced reliability of the package due to too small pad pitch. Therefore, when the die is further reduced, the aforementioned packaging technique cannot be satisfied. In order to solve this problem, U.S. Patent Publication No. 7,196,4,8 has disclosed a wafer which will be completed in a semiconductor process, and after testing and cutting, the test result is a good die ((4) (4) is repositioned on another U substrate. Above, and then the encapsulation process, so that the repositioned grains have a wider separation distance, so that the division on the die can be properly allocated, for example, 200919669, if using the lateral extension (fanQut) technology, It can solve the problem that the distance is too small, except for the signal handle or signal interference. However, in order to enable the semiconductor wafer to have a smaller and thinner package structure, the wafer will be thinned before wafer cutting. Treatment, for example, back grinding (four) side = thinning the wafer to 2~2 (Μ 'and then cutting the surface of the surface - this is the thinning of the grain, after reconfiguring - On the substrate, the private note cuts into a number (four) into a ^ body 'because of the grain (four)' makes the sealant is also very thin, so when the sealant is separated from the substrate, the seal body itself is stressed and the county produces Lin. Increase Lai Jin _Difficulties in the process. In addition, after the crystal cutting, when re-arranging on another substrate, since the size of the new substrate is larger than the original size, the subsequent ball-making process _ will not be aligned, and its package SUMMARY OF THE INVENTION In view of the problem of the ball placement and the nano-curve described in the background of the invention, the present invention provides an alignment mark on the back side of the paste crystal grain, and forms a gold lining on the crystal grain. The package structure and method for re-arranging the die of the conductive component and the solder pad, the method of re-inserting the plurality of crystal grains and breaking the package, so the main purpose of the invention is to arrange the adhesive layer on the button. Moreover, the plurality of alignment marks arranged on the surface of the die and the substrate can be accurately placed on the adhesive layer of the substrate, and the gold riding (UBM) is divided into electrical components and electrically connected to the soldering contact. In order to carry out the method of encapsulation of the grain re-arrangement, in the subsequent process, the process of the ball-planting process can be solved, and the body itself can overcome the stress riding, so that the body is kept flat after being separated from the substrate, which can effectively improve the manufacturing process. Rate and reliability and can be made A low voltage component, such as a memory component, such as a RAM. A further object of the present invention is to provide a method of packaging a crystal grain reconfiguring that can reconfigure grains cut at 12 o'clock to 8 twins. On the substrate of the circle, it is possible to reduce the package cost of the 12-inch wafer by using the package device that can effectively use the 8-inch wafer without the need to re-establish the package of the wafer. A further object is to provide a method for packaging a die reconfiguring so that the packaged wafers are, and are known to be, functionally normal wafers, which can save packaging materials and therefore also reduce the process. OBJECT OF THE INVENTION A further object of the present invention is to provide a method for packaging a die re-arrangement such that the packaged wafers are "Known good die" which can save packaging materials and can also be used. Reduce the cost of the process. According to the above description, the present invention provides a method for packaging a die reconfiguration, comprising: providing a plurality of crystal grains, each die having an active surface and a plurality of pads disposed on the active surface; and picking and placing a plurality of crystal grains On a substrate, each die is connected in a flip-chip manner to an adhesive layer disposed on the substrate; a polymer material layer is formed on the substrate and a portion of the die; and the mold is covered in the two-molecule material. On the layer, the polymer material layer is planarized, and the polymer material layer is filled between the plurality of crystal grains and covers each of the crystal grains; the mold device is removed to expose the surface of the polymer material layer and is separated from the substrate. Exposing the active surface of each die and each pad to form a gel, forming a first sacrificial layer to cover the active face of each die and each solder fillet; forming a first and second sacrificial layer Above the first sacrificial layer; removing a portion of the second sacrificial layer and the sacrificial layer to form a ί _ structure and forming a plurality of holes at the turn of each of the filaments of the dies Exposing each mattress; forming a complex The patterned metal line segments are electrically connected to the plurality of pads on the active surface of each of the die layers on the second sacrificial layer and the sacrificial layer; forming a patterned protective layer to cover the plurality of patterns a metal line segment and exposing a portion of the deuterated metal line segment on the first sacrificial layer; and cutting the encapsulant to form a plurality of separate completed packaged grains, wherein each of the five sides of the die Both are covered by a layer of polymer material. According to the above-mentioned crystal "the new configuration of the packaging method, the hair duck exposed - a wafer-level chip package structure" includes: - the die has a plurality of solder pads on the active surface, and a gel coated five crystal grains Surface, "patterned polymer acquisition layer" and a plurality of side-formed metal line segments 8 200919669 parts of the patterned polymer material layer, electrically connected to each of the crystal grains by a plurality of patterned metal line segments a plurality of active surfaces, wherein the patterned polymer material layer is formed on the active surface of the crystal grain and on the outer side thereof - part of the region is formed to extend outward (f (4)-like structure, and the towel extends outward The end of the scale has a higher structure and a hole is formed at a plurality of pads relative to the active surface of the die to expose each of the pads; a plurality of patterned metal segments are formed in the pattern The layer of the polymer material is electrically connected to the re-oiled line of the re-oiled (4) non-remaining polymer material on the surface of each crystal grain; and the protective layer covers a plurality of _ The golden secret part and the partial pattern r a sub-material layer and exposing one of a plurality of patterned metal line segments on the patterned polymer material layer at a higher position in the step structure. The implementation of the best implementation is as follows: (In order to make the understanding of the purpose, structure, characteristics, and Wei Weijin, the following examples are described in detail below.) β [Embodiment] The present invention is directed to __The method of sealing the grain re-arrangement, re-arranging a plurality of dies on the other substrate, and then performing the encapsulation method. In order to thoroughly understand the Μ, it will be detailed in the next shun In addition, the implementation of the present invention does not limit the manner in which the crystal card stack is cooked (10). The detailed steps of the well-known wafer formation method and the subsequent process of crystallization are not described in the details. In order to avoid unnecessary limitations of the present invention, however, for the preferred embodiment of the present invention, it will be described in detail. In addition to these detailed descriptions, this (4) is widely implemented in other implementations. And this issue is not subject to mosquitoes, which is subject to the scope of the patents that follow. In modern semiconductor packaging processes, wafers that have completed the front-end process (with the process) are thinned first. Processing (Thinningp Satoshi (4), for example, grinding the thickness of the wafer 200919669 to between 2 and 20 mil; then, performing wafer cutting (sawing pr〇cess) to form a single crystal grain; then, using a pick and place device ( Pickandplace) places one crystal grain one by one on another substrate 100, as shown in Fig. i. Obviously, the grain spacer area on the substrate 1 is larger than the crystal grain 11G, and therefore, these can be made The repositioned die 110 has a wider pitch between the solders (4) on the chip 11G. In addition, the package method used in this embodiment can cut the crystals of the 12-inch wafer. The granule 11G is reconfigured on the substrate 100 of the 8 吋 wafer, so that the packaged equipment of the 8 吋 wafer can be effectively used without the need to re-set the 12 吋 wafer packaging equipment, which can reduce the packaging cost of the 12 吋 wafer. . It is then emphasized that embodiments of the present invention do not limit the use of a substrate of 8 Å wafer size, as long as it can provide a bearing for the carrier 'eg glass, stone m circuit board or metal foil. For example, the substrate 1 of the present embodiment can be used, and therefore the shape of the substrate 1 is not limited. Referring to Figure 2, the wire-substrate has an alignment on the back side of the substrate. As shown in Fig. 2, the alignment is not in the x_y direction of the back surface of the surface of the crystal substrate, and a plurality of alignment marks 202 are provided. As is known from the previous statements, when a wafer (not shown) is formed to form a plurality of dies after dicing and then re-arranged to the new substrate 2G, due to the new substrate 20 The die spacer area is larger than the reconfigured die, and the ball implantation step (ball_nt) in the subsequent packaging process may not be aligned, and the conductive element (not shown in the figure) is accurately formed on the back surface of the die. The position of 'the package structure can be reduced by # degree. Therefore, in the specific embodiment of the present invention, the manner of forming the alignment target 2〇2 can be performed by using the ^o-etching process, which is formed on the back surface of the substrate 2〇 and forms a plurality of in the clever direction. Align m〇2' and its shape is the standard of the cross. In addition, the manner in which the alignment mark 2G2 is formed further includes a laser mark process to form a plurality of alignment marks on the back surface of the substrate 2A. Next, Figures 3A through 3G show schematic diagrams of various steps of an embodiment of the die rearrangement disclosed in the present invention. First, as shown in FIG. 3A, a plurality of crystal grains 200919669 (not shown in the figure) are arranged to be cut to form a plurality of crystal grains, each of which has an active surface and A plurality of soldering dies 212 are disposed on the active surface, and then a plurality of dies are reconfigured on the new substrate 2; the towel is provided with a sticky (four) 在 on the substrate Μ, and the layer 3 〇 is - Adhesive materials with elasticity, such as Shixi rubber (silk〇n can (6)), Shixi resin (coffee (10) ") elastic PU porous PU, acrylic rubber (acrylic secret (four) or die cutting glue, etc. The device (not shown) places the dies 21() one by one and attaches them to the adhesive layer 3 on the substrate, wherein _ is attached to the crystal (flip-clear mode and according to a plurality of alignment marks on the back side of the substrate) Then, the solder bump 212 on the active surface is connected to the adhesive layer % on the substrate 2 (). Then, referring to FIG. 3A, the polymer material layer is coated on the substrate 2 and on some of the crystal grains. 40 'such as polyimide, and use a mold device to flatten the polymer material layer 4〇, so that the polymer The material layer 40 forms a planarized surface, and the polymer material layer 40 is filled between the crystal grains 210 and the five faces of each of the crystal grains 21 are covered by the polymer material layer 4? 'A baking process can be selectively performed on the planarized polymer material layer 4 to cause the polymer material layer 40 to be further removed, and a demolding process is performed to form the mold device and the cured polymer material layer 40. Separating to expose the surface of the planarized polymer material layer 4; then forming a plurality of dicing streets on the surface of the polymer material layer 4 (using a dicing blade (not shown), such as 3B As shown in the figure; the depth of each scribe line is 0. ^ mil (mU), and the width of the _ track is 5 to 25 microns. In the preferred embodiment, the scribe line 41G can be vertically interlaced 'And can be used as a reference line when actually cutting the grain. Finally 'separate the polymer leakage layer 4G from the substrate 2〇, repair} the polymer material layer 4〇 and the plate 20 - the person to go to the Xuan water shot (not In the towel (wire), the polymer material (4) 4〇 and the adhesive layer 3〇 and the substrate 2G are separated from each other to form - a seal; this seal covers the five faces of each die 210 and exposes only the weld defects on the active face of each die. Due to the active face of the sealant relative to the die 2H) There are a plurality of cut roads on the back side, so when the first polymer material layer 40 and the substrate 2G_, the stress on the body is offset by the enthalpy formed by these _dao 41〇11 200919669', so it can be effectively secreted. The problem of Nachiqu. Next, as shown in Fig. 3C, a plurality of solder bumps on the active surface of each of the dies of 21 Å are added to form a dummy layer 5G and a second sacrificial layer 52, The material of the first sacrificial layer 5 and the sacrificial layer 52 may be p() lyimide or a high score? material. Then, a portion of the second sacrificial layer 52 and a portion of the sacrificial layer 5G are removed to form a stepped structure, and a plurality of holes are formed at a plurality of pads M2 of the active surface of each of the grains To expose each of the solder bumps 212; the step of removing a portion of the second sacrificial layer 52 and a portion of the sacrificial layer 5 to form a -P ladder structure includes: at the second sacrifice @ % Forming a patterned photoresist layer (not shown); then, performing a butterfly process, such as a wet butterfly, using the first sacrificial layer as an etchstop layer to etch to remove portions a second sacrificial layer 52; then, the remaining second hard layer 52 is used as a side mask 'gamma removal portion first-sacrificial layer 5', and a plurality of portions are formed at a plurality of pads 2丨2 The hole (9) is exposed to a plurality of weld beads 212. Here, the 'patterned second sacrificial layer 52 and the first sacrificial layer % are located on the active surface of each of the crystal grains 2 ι and its outer-partial region is formed - outwardly extending (fan (four) - stepped structure, wherein the outer portion The higher structure is the second sacrificial layer 52, as shown in FIG. 3D. Eighth, as shown in FIG. 3E, a plurality of patterned metal line segments 7 are formed in the second sacrificial layer 52 and the first sacrificial layer. Above the layer 5, and each patterned metal segment % is electrically connected to a plurality of pads 212 on the active surface of each of the other pads; wherein the step of forming the patterned metal segments 7〇 comprises: Forming a metal layer (not shown) to cover the second sacrificial layer η and the first sacrificial layer 50; viewing the semiconductor process, such as development and side, first, forming a patterned photoresist layer (not Shown in the figure) above the metal layer; the money is engraved to remove part of the metal layer, and the metal layer remaining on the sacrificial layer 52 and the plurality of solder pads 212 to form a plurality of patterned metal line slaves 70, And removing the patterned photoresist layer. In addition, the metal line segment may be a metal layer. The material may be Tl/Cu or Tiw/Cu; and the thickness of the UBM metal layer 7〇 formed on the phased n layer is about $micron. Next, as shown in FIG. 3F, a protective layer 8 is formed. Covering the structure of the junction 12 200919669 as shown in FIG. 3E; next, using a semiconductor process technology, such as development and etching, a patterned photoresist layer (not shown) is formed on the protective layer 80; etching Removing a portion of the protective layer 8A to expose the plurality of patterned metal segments 7〇 on the second sacrificial layer 52; and stripping the patterned photoresist layer. Here, the second sacrificial layer 52 is located. The patterned metal line segment 7〇 and the second sacrificial layer 52 can be regarded as a solder ball. However, the patterned metal line segment 70 can be electrically connected to the pad 212, which omits the general rewiring process (RDL). In the case of forming the metal line segment, one step of implanting the ball on the metal line segment is also necessary. Therefore, in the package structure of the die rearrangement, the patterned metal line segment 70 on the second sacrificial layer 52 can be replaced. The solder ball is used as a conductive element. Finally, the cutting encapsulant is cut to Forming a plurality of separate independent completed die, as shown in the first figure. Further, the method of forming a plurality of patterned metal segments 7〇 may also be after the stepped structure is formed on the second sacrificial layer 52, On the surface of a sacrificial layer 50 and a plurality of holes 60, a seed layer is formed first (seed layei〇 (not shown in Cai), and then a metal layer is formed on the seed layer by electric lithography, and then semiconductor weaving is performed. , for example, developing and _, forming a patterned photoresist layer (not shown) to remove portions of the metal layer and the seed layer; stripping the patterned photoresist layer to form a plurality of patterns The metal wire segment 7 is on the surface of the second sacrificial layer % as a conductive element. Although the present invention has been disclosed above in the preferred embodiment of the foregoing, it is not intended to limit the invention to any 'imager' Without departing from the spirit and scope of the present invention, it is possible to make a few changes and refinements. Therefore, the scope of the patent application is subject to the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view showing a prior art; Fig. 2 is a plan view of a package structure having a back surface of a declassified class; and 13 200919669 3A to 1 3G is a schematic diagram of various steps of a package structure formed by a package method of wafer realignment of wafer alignment marks in accordance with the techniques disclosed herein. [Main component symbol description] 100 substrate 110 die 20 substrate 210 die 202 alignment mark 212 pad 30 adhesion layer 40 polymer material layer 410 dicing street 50 first sacrificial layer 52 second sacrificial layer 60 hole 70 patterned Metal line segment 80 patterned protective layer 500 mold device 14