TW200919662A - Tenon-type package structure and method thereof - Google Patents

Tenon-type package structure and method thereof Download PDF

Info

Publication number
TW200919662A
TW200919662A TW96138726A TW96138726A TW200919662A TW 200919662 A TW200919662 A TW 200919662A TW 96138726 A TW96138726 A TW 96138726A TW 96138726 A TW96138726 A TW 96138726A TW 200919662 A TW200919662 A TW 200919662A
Authority
TW
Taiwan
Prior art keywords
package structure
carrier
protrusion
wafer
type package
Prior art date
Application number
TW96138726A
Other languages
Chinese (zh)
Other versions
TWI349353B (en
Inventor
Yi-Shao Lai
Tsung-Yueh Tsai
Hsiao-Chuan Chang
Original Assignee
Advanced Semiconductor Eng
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW96138726A priority Critical patent/TW200919662A/en
Publication of TW200919662A publication Critical patent/TW200919662A/en
Application granted granted Critical
Publication of TWI349353B publication Critical patent/TWI349353B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015Shape
    • H01L2924/10155Shape being other than a cuboid
    • H01L2924/10158Shape being other than a cuboid at the passive surface

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

A tenon-type package structure includes a carrying device and a chip. The carrying device has a first surface and a second surface opposite to the first surface. The first surface is installed with a bump. The chip is disposed on the first surface of the carrying device, and has a third surface and a fourth surface opposite to the third surface. The third surface is installed with a groove, and the shape, size, and position of the groove correspond to the bump. Therefore, the carrying device and the chip can be connected together through the connection of the bump and the groove.

Description

200919662 九、發明說明: 【發明所屬之技術領域】 本發明係_-種榫辆賴構及其製造方法,尤其是有關於如何將 晶片固定在所構裝承載器上的設置方式。 【先前技術】 隨著消費者對於電子產品小型化财功能絲的日益提升,直接推動 了電子構裝產業的蓬勃發展,為了把多個不同功能之晶片整合在同一封褒 模組内’除了減少晶片所佔據的空間,更需要節省電路板的面積,以有效 達到多功能整合,並降低整體製造的成本,翩在現今市場上並供應生產 的電子產品有,行動電話、數位相機、筆記型電腦等。 為了因應如上所述,即在有限空間當中容納數目龐·電子元件的需 求,產生了許多積體電路的封裝型式與生產製程,例如:球格陣列_ _ _y,BGA)是藉由錫球和電路板連接,以錫球取代傳統的接腳,並將錫球 以陣列的模式制、或是將晶面朝下並藉由職凸塊絲板結合的覆晶式 封裝㈣p Chip) '四方扁平職(Quad Flat paekage,QFp),是由金屬導線架 支撐封裝結構,藉著兩®或是四邊的引腳和電路板相連接,針對不同的封 裝型式’晶片與承載器之間的配置方式亦有不同,已習知的技藝,係透過 晶片黏結法將晶片固統_裝的承載器上,亦簡稱為黏晶,在黏晶製程 中係利用導電膠來進行黏著,現今的技術大多採用銀膠為固定黏著劑,但 使用銀膠的缺點在於’需要避免銀的遷觀象,gp_中所含有的成份銀 會渗出,而形成短路縣,其產生與環境中的轉有著密切_係,又過 量的銀膠’也會促使銀的遷移現紐生的機率,另相於黏晶製程的黏著 200919662 膠内,其環氧樹脂的成份若是含有過多的氯、鈉等離子,會引起金屬的腐 姓’造成破壞,降録率’而空觸產生也是使祕膠雜著劑所必須避 免的缺點,空_存在會引起導熱的不良’且容肖吸收溼氣,⑽因樹脂 中氣體的包人,亦或是製造過程_所捲人,承前述,在黏晶製程中如何避 免銀的遷移、樹脂中離子的含量過多以及空洞的產生,進而提升該封裝體 的良率。因此,本發明即是要提出—種新穎之半導體晶片封裝結構與村, 以供解決上述的問題。 [發明内容】 本發明的目的在於提供—種榫式職結構,其可利用設置在承載器上 的突出物與設置在晶片上的凹槽兩者插置卡接,以將晶片固定於 承載器上。 另目的在於提供一轉式封裝結構,其透過設置在承載器 的犬出物與&置在晶片上的凹槽,該凹槽與突出物的配合,提供 3位製程,再者藉由突出物與凹槽的插置卡接,亦免除了習知技蔽中必 =雜麵制_梅_紐,賴移、產细等問題。 該基::::厂發_~構.— 第-編 相對的第二表面,以及-晶片,該晶片具有— 第二表面及一相對的第 、有 物與晶片上⑽㈣,咖發糊綱—表面上的突出 著劑的方十 相插置卡接,而完全避免了習知技術中以黏 可能產生的對位^t。 固疋於所構裝的承载器上 200919662 依據本發明之上述目的,本發明還提供一種榫式封裝結構之製造方 法,其包含有如下步驟: 提供一承載器,該承載器具有一第一表面及一第-农r 衣卸夂弟一表面,該第一表面 係相對於該第二表面’且該第一表面係設有至少一突出物· 提供-晶片,其設置於該承載⑽第-表面,該晶片具有—第三表面 與-第四表面’該第三表面係相對於該第四表面,另該第三表面上設有至 少一凹槽其面對該承載器第一表面的突出物。 將該第-表面之突出物與第三表面所設置之凹槽對位後呈—相互卡合 之狀態;以及 藉由複數條銲線以將該第四表面電性連接至該承載器之第一表面。 綜上所述,本發明不僅可以卿設置在基板(承細上的突出物與設置 在晶片表面内的凹槽來形成對位準確的構裝體,用以消除基板與晶片間, 可能產生的對位準確性的贼,亦統了 f知技藝中使雌晶製程所產生 \ 的銀的遷移、樹脂中離子的含量以及空洞的產生等問題,啊並可大幅縮 短該封裝體的電性連接空間,強化電性效能,縮減了封裝體 【實施方式】 乂下將配σ圖式來姻本發明之榫式封裝結構,並且結合第—圖至第 四圖所示之結構4圖’對本伽榫式難結狀製造方法娜細介紹。 第1圖示意地顯示出_插掊 根據本發明之—較佳實施_榫式封裝結構的示 意圖。如第1圖所示,首畀捭 百蛛供-承載H ,在本實施例中係以—基板做 為範例說明。惟該承載器2Ω 亦可為任何適當的結構物或部件,而本發明 200919662 之實施亦不限於基板。 該承載器測上杨秦麵2G1 M树表面或第二 表面搬。在此特別要說明的是,“上,,及‘‘下,,在此係指顯式中所示之方 向’主要是配合於本文之醉定之方向辭彙,無承翻·或是本 發明之榫賴在纽個切方向並無必朗關係。在此實施例 十’該第-表面201係與該第二表面2〇2相對,惟此僅係實施本發明之一 種態樣,本發明並不僅限於上下相對的表面。 接著在該第—表面2G1設有-突出物加,而在該第三表請上則形 成有一凹槽K)3。該突出物2〇3及凹槽1〇3在位置及構形上係互相對應,故 -承載f上的突出物加可插入並卡合於—晶片卿表面内的凹槽 使仔U 1GG以及承載Is 2QG可以ϋ定在—起,形成—構裝體。此 將於下文中進一步加以說明。 實把例中’ D玄犬出物2〇3係設置成具有頂側表面及側邊外壁表面, 而相對於该突出物2〇3的此等表面,該凹槽1〇3亦具有相對應的底側表面 及側邊内壁表面,將一承載器的突出物2〇3插置於一晶片觸至凹槽 1〇3内時’該突出物203的頂側表面係可喃合至該凹槽103的底側表面上, 而。亥犬出物203的外壁表面則喷合於該凹槽1〇3的内壁表面,再藉由該凹 槽103以及大出物2〇3的卡合,以將該晶片加以固定在該承載器2⑻ 上。 示匕之外在5亥突出物203的頂侧表面及外壁表面之至少一者上設有 第-導電材料(圖中未示),在本實施例中該導電材料係為金屬材料,例如 200919662 金、銀、銅或其等的合金,但本發明並不限於此。該第—導電材料可由任何 適當的方式加以設至於該突出物2〇3的頂侧表面或外壁表面上,例如電鑛 塗佈或其減谢收她術。糾,她㈣糊表⑽ 壁表面上亦相對於該突出物2〇3之表面上的第—導電材料而設置有第二導 電材料(圖中未示),該凹槽1G3内的第二導電材料係設置成對應於該突出物 203上的第—導電材料’因此當—承載器200之突出物203插置於一日曰片 1⑻之凹槽如形成固定狀態時,該突出物203上的第一導電材料會無凹 槽103内的第二導電材料相接觸或連結。 同犬出物203上的第一導電材料一樣,凹槽⑽内的第二導電材料 可任何適當的導電材料,而在本Μ的較佳實施财,該導電材料最好是 =屬材料,例如金、銀、銅或其等的合金,但本發明並不限於此,且該第二 導電材料可由任何適當的方式加以設置於該凹槽ι〇3的底側表面或内壁表 面上例如電鑛、塗佈或其他此技藝中所知悉的技術。。 、再者,在本發日种,並不限制第—及第二導電材料是否相同,惟基於 製=的便概以及結合的可#性考慮,該等第—及第二導電材料,以相同 六又透過大出物2°3上的第-導電材料會與該凹槽103内的第 '材料以電性連接該晶#與基板,僅為本發明之—實施例,亦可以其 它適當的電性連接方式達成。 ^在圖不的實施例中,本發明承載器·的第一表面逝及第二表面搬 二相相對且相互平行的,並與該晶片觸的第三以及第四表面⑻、搬 才目-石、h - 订。換言之,該晶片100係設置成大致上與承載器2〇〇形成平行排 200919662 列的關係。惟此僅係本發明實施上的—簡樣,本發不侷限於此種態 樣,亦可應用於他種的排列情形。 ί 。月參閱第2 w其中顯不出類似於第j圖的示意圖與製程步驟,係用 以說明根據本發明實施例之榫式封裝,該晶㈣基板婦制聽體結構 示意圖。如第2圖所示,該承載器表面上之突出物2〇3係設置成具有 頂側表面及侧邊外壁表面,而相對於該突出物2〇3力此等表面,該晶片⑽ 表面内的凹槽卿青參閱第丄圖)亦具有相對應的底側表面及側邊内壁表 面’在一承載器200的突出物203插置於一晶片⑽之凹槽ι〇3内時,該 突出物203的頂側表面係可响合至該凹# 1〇3的底侧表面上,而該突出物 2〇3的外壁表面則喷合於該凹槽1〇3的内壁表面,卡接呈一構裝體。 請參閱第3目,其中顯示出根據本發明實施例之棒式封裝其電性連接 結構示意圖。其巾如同前面所說明,完成第2 _對位卡接的步驟後,再 進-步的將該晶片100與該承載器200進行打線結合,形成電性連接。在 此實施例中’該突出物2〇3係設置成具有頂側表面及側邊外壁表面,而相 對於該突出物203的此等表面,該凹槽肋亦具有相對應的底側表面及側 邊内壁表面’在—承載器的突出物2〇3插置於一晶片⑽之凹槽他 内時’該突出物2G3的頂侧表面係可喃合至該凹槽⑽的底側表面上,而 °亥犬出物203的外壁表面則哺合於該凹槽103的内壁表面,卡接呈—構穿 體。該卡接狀射財涉配合方式,也可在簡底側表面與”物的頂側 表面塗覆膠液點著固定。利用該承載器2〇〇的突出物203與該晶片⑽的 凹槽⑽間的配合及卡接可提供更鮮的餘方式,飾提升朗裝體的 200919662 良率。惟對於習知此技藝之人士而言,該等突出物加凹槽⑽的設置可 採用任何適當的配置,但是相鄰而承裁器的第一表面2〇ι與晶片副 的第三表面谢上互相插置配接的突出物泌及凹槽ι〇3則必須要有對應 的形狀、位置及數量,以利二者之接合。惟就製造便利性而言,自當以相 同數量、位置及形狀的突出物203及凹槽1〇3為宜。 々另卜.亥曰曰片100更包3至少—通孔(圖中未示),以電性連接該晶片的 第三表面他和第四表面搬,其連接,可以透過任何適當的方式達成。 在本發明的較佳實施例中,此等構件間的電性連接係透過於該晶片⑽内 的通孔中填人«材料來達成,在本實施财係在該通孔中電鑛一金屬材 料來實現該“之該第三表面和該第喊_雜連接,謂^⑽的 第四表面1〇2與承載器200之第一表面2〇1係以設置在銲塾搬上的導線 3〇1來加以連接而形成制的電性連接。在本發日月的—較佳實施例中,該等 導線、焊墊係由金屬製成,例如金、銀、銅或其等的合金。 進v參閱第4圖,其中係顯示出第3圖中的構裝體進行膠體封裝後 ,丁%、圖如第4圖所不,該承載器2〇〇與晶片1〇〇所構成的構裝體上可 乂#]用Mg或疋其他適當的材料進行封裝作業。換言之,設置一封勝 4〇1在該承載益200之第一表面2〇1上’該封膠4〇1可覆蓋部分該承載器 200的第-表面201,並且覆蓋至少部分該晶片1〇〇和該導線3〇卜再者, 吸置多個錫球(圖中未示)於該承載器2〇〇的第二表面2〇2上,以供與其他外 f3裝置進行電性連接。錫球%的設置是此技藝中所知悉的技術,在此不再 多加贅述。 200919662 第5 _根據本剌之榫式封裝結構之封裝方法流雜。如第5圖所 _示,本發明提供一承(請參見第1圖中元件符號),該承載器具有— 第一表面(請參見第1圖其中元件符號加)及—第二表面(請參見第丨圖其中 元件符號202),該第-表面軸對於該第二表面,且轉—表面係設有至 少一突出物(請參見第i圖其中元件符號1 2〇3),該突出物具有頂側表面及多 個側邊外壁表面(請參見步驟1〇);再提供一晶片(請參見第工圖其中元件符 唬100),設置於該承載器的第一表面,該晶片具有一第三表面(請參見第! { ®其中元件符號繼)與一第四表面(請參見第1圖其中元件符號脱),該第 三表面係相對於該第四表面,並於第三表面上設有至少一凹槽(請參見第! 圖其中7G件魏1〇3),具有與該突出物相對應的細表面及側邊内壁表面 (請參見步驟⑴,並於第四表面上設有至少一銲塾(請參見第3圖其中元件 符號302),更特殊的,該晶片包含至少一通孔,電性連接該晶月之該第三表 面和該第四表面;再者’於步驟11完成後,藉由該突出物之頂側表面及側 邊外壁表面’對位㈣合於該凹槽姆應的底絲面及側勒壁表面,進 12 1 而將該晶片111定於該承健上呈-構裝體(請參見步驟12) 後,透過打 2 線步驟由複數條銲線電性連接該承載器以及該晶片(請參見步驟13),另形 3 成-封膠(請參見第4 5 6 7圖其中元件符號),設置在該第—表面上,並覆蓋 4 部分晶>1以及複數條銲線與該第一表面(請參見步驟14),又形成複數個錫 5 球於該承載器的第二表面做電性連接(請參見步驟15)。 6 综上所述’本發明所提供的榫式封裝結構不僅避免了習知技藝中使用 7 黏晶製程所產生的銀的遷移、樹脂中離子的含量以及空洞的產生等問題, 200919662 同時亦藉由設置在承載器第一表面及第二表面上的凹槽與突出物的卡接形 成一封裝體’形成對位準確的構裝體。 本發明透過上述的技術手段,來實現其主要目的與效能,而此等技術 手段未見於任何習知之技術,是以本發明確實合於專利法的相關規定,爰 依法提出帽’惟其專利健範圍當視後附之巾請專利範鼠其等同領域 而疋,不應文限於前述各實施例之說明的限^,凡熟悉此領狀技藝者, 在不麟本創作精㈣範圍内,所作之更動或潤飾,均應視為屬於本創作 權利範圍内之改變。 【圖式簡單說明】 第1圖係根據本伽之榫式封i轉的示意圖。 第2圖係、根據本發明之榫式封裝其巾該晶丨與基板雛後的結構示意 圖。 第3圖係根據本發明之榫式峨性連接結構示意圖。 ㈣物麵的示意圖。 第5圖係根據本發明之榫式封裝結構之封裝方法流程圖。 13 200919662 【主要元件符號說明】 100 晶片 101 第三表面 102 第四表面 103 凹槽 200 承載器 201 第一表面 202 第二表面 203 突出物 301 導線 302 銲墊 封膠 401200919662 IX. Description of the Invention: [Technical Field] The present invention relates to a structure and a method of manufacturing the same, and more particularly to a method of how to fix a wafer on a carrier. [Prior Art] With the increasing consumer awareness of the miniaturization of electronic products, the electronic assembly industry has been directly promoted, in order to integrate multiple wafers with different functions into the same package. The space occupied by the chip needs to save the area of the circuit board to effectively achieve multi-functional integration and reduce the cost of overall manufacturing. The electronic products that are produced in the market today include mobile phones, digital cameras, and notebook computers. Wait. In order to accommodate the demand for a number of Pang electronic components in a limited space as described above, a package type and a production process of a plurality of integrated circuits are produced, for example, a ball grid array _ _ _y, BGA is by solder balls and The board is connected, the solder ball is used to replace the traditional pin, and the solder ball is made in an array mode, or the flip chip is turned down and the flip chip is combined by the bump wire plate (4) p Chip) The Quad Flat Paekage (QFp) is a metal lead frame supporting package structure. It is connected by two or four-sided pins and a circuit board, and the configuration between the chip and the carrier is also different for different package types. There are different, well-known techniques, which are based on the wafer bonding method, which is also referred to as a bonded crystal, which is also referred to as a sticky crystal. In the adhesive bonding process, the conductive adhesive is used for adhesion. Most of the current technologies use silver. Glue is a fixed adhesive, but the disadvantage of using silver glue is that 'need to avoid the migration of silver, the silver contained in gp_ will ooze out, and the short-circuit county will be formed, which is closely related to the rotation in the environment. Excessive Glue' will also promote the migration of silver to Newton's chance. In addition, the adhesion of the adhesive process to the 200919662 adhesive, if the epoxy resin composition contains too much chlorine, sodium, etc., will cause the metal's rot to cause damage. , the drop rate 'and the empty touch is also a disadvantage that must be avoided by the secret adhesive. The presence of air _ will cause poor heat conduction and absorb moisture, (10) due to the inclusion of gas in the resin, or In the manufacturing process, according to the above, how to avoid the migration of silver, the excessive content of ions in the resin and the generation of voids in the die-bonding process, thereby improving the yield of the package. Therefore, the present invention is to propose a novel semiconductor chip package structure and village for solving the above problems. SUMMARY OF THE INVENTION It is an object of the present invention to provide a cymbal structure that can be inserted and engaged with a protrusion provided on a carrier and a groove provided on a wafer to fix the wafer to the carrier. on. Another object is to provide a one-turn package structure that provides a 3-bit process by penetrating the dog's product disposed on the carrier with a recess placed on the wafer, the groove and the protrusion, and by highlighting The insertion and snapping of the object and the groove also eliminates the problems of the conventional technique, such as the miscellaneous noodle system, the plum-yellow, the shifting, and the thinning. The base::::factory _~ constituting. - the first surface of the second surface, and - the wafer, the wafer has - the second surface and an opposite first, the object and the wafer (10) (four), the coffee paste - The ten-phase of the protruding agent on the surface is inserted and snapped, and the alignment which may be generated by sticking in the prior art is completely avoided. According to the above object of the present invention, the present invention further provides a method for manufacturing a 榫-type package structure, comprising the steps of: providing a carrier having a first surface and a first surface of the first surface is opposite to the second surface 'and the first surface is provided with at least one protrusion · providing - wafer disposed on the first surface of the bearing (10) The wafer has a third surface and a fourth surface, the third surface is opposite to the fourth surface, and the third surface is provided with at least one groove facing the protrusion of the first surface of the carrier . And the first surface is electrically connected to the carrier by a plurality of bonding wires a surface. In summary, the present invention can not only be disposed on the substrate (the protrusion on the substrate and the groove disposed in the surface of the wafer to form an alignment accurate assembly for eliminating the possibility between the substrate and the wafer. The thief of the alignment accuracy also has problems in the migration of silver generated by the female crystal process, the content of ions in the resin, and the generation of voids, and can greatly shorten the electrical connection of the package. Space, strengthen electrical performance, reduce the package [Embodiment] 乂 将 将 将 来 来 来 来 来 姻 姻 姻 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The 榫 难 难 制造 制造 。 。 。 。 。 。 。 。 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第- Carrying H, in the present embodiment, the substrate is taken as an example. However, the carrier 2 Ω can also be any suitable structure or component, and the implementation of the invention 200919662 is not limited to the substrate. Yang Qin Noodle 2G1 M tree surface or The second surface is moved. In particular, the words "up," and "under," in this direction, are indicated in the direction indicated by the words in the direction of the drunkenness of this article. Or the present invention does not have a relationship in the direction of the tangential direction. In this embodiment, the first surface 201 is opposite to the second surface 2 〇 2, but only one mode of the present invention is implemented. The present invention is not limited to the upper and lower opposite surfaces. Then, the first surface 2G1 is provided with a protrusion plus, and the third surface is formed with a groove K) 3. The protrusion 2〇3 and The grooves 1〇3 correspond to each other in position and configuration, so that the protrusions on the bearing f plus the grooves that can be inserted and engaged in the surface of the wafer make the U 1GG and the bearing Is 2QG can be determined at Starting up, forming a structure. This will be further explained below. In the example, the 'D 玄 canine 2 〇 3 series is arranged to have a top side surface and a side outer wall surface, with respect to the protrusion 2此3 of the surface, the groove 1〇3 also has a corresponding bottom side surface and a side inner wall surface, which will be a bearing When the protrusion 2〇3 of the device is inserted into a wafer and touches the groove 1〇3, the top side surface of the protrusion 203 can be conjugated to the bottom side surface of the groove 103, and the dog is out. The outer wall surface of the object 203 is sprayed onto the inner wall surface of the groove 1〇3, and the wafer 103 is fixed to the carrier 2 (8) by the engagement of the groove 103 and the large object 2〇3. A first conductive material (not shown) is disposed on at least one of the top side surface and the outer wall surface of the 5H protrusion 203, and the conductive material is a metal material in the embodiment, for example, 200919662 An alloy of gold, silver, copper or the like, but the invention is not limited thereto. The first conductive material may be applied to the top side surface or the outer wall surface of the protrusion 2〇3, such as an electric ore, in any suitable manner. Coating or thanking her for her surgery. Correction, she (4) paste table (10) on the surface of the wall is also provided with a second conductive material (not shown) relative to the first conductive material on the surface of the protrusion 2〇3, the second conductive in the groove 1G3 The material is disposed to correspond to the first conductive material on the protrusion 203. Therefore, when the protrusion 203 of the carrier 200 is inserted into the groove of the one-day film 1 (8), when the fixed state is formed, the protrusion 203 The first conductive material will contact or bond with the second conductive material in the recess 103. Like the first conductive material on the dog discharge 203, the second conductive material in the recess (10) may be any suitable conductive material, and in the preferred implementation of the present invention, the conductive material is preferably a genus material, such as An alloy of gold, silver, copper or the like, but the invention is not limited thereto, and the second conductive material may be disposed on the bottom side surface or the inner wall surface of the groove ι 3, such as an electric ore, in any suitable manner. , coating or other techniques known in the art. . Furthermore, in the present day, it is not limited whether the first and second conductive materials are the same, but the first and second conductive materials are the same based on the basis of the system and the feasibility of the combination. Sixth, the first conductive material on the large output 2°3 is electrically connected to the first material in the groove 103 to electrically connect the crystal# to the substrate, which is only the embodiment of the present invention, and may also be other suitable The electrical connection method is achieved. In the embodiment, the first surface of the carrier of the present invention is opposite to the second surface and is parallel to each other and is in contact with the third and fourth surfaces (8) of the wafer. Stone, h - set. In other words, the wafer 100 is arranged to form a substantially parallel relationship with the carrier 2〇〇 in the 200919662 column. However, this is only a simple example of the implementation of the present invention, and the present invention is not limited to this aspect, and can be applied to the arrangement of other kinds. ί. Referring to Fig. 2, a schematic diagram and a process step similar to that of Fig. j are shown, which are used to illustrate a schematic diagram of a scorpion-type package according to an embodiment of the present invention. As shown in Fig. 2, the protrusions 2〇3 on the surface of the carrier are arranged to have a top side surface and a side outer wall surface, and the surface is in the surface of the wafer (10) with respect to the protrusion 2〇3 The groove has a corresponding bottom side surface and a side inner wall surface. When a protrusion 203 of a carrier 200 is inserted into a groove ι 3 of a wafer (10), the protrusion The top side surface of the object 203 can be coupled to the bottom side surface of the recess #1〇3, and the outer wall surface of the protrusion 2〇3 is sprayed onto the inner wall surface of the recess 1〇3, and the card is A structure. Referring to Figure 3, there is shown a schematic diagram of an electrical connection structure of a rod package according to an embodiment of the present invention. The towel is as described above, and after the step of the second aligning is completed, the wafer 100 is further bonded to the carrier 200 to form an electrical connection. In this embodiment, the protrusion 2〇3 is disposed to have a top side surface and a side outer wall surface, and the groove ribs have corresponding bottom side surfaces with respect to the surfaces of the protrusions 203 and The side inner wall surface 'when the protrusion 2〇3 of the carrier is inserted into the groove of a wafer (10), the top side surface of the protrusion 2G3 can be conjugated to the bottom side surface of the groove (10) The outer wall surface of the hoof dog 203 is fed to the inner wall surface of the groove 103, and is snapped into the body. The card-connecting method may also be applied to the top side surface of the object and the top surface of the object is coated with glue. The protrusion 203 of the carrier 2 and the groove of the wafer (10) are fixed. (10) The matching and snapping can provide a more fresh way to enhance the 200919662 yield of the erected body. However, for those skilled in the art, the arrangement of the protrusions and grooves (10) can be any suitable. Configuration, but adjacent to the first surface 2 of the dresser and the third surface of the wafer pair, the protrusion and the groove ι 3 of the interdigitated mating of the wafer pair must have a corresponding shape, position And the quantity to facilitate the joint of the two. However, in terms of manufacturing convenience, it is preferable to use the same number, position and shape of the protrusion 203 and the groove 1〇3. The package 3 is at least a through hole (not shown) for electrically connecting the third surface of the wafer to the fourth surface, and the connection thereof can be achieved by any suitable means. In a preferred embodiment of the invention The electrical connection between the components is filled through the through holes in the wafer (10). In the implementation, in the implementation system, the metal material is electro-mineralized in the through hole to realize the “the third surface and the first shunt-heap connection, and the fourth surface 1〇2 of the ^(10) and the carrier 200 The first surface 2〇1 is electrically connected by being connected by a wire 3〇1 provided on the pad. In the preferred embodiment of the present invention, the wires and pads are made of a metal such as an alloy of gold, silver, copper or the like. Referring to FIG. 4, the structure of the carrier in FIG. 3 is shown in Fig. 3, and the structure of the carrier 2 is the same as that of the wafer. The package can be packaged with Mg or other suitable materials. In other words, a win is set on the first surface 2〇1 of the load 200. The sealant 4〇1 covers a portion of the first surface 201 of the carrier 200 and covers at least a portion of the wafer 1〇. The wire and the wire 3 are further immersed in a plurality of solder balls (not shown) on the second surface 2〇2 of the carrier 2〇〇 for electrical connection with other external f3 devices. The setting of the tin ball % is a technique known in the art and will not be repeated here. 200919662 No. 5 _ The packaging method according to the 榫 封装 package structure is complicated. As shown in Fig. 5, the present invention provides a bearing (see the symbol of the component in Fig. 1) having a first surface (see Fig. 1 in which the component symbol is added) and a second surface (please Referring to the figure (where the symbol is 202), the first-surface axis is for the second surface, and the surface-to-surface is provided with at least one protrusion (see the figure i 1 in the symbol 1 2〇3), the protrusion Having a top side surface and a plurality of side outer wall surfaces (please refer to step 1); further providing a wafer (see the figure in which the component symbol 唬100) is disposed on the first surface of the carrier, the wafer has a a third surface (see item! {® where the component symbol is followed by) and a fourth surface (see Figure 1 where the component symbol is removed), the third surface relative to the fourth surface and on the third surface There is at least one groove (see Fig. Fig. 7G piece Wei 1〇3), which has a thin surface corresponding to the protrusion and a side inner wall surface (please refer to step (1) and is provided on the fourth surface At least one solder fillet (see Figure 3, where component symbol 302), and more specifically, the wafer contains at least a through hole electrically connecting the third surface and the fourth surface of the crystal moon; and further, after the step 11 is completed, the top side surface of the protrusion and the outer wall surface of the side edge are aligned with each other The surface of the bottom surface of the groove and the surface of the side wall, and the wafer 111 is placed on the bearing-on-frame (see step 12), and the plurality of wires are welded through the 2-wire step. The wire is electrically connected to the carrier and the wafer (see step 13), and the other is formed into a sealant (see the symbol of the component in the figure 4 5 6 7), which is disposed on the first surface and covers 4 parts. The crystal > 1 and the plurality of bonding wires and the first surface (see step 14) form a plurality of tin 5 balls electrically connected to the second surface of the carrier (see step 15). The 榫-type package structure provided by the present invention not only avoids the migration of silver generated by the 7-bonding process, the content of ions in the resin, and the generation of voids in the prior art, and 200919662 is also provided by The grooves on the first surface and the second surface of the carrier are engaged with the protrusions to form a package 'Forming an accurate alignment structure. The present invention achieves its main purpose and performance through the above technical means, and these technical means are not found in any conventional technology, and the present invention is indeed in compliance with the relevant provisions of the patent law. , 提出 提出 提出 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 惟 ' 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟 惟Within the scope of Lin Ben's creation (4), the changes or refinements made shall be regarded as changes within the scope of this Creative Rights. [Simplified Schematic] Figure 1 is a schematic diagram of the rotation according to the 伽 榫 。. 2 is a schematic view showing the structure of the wafer and the substrate after the package according to the present invention. Fig. 3 is a schematic view showing the squat connection structure according to the present invention. (4) Schematic diagram of the object surface. Figure 5 is a flow chart showing the packaging method of the 封装-type package structure according to the present invention. 13 200919662 [Main component symbol description] 100 wafer 101 third surface 102 fourth surface 103 groove 200 carrier 201 first surface 202 second surface 203 protrusion 301 wire 302 pad gasket seal 401

Claims (1)

200919662 十、申請專利範圍: 1. 一種榫式封裝結構,其包含有·· 一承載器,具有一第—表面及—第二表 第二表面,且該第-表面係設有至少―突^ ,1,該第—表面係相對於該 一晶月,係設置於該承載器的第—表面 一第四表面,該第三表面係相對於該第四表面 一凹槽其面對該承載器第一表面的突出物。 口亥曰曰片具有一第三表面與 另垓第三表面上設有至少 2.如申請專利範圍第1 基板。 項所述之榫式封裝結構 其中該承載器可為一 其中該承載器還為一 其中該承載器與該晶 其中該突出物之表面 其中該凹槽之表面及 3.如申請專利範圍第i項所述之榫式封襄結構 導線架。 4.如申請專利範圍第1項所述之榫式封裝結構 片呈平行設置。 5. 如申請專利範圍第1項所述之榫式封裴結構 及側邊之外壁係鍍覆有導電金屬材料。 6. 如申請專利範圍第1項所述之榫式封裝結構 側邊之内壁係錢覆有導電金屬材料。 …7·如申請專利範圍第i項所述之榫式封農結構,其中該突出物可與該 第二表面所設置的凹槽對位後呈一相互卡合之狀態。 8.如申請專娜圍第7項所述之榫式封裝結構,其中該卡合狀態可為 一干涉配合的方式。 15 200919662 其中該卡合狀態還可 9.如申請專利範圍第7項所述之榫式封裝結構 於凹槽底部、突出物處塗覆膠液,黏著固定。 !〇·如申請專利顧第丨項所述之榫式封裝結構,其中該第—表面與該 第四表面係分別設置有至少一個銲墊。 11.如申請專利範圍第項所述之榫式封裝結構,其中該第—表維亥 第四表面還分職置有複數條職與該銲衫相互之電性連接。 Λ Α如申請專卿第η項所述之榫式封裝結構,其中該銲線可為銅、 銀或金等導電金屬材料。 、13·如中請專纖圍第1項所述之榫式雜結構,其找^更包含 至少-個通孔,用以電性連接該晶片的第三表面和第四表面· Η·如申請補細第丨顿述之榫辆裝結構,其中更包含—封勝設 置於該第四絲上,域蓋部份之^ '魏條躲、該第_表面。 15.如申請專利範圍第!項所述之榫式封裝結構,其中更包含複數各錫 球置於第二表面上。 16·如申料利補第丨項所述之榫式封驗構,其中在該晶片之第三 表面和錄動之第—表面之間更包含—轉,用雜著該“和該承載 器· 17.種榫式封裝結構之製造方法,其步驟包含: /提供-承龜,該承載器具有―第―表面及—第二表面,該第—表 面係招對於该第二表面,且該第—表面係設有至少—突出物; 提供一晶片,其設置於該承載器的第一表面,該晶片具有—第三表 16 200919662 面與-第四表面,該第三表面係相對於該第四表面,另該第三表面上設有 至少-凹槽其面對該承載器第—表面的突出物。; 將該第-表面之突出物與第三表面所設置之凹槽對位後呈一相互 卡合之狀態;以及 精由驳數條銲線以將該第四表面電性連接至該承載器之第一表面。 如申請專利範圍第13項所述之封裝結構之製造方法,其中該卡合 狀態可為一干涉配合方式。 19·如申請細刪13項所述之封錢構之製造方法,其中於對位 後還包含有-打齡驟,其糊銲線使辟—絲鄕四表轉成電性連 接。 2〇·如申請專利範圍第15項所述之榫式封裝結構,其中該銲線可為銅、 銀或金等導電金屬材料。 21. 如申請專利範圍第13項所述之封裝結構之製造方法,其中還有_ 封膠步驟,其係將封膠設置於該第四表面上,並覆蓋部份之晶片、複數條 銲線、該第一表面。 22. 如申料利棚第η項所狀封裝轉之製造方法,射於封勝 後還包含一植錫球步驟,其係形成複數各錫球於第二表面上。 17200919662 X. Patent Application Range: 1. A 榫-type package structure comprising a carrier having a first surface and a second surface of the second surface, and the first surface is provided with at least a protrusion And the first surface is disposed on the first surface of the carrier with respect to the first crystal, and the third surface is opposite to the fourth surface and faces the carrier. A protrusion of the first surface. The mouth piece has a third surface and the other third surface is provided with at least 2. The first substrate as claimed in the patent. The 封装-type package structure of the present invention, wherein the carrier may be one of the carrier and the surface of the protrusion and the surface of the protrusion, wherein the surface of the groove is 3. The truss sealing structure lead frame described in the item. 4. The package of the 榫-type package structure as described in claim 1 is arranged in parallel. 5. The 裴-type sealing structure and the side outer wall as described in the scope of claim 1 are plated with a conductive metal material. 6. The inner wall of the side of the 封装-type package structure as described in claim 1 is covered with a conductive metal material. The shackle-type agricultural structure as described in claim i, wherein the protrusions are in a state of being engaged with each other after the grooves provided on the second surface are aligned. 8. If the application of the 榫-type package structure described in Item 7 of the stipulations is applied, the engagement state may be an interference fit. 15 200919662 wherein the engagement state is also 9. The 封装-type package structure as described in claim 7 of the patent application is applied to the bottom of the groove and the glue at the protrusion, and is fixed by adhesion. The 榫-type package structure as described in the patent application, wherein the first surface and the fourth surface system are respectively provided with at least one bonding pad. 11. The package structure of claim 1, wherein the fourth surface of the first table is further divided into a plurality of posts and electrically connected to the soldering shirt. Α For example, the application of the 榫-type package structure described in item η, wherein the wire can be a conductive metal material such as copper, silver or gold. 13. In the case of the 榫-type hybrid structure described in the first item, the search includes at least one through hole for electrically connecting the third surface and the fourth surface of the wafer. Apply for the 丨 丨 丨 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫 榫15. If you apply for a patent scope! The package structure of the present invention further comprises a plurality of solder balls disposed on the second surface. The method of claim 1 , wherein the third surface of the wafer and the first surface of the recording are further included, and the carrier is mixed with the carrier 17. A method of manufacturing a 榫-type package structure, the method comprising: providing/supporting a turtle having a “first surface” and a second surface, the first surface being applied to the second surface, and the The first surface is provided with at least a protrusion; a wafer is provided on the first surface of the carrier, the wafer has a third surface 16 200919662 surface and a fourth surface, the third surface is opposite to the a fourth surface, the third surface is provided with at least a groove facing the first surface of the carrier; and the protrusion of the first surface is aligned with the groove provided by the third surface And in a state in which the plurality of bonding wires are electrically connected to the first surface of the carrier, as in the manufacturing method of the package structure according to claim 13 of the patent application, Wherein the engagement state can be an interference fit mode. The manufacturing method of the sealed money structure described in Item 13 is deleted in detail, wherein after the alignment, the ageing is also included, and the paste-bonding wire turns the four-folder into an electrical connection. 2〇·If applying for a patent The 封装-type package structure according to Item 15, wherein the wire bonding wire is a conductive metal material such as copper, silver or gold. 21. The manufacturing method of the package structure according to claim 13 of the patent application, wherein a sealing step of disposing the encapsulant on the fourth surface and covering a portion of the wafer, the plurality of bonding wires, and the first surface. 22. The packaging is manufactured according to the item n of the shed The method, after the sealing, further comprises a step of implanting a solder ball, which forms a plurality of solder balls on the second surface.
TW96138726A 2007-10-16 2007-10-16 Tenon-type package structure and method thereof TW200919662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW96138726A TW200919662A (en) 2007-10-16 2007-10-16 Tenon-type package structure and method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96138726A TW200919662A (en) 2007-10-16 2007-10-16 Tenon-type package structure and method thereof

Publications (2)

Publication Number Publication Date
TW200919662A true TW200919662A (en) 2009-05-01
TWI349353B TWI349353B (en) 2011-09-21

Family

ID=44727187

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96138726A TW200919662A (en) 2007-10-16 2007-10-16 Tenon-type package structure and method thereof

Country Status (1)

Country Link
TW (1) TW200919662A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106304631A (en) * 2015-06-29 2017-01-04 富葵精密组件(深圳)有限公司 Circuit board crimping structure and circuit board crimping structure manufacture method

Also Published As

Publication number Publication date
TWI349353B (en) 2011-09-21

Similar Documents

Publication Publication Date Title
TWI697086B (en) Chip packaging structure and manufacturing method thereof
TWI429050B (en) Stack die packages
TW546795B (en) Multichip module and manufacturing method thereof
TWI312569B (en) Semiconductor package on which a semiconductor device is stacked and production method thereof
TWI398933B (en) Package structure of integrated circuit device and manufacturing method thereof
TW201248812A (en) Flip-chip, face-up and face-down centerbond memory wirebond assemblies
TW432558B (en) Dual-chip packaging process and method for forming the package
TW200947668A (en) Stacked type chip package structure
TW529141B (en) Stacking type multi-chip package and its manufacturing process
TW200910564A (en) Multi-substrate block type package and its manufacturing method
TW456008B (en) Flip chip packaging process with no-flow underfill method
TWI311806B (en) Cob type ic package for improving bonding of bumps embedded in substrate and method for fabricating the same
TWI355731B (en) Chips-between-substrates semiconductor package and
TW200919662A (en) Tenon-type package structure and method thereof
TW200926316A (en) Semiconductor package and method thereof
TWI273681B (en) Semiconductor package with flip chip on leadless leadframe
TW201508877A (en) Semiconductor package and manufacturing method thereof
TWI306217B (en) Insertion-type semiconductor device and fabrication method thereof
TWI389296B (en) Stackable package and method for making the same and semiconductor package
CN102832190B (en) Semiconductor device with flip chip and manufacturing method of semiconductor device
TWI250623B (en) Chip-under-tape package and process for manufacturing the same
TWI462254B (en) Dual-leadframe multi-chip package and method of manufacture
TWI244173B (en) Semiconductor chip package structure
TW200409037A (en) Card-type electronic device in packaging form and the manufacturing method thereof
TWI380417B (en) Thin type multi-chip package

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees