TWI462254B - Dual-leadframe multi-chip package and method of manufacture - Google Patents

Dual-leadframe multi-chip package and method of manufacture Download PDF

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Publication number
TWI462254B
TWI462254B TW099112017A TW99112017A TWI462254B TW I462254 B TWI462254 B TW I462254B TW 099112017 A TW099112017 A TW 099112017A TW 99112017 A TW99112017 A TW 99112017A TW I462254 B TWI462254 B TW I462254B
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Taiwan
Prior art keywords
wafer
lead frame
contact region
holder
wafer holder
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TW099112017A
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Chinese (zh)
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TW201138044A (en
Inventor
Kai Liu
Lei Shi
Jun Lu
Anup Bhalla
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Alpha & Omega Semiconductor
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Priority to TW099112017A priority Critical patent/TWI462254B/en
Publication of TW201138044A publication Critical patent/TW201138044A/en
Application granted granted Critical
Publication of TWI462254B publication Critical patent/TWI462254B/en

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

雙引線框架多晶片共同封裝體及其製造方法 Double lead frame multi-chip common package and manufacturing method thereof

本發明涉及一種半導體封裝結構和製造方法，特別涉及一種雙引線框架多晶片共同封裝體及其製造方法。 The present invention relates to a semiconductor package structure and a manufacturing method, and more particularly to a dual lead frame multi-chip common package and a method of fabricating the same.

功率金屬氧化物半導體場效應晶體(metal-oxide-semiconductor field effect transistor，簡稱MOSFET)器件具有高集成密度、高可靠性、極低的靜態漏電流和不斷改進的功率處理能力，被廣泛的應用在消費電子、電腦等領域。 Metal-oxide-semiconductor field effect transistor (MOSFET) devices have high integration density, high reliability, extremely low static leakage current and improved power handling capability, and are widely used in applications. Consumer electronics, computers and other fields.

現有技術中，如第1圖所示，在封裝上管金屬氧化物半導體場效應電晶體(HS MOSFET)2和下管金屬氧化物半導體場效應電晶體(LS MOSFET)1時，將上管MOSFET 2和下管MOSFET 1分別設置在一引線框架晶片座4和晶片座3上，通過引線5分別連接下管MOSFET 1和上管MOSFET 2、下管MOSFET 1的頂部接觸區與晶片座3以及上管MOSFET 2的底部接觸區與晶片座3。 In the prior art, as shown in FIG. 1, when the upper metal oxide semiconductor field effect transistor (HS MOSFET) 2 and the lower metal oxide semiconductor field effect transistor (LS MOSFET) 1 are packaged, the upper MOSFET is used. 2 and the lower tube MOSFET 1 are respectively disposed on a lead frame wafer holder 4 and the wafer holder 3, and are connected to the top contact MOSFET 1 and the upper tube MOSFET 2, the top contact region of the lower tube MOSFET 1 and the wafer holder 3 and the upper portion through the lead 5, respectively. The bottom contact region of the MOSFET 2 is connected to the wafer holder 3.

現有技術中，如第2圖所示，將表面安裝型的電容11設置在半導體封裝12的表面，以降低寄生電感。 In the prior art, as shown in Fig. 2, a surface mount type capacitor 11 is provided on the surface of the semiconductor package 12 to reduce parasitic inductance.

在上述器件的封裝中，通過引線連接晶片，增加了晶片之間的電阻和電感，另外在半導體封裝表面設置電容器，增加了半導體封裝的尺寸及成本。 In the package of the above device, the wiring is connected by wires, the resistance and inductance between the wafers are increased, and a capacitor is provided on the surface of the semiconductor package, which increases the size and cost of the semiconductor package.

本發明的目的是提供一種雙引線框架多晶片共同封裝體及其製造方法，該封裝結構將連接片用於晶片之間的連接及晶片與晶片座之間的連接，降低了晶片之間的電阻和 電感，並且在封裝中集成了一個旁路電容，降低了封裝過程中的寄生電感，提高了整個器件的能量轉換效率，並同時減小了半導體封裝的尺寸，本發明的工藝操作簡單，易操作，製造成本低。 It is an object of the present invention to provide a dual lead frame multi-chip common package and a method of fabricating the same, which use a connection piece for connection between wafers and a connection between a wafer and a wafer holder, thereby reducing resistance between wafers with Inductance, and a bypass capacitor integrated in the package, reducing the parasitic inductance in the packaging process, improving the energy conversion efficiency of the entire device, and simultaneously reducing the size of the semiconductor package, the process of the invention is simple and easy to operate , manufacturing costs are low.

為了達到上述目的，本發明的技術方案是：一種雙引線框架多晶片共同封裝體，其特點是，包括：第一引線框架及第二引線框架，所述第一引線框架包括一個第一晶片座和多個外部引腳，所述第二引線框架包括一個第二晶片座和一個與第二晶片座一體構成的立體連接片；分別具有數個頂部接觸區及一底部接觸區的第一晶片及第二晶片；所述第一晶片設置在第一晶片座上，所述第二晶片設置在第二晶片座上；所述第一晶片的底部接觸區與第一晶片座電連接，所述第二晶片的底部接觸區與第二晶片座電連接；所述立體連接片連接第一晶片的一第一頂部接觸區，使第一晶片與第二晶片座電學連接，從而使第一晶片的第一頂部接觸區與第二晶片的底部接觸區電學連通。 In order to achieve the above object, the technical solution of the present invention is: a dual lead frame multi-chip common package, comprising: a first lead frame and a second lead frame, the first lead frame including a first wafer holder And a plurality of external leads, the second lead frame includes a second wafer holder and a three-dimensional connecting piece integrally formed with the second wafer holder; a first wafer having a plurality of top contact regions and a bottom contact region, respectively a second wafer; the first wafer is disposed on the first wafer holder, and the second wafer is disposed on the second wafer holder; the bottom contact region of the first wafer is electrically connected to the first wafer holder, the The bottom contact region of the two wafers is electrically connected to the second wafer holder; the three-dimensional connecting sheet is connected to a first top contact region of the first wafer, so that the first wafer and the second wafer holder are electrically connected, thereby making the first wafer A top contact region is in electrical communication with the bottom contact region of the second wafer.

上述的雙引線框架多晶片共同封裝體，其中，還包括一個頂部連接片，所述頂部連接片連接第二晶片的一頂部接觸區及至少一外部引腳。 The dual lead frame multi-chip common package described above further includes a top tab connected to a top contact region of the second wafer and at least one external lead.

上述的雙引線框架多晶片共同封裝體，其中，所述頂部連接片進一步延伸連接第一晶片的一第二頂部接觸區。 The dual lead frame multi-chip common package described above, wherein the top tab further extends to connect a second top contact region of the first wafer.

上述的雙引線框架多晶片共同封裝體，其中，所述多個晶片還包括具有一頂部接觸區及一底部接觸 區的第三晶片，所述第三晶片設置在第一晶片座上，所述第三晶片的底部接觸區與第一晶片座電連接；所述頂部連接片進一步延伸連接第三晶片的頂部接觸區。 The dual lead frame multi-chip common package described above, wherein the plurality of wafers further comprise a top contact region and a bottom contact a third wafer of the region, the third wafer being disposed on the first wafer holder, the bottom contact region of the third wafer being electrically connected to the first wafer holder; the top tab further extending to connect the top contact of the third wafer Area.

上述的雙引線框架多晶片共同封裝體，其中，所述第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述第三晶片為旁路電容。 The above dual-lead frame multi-chip common package, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer is a lower tube metal oxide semiconductor field effect transistor, the The three wafers are bypass capacitors.

一種雙引線框架多晶片共同封裝體，其特點是，包括：兩個引線框架，分別為第一引線框架及第二引線框架，所述第一引線框架包括一個第一晶片座和多個外部引腳，所述第二引線框架包括一個第二晶片座；多個晶片，所述多個晶片分別具有頂部接觸區及底部接觸區；所述多個晶片進一步包括第一晶片、第二晶片及第三晶片；所述第一晶片及第三晶片設置在第一晶片座上，所述第二晶片設置在第二晶片座上，所述第一晶片及第三晶片的底部接觸區分別與第一晶片座電學連接，所述第二晶片的底部接觸區與第二晶片座電學連接，所述第一晶片和第二晶片還分別包括頂部柵接觸區，第一晶片和第二晶片的柵接觸區分別與第一引線框架的外部引腳連接；一個頂部連接片，用於多晶片共同封裝體內的連接，所述頂部連接片連接第二晶片的頂部接觸區及外部引腳，並且所述頂部連接片同時連接第三晶片的頂部接觸區；所述第一晶片的頂部接觸區與所述第二晶片座電學連接。 A dual lead frame multi-chip common package, comprising: two lead frames, respectively a first lead frame and a second lead frame, the first lead frame comprising a first wafer holder and a plurality of external leads a second lead frame comprising a second wafer holder; a plurality of wafers having a top contact region and a bottom contact region, respectively; the plurality of wafers further comprising a first wafer, a second wafer, and a plurality a third wafer; the first wafer and the third wafer are disposed on the first wafer holder, the second wafer is disposed on the second wafer holder, and the bottom contact regions of the first wafer and the third wafer are respectively associated with the first wafer The wafer holder is electrically connected, the bottom contact region of the second wafer is electrically connected to the second wafer holder, and the first wafer and the second wafer further comprise a top gate contact region, a gate contact region of the first wafer and the second wafer, respectively Connected to the external leads of the first lead frame; a top tab for the connection in the multi-chip co-package, the top tab connecting the top contact area of the second wafer and the outside Foot, while the connecting piece and the top connecting the top contacting zone of the third wafer; the top contacting zone of the first wafer is connected to the second electrical base wafer.

上述的雙引線框架多晶片共同封裝體，其中，通過引線連接第一晶片的頂部接觸區與第二引線框架的內部引 腳。 The above-described two-lead frame multi-chip common package in which a top contact region of a first wafer and an internal lead of a second lead frame are connected by a wire foot.

上述的雙引線框架多晶片共同封裝體，其中，所述第一晶片和第三晶片集成為一個晶片設置在第一引線框架上。 The above described two-lead frame multi-chip common package, wherein the first wafer and the third wafer are integrated as one wafer disposed on the first lead frame.

上述的雙引線框架多晶片共同封裝體，其中，所述的第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述第三晶片為旁路電容。 The above dual-lead frame multi-chip common package, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer is a lower tube metal oxide semiconductor field effect transistor, The third chip is a bypass capacitor.

一種雙引線框架多晶片共同封裝體的製作方法，其特點是，包括以下步驟：步驟1：提供一個第一引線框架，所述第一引線框架包括第一晶片座和多個外部引腳；步驟2：提供多個晶片，包括第一晶片及第二晶片，所述第一晶片及第二晶片分別包括底部接觸區及頂部接觸區；步驟3：將所述第一晶片設置在第一晶片座上，第一晶片的底部接觸區與第一晶片座通過粘接材料電學連接；步驟4：提供一個第二引線框架及一個立體連接片，所述第二引線框架包括一個第二晶片座，所述第二晶片座與所述立體連接片為一體化成形結構，立體連接片連接第一晶片的頂部接觸區；步驟5：將第二晶片設置在第二晶片座上，第二晶片的底部接觸區與第二晶片座電學連接；步驟6：提供一個頂部連接片，所述頂部連接片連接第二晶片的頂部接觸區及第一引線框架的外部引腳。 A method for fabricating a dual-lead frame multi-chip common package, comprising: the following steps: Step 1: providing a first lead frame, the first lead frame comprising a first wafer holder and a plurality of external pins; 2: providing a plurality of wafers, including a first wafer and a second wafer, the first wafer and the second wafer respectively including a bottom contact region and a top contact region; and step 3: disposing the first wafer on the first wafer holder The bottom contact area of the first wafer is electrically connected to the first wafer holder by a bonding material; step 4: providing a second lead frame and a three-dimensional connecting piece, the second lead frame including a second wafer holder, The second wafer holder and the three-dimensional connecting piece are integrally formed structures, and the three-dimensional connecting piece is connected to the top contact area of the first wafer; Step 5: the second wafer is disposed on the second wafer holder, and the bottom of the second wafer is in contact with The region is electrically connected to the second wafer holder; step 6: providing a top tab, the top tab connecting the top contact region of the second wafer and the external lead of the first lead frame

一種雙引線框架多晶片共同封裝體的封裝製作方法， 其特點是，包括以下步驟：步驟1：提供一個第一引線框架，所述第一引線框架包括第一晶片座及多個外部引腳；步驟2：提供多個晶片，多個晶片包括第一晶片、第二晶片及第三晶片，將第一晶片及第三晶片設置在第一晶片座上，所述多個晶片都分別包含底部接觸區及頂部接觸區，將第一晶片及第三晶片的底部接觸區與第一晶片座電學連接；步驟3：提供一個第二引線框架，所述第二引線框架包括第二晶片座，連接第一晶片的頂部接觸區及第二晶片座；步驟4：將第二晶片設置在第二晶片座引上，並將所述第二晶片與所述第二晶片座電學連接；步驟5：提供一個頂部連接片，並將頂部連接片連接第二晶片的頂部接觸區及第一引線框架的外部引腳，並且所述頂部連接片同時連接第三晶片的頂部接觸區；步驟6：第一晶片和第二晶片的頂部接觸區包括一個柵接觸區，第一晶片和第二晶片的柵接觸區分別與第一引線框架的外部引腳連接；步驟7：清洗引線框架，用塑封體封裝引線框架、連接片及晶片，僅露出部分引線框架的外部引腳，電鍍引腳。 Method for manufacturing package of double lead frame multi-chip common package, The method comprises the following steps: Step 1: providing a first lead frame, the first lead frame comprises a first wafer holder and a plurality of external pins; Step 2: providing a plurality of wafers, the plurality of wafers including the first a first wafer and a third wafer are disposed on the first wafer holder, the plurality of wafers respectively including a bottom contact region and a top contact region, and the first wafer and the third wafer The bottom contact region is electrically connected to the first wafer holder; step 3: providing a second lead frame, the second lead frame including a second wafer holder connecting the top contact region of the first wafer and the second wafer holder; Disposing a second wafer on the second wafer holder and electrically connecting the second wafer to the second wafer holder; Step 5: providing a top tab and connecting the top tab to the second wafer a top contact region and an outer lead of the first lead frame, and the top tab is simultaneously connected to the top contact region of the third wafer; step 6: the top contact region of the first wafer and the second wafer includes a gate a contact region, a gate contact region of the first wafer and the second wafer are respectively connected to an external pin of the first lead frame; Step 7: cleaning the lead frame, and packaging the lead frame, the connecting piece and the wafer with the plastic package, exposing only a part of the lead frame External pins, plated pins.

上述的雙引線框架多晶片共同封裝體的製造方法，其中，在步驟3中，還包括一個立體連接片，所述立體連接片與所述第二晶片座為一體化成形結構，或所述立體連接片和所述第二晶片座電學連接，將所述立體連接片與第一晶片的頂部接觸區連接，從而使第一晶片的頂部接觸區與 第二晶片座電學連接。 The method for manufacturing a dual-lead frame multi-chip common package, wherein in step 3, a three-dimensional connecting piece is further included, and the three-dimensional connecting piece and the second wafer holder are integrally formed, or the three-dimensional The connecting piece and the second wafer holder are electrically connected, and the three-dimensional connecting piece is connected to a top contact area of the first wafer, so that the top contact area of the first wafer is The second wafer holder is electrically connected.

上述的雙引線框架多晶片共同封裝體的封裝製作方法，其中，在步驟3中，還包括多個引線，通過所述引線連接第一晶片的頂部接觸區與第二晶片座。 In the above method for manufacturing a dual-lead frame multi-chip common package, in step 3, a plurality of leads are further included, and the top contact region of the first wafer and the second wafer holder are connected by the leads.

上述的雙引線框架多晶片共同封裝體的製造方法，其中，在步驟2中，首先將第一晶片與第三晶片集成在一個集成晶片中，然後將所述集成晶片設置在第一引線框架上。 The above method for manufacturing a dual lead frame multi-chip common package, wherein in step 2, first and third wafers are first integrated in one integrated wafer, and then the integrated wafer is disposed on the first lead frame .

上述的雙引線框架多晶片共同封裝體的製造方法，其中，在步驟6中還包括以下步驟：a)在第一晶片的柵極、第二晶片的柵極上回流焊料球形成凸點；b)用引線分別連接第一晶片和第二晶片上的柵接觸區與第一引線框架的外部引腳。 The method for manufacturing a dual-lead frame multi-chip common package, wherein the step 6 further comprises the steps of: a) reflowing the solder balls on the gates of the first wafer and the gates of the second wafer to form bumps; b) The gate contact regions on the first and second wafers and the external leads of the first lead frame are respectively connected by leads.

上述的雙引線框架多晶片共同封裝體的製造方法，其中，通過粘接材料將晶片設置在晶片座上，並且通過粘接材料進行連接片與晶片頂部接觸區的連接，所述立體連接片及頂部連接片上設置多個孔，通過所述多個孔吸附粘接材料，使連接片與晶片的頂部接觸區之間穩定連接。 The above method for manufacturing a dual-lead frame multi-chip common package, wherein a wafer is placed on a wafer holder by an adhesive material, and a connection between the connection sheet and the top contact area of the wafer is performed by an adhesive material, the three-dimensional connection sheet and A plurality of holes are disposed in the top connecting piece, and the bonding material is adsorbed through the plurality of holes to stably connect the connecting piece to the top contact area of the wafer.

上述的雙引線框架多晶片共同封裝體的製造方法，其中，所述第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述的第三晶片為旁路電容。 The above method for manufacturing a dual-lead frame multi-chip common package, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer is a lower tube metal oxide semiconductor field effect transistor. The third wafer is a bypass capacitor.

上述的雙引線框架多晶片共同封裝體的製造方法，其中，所述第一引線框架和第二引線框架為一個整體框架。 The above method for manufacturing a dual lead frame multi-chip common package, wherein the first lead frame and the second lead frame are an integral frame.

本發明一種雙引線框架多晶片共同封裝體及其製造由於採用上述技術方案，使之與現有技術相比，具有以下優 點和積極效果： The invention provides a double lead frame multi-chip common package and a manufacturing method thereof, and adopts the above technical solution to make it have the following advantages compared with the prior art. Points and positive effects:

1、本發明通過一個連接片同時連接兩個晶片及引線框架的引腳，簡化了製作工藝。 1. The present invention simplifies the fabrication process by simultaneously connecting two wafers and lead pins of a lead frame through a connecting piece.

2、本發明由於將連接片用於晶片之間及晶片與晶片座之間的連接，降低了晶片之間的電阻和電感，並且縮小了晶片之間的距離。 2. The present invention reduces the resistance and inductance between the wafers and reduces the distance between the wafers by using the tabs for the connection between the wafers and between the wafers and the wafer holders.

3、本發明由於在晶片的封裝中集成一個旁路電容，從而使寄生電感最小化，提高了整個器件的能量轉換效率。 3. The present invention minimizes parasitic inductance by integrating a bypass capacitor in the package of the wafer, thereby improving the energy conversion efficiency of the entire device.

4、本發明雙引線框架多晶片共同封裝體的工藝製作簡單、易操作，製造成本低。 4. The process of the dual-lead frame multi-chip common package of the invention is simple in process, easy to operate, and low in manufacturing cost.

實施例一、如第3圖所示，一種雙引線框架多晶片共同封裝體，包括兩個引線框架，兩個晶片及兩個連接片。兩個引線框架分別為第一引線框架101及第二引線框架102，第一引線框架101包括第一晶片座110及多個外部引腳111、112、113、114及多個內部引腳(可選項，圖中未顯示)，多個外部引腳是為了與內部晶片對應連接，實際應用時可按需要增加或者減少；第二引線框架102包括第二晶片座120及多個內部引腳(可選項圖中未顯示)及多個連筋121、122，連筋121、122用於引線框架之間的連接，同時對引線框架起加固作用。多個晶片分別具有頂部接觸區(圖中未顯示)及底部接觸區(圖中未顯示)，兩個晶片分別為第一晶片130及第二晶片140；通過粘接材料，優選地如通過導電膠或焊錫膏將第一晶片130設置在第一晶片座110上，同樣，通過粘接材料將第二晶片140設置在 第二晶片座120上；第一晶片130的底部接觸區與第一引線框架101的外部引腳112電學連接，第二晶片140的底部接觸區與第二晶片座120電學連接。連接片用於多晶片共同封裝體內的連接，兩個連接片包括立體連接片150及頂部連接片160，優選地，立體連接片150與第二晶片座120為一體化成形結構，為第二引線框架102的一個組成部分，或者，立體連接片150與第二晶片座120電學連接；同時通過導電粘接材料的粘結作用立體連接片150連接第一晶片130的頂部接觸區，使第一晶片130與第二晶片座120電學連接，由於第二晶片140與第二晶片座120電學連接，因而通過立體連接片150及第二晶片座120，第一晶片130與第二晶片140電學連通。頂部連接片160連接第二晶片140的頂部接觸區及第一晶片座的110外部引腳114，優選地，第一晶片130為上管金屬氧化物半導體場效應電晶體，第二晶片140為下管金屬氧化物半導體場效應電晶體。在本實施例中，立體連接片150及頂部連接片160，一方面縮小了上管金屬氧化物半導體場效應電晶體和下管金屬氧化物半導體場效應電晶體之間的距離，另一方面減少了晶片之間的電感和電阻，其中由於立體連接片150與第二晶片座120一體成形，確保立體連接片150與第二晶片座120之間穩定連接，本實施例列舉了兩個晶片的封裝，在實際封裝過程中，可在雙引線框架上設置多個晶片，通過連接片連接各個晶片，實現雙引線框架多晶片的共同封裝，製作工藝簡單方便。 Embodiment 1 As shown in FIG. 3, a dual lead frame multi-chip common package includes two lead frames, two wafers and two connecting pieces. The two lead frames are respectively a first lead frame 101 and a second lead frame 102. The first lead frame 101 includes a first wafer holder 110 and a plurality of external pins 111, 112, 113, 114 and a plurality of internal pins ( Option, not shown in the figure), the plurality of external pins are for corresponding connection with the internal chip, and may be added or reduced as needed in actual application; the second lead frame 102 includes the second wafer holder 120 and a plurality of internal pins ( Not shown in the option diagram) and a plurality of connecting ribs 121, 122, the connecting ribs 121, 122 are used for the connection between the lead frames, and at the same time, the lead frame is reinforced. The plurality of wafers respectively have a top contact region (not shown) and a bottom contact region (not shown), and the two wafers are a first wafer 130 and a second wafer 140, respectively; through an adhesive material, preferably as conductive The first wafer 130 is disposed on the first wafer holder 110 by glue or solder paste, and the second wafer 140 is disposed on the bonding material by the bonding material. The bottom contact area of the first wafer 130 is electrically connected to the outer lead 112 of the first lead frame 101, and the bottom contact area of the second wafer 140 is electrically connected to the second wafer holder 120. The connecting piece is used for the connection in the multi-chip co-package. The two connecting pieces include the three-dimensional connecting piece 150 and the top connecting piece 160. Preferably, the three-dimensional connecting piece 150 and the second wafer base 120 are integrally formed into a second lead. An integral part of the frame 102, or the three-dimensional connecting piece 150 is electrically connected to the second wafer holder 120; at the same time, the three-dimensional connecting piece 150 is connected to the top contact area of the first wafer 130 by the bonding of the conductive bonding material, so that the first wafer The first wafer 130 is electrically connected to the second wafer 140 through the three-dimensional connecting sheet 150 and the second wafer holder 120. The first wafer 130 is electrically connected to the second wafer holder 120. The top tab 160 is connected to the top contact region of the second wafer 140 and the outer lead 114 of the first wafer holder 110. Preferably, the first wafer 130 is an upper tube metal oxide semiconductor field effect transistor, and the second wafer 140 is lower. Tube metal oxide semiconductor field effect transistor. In this embodiment, the three-dimensional connecting piece 150 and the top connecting piece 160 reduce the distance between the upper tube metal oxide semiconductor field effect transistor and the lower tube metal oxide semiconductor field effect transistor on the one hand, and reduce on the other hand. The inductance and the resistance between the wafers, wherein the three-dimensional connection piece 150 and the second wafer holder 120 are integrally formed to ensure a stable connection between the three-dimensional connection piece 150 and the second wafer holder 120. This embodiment exemplifies the package of two wafers. In the actual packaging process, a plurality of wafers can be arranged on the double lead frame, and each wafer is connected through the connecting piece to realize common packaging of the double lead frame multi-chip, and the manufacturing process is simple and convenient.

雙引線框架多晶片共同封裝體在製作過程，如第4圖所示，包括以下幾個步驟：首先，提供一個第一引線框架 101，第一引線框架101包括晶片座110及多個外部引腳111、112、113、114，還可選擇性地包括多個內部引腳(圖中未顯示)；同時提供多個晶片，包括第一晶片130及第二晶片140，優選地，第一晶片130為上管金屬氧化物半導體場效應電晶體，第二晶片140為下管金屬氧化物半導體場效應電晶體，第一晶片130及第二晶片140分別包括底部接觸區及頂部接觸區；其次，通過導電粘接材料將第一晶片130設置在第一晶片座110上，第一晶片130的底部接觸區與第一晶片座電學連接，並通過連接第一晶片座110的外部引腳112引出；接著，提供一個第二引線框架102及一個立體連接片150，第二引線框架102包括晶片座120，還可包括多個內部引腳(圖中未顯示)多個連筋121、122，優選地，第二晶片座120與立體連接片150為一體化成形結構，為第二引線框架102的一個組成部分，或立體連接片150與第二晶片座120電學連接，立體連接片150通過導電粘接劑連接第一晶片130的頂部接觸區；然後，通過導電粘接材料，例如通過導電膠或焊錫膏將第二晶片140設置在第二晶片座120上，第二晶片140的底部接觸區與第二晶片座120電學連接；最後，提供一個頂部連接片160，頂部連接片160連接第二晶片140的頂部接觸區及第一引線框架101的外部引腳114。 The two-lead frame multi-chip common package is in the manufacturing process, as shown in FIG. 4, and includes the following steps: First, a first lead frame is provided. 101. The first lead frame 101 includes a wafer holder 110 and a plurality of external leads 111, 112, 113, 114, and optionally includes a plurality of internal leads (not shown); and simultaneously providing a plurality of wafers, including First wafer 130 and second wafer 140, preferably, first wafer 130 is an upper tube metal oxide semiconductor field effect transistor, second wafer 140 is a lower tube metal oxide semiconductor field effect transistor, first wafer 130 and The second wafer 140 includes a bottom contact region and a top contact region, respectively. Secondly, the first wafer 130 is disposed on the first wafer holder 110 by a conductive bonding material, and the bottom contact region of the first wafer 130 is electrically connected to the first wafer holder. And being connected by the external pin 112 connected to the first wafer holder 110; then, a second lead frame 102 and a three-dimensional connecting piece 150 are provided, the second lead frame 102 includes the wafer holder 120, and may also include a plurality of internal pins (not shown) a plurality of connecting ribs 121, 122. Preferably, the second wafer holder 120 and the three-dimensional connecting piece 150 are integrally formed structures, which are an integral part of the second lead frame 102, or the three-dimensional connecting piece 150 and First The two wafer holders 120 are electrically connected, and the three-dimensional connecting sheets 150 are connected to the top contact region of the first wafer 130 by a conductive adhesive; then, the second wafer 140 is disposed in the second by a conductive bonding material, for example, by a conductive paste or solder paste. On the wafer holder 120, the bottom contact region of the second wafer 140 is electrically connected to the second wafer holder 120; finally, a top tab 160 is provided, and the top tab 160 is connected to the top contact region of the second wafer 140 and the first lead frame 101. External pin 114.

實施例二、如第5圖所示，一種雙引線框架多晶片共同封裝體，包括兩個引線框架、三個晶片及兩個連接片。兩個引線框架分別為第一引線框架201及第二引線框架202，第一引線框架201包括第一晶片座210及多個外部引腳211、212、213、214、215及選擇性的多個內部引腳(圖 中未顯示)，多個外部引腳是為了與內部晶片對應連接，實際應用時可按需要增加或者減少；第二引線框架202包括第二晶片座220和選擇性的多個內部引腳(圖中未顯示)及多個連筋221、222，連筋221、222用於引線框架之間的連接，同時對引線框架起加固作用。多個晶片分別具有頂部接觸區及底部接觸區，多個晶片包括第一晶片230、第二晶片240及第三晶片250；第一晶片230及第三晶片250通過導電粘接材料設置在第一晶片座210上，同樣通過導電粘接材料將第二晶片240設置在第二晶片座220上，優選地，導電粘接材料為錫焊膏或導電膠。第一晶片230及第三晶片250的底部接觸區分別與第一晶片座210的外部引腳212、213電學連接，第二晶片240的底部接觸區與第二晶片座220電學連接；第一晶片230和第二晶片240還分別包括柵接觸區2311、2411，第一晶片230和第二晶片240的柵接觸區2311、2411分別與第一晶片座210的外部引腳211、214電學連接，優選地，第一晶片230及第二晶片240的柵接觸區2311、2411通過引線280分別與第一引線框架210的外部引腳211、214連接。兩個連接片分別為立體連接片260及頂部連接片270，立體連接片260及頂部連接片270上分別設有多個孔261、271，多個孔261、271用於吸附粘接材料，使連接片與晶片的頂部接觸區之間穩定連接，優選地，立體連接片260和第二晶片座220一體成型，為第二引線框架202的一個組成部分，或者立體連接片260與第二晶片座220電學連接，立體連接片260連接第一晶片230的頂部接觸區，從而使第一晶片230的頂部接觸區與第二晶片座220電學連接；頂部連 接片270用於多晶片共同封裝體內的連接，頂部連接片270連接第二晶片220的頂部接觸區及第一引線框架201的外部引腳215，並且頂部連接片270同時連接第三晶片250的頂部接觸區；優選地，第一晶片230為上管金屬氧化物半導體場效應電晶體，第二晶片240為下管金屬氧化物半導體場效應電晶體，第三晶片250為旁路電容，旁路電容250用於降低寄生電感，在本實施例中，立體連接片260及頂部連接片270，一方面縮小了上管金屬氧化物半導體場效應電晶體和下管金屬氧化物半導體場效應電晶體之間的距離，另一方面同時減少了晶片之間的電感和電阻，其中由於立體連接片260與第二晶片座220一體成形，立體連接片260與第二晶片座220之間的連接穩定，此外，旁路電容降低電路中的寄生電感，提高了整個器件的能量轉換效率，本實施例列舉了兩個晶片的封裝，在實際封裝過程中，可在雙引線框架上設置多個晶片，通過連接片連接各個晶片，實現雙引線框架多晶片的共同封裝。 Embodiment 2 As shown in FIG. 5, a dual lead frame multi-chip common package includes two lead frames, three wafers and two connecting pieces. The two lead frames are respectively a first lead frame 201 and a second lead frame 202. The first lead frame 201 includes a first wafer holder 210 and a plurality of external leads 211, 212, 213, 214, 215 and a plurality of optional Internal pin Not shown in the figure), the plurality of external pins are for corresponding connection with the internal wafer, and may be added or reduced as needed in actual application; the second lead frame 202 includes the second wafer holder 220 and a plurality of selective internal pins (Fig. Not shown in the middle) and a plurality of connecting ribs 221, 222, the connecting ribs 221, 222 are used for the connection between the lead frames, and at the same time, the lead frame is reinforced. The plurality of wafers respectively have a top contact area and a bottom contact area, and the plurality of wafers include a first wafer 230, a second wafer 240, and a third wafer 250; the first wafer 230 and the third wafer 250 are disposed at first by a conductive bonding material On the wafer holder 210, the second wafer 240 is also disposed on the second wafer holder 220 by a conductive bonding material. Preferably, the conductive bonding material is a solder paste or a conductive paste. The bottom contact regions of the first wafer 230 and the third wafer 250 are electrically connected to the external leads 212, 213 of the first wafer holder 210, respectively, and the bottom contact region of the second wafer 240 is electrically connected to the second wafer holder 220; The 230 and second wafers 240 further include gate contact regions 2311, 2411, respectively, and the gate contact regions 2311, 2411 of the first wafer 230 and the second wafer 240 are electrically connected to the external leads 211, 214 of the first wafer holder 210, respectively. The gate contact regions 2311, 2411 of the first wafer 230 and the second wafer 240 are respectively connected to the external leads 211, 214 of the first lead frame 210 by wires 280. The two connecting pieces are respectively a three-dimensional connecting piece 260 and a top connecting piece 270. The three-dimensional connecting piece 260 and the top connecting piece 270 are respectively provided with a plurality of holes 261 and 271, and the plurality of holes 261 and 271 are used for adsorbing the bonding material. The connection piece is stably connected with the top contact area of the wafer. Preferably, the three-dimensional connection piece 260 and the second wafer holder 220 are integrally formed as one component of the second lead frame 202, or the three-dimensional connection piece 260 and the second wafer holder 220 electrically connected, the three-dimensional connecting piece 260 is connected to the top contact area of the first wafer 230, so that the top contact area of the first wafer 230 is electrically connected to the second wafer holder 220; The tab 270 is used for the connection in the multi-chip co-package, the top tab 270 is connected to the top contact region of the second wafer 220 and the outer lead 215 of the first lead frame 201, and the top tab 270 is simultaneously connected to the third wafer 250. a top contact region; preferably, the first wafer 230 is an upper tube metal oxide semiconductor field effect transistor, the second wafer 240 is a lower tube metal oxide semiconductor field effect transistor, and the third wafer 250 is a bypass capacitor, bypass The capacitor 250 is used to reduce the parasitic inductance. In the embodiment, the three-dimensional connecting piece 260 and the top connecting piece 270 reduce the upper tube metal oxide semiconductor field effect transistor and the lower tube metal oxide semiconductor field effect transistor. The distance between the wafers and the second wafer holder 220 is stabilized by the distance between the three-dimensional connection piece 260 and the second wafer holder 220, and the connection between the three-dimensional connection piece 260 and the second wafer holder 220 is stabilized. The bypass capacitor reduces the parasitic inductance in the circuit and improves the energy conversion efficiency of the entire device. This embodiment exemplifies the package of two wafers in the actual package. Process, the wafer may be provided on a plurality of two-wire frame, is connected by a respective connecting piece wafer achieve common leadframe package multiple double wafer.

雙引線框架多晶片共同封裝體在製作過程時，如第6-10圖所示，包括以下步驟，如第7圖所示，首先提供一個第一引線框架201，第一引線框架201包括第一晶片座210及多個外部引腳211、212、213、214、215，還可選擇性地包括多個內部引腳(圖中未顯示)；其次提供多個晶片，多個晶片包括第一晶片230、第二晶片240及第三晶片250，優選地，第一晶片230為上管金屬氧化物半導體場效應電晶體，第二晶片240為下管金屬氧化物半導體場效應電晶體，第三晶片250為旁路電容，第一晶片230、第二晶片240及第三晶片250都分別包含底部接觸區(圖 中未顯示)及頂部接觸區231、241、251，如第8圖所示，將第一晶片230及第三晶片250設置在第一晶片座210上，優選地，通過粘接劑，例如通過導電膠或焊錫膏將第一晶片230及第三晶片250設置在第一晶片座210上，同時將第一晶片230及第三晶片250的底部接觸區與第一晶片座210電學連接；再次，如第9圖所示，提供一個第二引線框架202及一個立體連接片260，優選地，立體連接片260與第二晶片座220為一體化成形結構，或立體連接片260和第二晶片座220電學連接，第二引線框架202包括多個連筋221、222，立體連接片260上設有多個孔261，在孔位置吸附粘接劑，通過粘接劑將立體連接片260與第一晶片230的頂部接觸區231連接，優選地，將立體連接片260與第一晶片230的源接觸區連接，從而使第一晶片230的頂部接觸區與第二晶片座220電學連接；接著，如第10圖所示，將第二晶片240設置在第二晶片座220上，並將第二晶片240的底部接觸區與第二晶片座220電學連接；然後提供一個頂部連接片270，頂部連接片270上設有多個孔271，在多個孔271的位置吸附粘接劑，從而連接頂部連接片270及第二晶片的頂部接觸區，同時頂部連接片270連接第一引線框架201的外部引腳215及第三晶片250的頂部接觸區251；接著，在第一晶片和第二晶片的柵接觸區2311、2411處回流焊料球形成凸點，通過引線280分別將第一晶片及第二晶片的柵接觸區2311、2411連接至第一引線框架的引腳211、214上；最後，清洗引線框架用塑封體封裝晶片座、連接片及晶片，僅露出部分引線框架的外部引腳以及電鍍引腳。 The double lead frame multi-chip common package is included in the manufacturing process, as shown in FIGS. 6-10, and includes the following steps. As shown in FIG. 7, a first lead frame 201 is first provided, and the first lead frame 201 includes the first The wafer holder 210 and the plurality of external leads 211, 212, 213, 214, 215 may also optionally include a plurality of internal leads (not shown); secondly, a plurality of wafers including a first wafer 230, second wafer 240 and third wafer 250, preferably, the first wafer 230 is an upper tube metal oxide semiconductor field effect transistor, the second wafer 240 is a lower tube metal oxide semiconductor field effect transistor, a third wafer 250 is a bypass capacitor, and the first wafer 230, the second wafer 240, and the third wafer 250 each include a bottom contact region (FIG. And the top contact regions 231, 241, 251, as shown in FIG. 8, the first wafer 230 and the third wafer 250 are disposed on the first wafer holder 210, preferably by an adhesive, for example The conductive paste or the solder paste disposes the first wafer 230 and the third wafer 250 on the first wafer holder 210 while electrically connecting the bottom contact regions of the first wafer 230 and the third wafer 250 to the first wafer holder 210; As shown in FIG. 9, a second lead frame 202 and a three-dimensional connecting piece 260 are provided. Preferably, the three-dimensional connecting piece 260 and the second wafer holder 220 are integrally formed, or the three-dimensional connecting piece 260 and the second wafer holder. 220 electrically connected, the second lead frame 202 includes a plurality of connecting ribs 221, 222, the three-dimensional connecting piece 260 is provided with a plurality of holes 261, the adhesive is adsorbed at the hole position, and the three-dimensional connecting piece 260 is firstly bonded by the adhesive The top contact region 231 of the wafer 230 is connected, preferably, the three-dimensional connection piece 260 is connected to the source contact region of the first wafer 230, so that the top contact region of the first wafer 230 is electrically connected to the second wafer holder 220; As shown in FIG. 10, the second wafer 240 is to be The second wafer holder 220 is disposed on the second wafer holder 220, and the bottom contact region of the second wafer 240 is electrically connected to the second wafer holder 220; then a top connecting piece 270 is provided, and the top connecting piece 270 is provided with a plurality of holes 271, The holes 271 are positioned to adsorb the adhesive to connect the top tabs 270 and the top contact regions of the second wafer, while the top tabs 270 connect the outer leads 215 of the first lead frame 201 and the top contact regions of the third wafer 250. 251; then, reflowing the solder balls at the gate contact regions 2311, 2411 of the first and second wafers to form bumps, and connecting the gate contact regions 2311, 2411 of the first and second wafers to the first through the leads 280, respectively On the leads 211, 214 of the lead frame; finally, the cleaning lead frame encapsulates the wafer holder, the connecting piece and the wafer with the plastic body, and exposes only the external pins of the lead frame and the plating pins.

實施例三、如實施例11所示，一種雙引線框架多晶片共同封裝體，包括兩個引線框架、兩個連接片及三個晶片，兩個引線框架分別為第一引線框架301及第二引線框架302，兩個連接片分別為立體連接片350及頂部連接片360，三個晶片分別為第一晶片、第二晶片340及第三晶片，優選地，第一晶片上管金屬氧化物半導體場效應電晶體，第二晶片340為下管金屬氧化物半導體場效應電晶體，第三晶片為旁路電容，如第10圖所示，實施例三與實施例二基本相同，區別在於，上管金屬氧化物半導體場效應電晶體和旁路電容首先集成為一個晶片330設置在第一晶片座310上，將上管金屬氧化物半導體場效應電晶體與旁路電容集成在一個集成晶片上，降低了晶片的寄生電感，提高了整個器件的能量轉換效率，並且提高晶片封裝的集成度。 Embodiment 3 As shown in Embodiment 11, a dual lead frame multi-chip common package includes two lead frames, two connecting pieces and three wafers, and the two lead frames are respectively a first lead frame 301 and a second The lead frame 302, the two connecting pieces are a three-dimensional connecting piece 350 and a top connecting piece 360, respectively, the three wafers are a first wafer, a second wafer 340 and a third wafer, respectively, preferably a first wafer upper metal oxide semiconductor The field-effect transistor, the second wafer 340 is a lower-tube metal-oxide-semiconductor field-effect transistor, and the third wafer is a bypass capacitor. As shown in FIG. 10, the third embodiment is basically the same as the second embodiment. The difference is that The tube metal oxide semiconductor field effect transistor and the bypass capacitor are first integrated into a wafer 330 disposed on the first wafer holder 310, and the upper metal oxide semiconductor field effect transistor and the bypass capacitor are integrated on an integrated wafer. The parasitic inductance of the wafer is reduced, the energy conversion efficiency of the entire device is improved, and the integration of the chip package is improved.

實施例四、如第12圖所示，一種雙引線框架多晶片共同封裝體，包括兩個引線框架、三個晶片及一個連接片。兩個引線框架分別為第一引線框架401及第二引線框架402，優選地，第一引線框架和第二引線框架為一個整體基板的兩個部分，整個基板可包括多個部分，第一引線框架401包括第一晶片座410及多個外部引腳411、412、413、414、415，還可選擇性地包括多個內部引腳(圖中未顯示)，第二引線框架402包括第二晶片座420及多個連筋421、422，還可包括多個內部引腳(圖中未顯示)。多個晶片分別具有頂部接觸區及底部接觸區，多個晶片包括第一晶片430、第二晶片440及第三晶片450；優選地，第一晶片430為上管金屬氧化物半導體場效應電晶體，第二晶片440為 下管金屬氧化物半導體場效應電晶體，第三晶片450為旁路電容。第一晶片430及第三晶片450通過粘接材料設置在第一晶片座410上，第二晶片440通過粘接材料設置在第二晶片座420上，第一晶片430及第三晶片450的底部接觸區分別與第一晶片座410電學連接，第二晶片440的底部接觸區與第二晶片座420電學連接，第一晶片430和第二晶片440還分別包括柵接觸區4311、4411，第一晶片430和第二晶片440的柵接觸區4311、4411分別與第一引線框架401的外部引腳411、414電學連接，優選地，第一晶片430及第二晶片440的柵接觸區4311、4411通過引線480分別與第一晶片座410的外部引腳411、414連接。一個連接片為頂部連接片460，頂部連接片460上設有多個孔461，多個孔461用於吸附粘接材料，從而更好的連接頂部連接片460及第二晶片420的頂部接觸區；頂部連接片460連接第二晶片420的頂部接觸區及第一引線框架401的外部引腳415，並且頂部連接片460同時連接第三晶片450的頂部接觸區；第一晶片430的頂部接觸區4312通過引線470與第二晶片座420電學連接，從而使第一晶片430與第二晶片420電學連接，在本實施例中，頂部連接片460用於晶片之間及晶片與晶片座之間的連接，降低了晶片之間的電感，提高了連接的穩定性，同時在局部晶片之間通過引線連接，提高了晶片連接的靈活性。 Embodiment 4 As shown in FIG. 12, a dual lead frame multi-chip common package includes two lead frames, three wafers, and a connecting piece. The two lead frames are respectively a first lead frame 401 and a second lead frame 402. Preferably, the first lead frame and the second lead frame are two parts of one integral substrate, and the entire substrate may include a plurality of parts, the first lead The frame 401 includes a first wafer holder 410 and a plurality of external leads 411, 412, 413, 414, 415, and optionally a plurality of internal leads (not shown), and the second lead frame 402 includes a second The wafer holder 420 and the plurality of ribs 421, 422 may further include a plurality of internal pins (not shown). The plurality of wafers respectively have a top contact region and a bottom contact region, and the plurality of wafers include a first wafer 430, a second wafer 440, and a third wafer 450; preferably, the first wafer 430 is an upper tube metal oxide semiconductor field effect transistor The second wafer 440 is The lower tube metal oxide semiconductor field effect transistor, the third wafer 450 is a bypass capacitor. The first wafer 430 and the third wafer 450 are disposed on the first wafer holder 410 by an adhesive material, and the second wafer 440 is disposed on the second wafer holder 420 by an adhesive material, the bottom of the first wafer 430 and the third wafer 450. The contact regions are electrically connected to the first wafer holder 410, the bottom contact region of the second wafer 440 is electrically connected to the second wafer holder 420, and the first wafer 430 and the second wafer 440 further include gate contact regions 4311, 4411, respectively. The gate contact regions 4311, 4411 of the wafer 430 and the second wafer 440 are electrically connected to the external leads 411, 414 of the first lead frame 401, respectively, preferably the gate contact regions 4311, 4411 of the first wafer 430 and the second wafer 440. The leads 480 are respectively connected to the external pins 411, 414 of the first wafer holder 410. One connecting piece is a top connecting piece 460, and the top connecting piece 460 is provided with a plurality of holes 461 for adsorbing the bonding material, thereby better connecting the top connecting piece of the top connecting piece 460 and the second wafer 420. The top tab 460 connects the top contact region of the second wafer 420 and the outer lead 415 of the first lead frame 401, and the top tab 460 simultaneously connects the top contact region of the third wafer 450; the top contact region of the first wafer 430 4312 is electrically connected to the second wafer holder 420 via a lead 470 to electrically connect the first wafer 430 with the second wafer 420. In the present embodiment, the top tab 460 is used between the wafers and between the wafer and the wafer holder. The connection reduces the inductance between the wafers, improves the stability of the connection, and improves the flexibility of the wafer connection by connecting the wires between the partial wafers.

雙引線框架多晶片共同封裝體的製作過程，包括以下步驟，首先提供一個整體基板，整體基板包括第一引線框架401及第二引線框架402，第一引線框架401包括第一晶片座410及多個外部引腳411、412、413、414、415，還 可包括多個內部引腳(圖中未顯示)，第二引線框架402包括第二晶片座420及多個連筋421、422，還可包括多個內部引腳(圖中未顯示)，優選地，第一引線框架401和第二引線框架402為一個整體框架，然後提供多個晶片，多個晶片包括第一晶片430、第二晶片440及第三晶片450，優選地，第一晶片430為上管金屬氧化物半導體場效應電晶體，第二晶片440為下管金屬氧化物半導體場效應電晶體，第三晶片450為旁路電容，將第一晶片430及第三晶片450設置在第一晶片座410上，優選地，通過粘結劑，例如通過導電膠或焊錫膏將第一晶片430及第三晶片450設置在第一晶片座410上，同時將第一晶片430及第三晶片450的底部接觸區電學連接第一晶片座410與外部引腳412、413電學連接；再次，通過引線470連接第一晶片430的頂部接觸區及第二晶片座或與第二晶片座電學連接的內部引腳(圖中未顯示)，然後，將第二晶片440設置在第二晶片座上，第二晶片440與第二晶片座420電學連接；接著提供一個頂部連接片460，頂部連接片460上設有多個孔461，多個孔461吸附粘接材料，連接頂部連接片460與第二晶片440的頂部接觸區，將頂部連接片460連接第二晶片440的頂部接觸區及第一引線框架401的外部引腳415，並且頂部連接片460同時連接第三晶片450的頂部接觸區；接著，通過引線480分別將第一晶片430及第二晶片440的柵接觸區4311、4411連接至第一引線框架的引腳411、414上；最後，清洗引線框架，用塑封體封裝晶片座、連接片及晶片，僅露出部分引線框架的外部引腳，電鍍引腳。 The manufacturing process of the dual-lead frame multi-chip common package includes the following steps. First, a unitary substrate is provided. The whole substrate includes a first lead frame 401 and a second lead frame 402. The first lead frame 401 includes a first wafer holder 410 and a plurality of External pins 411, 412, 413, 414, 415, also The plurality of internal leads (not shown) may be included. The second lead frame 402 includes a second wafer holder 420 and a plurality of connecting ribs 421, 422, and may further include a plurality of internal pins (not shown), preferably The first lead frame 401 and the second lead frame 402 are an integral frame, and then a plurality of wafers are provided. The plurality of wafers include a first wafer 430, a second wafer 440, and a third wafer 450. Preferably, the first wafer 430 For the upper MOSFET, the second wafer 440 is a lower MOSFET, the third wafer 450 is a bypass capacitor, and the first wafer 430 and the third wafer 450 are disposed at On a wafer holder 410, preferably, the first wafer 430 and the third wafer 450 are disposed on the first wafer holder 410 by an adhesive, for example, by a conductive paste or solder paste, while the first wafer 430 and the third wafer are simultaneously The bottom contact region of 450 is electrically connected to the first wafer holder 410 to be electrically connected to the external leads 412, 413; again, the top contact region of the first wafer 430 and the second wafer holder are connected by wires 470 or electrically connected to the second wafer holder. Internal pin (in the figure) Displaying, then, the second wafer 440 is disposed on the second wafer holder, the second wafer 440 is electrically connected to the second wafer holder 420; then a top connecting piece 460 is provided, and the top connecting piece 460 is provided with a plurality of holes 461 The plurality of holes 461 adsorb the bonding material, connect the top tab 460 to the top contact area of the second wafer 440, and connect the top tab 460 to the top contact region of the second wafer 440 and the external lead 415 of the first lead frame 401. And the top tab 460 is simultaneously connected to the top contact region of the third wafer 450; then, the gate contact regions 4311, 4411 of the first wafer 430 and the second wafer 440 are respectively connected to the pins 411 of the first lead frame through the leads 480 Finally, the lead frame is cleaned, and the wafer holder, the connecting piece and the wafer are packaged by the plastic sealing body, and only the external pins of the part of the lead frame are exposed, and the pins are plated.

當然，必須認識到，上述介紹是有關本發明優選實施例的說明，只要不偏離隨後所附權利要求所顯示的精神和範圍，本發明還存在著許多修改。 Of course, it is to be understood that the foregoing description has been described in connection with the preferred embodiments of the invention, and the invention

本發明決不是僅局限於上述說明或附圖所顯示的細節和方法。本發明能夠擁有其他的實施例，並可採用多種方式予以實施。另外，大家還必須認識到，這裏所使用的措辭和術語以及文摘只是為了實現介紹的目的，決不是僅僅局限於此。 The present invention is by no means limited to the details and methods shown in the above description or the drawings. The invention is capable of other embodiments and of various embodiments. In addition, you must also understand that the words and terms used herein and the abstracts are for the purpose of illustration only and are by no means limited.

正因為如此，本領域的技術人員將會理解，本發明所基於的觀點可隨時用來作為實施本發明的幾種目標而設計其他結構、方法和系統。所以，至關重要的是，所附的權利要求將被視為包括了所有這些等價的建構，只要它們不偏離本發明的精神和範圍。 As such, those skilled in the art will appreciate that the present invention is based on the teachings of the present invention as well as other structures, methods and systems. Therefore, it is essential that the appended claims be construed as including all such equivalents

1‧‧‧下管金屬氧化物半導體場效應電晶體(LS MOSFET) 1‧‧‧Underlined Metal Oxide Semiconductor Field Effect Transistor (LS MOSFET)

2‧‧‧上管金屬氧化物半導體場效應電晶體(HS MOSFET) 2‧‧‧Upper tube metal oxide semiconductor field effect transistor (HS MOSFET)

3‧‧‧晶片座 3‧‧‧ Wafer holder

4‧‧‧引線框架晶片座 4‧‧‧ lead frame wafer holder

5、280、470、480‧‧‧引線 5, 280, 470, 480‧‧‧ lead

11‧‧‧電容 11‧‧‧ Capacitance

12‧‧‧半導體封裝 12‧‧‧Semiconductor package

101、201、301、401‧‧‧第一引線框架 101, 201, 301, 401‧‧‧ first lead frame

102、202、302、402‧‧‧第二引線框架 102, 202, 302, 402‧‧‧second lead frame

110、210、310、410‧‧‧第一晶片座 110, 210, 310, 410‧‧‧ first wafer holder

111、112、113、114、211、212、213、214、215、411、412、413、414、415‧‧‧外部引腳 111, 112, 113, 114, 211, 212, 213, 214, 215, 411, 412, 413, 414, 415‧‧‧ external pins

120、220、320、420‧‧‧第二晶片座 120, 220, 320, 420‧‧‧ second wafer holder

121、122、221、222、421、422‧‧‧連筋 121, 122, 221, 222, 421, 422‧‧‧

130、230、430‧‧‧第一晶片 130, 230, 430‧‧‧ first wafer

140、240、340、440‧‧‧第二晶片 140, 240, 340, 440‧‧‧ second wafer

150、260、350‧‧‧立體連接片 150, 260, 350‧‧‧ three-dimensional connecting piece

160、270、360、460‧‧‧頂部連接片 160, 270, 360, 460‧‧‧ top connecting piece

250、450‧‧‧第三晶片 250, 450‧‧‧ third chip

231、241、251、4312‧‧‧頂部接觸區 231, 241, 251, 4312‧‧‧ top contact area

261、271、461‧‧‧孔 261, 271, 461‧ ‧ holes

2311、2411、4311、4411‧‧‧柵接觸區 2311, 2411, 4311, 4411‧‧‧ gate contact area

330‧‧‧晶片 330‧‧‧ wafer

參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。 Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.

第1圖為現有技術中上管MOSFET和下管MOSET的封裝結構示意圖。 FIG. 1 is a schematic diagram of a package structure of an upper tube MOSFET and a lower tube MOSET in the prior art.

第2圖為現有技術中在半導體封裝表面設置電容的結構示意圖。 FIG. 2 is a schematic view showing the structure of a capacitor disposed on a surface of a semiconductor package in the prior art.

第3圖為實施例一雙引線框架多晶片共同封裝體的結構示意圖。 FIG. 3 is a schematic structural view of a dual lead frame multi-chip common package of the embodiment.

第4圖為實施例一雙引線框架多晶片共同封裝體的製作方法流程圖 4 is a flow chart of a method for fabricating a dual-lead frame multi-chip common package of the first embodiment

第5圖為實施例二雙引線框架多晶片共同封裝體的結構示意圖。 FIG. 5 is a schematic structural view of a two-lead frame multi-chip common package of the second embodiment.

第6圖為實施例二雙引線框架多晶片共同封裝體的製作方法流程圖。 FIG. 6 is a flow chart showing a method for fabricating the dual-lead frame multi-chip common package of the second embodiment.

第7圖為實施例二雙引線框架多晶片共同封裝體的製作方法過程中提供的第一引線框架結構示意圖。 FIG. 7 is a schematic structural view of a first lead frame provided during the manufacturing method of the dual lead frame multi-chip common package of the second embodiment.

第8圖為實施例二雙引線框架多晶片共同封裝體的製作方法過程中將第一晶片和第三晶片設置在第一晶片座上的結構示意圖。 FIG. 8 is a structural schematic view showing the first wafer and the third wafer disposed on the first wafer holder during the manufacturing method of the dual-lead frame multi-chip common package of the second embodiment.

第9圖為實施例二雙引線框架多晶片共同封裝體的製作方法過程中一體化成形的第二晶片座及立體連接片的結構示意圖。 FIG. 9 is a schematic structural view of the second wafer holder and the three-dimensional connecting piece integrally formed in the manufacturing method of the double lead frame multi-chip common package in the second embodiment.

第10圖為實施例二雙引線框架多晶片共同封裝體的製作方法過程中一個第二晶片及頂部連接片的結構示意圖。 FIG. 10 is a schematic structural view of a second wafer and a top connecting piece in the manufacturing method of the dual lead frame multi-chip common package of the second embodiment.

第11圖為實施例三雙引線框架多晶片共同封裝體的結構示意圖。 Figure 11 is a schematic view showing the structure of a three-lead frame multi-chip common package of the third embodiment.

第12圖為實施例四雙引線框架多晶片共同封裝體的結構示意圖。 Figure 12 is a schematic view showing the structure of a four-lead frame multi-chip common package of the fourth embodiment.

第13圖為實施例四雙引線框架多晶片共同封裝體的製作方法流程圖。 FIG. 13 is a flow chart showing a method for fabricating the four-lead frame multi-chip common package of the fourth embodiment.

201‧‧‧第一引線框架 201‧‧‧First lead frame

202‧‧‧第二引線框架 202‧‧‧Second lead frame

210‧‧‧第一晶片座 210‧‧‧First wafer holder

211、212、213、214、215‧‧‧外部引腳 211, 212, 213, 214, 215‧‧‧ external pins

220‧‧‧第二晶片座 220‧‧‧Second wafer holder

221、222‧‧‧連筋 221, 222‧‧‧ reinforced bars

230‧‧‧第一晶片 230‧‧‧First chip

240‧‧‧第二晶片 240‧‧‧second chip

250‧‧‧第三晶片 250‧‧‧ Third chip

251‧‧‧頂部接觸區 251‧‧‧Top contact area

260‧‧‧立體連接片 260‧‧‧Three-dimensional connecting piece

261、271‧‧‧孔 261, 271‧‧ holes

270‧‧‧頂部連接片 270‧‧‧Top connecting piece

280‧‧‧引線 280‧‧‧ lead

2311、2411‧‧‧柵接觸區 2311, 2411‧‧‧ gate contact area

Claims (17)

一種雙引線框架多晶片共同封裝體，其特徵在於，包括：第一引線框架及第二引線框架，其中所述第一引線框架包括一個第一晶片座和多個外部引腳，所述第二引線框架包括一個第二晶片座和一個與所述第二晶片座一體構成的立體連接片；分別具有數個頂部接觸區及一底部接觸區的第一晶片及第二晶片，其中所述第一晶片設置在所述第一晶片座上，所述第二晶片設置在所述第二晶片座上，所述第一晶片的底部接觸區與所述第一晶片座電連接，所述第二晶片的底部接觸區與所述第二晶片座電連接；以及一個頂部連接片，所述頂部連接片電連接所述第二晶片的頂部接觸區及所述第一引線框架的一外部引腳；其中所述立體連接片電連接所述第一晶片的一第一頂部接觸區，使所述第一晶片與所述第二晶片座電學連接，從而使所述第一晶片的所述第一頂部接觸區與所述第二晶片的所述底部接觸區電學連通。 A dual lead frame multi-chip common package, comprising: a first lead frame and a second lead frame, wherein the first lead frame comprises a first wafer holder and a plurality of external pins, the second The lead frame includes a second wafer holder and a three-dimensional connecting piece integrally formed with the second wafer holder; a first wafer and a second wafer respectively having a plurality of top contact regions and a bottom contact region, wherein the first a wafer is disposed on the first wafer holder, the second wafer is disposed on the second wafer holder, and a bottom contact region of the first wafer is electrically connected to the first wafer holder, the second wafer a bottom contact region electrically connected to the second wafer holder; and a top tab electrically connecting the top contact region of the second wafer and an external lead of the first lead frame; The three-dimensional connecting piece electrically connects a first top contact region of the first wafer, electrically connecting the first wafer and the second wafer holder, thereby connecting the first top of the first wafer The bottom contact region and the second region electrically communicates wafer. 如申請專利範圍第1項所述的雙引線框架多晶片共同封裝體，其特徵在於，所述頂部連接片進一步延伸電連接所述第一晶片的一第二頂部接觸區。 The dual lead frame multi-chip common package of claim 1, wherein the top tab further extends electrically to a second top contact region of the first wafer. 如申請專利範圍第1項所述的雙引線框架多晶片共同封裝體，其特徵在於，還包括具有一頂部接觸區及一底部接觸區的第三晶片，所述第三晶片設置在所述第一晶片座上，所述第三晶片的所述底部接觸區與所述第一晶片座電連接；所述頂部 連接片進一步延伸電連接所述第三晶片的所述頂部接觸區。 The dual lead frame multi-chip common package of claim 1, further comprising a third wafer having a top contact region and a bottom contact region, wherein the third wafer is disposed in the The bottom contact region of the third wafer is electrically connected to the first wafer holder on a wafer holder; the top portion The tab further extends electrically to connect the top contact region of the third wafer. 如申請專利範圍第3項所述的雙引線框架多晶片共同封裝體，其特徵在於，所述第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述第三晶片為旁路電容。 The dual lead frame multi-chip common package according to claim 3, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer is a lower tube metal oxide. The semiconductor field effect transistor, the third wafer is a bypass capacitor. 一種雙引線框架多晶片共同封裝體，其特徵在於，包括：兩個引線框架，分別為第一引線框架及第二引線框架，所述第一引線框架包括一個第一晶片座和多個外部引腳，所述第二引線框架包括一個第二晶片座；多個晶片，所述多個晶片皆具有頂部接觸區及底部接觸區，其中所述多個晶片進一步包括第一晶片、第二晶片及第三晶片，所述第一晶片及所述第三晶片設置在所述第一晶片座上，所述第二晶片設置在所述第二晶片座上，所述第一晶片的底部接觸區及所述第三晶片的底部接觸區皆與所述第一晶片座電學連接，所述第二晶片的底部接觸區與所述第二晶片座電學連接，所述第一晶片和所述第二晶片還皆包括頂部柵接觸區，所述第一晶片的頂部柵接觸區和第二晶片的頂部柵接觸區分別與所述第一引線框架的二個外部引腳電學連接；以及一個頂部連接片，用於多晶片共同封裝體內的電學連接，所述頂部連接片電學連接所述第二晶片的頂部接觸區及所述第一引線框架的外部引腳，並且所述頂部連接片同時電學連接所述第三晶片的頂部接觸區；以及所述第一晶片的頂部接觸區與所述第二晶片座電學連 接。 A dual lead frame multi-chip common package, comprising: two lead frames, respectively a first lead frame and a second lead frame, the first lead frame comprising a first wafer holder and a plurality of external leads a second lead frame comprising a second wafer holder; a plurality of wafers each having a top contact region and a bottom contact region, wherein the plurality of wafers further comprises a first wafer, a second wafer, and a third wafer, the first wafer and the third wafer are disposed on the first wafer holder, and the second wafer is disposed on the second wafer holder, a bottom contact area of the first wafer and The bottom contact region of the third wafer is electrically connected to the first wafer holder, and the bottom contact region of the second wafer is electrically connected to the second wafer holder, the first wafer and the second wafer Also including a top gate contact region, the top gate contact region of the first wafer and the top gate contact region of the second wafer are electrically connected to the two outer leads of the first lead frame, respectively; and a top connection An electrical connection for use in a multi-chip co-package, the top tab electrically connecting a top contact region of the second wafer and an outer lead of the first lead frame, and the top tab is electrically connected at the same time a top contact region of the third wafer; and a top contact region of the first wafer electrically connected to the second wafer holder Pick up. 如申請專利範圍第5項所述的雙引線框架多晶片共同封裝體，其特徵在於，通過引線電學連接所述第一晶片的頂部接觸區與所述第二引線框架的內部引腳。 The dual lead frame multi-chip common package of claim 5, wherein the top contact area of the first wafer and the inner lead of the second lead frame are electrically connected by a lead. 如申請專利範圍第5項所述的雙引線框架多晶片共同封裝體，其特徵在於，所述第一晶片和所述第三晶片集成為一個晶片設置在所述第一引線框架上。 The dual lead frame multi-chip common package of claim 5, wherein the first wafer and the third wafer are integrated as one wafer disposed on the first lead frame. 如申請專利範圍第6項或第7項所述的雙引線框架多晶片共同封裝體，其特徵在於，所述的第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述第三晶片為旁路電容。 The dual lead frame multi-chip common package according to claim 6 or 7, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer The lower transistor is a metal oxide semiconductor field effect transistor, and the third wafer is a bypass capacitor. 一種雙引線框架多晶片共同封裝體的製作方法，其特徵在於，包括以下步驟：步驟1：提供一個第一引線框架，所述第一引線框架包括第一晶片座和多個外部引腳；步驟2：提供多個晶片，所述多個晶片包括第一晶片及第二晶片，所述第一晶片及所述第二晶片皆包括底部接觸區及頂部接觸區；步驟3：將所述第一晶片設置在所述第一晶片座上，所述第一晶片的底部接觸區與所述第一晶片座通過粘接材料電學連接；步驟4：提供一個第二引線框架及一個立體連接片，所述第二引線框架包括一個第二晶片座，所述第二晶片座與所述立體連接片為一體化成形結構，所述立體連接片電學連接所述第一晶片的頂部接觸區；步驟5：將所述第二晶片設置在所述第二晶片座上， 所述第二晶片的底部接觸區與所述第二晶片座電學連接；以及步驟6：提供一個頂部連接片，所述頂部連接片電學連接所述第二晶片的頂部接觸區及所述第一引線框架的外部引腳。 A method for fabricating a dual-lead frame multi-chip common package, comprising the steps of: providing a first lead frame, the first lead frame comprising a first wafer holder and a plurality of external leads; 2: providing a plurality of wafers, the plurality of wafers including a first wafer and a second wafer, the first wafer and the second wafer each including a bottom contact region and a top contact region; and step 3: the first a wafer is disposed on the first wafer holder, a bottom contact region of the first wafer is electrically connected to the first wafer holder by an adhesive material; and step 4: providing a second lead frame and a three-dimensional connecting piece, The second lead frame includes a second wafer holder, the second wafer holder and the three-dimensional connecting piece are integrally formed structures, and the three-dimensional connecting piece electrically connects the top contact area of the first wafer; Step 5: Locating the second wafer on the second wafer holder, a bottom contact region of the second wafer is electrically connected to the second wafer holder; and step 6: providing a top tab, the top tab electrically connecting the top contact region of the second wafer and the first The external pins of the lead frame. 一種雙引線框架多晶片共同封裝體的封裝製作方法，其特徵在於，包括以下步驟：步驟1：提供一個第一引線框架，所述第一引線框架包括第一晶片座及多個外部引腳；步驟2：提供多個晶片，所述多個晶片包括第一晶片、第二晶片及第三晶片，將所述第一晶片及所述第三晶片設置在所述第一晶片座上，所述多個晶片都分別包含底部接觸區及頂部接觸區，將所述第一晶片的底部接觸區及所述第三晶片的底部接觸區與所述第一晶片座電學連接；步驟3：提供一個第二引線框架，所述第二引線框架包括第二晶片座，電學連接所述第一晶片的頂部接觸區及所述第二晶片座；步驟4：將所述第二晶片設置在所述第二晶片座上，並將所述第二晶片的底部接觸區與所述第二晶片座電學連接；步驟5：提供一個頂部連接片，並將所述頂部連接片電學連接所述第二晶片的頂部接觸區及所述第一引線框架的外部引腳，並且所述頂部連接片同時電學連接所述第三晶片的頂部接觸區；步驟6：所述第一晶片的頂部接觸區和所述第二晶片的頂部接觸區皆包括一個柵接觸區，所述第一晶片的柵接 觸區和所述第二晶片的柵接觸區分別與所述第一引線框架的二個外部引腳電學連接；以及步驟7：清洗所述第一和所述第二引線框架，用塑封體封裝所述第一和所述第二引線框架、所述頂部連接片及所述多個晶片，僅露出部分引線框架的外部引腳，電鍍引腳。 A method for fabricating a dual-lead frame multi-chip common package, comprising the steps of: providing a first lead frame, the first lead frame comprising a first wafer holder and a plurality of external leads; Step 2: providing a plurality of wafers, the plurality of wafers including a first wafer, a second wafer, and a third wafer, wherein the first wafer and the third wafer are disposed on the first wafer holder, Each of the plurality of wafers includes a bottom contact region and a top contact region, respectively electrically connecting the bottom contact region of the first wafer and the bottom contact region of the third wafer to the first wafer holder; Step 3: providing a a second lead frame, the second lead frame includes a second wafer holder electrically connecting the top contact region of the first wafer and the second wafer holder; and step 4: disposing the second wafer in the second a wafer holder, and electrically connecting a bottom contact region of the second wafer to the second wafer holder; step 5: providing a top tab and electrically connecting the top tab to the second wafer a contact region and an outer lead of the first lead frame, and the top tab simultaneously electrically connects the top contact region of the third wafer; step 6: a top contact region of the first wafer and the first The top contact regions of the two wafers each include a gate contact region, and the first wafer is gated The contact regions and the gate contact regions of the second wafer are electrically connected to the two external leads of the first lead frame, respectively; and the step 7: cleaning the first and the second lead frames, and packaging with a plastic package The first and the second lead frame, the top connecting piece and the plurality of wafers expose only external pins of a part of the lead frame, and are plated with pins. 如申請專利範圍第10項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，在步驟3中，還包括一個立體連接片，所述立體連接片與所述第二晶片座為一體化成形結構，或所述立體連接片和所述第二晶片座電學連接，將所述立體連接片與所述第一晶片的頂部接觸區電學連接，從而使所述第一晶片的頂部接觸區與所述第二晶片座電學連接。 The method for manufacturing a dual-lead frame multi-chip common package according to claim 10, further comprising, in step 3, a three-dimensional connecting piece, the three-dimensional connecting piece and the second wafer holder Forming an integrally formed structure, or electrically connecting the three-dimensional connecting piece and the second wafer holder, electrically connecting the three-dimensional connecting piece to a top contact area of the first wafer, thereby making the top of the first wafer A contact region is electrically connected to the second wafer holder. 如申請專利範圍第11項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，在步驟2中，首先將所述第一晶片與所述第三晶片集成在一個集成晶片中，然後將所述集成晶片設置在所述第一引線框架上。 The method for manufacturing a dual-lead frame multi-chip common package according to claim 11, wherein in step 2, the first wafer and the third wafer are first integrated in one integrated wafer. And then placing the integrated wafer on the first lead frame. 如申請專利範圍第11項或第12項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，在步驟6中還包括以下步驟：a)在所述第一晶片的柵極、所述第二晶片的柵極上回流焊料球形成凸點；b)用引線分別電學連接所述第一晶片和所述第二晶片上的柵接觸區與所述第一引線框架的外部引腳。 The method for manufacturing a dual-lead frame multi-chip common package according to claim 11 or 12, further comprising the step of: a) at the gate of the first wafer; Reflowing the solder balls on the gate of the second wafer to form bumps; b) electrically connecting the gate contact regions on the first and second wafers with the external leads of the first lead frame by wires respectively . 如申請專利範圍第10項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，通過粘接材料將晶片設 置在晶片座上，並且通過粘接材料進行連接片與晶片頂部接觸區的連接，所述立體連接片及所述頂部連接片上設置多個孔，通過所述多個孔吸附粘接材料，使連接片與晶片的頂部接觸區之間穩定連接。 The method for manufacturing a dual-lead frame multi-chip common package according to claim 10, characterized in that the wafer is provided by an adhesive material Positioned on the wafer holder, and the connection between the connecting piece and the top contact area of the wafer is performed by an adhesive material. The three-dimensional connecting piece and the top connecting piece are provided with a plurality of holes through which the bonding material is adsorbed. The tab is in stable connection with the top contact area of the wafer. 如申請專利範圍第10項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，所述第一晶片為上管金屬氧化物半導體場效應電晶體，所述第二晶片為下管金屬氧化物半導體場效應電晶體，所述的第三晶片為旁路電容。 The method for manufacturing a dual-lead frame multi-chip common package according to claim 10, wherein the first wafer is an upper tube metal oxide semiconductor field effect transistor, and the second wafer is lower A metal oxide semiconductor field effect transistor, the third wafer being a bypass capacitor. 一種雙引線框架多晶片共同封裝體的封裝製作方法，其特徵在於，包括以下步驟：步驟1：提供一個第一引線框架，所述第一引線框架包括第一晶片座及多個外部引腳；步驟2：提供多個晶片，所述多個晶片包括第一晶片、第二晶片及第三晶片，將所述第一晶片及所述第三晶片設置在所述第一晶片座上，所述多個晶片都分別包含底部接觸區及頂部接觸區，將所述第一晶片的底部接觸區及所述第三晶片的底部接觸區皆與所述第一晶片座電學連接；步驟3：提供一個第二引線框架，所述第二引線框架包括第二晶片座，通過多個引線電學連接所述第一晶片的頂部接觸區與所述第二晶片座；步驟4：將所述第二晶片設置在所述第二晶片座上，並將所述第二晶片與所述第二晶片座電學連接；步驟5：提供一個頂部連接片，並將所述頂部連接片電學連接所述第二晶片的頂部接觸區及所述第一引線框架的外部引腳，並且所述頂部連接片同時電學連接所述第三晶片的頂部接觸區； 步驟6：所述第一晶片的頂部接觸區和所述第二晶片的頂部接觸區皆包括一個柵接觸區，所述第一晶片的柵接觸區和所述第二晶片的柵接觸區分別與所述第一引線框架的二個外部引腳電學連接；以及步驟7：清洗所述第一和所述第二引線框架，用塑封體封裝所述第一和所述第二引線框架、所述頂部連接片及所述多個晶片，僅露出部分引線框架的外部引腳，電鍍引腳。 A method for fabricating a dual-lead frame multi-chip common package, comprising the steps of: providing a first lead frame, the first lead frame comprising a first wafer holder and a plurality of external leads; Step 2: providing a plurality of wafers, the plurality of wafers including a first wafer, a second wafer, and a third wafer, wherein the first wafer and the third wafer are disposed on the first wafer holder, Each of the plurality of wafers includes a bottom contact region and a top contact region, respectively, electrically connecting the bottom contact region of the first wafer and the bottom contact region of the third wafer to the first wafer holder; Step 3: providing a a second lead frame, the second lead frame including a second wafer holder electrically connecting a top contact region of the first wafer and the second wafer holder through a plurality of leads; and step 4: setting the second wafer On the second wafer holder, and electrically connecting the second wafer to the second wafer holder; Step 5: providing a top tab and electrically connecting the top tab to the second wafer External pin top contacting zone and the first lead frame and electrically connecting the top plate while the top portion is connected to the contact region of the third wafer; Step 6: the top contact region of the first wafer and the top contact region of the second wafer each include a gate contact region, and the gate contact region of the first wafer and the gate contact region of the second wafer are respectively The two outer leads of the first lead frame are electrically connected; and step 7: cleaning the first and the second lead frames, encapsulating the first and the second lead frames with a plastic body, The top tab and the plurality of wafers expose only the outer leads of a portion of the leadframe and are plated with pins. 如申請專利範圍第16項所述的雙引線框架多晶片共同封裝體的製造方法，其特徵在於，所述第一引線框架和所述第二引線框架為一個整體框架。 The method of manufacturing a dual lead frame multi-chip common package according to claim 16, wherein the first lead frame and the second lead frame are an integral frame.
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