200919639 九、發明說明： 【發明所屬之技術領域】 本發明整體而言係關於一種用於分離半導體晶圓為個別 半導體晶粒之方法。 【先前技術】 在積體電路構造中，藉由一系列材料沉積及移除製程， 複數個積體電路（半導體晶粒）被同時形成於一單個半導體 晶圓上。該等個別半導體晶粒然後在_被稱為鑛切之製程 中從該晶圓上分離。晶圓鋸切大體上包括以一圓形鋸刀片 鋸該晶圓或藉由刻劃及斷裂該晶圓（若該晶圓係結晶的卜 在該半導體晶圓之該等晶粒被分離處之該等部分係為習稱 之切口，或在半導體製造業界之說法係稱之為劃道或刻劃 道。刻劃道寬度由晶圓特性、刀片尺寸及特性、劃線工具 尺寸及特性等等之結合所指定。 熟習此項技術者將瞭解到一習知的刻劃道可具有一約6 2 微米之劃道寬度。就約3〇微米之刀片£度或刻劃工具寬度 及62微米之劃道寬度而言’於該刀片或刻劃工具之任一側 僅有16微米之餘隙。然而，該半導體製造業正朝向更窄之 刻劃道（例如’ 52微米及以τ)發展，致力於獲得每晶圓之 更高晶粒產量。為加工一 52微米之劃道寬度，該刀片或刻 劃工具必須不厚於2〇微米以保持於該刀片之任一側上之相 同餘隙 '然而，減小該鋸刀片厚度或刻劃工具厚度以促成 一較窄切口在實務上有其限制。 因此，本技術需要的係一種用於分離一半導體晶圓為其 131320.doc 200919639 個別晶粒之方法’該方法不受限於上述厚度。 【發明内容】 為解決上述之先前技術之缺點，提供一種用於分離—半 導體晶圓為個別半導體晶粒之方法。除其他步驟外，該用 於分離該半導體晶圓之方法可包含將一雜質植入至該半導 體晶圓接近半導體晶粒相互結合之接面處的區域中，該雜 質經構形以打斷在該半導體晶圓中接近該等接面處之鍵 合，並造成弱化區域。該方法可進一步包含在置放雜質至 該等區域中後移除該半導體晶圓之相反表面之部分。用於 分離該半導體晶圓之方法可額外地包含沿該等弱化之區域 分離具有S亥雜質及該等經移除區域之半導體晶圓為個別半 導體晶粒。 【實施方式】 本發明揭示之内容係至少部分係基於以下之認知：雜質 可被植入半導體晶圓之一接近半導體晶粒相互結合之接面 處，以幫助該半導體晶圓分離為其個別半導體晶粒。本發 明揭示之内容進一步瞭解到該等所植入之雜質可打斷在該 半導體晶圓内接近該等接面之鍵合，造成弱化之區域，及 可/。該等弱化之區域將該半導體晶圓分離為其個別晶粒。 圖1闡釋一流程圖100，其顯示一種製造半導體晶粒之方 法之-實施例。除該製造半導體晶粒之方法外，該流程圖 包含-包含一種分離半導體晶圓為個別半導體晶粒之方法 之子集。因此，該流程圖100並非用以將該所揭示内容限 制於任何特定步驟。 131320.doc 200919639 該机％圖100始於—開始步驟1〇5。其後，在步驟1⑺ 中，’獲得—半導體晶圓。該半導體晶圓可包括許多不同的 材料。舉例而言，其中，該半導體晶圓可包括—半導體、 導，或用於微電子學或類似技術領域中之絕緣材料。舉例 而3 ’可使用諸如GaAS、Inp或GaN之類之週期表第叫 族^導體、週期表第（IIIMV)族半導體之合金、鍺化 夕石厌化石夕、合成石英及熔融石夕石以及此等材料或未列出 之材料之結合。 \ 山該半導體晶圓可以製造之許多不同步驟而獲得。舉例而 Π實施例中，該半導體晶圓係—僅 寺徵於其中（例如，直接取自錠）之裸半導體晶圓。i Λ施例中’ 4半導體晶圓包括複數層’其中之一層可 絕緣體上，，在再-實:例 於該等上述材料之㉟/ j複數層包含可以係類似 p勺入 在此實施例中，該半導體晶圓可早 上W個或多個功能特徵（例如’主動特徵）於其中或其 其後’在步驟m中，可在該半導體晶圓上、内或 形成一個或多個額外的 一 多不同的處理步驟。^= 此步驟120可包含許 舉例而言，該步驟120可包含开,点 個或多個主動特徵(例如，電晶體特 ：成- 應器特徵等)於該半導體晶圓上、内、上方二特徵、感 額外地包含形成互連特徵於該半導體、：驟:可 該步驟120亦^相⑽ Μ上方。 又夕個忐致抗蝕劑特徵於 131320.doc 200919639 該半導體晶圓上、内或上方。然而，該步驟丨2〇不應受限 於任何單一處理步驟或處理步驟之整體。 在步驟120後，在步驟13〇中，抗蝕劑可被圖案化以曝露 接近接面之該半導體晶圓之區域（其中半導體晶粒相互結 合）。熟習此項技術者瞭解圖案化抗姓劑（例如，在一實施 例中之光致抗蝕劑）的程序。舉例而言，圖案化抗蝕劑之 程序可始於施加一抗蝕劑材料層至該半導體晶圓，隨後選 擇性地曝露該抗钱劑層於一能源，其中由於其曝露於該能 源，該抗蝕劑層之部分之特性改變。在此曝露（曝光）之 後，該抗蝕劑層然後可（例如）藉由一採用液體化學溶劑之 ’’濕式顯影程序”形成，以選擇性地移除該抗蝕劑之部分。 將造成的係於該抗钮劑中之一所需圖案，其在此實施例中 將曝路接近接面之該半導體晶圓之該等區域，其中半導體 晶粒相互結合。在另—實施例中’該抗敍劑將曝露在該半 導體晶圓中之該等刻劃道之至少一部分。 在步驟140中，雜質可被置放至該半導體晶圓之區域（例 〇 ’此實施例中之該等所曝露的區域）中。在—實施例 圓内質㈣形以打斷接近該等接面之在該半導體晶 域之雜質；之區域。用於最終形成該等弱化區 I:二變。舉例而言，在-實施例中，該等雜質係 個或夕個稀有氣體離子。舉例而言 ^ AA ^ 發見早獨的或係 、，-口《的風離子與氦離子皆可 # t ^ ^ ^ 下為6亥雜質。然而，該 雜貝了包括诸如爛離子或磷離子或 離子之纟士人夕相从廿 卞雕子與先前所遠 …之類的其他離子。然而，在特定應用中，應避 131320.doc 200919639 免棚與^4 ’以便防止周圍區域之反摻雜。亦可使用其他雜 質。 利用多種不同程序，可將該等雜質置放於該半導體晶圓 内。然而，在一實施例中，利用一植入技術將該等雜質置 放於該半導體晶圓内。舉例而言，在一實施例中，利用一 在約10 keV至約1000 keV範圍内之植入能量與一在約1E12 原子/cm3至1E1 6原子/cm3範圍内之植入劑量將該等雜質植 入該半導體晶圓内。在另一實施例中，選擇該等植入條 件，使得該等弱化區域從該半導體晶圓之表面延伸，該植 入最初接觸於一相反表面。雖然如此，亦可使用其他植入 條件，包含不需要先前所述之抗蝕劑之植入。 其後，在步驟150中，沿該等弱化區域，具有該雜質於 其中之該半導體晶圓可被分離為其個別半導體晶粒。將該 半導體晶圓分離為該等個別晶粒可包含許多不同步驟或多 個步驟之結合。舉例而f，在—實施例中，具有㈣弱化 區域之半導體晶圓可經受一熱應力以促使該等弱化區域破 裂’因此允許該等半導體晶粒分離。其中，藉由將具有該 等雜質包含於其中之半導體晶圓退火於適當溫度可給予該 熱應力。熟習此項技術者瞭解為破裂該半導體晶圓所需之 適當溫度同時仍在該所分配的熱預算内。 同樣地，具有該等弱化區域之該半導體晶圓可經受一機 械應力以促使該等弱化區域破裂。其中，藉由一越過該半 導體晶圓之表面滾動之機械裝置可給予該機械應力。在一 替代實施例中，機械應力與熱應力兩者被用於幫助該等半 131320.doc -10- 200919639 導體晶粒之分離。在破裂該半導體晶圓為其個別晶粒後， 該製程可停止於停止步驟155。 圖1之流程圖1〇〇包含可用於製造如本發明揭示之内容之 只施例之半導體晶粒之步驟。在替代實施例中，更少之 步驟或額外的步驟可被用於製造如本發明揭示之内容之替 代實施例之半導體晶粒。另外，該等步驟之每一步驟被引 導之特定順序可改變。因此，舉例而言，在特定實施例 中’步驟130與140可先於步驟12〇發生。 圖2A-4B闡釋處理步驟，其顯示一種分離一半導體晶圓 為個別半導體晶粒之方法之一實施例。圖2 A最初闡釋一 半導體晶圓210。顯示於圖2A中之晶圓包含一缺口 26〇及一 個或多個晶粒區域270。如熟習此項技術者預期，該缺口 260可連同該晶圓210之中心（或另一已知點）一起被用於調 整該晶圓210上之各種不同特徵，包含特定半導體特徵之 位置、該等晶粒區域等等。 該一個或多個晶粒區域270代表於該半導體晶圓21〇上之 不同晶粒之晶粒邊界。此等晶粒邊界可基本上係該晶圓 210被鋸切為其個別半導體晶粒之該等刻劃道。而且，該 等晶粒區域270可以係利用一放大構件與否之肉眼可見的 或不可見的。在一給定晶圓21 〇上之晶粒區域27〇之數目基 於aa圓2 1 0之尺寸及每一個別晶粒區域27〇之所需尺寸上。 轉到圖2B，顯不的係圖2A之半導體晶圓21〇之一部分之 放大圖。如示，§亥半導體晶圓21〇包含不同材料、層及特 徵之一整體。舉例而言，該半導體晶圓21〇包含一基層 I31320.doc -11 - 200919639 2 12(例如纟f她例中之單晶梦）、—主動特徵層2 μ(例 如，在-實施合J中包含電晶體裝置）及一互連特徵層⑽(例 如，在一實施例中包含一個或多個互連層）。其中，該基 層212、主動特徵層214及互連特徵層216可包括上述材料 之任-者或其整體。同樣，在此製造步驟中，額外層可存 在於該半導體晶圓21 〇中。 如圖2B所示’圖案化的抗蝕劑22〇被形成於該半導體晶 圓210之上方以曝露該半導體晶圓21〇之區域。一類似 於上述之製程可用於圖案化該抗蝕劑22〇。在一實施例 中，該等所曝露之區域23〇位於接近接面 晶粒_目互結旬。在另—實施财，㈣料 230曝路s亥半導體晶圓210中之刻劃道之至少一部分。 在一實施例中，該等所曝露之區域23〇具有一小於約5微 米之寬度（w)。在一替代實施例中，該等所曝露之區域23〇 具有一小於約1微米之寬度（w)。該等前述寬度（W)為明顯 小於一鋸刀片或刻劃工具之寬度，如在過去之以鋸切該半 導體晶圓210為其個別半導體晶粒之可能已使用之寬度。 因此，可節約相當大的半導體晶圓21〇之基板面。 圖2B進一步闡釋一雜質24〇穿過該抗蝕劑22〇中之開口被 引進至該等所曝露之區域230中。其中，利用一類似於上 述之製程，該雜質240可被置放於該半導體内。如上所 述，該雜質240經構形以打斷接近該等接面之在該半導體 日曰圓210中之該等鍵合（其中該等半導體晶粒270相互結 合）。該雜質240可進一步造成該半導體晶圓21〇中之弱化 131320.doc -12- 200919639 區域250。在一實施例中，該等弱化區域之 垂直於-該雜質240被置放之最初表面。這係與= 產生一延伸為大體上平行於該表面之弱化區域之製程之直 接對照。 圖2A與2B之實施例闈釋該抗蝕劑22〇被用於精確置放該 雜質240於該半導體基板21〇内。然而，其他實施例存在， 其中不需要抗蝕劑。舉例而言，一已知實施例存在，其中 使用一直接寫入植入。舉例而言，以一”座標台驅動之一 質子束被用於包含該半導體基板21〇内之雜質24〇。 圖3 A與3B闡釋在移除該半導體晶圓2丨〇之一背側（例如， 6亥雜質240被最初置放之表面之相反表面）之至少一部分 後之圖2A與2B之半導體晶圓21〇。在一實施例中，一常規 的晶圓背研被用於減小該半導體晶圓21〇之厚度至一在約 200微米至約400微米範圍内之數值。在一替代實施例中， 使用一更多或更少之背研。移除該半導體晶圓21〇之背側 之至少一部分之製程被設計為幫助將該半導體晶圓21〇分 離為其個別半導體晶粒。 圖4A與4B闡釋在沿該等弱化區域250分離具有該雜質 240之半導體晶圓21〇為個別半導體晶粒41〇後之圖3A與3B 之半導體晶圓210。如先前所示，分離該半導體晶圓21〇為 其個別晶粒之製程可與應力之增加相關。圖4A與4B之實 施例闡釋利用一滾筒420之所施加之機械應力之使用。當 一滾筒420被用於此實施例以提供該應力時，熟習此項技 術者瞭解各種其他技術及裝置可被使用。應再注意，亦可 131320.doc -13- 200919639 使用熱應力或其他形式的應力（例如，聲應力）。 關於圖】請之上述製程顯示在形成—個或多個特徵於 其中後，特別係在形成該等互連結構後，該雜質被置放於 該半導體晶_。特定實施例可存在，其中該雜質在任何 特徵被形成於其上或其内之前被包含在該半導體晶圓内。 同樣’特定實施例可存在，I中該雜質在形成該等主動特 徵於其上或其内之不久後被包含在該半導體晶圓内。 以上揭*之該等發明的態樣提供優於常規製程之益處。 舉例而言，以上揭示之内容允許更多的矽利用，因為該等 晶粒道（die lanes)可小於在其他鋸及刻劃技術中之所允許 的晶粒道。而且，其可基本上4有一較低之製程成本，因 為與購買及維持常規鑛及劃片工具之成本作比較，以分離 該半導體晶圓為其個別晶粒之植入使用之成本可以係小 的。 關於一雜質之内含物及其它相關資訊之額外詳情可在美 國專利第 6,335,258 號、第 6,020,252 號、第 5,877,070 號、 第6,3 72,609號及美國專利申請案公開第2〇〇4/〇171232號與 第2004/0166649號中找到，其全部以引用的方式併入本文 中’如同其全文以引用的方式併入本文中。 热習以上揭示之此項技術之人士將可瞭解，在不違背本 發明之範圍的情況下，仍可對上述實施例施行其他及進一 步的増添、删減、替代及修飾。 【圖式簡單說明】 為了對本發明之更全面的瞭解，以上之說明可以配合該 131320.doc -14- 200919639 等附圖來閱讀，其中： 圖1闡釋一流程圖，其中顯示一種製造半導體晶粒之方 法之一實施例；及 圖2A-2B闡釋處理步驟，其中顯示一種分離一半導體晶 圓為個別半導體晶粒之方法之一實施例。 【主要元件符號說明】 210 半導體晶圓 212 基層 214 主動特徵層 216 互連特徵層 220 圖案化的抗蝕劑 230 所曝露之區域 240 雜質 250 弱化區域 260 缺口 270 半導體晶粒 410 個別半導體晶粒 420 滾筒 I31320.doc -15-200919639 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention generally relates to a method for separating semiconductor wafers into individual semiconductor dies. [Prior Art] In an integrated circuit configuration, a plurality of integrated circuits (semiconductor dies) are simultaneously formed on a single semiconductor wafer by a series of material deposition and removal processes. The individual semiconductor dies are then separated from the wafer in a process known as a bead cut. Wafer sawing generally includes sawing the wafer with a circular saw blade or by scribing and breaking the wafer (if the wafer is crystallized, the wafers are separated at the semiconductor wafer) These sections are known as slits, or in the semiconductor manufacturing industry, are referred to as scribes or scribe lanes. The scribe lane width is determined by wafer characteristics, blade size and characteristics, marking tool size and characteristics, etc. As will be appreciated by those skilled in the art, it will be appreciated that a conventional scribe lane can have a scribe width of about 62 microns. For a blade of about 3 microns, or a scribe tool width and 62 microns. In terms of scribe width, there is only a 16 micron gap on either side of the blade or scoring tool. However, the semiconductor manufacturing industry is moving towards a narrower scribe (eg '52 micron and τ), Dedicated to achieving higher die yield per wafer. To process a 52 micron scratch width, the blade or scoring tool must be no thicker than 2 microns to maintain the same clearance on either side of the blade. 'However, reduce the thickness of the saw blade or the thickness of the scoring tool to facilitate The narrower slit has practical limitations. Therefore, what is needed in the art is a method for separating a semiconductor wafer from its individual die of 131320.doc 200919639. The method is not limited to the above thickness. To address the shortcomings of the prior art described above, a method for separating a semiconductor wafer into individual semiconductor dies is provided. Among other steps, the method for separating the semiconductor wafer can include implanting an impurity into the semiconductor wafer. In a region where the semiconductor wafer is adjacent to the junction where the semiconductor dies are bonded to each other, the impurity is configured to break the bonding in the semiconductor wafer near the junction and cause a weakened region. The method can further Included in the portion of the opposite surface of the semiconductor wafer that is removed after the impurities are placed into the regions. The method for separating the semiconductor wafer can additionally include separating the Hashes along the weakened regions and the The semiconductor wafer in the removed region is an individual semiconductor die. [Embodiment] The disclosure of the present invention is based, at least in part, on the following recognition: One of the semiconductor wafers can be implanted close to the interface where the semiconductor dies are bonded to each other to help separate the semiconductor wafer into individual semiconductor dies. The disclosure of the present invention further understands that the implanted impurities can be Interrupting the bonding in the semiconductor wafer close to the junctions, causing weakened regions, and the weakened regions separate the semiconductor wafer into individual dies. FIG. 1 illustrates a flow chart 100. An embodiment of a method of fabricating a semiconductor die is shown. In addition to the method of fabricating a semiconductor die, the flow diagram includes a subset comprising a method of separating a semiconductor wafer into individual semiconductor dies. Figure 100 is not intended to limit the disclosure to any particular step. 131320.doc 200919639 The machine % chart 100 begins with - starting step 1〇5. Thereafter, in step 1 (7), the semiconductor wafer is obtained. The semiconductor wafer can comprise a number of different materials. For example, wherein the semiconductor wafer can include a semiconductor, a conductive, or an insulating material used in the field of microelectronics or the like. For example, 3 ' may use a periodic table called a gas conductor such as GaAS, Inp or GaN, an alloy of the (IIIMV) semiconductor of the periodic table, an anthracite stone, a synthetic quartz, and a molten stone. A combination of these materials or materials not listed. \ Mountain This semiconductor wafer can be obtained in many different steps. By way of example, in the embodiment, the semiconductor wafer is a bare semiconductor wafer in which only the temple is taken (e.g., taken directly from the ingot). In the embodiment, the '4 semiconductor wafer includes a plurality of layers' on one of the layers of the insulator, and in the re-real: the 35/j complex layer of the above materials may contain a similar p-spray into the embodiment. The semiconductor wafer may have one or more additional features in the morning or in the presence or absence of one or more functional features (eg, 'active features') or thereafter 'in step m'. A lot of different processing steps. ^= This step 120 can include, by way of example, the step 120 can include on, one or more active features (eg, transistor features, transistor features, etc.) on, within, and over the semiconductor wafer. The second feature, the sensation additionally includes forming an interconnect feature on the semiconductor, and the step 120 can also be performed above the phase (10). An additional resist is characterized by 131320.doc 200919639 on, in or above the semiconductor wafer. However, this step 〇2〇 should not be limited to any single processing step or processing step as a whole. After step 120, in step 13A, the resist can be patterned to expose regions of the semiconductor wafer proximate the junction (where the semiconductor grains are bonded to each other). Those skilled in the art are aware of procedures for patterning anti-surname agents (e.g., photoresists in an embodiment). For example, the process of patterning a resist may begin by applying a layer of resist material to the semiconductor wafer, and then selectively exposing the anti-money agent layer to an energy source, wherein the exposure to the energy source, The properties of portions of the resist layer change. After exposure (exposure), the resist layer can then be formed, for example, by a ''wet development procedure' using a liquid chemical solvent to selectively remove portions of the resist. A desired pattern of one of the anti-buckling agents, which in this embodiment will be exposed to the regions of the semiconductor wafer that are adjacent to the junction, wherein the semiconductor dies are bonded to each other. In another embodiment The anti-study agent will be exposed to at least a portion of the scribe lanes in the semiconductor wafer. In step 140, impurities can be placed in the region of the semiconductor wafer (eg, such an embodiment in the embodiment) In the exposed region), in the embodiment, the inner end (4) is shaped to break the impurity in the semiconductor crystal domain close to the junction; for finally forming the weakened region I: two variations. In other words, in the embodiment, the impurities are one or a rare gas ion. For example, ^AA ^ can be seen as a single or a system, and the mouth and the ion can be #t ^ ^ ^ is 6 hex impurities. However, the scallops include such as rotten ions or Ions or ions of the gentleman's eve from the 廿卞 子 与 与 与 与 与 与 先前 先前 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 然而 131 131 131 131 131 131 131 131 131 131 131 131 Other impurities may be used. The impurities may be placed in the semiconductor wafer using a variety of different procedures. However, in one embodiment, the impurities are placed in the semiconductor using an implant technique. In the wafer, for example, in one embodiment, an implant energy in the range of about 10 keV to about 1000 keV and an implant dose in the range of about 1E12 atoms/cm3 to 1E1 6 atoms/cm3 are utilized. The impurities are implanted into the semiconductor wafer. In another embodiment, the implantation conditions are selected such that the weakened regions extend from the surface of the semiconductor wafer, the implant initially contacting an opposite surface. Nonetheless, other implantation conditions can be used, including the implantation of a resist that is not previously described. Thereafter, in step 150, along the weakened regions, the semiconductor wafer having the impurity therein can be Separated into Individual semiconductor dies. Separating the semiconductor wafer into the individual dies may comprise a number of different steps or a combination of steps. For example, in an embodiment, a semiconductor wafer having a (four) weakened region may be subjected to a Thermal stresses cause the weakened regions to rupture' thus allowing separation of the semiconductor crystallites, wherein the thermal stress can be imparted by annealing a semiconductor wafer having such impurities therein to a suitable temperature. Knowing the appropriate temperature required to break the semiconductor wafer while still within the allocated thermal budget. Likewise, the semiconductor wafer with the weakened regions can undergo a mechanical stress to cause the weakened regions to rupture. The mechanical stress can be imparted by a mechanical device that rolls over the surface of the semiconductor wafer. In an alternate embodiment, both mechanical and thermal stresses are used to aid in the separation of the conductor halves of the semiconductor. After the semiconductor wafer is ruptured into its individual dies, the process can be stopped at stop step 155. The flow chart of Figure 1 includes the steps of a semiconductor die that can be used to fabricate only the embodiments of the present disclosure. In alternative embodiments, fewer steps or additional steps may be used to fabricate semiconductor dies as an alternative embodiment of the present disclosure. In addition, the particular order in which each step of the steps is directed may vary. Thus, for example, in certain embodiments, 'steps 130 and 140 may occur prior to step 12〇. 2A-4B illustrate process steps that illustrate one embodiment of a method of separating a semiconductor wafer into individual semiconductor dies. Figure 2A initially illustrates a semiconductor wafer 210. The wafer shown in Figure 2A includes a notch 26" and one or more die regions 270. As is well known to those skilled in the art, the gap 260 can be used along with the center of the wafer 210 (or another known point) to adjust various features on the wafer 210, including the location of a particular semiconductor feature, Equal grain areas and so on. The one or more die regions 270 represent grain boundaries of different grains on the semiconductor wafer 21 . These grain boundaries may be substantially such that the wafer 210 is sawn as the scribe lanes of its individual semiconductor dies. Moreover, the grain regions 270 can be visible or invisible to the naked eye using a magnifying member. The number of die regions 27 在 on a given wafer 21 基 is based on the size of the aa circle 210 and the desired size of each individual die region 27 。. Turning to Figure 2B, an enlarged view of a portion of the semiconductor wafer 21 of Figure 2A is shown. As shown, §Hai Semiconductor Wafer 21〇 contains one of the different materials, layers and features. For example, the semiconductor wafer 21A includes a base layer I31320.doc -11 - 200919639 2 12 (for example, a single crystal dream in her case), and an active feature layer 2 μ (for example, in the implementation of the joint J) A transistor device is included) and an interconnect feature layer (10) (eg, one or more interconnect layers are included in one embodiment). Wherein, the base layer 212, the active feature layer 214, and the interconnect feature layer 216 can comprise any of the above materials or an entirety thereof. Also, in this fabrication step, an additional layer may be present in the semiconductor wafer 21 . As shown in Fig. 2B, a patterned resist 22 is formed over the semiconductor wafer 210 to expose a region of the semiconductor wafer 21A. A process similar to that described above can be used to pattern the resist 22". In one embodiment, the exposed regions 23 are located near the junction of the die. In another implementation, (4) material 230 is exposed to at least a portion of the scribe lane in the semiconductor wafer 210. In one embodiment, the exposed regions 23A have a width (w) of less than about 5 microns. In an alternate embodiment, the exposed regions 23A have a width (w) of less than about 1 micron. The aforementioned width (W) is significantly less than the width of a saw blade or scoring tool, as has been used in the past to saw the width of the semiconductor wafer 210 for its individual semiconductor dies. Therefore, a substantial surface area of the semiconductor wafer 21 can be saved. Figure 2B further illustrates the introduction of an impurity 24 through the opening in the resist 22 into the exposed regions 230. Wherein, the impurity 240 can be placed in the semiconductor using a process similar to that described above. As described above, the impurities 240 are configured to interrupt the bonding in the semiconductor iridium circle 210 near the junctions (where the semiconductor dies 270 are bonded to each other). The impurity 240 can further cause a weakening of the semiconductor wafer 21 131 131320.doc -12- 200919639 region 250. In one embodiment, the weakened regions are perpendicular to the initial surface on which the impurities 240 are placed. This is in direct contrast to = a process that produces a weakened region that extends substantially parallel to the surface. The embodiment of Figures 2A and 2B demonstrates that the resist 22 is used to accurately place the impurities 240 in the semiconductor substrate 21(R). However, other embodiments exist in which no resist is required. For example, a known embodiment exists in which a direct write implant is used. For example, a proton beam is driven by a "coordinate table" to be used to contain impurities 24 in the semiconductor substrate 21. Figures 3A and 3B illustrate the removal of one side of the semiconductor wafer 2 ( For example, at least a portion of the opposite surface of the surface on which the 6-week impurity 240 is initially placed) is followed by the semiconductor wafer 21 of FIGS. 2A and 2B. In one embodiment, a conventional wafer back-grind is used to reduce The thickness of the semiconductor wafer 21 is up to a value in the range of from about 200 microns to about 400 microns. In an alternate embodiment, a more or less back is used. The semiconductor wafer 21 is removed. At least a portion of the process of the back side is designed to help separate the semiconductor wafer 21 from its individual semiconductor dies. Figures 4A and 4B illustrate the separation of the semiconductor wafer 21 having the impurity 240 along the weakened regions 250. The semiconductor wafer 210 of FIGS. 3A and 3B is followed by individual semiconductor dies 41. As previously indicated, the process of separating the semiconductor wafer 21 into individual dies can be associated with an increase in stress. Implementation of Figures 4A and 4B An example illustrates the application of a roller 420 Use of mechanical stress. When a roller 420 is used in this embodiment to provide this stress, those skilled in the art will appreciate that various other techniques and devices can be used. It should be noted that it can also be used as 131320.doc -13- 200919639 Thermal stress or other forms of stress (for example, acoustic stress). The above process is shown after the formation of one or more features, especially after the formation of the interconnect structure, the impurity is placed In the semiconductor crystal, a particular embodiment may be present in which the impurity is included in the semiconductor wafer before any features are formed thereon or within. Also, a particular embodiment may exist, in which the impurity is formed. The active features are included in the semiconductor wafer shortly thereafter or within. The aspects of the inventions disclosed above provide benefits over conventional processes. For example, the above disclosure allows for more A large number of defects are utilized because the die lanes can be smaller than those allowed in other sawing and scoring techniques. Moreover, they can have a lower process cost. In comparison with the cost of purchasing and maintaining conventional ore and dicing tools, the cost of separating the semiconductor wafer for implantation of individual dies can be small. Additional for inclusion of impurities and other related information The details can be found in U.S. Patent Nos. 6,335,258, 6,020,252, 5,877,070, 6, 3, 72, 609, and U.S. Patent Application Publication Nos. 2, 4, 171, 232, and 2004/0166649, all of which are incorporated herein by reference. The manner in which it is incorporated by reference is hereby incorporated by reference in its entirety in its entirety herein in its entirety in its entirety in its entirety in the the the the the the Examples of other and further additions, deletions, substitutions and modifications. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, the above description can be read in conjunction with the drawings, such as 131320.doc -14-200919639, wherein: Figure 1 illustrates a flow chart showing a fabrication of a semiconductor die One embodiment of the method; and Figures 2A-2B illustrate a processing step in which one embodiment of a method of separating a semiconductor wafer into individual semiconductor dies is shown. [Main component symbol description] 210 semiconductor wafer 212 base layer 214 active feature layer 216 interconnect feature layer 220 patterned resist 230 exposed region 240 impurity 250 weakened region 260 notch 270 semiconductor die 410 individual semiconductor die 420 Roller I31320.doc -15-