200847258 九、發明說明： 【發明所屬之技術領域】 本發明一般係關於半導體元件並特別係關於從半導體晶 圓分離產品及測試晶粒之方法。 【先前技術】 許多微控制器及微處理器包含嵌入式記憶體，比如 ROM。一般而言，嵌入式R〇M生產後則不可能修改其記 憶體。在一次寫入記憶體中，其記憶體只能修改一次。 在本行業中開發嵌入式處理器之軟體應用係標準的。為 了開發並測試即時（或全速）矽軟體，有必要將唯讀記憶體 與從外部可接觸的外合焊墊接合。内部記憶體則獨立並= 由與外合焊墊連接之外部記憶體代替。 現今製造商使用加工矽外合記憶體。然而，該標準方法 要求外合焊墊之供應佔據大量的矽面積，而導致產品成本 明顯增加。製造商已透過吸收成本或製造兩種矽變體解決 此問題，其中-個用於加工目的，其包括外合焊塾及一個 不包括外合焊墊之產品版本。兩種方法皆引起生產成本之 增力口。 因此，需要-種有成本效益的生產半導體晶圓之方法， 該方法可用以達到產品及加工目的。本發明可解決此需 要。 【發明内容】 本文揭示-種利用半導體晶圓之方法及系統。該晶圓包 括複數個半導體晶粒及複數個散布其間的劃線區域。該方 127214.doc 200847258 法及糸、、充^括於劃線區域人 邋騁曰m μ ΛΑ ^形成外a烊墊，以致布置於半 導體日日0上的外合焊墊 旻數個丰導體晶粒之間。該方 法及糸、、充又包括將半導曰 、 體日日^刀離成個別晶粒，以致當半 導體晶粒以第一插古4·、八μ 冰w道 方式刀離時提供至少—個產品晶粒。此 外，當半導體晶圓以筮—、 弟一種方式分離時提供至少一個測試 晶粒。 因此，本發日月之_個優㈣提供能從—半㈣晶圓上提 f200847258 IX. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to semiconductor devices and, more particularly, to methods for separating products from semiconductor wafers and testing dies. [Prior Art] Many microcontrollers and microprocessors contain embedded memory, such as a ROM. In general, it is impossible to modify the memory after the embedded R〇M is produced. In a write-once memory, its memory can only be modified once. The software application standard for developing embedded processors in the industry. In order to develop and test instant (or full speed) software, it is necessary to bond the read-only memory to the externally accessible external pads. The internal memory is independent and = replaced by an external memory connected to the external pad. Today's manufacturers use processed 矽 external memory. However, this standard method requires that the supply of the external solder pads occupy a large amount of germanium, resulting in a significant increase in product cost. Manufacturers have solved this problem by absorbing costs or manufacturing two variants, one for processing purposes, including external soldering and a version of the product that does not include external solder pads. Both methods lead to an increase in production costs. Therefore, there is a need for a cost effective method of producing semiconductor wafers that can be used for product and processing purposes. The present invention addresses this need. SUMMARY OF THE INVENTION [0005] Disclosed herein are methods and systems for utilizing semiconductor wafers. The wafer includes a plurality of semiconductor dies and a plurality of scribe regions interspersed therebetween. The party 127214.doc 200847258 method and 糸,, and the inclusion of the 划线m μ ΛΑ ^ in the scribe area form the outer a 烊 pad, so that the outer bonding pad arranged on the semiconductor day 0 has a number of conductors Between the grains. The method, the 糸, and the charging further comprise separating the semi-conducting 曰 and the body ^ knife into individual dies, so that when the semiconductor dies are separated by the first arranging, the arranging, and at least Product grain. In addition, at least one test die is provided when the semiconductor wafers are separated in a manner that is separate. Therefore, the _ a good (four) of the current day and month provides the ability to extract from the half (four) wafer
^數個產品晶粒或複數個測試晶粒的分離方法。 【實施方式】 本1明般係關於半導體元件並特別係關於從半導體晶 圓分離產品及測試晶粒之方法。在專利申請案之文本中提 供的以下描述使得一般技術者能夠製造並使用本發明，且 文本中犏述之一般原理及特徵便於熟習此項技術者瞭解。 因而本發明用意並非侷限於所示實施例，而是與文本中描 述之原理及特徵相一致的最大範圍符合。 /圖1顯示一半導體晶圓100之俯視圖，其展示了由小正方 7表示的複數個半導體晶粒丨0丨。半導體1之特徵還有外 2塾及測試電路（在後續圖中顯示）。-半導體晶圓100可 私疋為一產品或測試/加工晶圓。如果半導體晶圓被指 、用作產σα，則半導體晶粒隨後被分離成個別半導體晶 粒，其包括破壞性地移除布置在劃線區域内的測試電路及 外口知墊。或者如果半導體晶圓被指定用作測試，則測試 方塊藉由鋸穿鄰近半導體方塊分離而維持測試電路及外合 焊墊之整體性。 127214.doc 200847258 依照一個實施例，術語，’分離”（及該術語之其他動詞時 悲）係私一個將半導體晶圓分割成個別半導體晶粒或方塊 的過权。該術語也可以表示為單一化、劃分或切斷。 一個實施例中，布置於半導體晶圓100上的每個半導體 晶粒101係相同的且各包括記憶體電路用以安全儲存資 料。該實施例中，半導體晶粒101係一個微控制器且其記 憶體電路以唯讀記憶體（R0M)形式提供。代替實施例中， 半導體晶粒1 0 1係一個微處理器。 们貝加例中的半導體晶圓1 0 0透過使用傳統半導體製 造技術加工而於其上形成半導體晶粒101。依照一個實施 例，在半導體晶粒1〇1的製造過程中，也形成測試電路及 外合焊墊。 如先前陳述之内容，一半導體晶圓可指定為一產品或測 試/加工晶圓。如果半導體晶圓被指定用作產品，則半導 體晶粒隨後被分離成個別半導體晶粒，其包括破壞性地移 除測試電路及布置在劃線區域内的外合焊墊。 圖2顯示個當半導體晶圓被指定用作產品時的3Χ3半導 體晶粒塊之範例佈局圖。一般技術者應瞭解此佈局圖並不 局限於一個3X3半導體晶粒塊並應瞭解一個半導體晶粒塊 可於其上合併或多或少的半導體方塊。在半導體晶圓被指 定用作產品的實施例中，該半導體晶圓被分離成個別半導 體方塊201將半導體晶圓分離成個別半導體方塊2〇 1可透 過使用鋸切技術、雷射磨損、金剛石劃線或附加晶圓處理 技術，比如選擇性化學蝕刻而實現。一個實施例中使用鋸 127214.doc 200847258 切技術將半導體晶圓分離成個別半導體方塊以生成產品。 使用鋸切技術之實施例中，第一鋸切過程沿著劃線區域 209的一組劃線203進行。實施例中劃線區域2〇9之寬度大 約為70微米。換句話而言，布置於半導體晶圓上的鄰近半 導體晶粒之間的間距至少係70微米。在第一鋸切過程中， 使用一寬度小於劃線區域209之寬度的鋸條以切割一淺薄 深度而足夠切割進半導體晶圓表層内，而不是深至完全切 穿該半導體晶圓。實施例中此錯切過程破壞性地移除書彳線 區域209内的測試電路及外合焊墊202。 其次，依照一個實施例，半導體晶圓要經受第二鋸切過 程，以致第二次切割沿著劃線區域2〇9内第一次切割的路 線進行。一個實施例中使用一狹窄寬度的鋸條以完全切穿 半導體晶圓。第二鋸切過程從而將晶圓完全切斷並分離成 個別半導體方塊，該過程增強抵制未經授權之存取的安全 性。 應瞭解由於測試電路及外合焊墊202皆從其各自元件晶 粒被移除，此時該元件之進一步測試係極不可能的。此外 還應瞭解由於測試電路及外合焊墊2〇2在其移除過程中被 破壞，其視覺檢測及逆向工程幾乎不可能實現，此外還增 強了此等元件抵制駭客存取之安全性。也應瞭解測試電路 及外合焊墊之任何殘留片段現不能用以探測電活動或此等 元件之特徵，因為此等不起作用的測試電路及外合焊墊之 片段在缺乏來自曾存在但現已被破壞的測試電路的啟動信 號時被放棄或保持隔離。 127214.doc 200847258 應瞭解雖然在以上描述的實施例中，測試電路及外合焊 墊形式的部件被破壞性地移除以增強完成元件之安全性， 但完成元件之安全性或者另外又可透過其他部件之破壞性 的移除而增強，比如擴充式測試模式電路或用以解拌元件 匯流排、中央處理器或記憶體（另外已攪拌）之存取的電 路。^ Separation of several product grains or a plurality of test grains. [Embodiment] This is a general description of a semiconductor device and, in particular, a method for separating a product from a semiconductor wafer and testing a crystal grain. The following description is provided to enable a person skilled in the art to make and use the invention, and the general principles and features described in the text are readily apparent to those skilled in the art. Therefore, the invention is not intended to be limited to the illustrated embodiments, but rather to the maximum extents consistent with the principles and features described in the text. / Figure 1 shows a top view of a semiconductor wafer 100 showing a plurality of semiconductor dies 丨 丨 由 represented by a small square 7. Semiconductor 1 is also characterized by an external circuit and a test circuit (shown in the subsequent figures). - The semiconductor wafer 100 can be a product or a test/process wafer. If a semiconductor wafer is referred to as producing σα, the semiconductor dies are subsequently separated into individual semiconductor granules, which include destructively removing test circuitry and external shims disposed within the scribe region. Or if the semiconductor wafer is designated for testing, the test block maintains the integrity of the test circuit and the external pad by sawing through adjacent semiconductor blocks. 127214.doc 200847258 According to one embodiment, the term 'separation' (and other verbs of the term) is a privilege of dividing a semiconductor wafer into individual semiconductor dies or blocks. The term can also be expressed as a single. In one embodiment, each of the semiconductor dies 101 disposed on the semiconductor wafer 100 is identical and each includes a memory circuit for safely storing data. In this embodiment, the semiconductor die 101 A microcontroller is provided and its memory circuit is provided in the form of a read-only memory (ROM). In the alternative embodiment, the semiconductor die 110 is a microprocessor. The semiconductor wafer in the case of the Beiga is 1 0 0 The semiconductor die 101 is formed thereon by processing using conventional semiconductor fabrication techniques. According to one embodiment, the test circuit and the external bond pad are also formed during the fabrication of the semiconductor die 101. As previously stated, A semiconductor wafer can be designated as a product or test/process wafer. If a semiconductor wafer is designated for use as a product, the semiconductor die is subsequently separated into individual semiconductors. The die includes destructive removal of the test circuit and the outer pad disposed within the scribe region. Figure 2 shows an example layout of a 3 Χ 3 semiconductor die when the semiconductor wafer is designated for use as a product. One of ordinary skill in the art will appreciate that the layout is not limited to a 3X3 semiconductor die and that a semiconductor die can be combined with more or less semiconductor blocks. The semiconductor wafer is designated for implementation as a product. In an example, the semiconductor wafer is separated into individual semiconductor blocks 201 to separate the semiconductor wafer into individual semiconductor blocks. 〇1 can be achieved by using sawing techniques, laser wear, diamond scribing, or additional wafer processing techniques, such as selectivity. Chemical etching is achieved. In one embodiment, the semiconductor wafer is separated into individual semiconductor blocks using a saw 127214.doc 200847258 dicing technique to create a product. In an embodiment using a sawing technique, the first sawing process is along a scribe region 209. The set of scribe lines 203 is performed. In the embodiment, the scribe line region 2 〇 9 has a width of about 70 μm. In other words, the neighbors arranged on the semiconductor wafer The spacing between the semiconductor dies is at least 70 microns. During the first sawing process, a saw blade having a width smaller than the width of the scribe region 209 is used to cut a shallow depth enough to be cut into the surface of the semiconductor wafer instead of The semiconductor wafer is deeply cut through. In this embodiment, the miscut process destructively removes the test circuitry and the outer pads 202 in the bookwire region 209. Second, in accordance with one embodiment, the semiconductor wafer is subjected to The second sawing process is such that the second cut is performed along the first cut route in the scribe line region 2 。 9. In one embodiment, a narrow width saw blade is used to completely cut through the semiconductor wafer. The process thus completely severes and separates the wafer into individual semiconductor blocks, a process that enhances the security against unauthorized access. It will be appreciated that since both the test circuit and the outer pad 202 are removed from their respective component crystals, further testing of the component is highly unlikely. In addition, it should be understood that since the test circuit and the external bonding pad 2〇2 are destroyed during the removal process, visual inspection and reverse engineering are almost impossible to realize, and the safety of these components to resist hacker access is enhanced. . It should also be understood that any residual fragments of the test circuit and the external solder pads are not currently available for detecting electrical activity or characteristics of such components, as such inoperative test circuits and fragments of external pads are present in the absence of The start signal of the test circuit that has been destroyed is abandoned or remains isolated. 127214.doc 200847258 It should be understood that although in the embodiments described above, the components in the form of test circuits and external pads are destructively removed to enhance the safety of the completed components, the safety of the completed components is otherwise permeable. Enhancements are caused by destructive removal of other components, such as extended test mode circuits or circuits for unwinding access to component busses, central processing units, or memory (other stirred).
一個實施例中，半導體晶圓可被指定用作測試或仿真。 圖3顯示一 3X3半導體晶粒塊31〇、鄰近測試/仿真晶粒3〇4 之半導體方塊301上投射的鋸切線305及相應外合焊墊3〇2 之放大區域圖。一個實施例中被指定用作測試或仿真之半 導體晶圓要經受一個分離過程，該過程相關於以上描述之 用以分離布置於產品晶圓上的晶粒之分離過程。 一個實施例中當半導體晶圓被指定用作測試或仿真晶圓 時，一後續分離過程與以下描述相一致··第一鋸切過程係 沿著投射於半導體方塊3〇 1上的鋸切線3〇5切割至一預先確 定的深度而進行，以致凹槽切割於鄰近的半導體方塊3〇ι 中；第二鋸切過程係沿著由第一鋸切過程形成的凹槽而進 行，以致鄰近的半導體方塊301被切割成兩半、四份或半 導體方塊301原始大小的任何分數。 圖4顯示一已鋸半導體晶圓結構411 其特徵為一個有相 應外合焊墊4〇2、 的仿真/測試晶粒404。 母半導體晶圓上分離， 構整體性保持完整。圖 測試電路413及鄰近已鋸半導體方塊412 如圖所示，仿真/測試晶粒4〇4從其 而外合焊墊402及測試電路413之結 4又顯示鋸齒邊緣414，該鋸齒邊緣 127214.doc 200847258 意味了前述鑛切滿@ . 、 砍骑刀過私。一個實施例中，“鋸齒邊緣，，被定義 為任何不平坦表面。與 舉例而言，鄰近已鋸半導體方塊412 有由於上述鋸割方法形成的鋸齒邊緣。 還應瞭解製造外合焊塾可使靜電損害（esd)達到最小 、又而口 ESD係由半導體元件内互連中的電荷累積 引起的。電荷通常在製程中的半導體元件内引發，這些製 :例如但不局限於化學機械拋光、層間電介質蝕刻及電漿 沉積或#刻。-個實施例中，細保護可透過在汲極區形 成矽化物層及在外合焊墊元件内嵌入天線二極體而實 現。 、 一般而言，元件按照慣例生產有ESD保護而適用於人為 操作（大約6kV)或機械模型（大約2〇〇v)。這對於保護/生產 原係必要的。畫j線焊墊應肖+，劃線區域内用以放置焊 墊、緩衝電路及ESD保護電路的可利用空間係有限的。被 指定用作仿真的半導體晶圓巾，劃線區域内ESD保護電路 的大】可減小以谷許焊墊及補充電路（緩衝電路及esd保護 電路）有更大空間。一個實施例中，ESD保護電路可低於生 產元件可接文的水準。然而，實施例中ESD保護的減少對 於仿真（測試晶粒）較不重要，因為相對於生產晶粒的大體 積而言’用於測試的晶粒的體積很小。 各種實施例中，ESD保護電路可布置在鄰近於外合焊墊 或在外合焊墊下方的位置，以致提供ESD保護。 雖然本發明已依照所示實施例進行描述，一般技術者應 欣然認可實施例可有變更且此等變更在本發明之精神與範 127214.doc -11- 200847258 圍之内。因此，一般技術者可在未脫離附加請求項之精才 與範圍的情況下做出許多修改。 月子 【圖式簡單說明】 本發明以範例方式闡明並不侷限於所附圖式中的圖幵）， 圖中相似苓考號碼表示類似構件且在所附圖式中： 圖1顯示一半導體晶圓之俯視圖，其特徵為藉由小正方 形表示的複數個半導體晶粒。 Θ ,、、、員示半導體晶圓上一 3X3半導體晶粒塊及劃線區域之 外合焊墊電路的放大區域圖。 圖3顯示一 3X3半導體晶粒塊、鄰近測試/仿真晶粒之半 導體方塊上的鋸切線及相應外合焊墊之放大區域圖。 圖4顯示一已鋸半導體晶圓結構，其特徵為一個有相應 外合焊墊、測試電路及鄰近已鋸半導體方塊的仿真/測試 晶粒。 【主要元件符號說明】 100 半導體晶圓 101 半導體晶粒 201 個別半導體方塊 202 外合焊墊 203 劃線 209 劃線區域 210 半導體晶粒塊 301 半導體方塊 302 外合焊墊 127214.doc -12- 200847258 304 仿真/測試晶粒 305 鋸切線 310 半導體晶粒塊 402 外合焊墊 404 仿真/測試晶粒 411 已鋸半導體晶圓結構 412 鄰近已鋸半導體方塊 413 測試電路 414 鋸齒邊緣 127214.doc -13-In one embodiment, the semiconductor wafer can be designated for testing or simulation. 3 shows an enlarged area view of a 3X3 semiconductor die block 31A, a sawing line 305 projected on a semiconductor block 301 adjacent to the test/simulation die 3〇4, and a corresponding external bond pad 3〇2. A semiconductor wafer designated for testing or simulation in one embodiment is subjected to a separation process associated with the separation process described above for separating the crystal grains disposed on the product wafer. In one embodiment, when a semiconductor wafer is designated for testing or simulating a wafer, a subsequent separation process is consistent with the following description. The first sawing process is along a sawing line 3 projected onto the semiconductor block 3〇1. 〇5 is cut to a predetermined depth so that the grooves are cut into adjacent semiconductor blocks 3〇; the second sawing process is performed along the grooves formed by the first sawing process so that adjacent The semiconductor block 301 is cut into two, four, or any fraction of the original size of the semiconductor block 301. Figure 4 shows a sawed semiconductor wafer structure 411 characterized by a dummy/test die 404 having corresponding outer pads 4〇2. The mother semiconductor wafer is separated and the integrity of the structure remains intact. The graph test circuit 413 and the adjacent saw semiconductor block 412, as shown, the dummy/test die 4〇4 from which the junction 402 and the test circuit 413 junction 4 again show a sawtooth edge 414, the sawtooth edge 127214. Doc 200847258 means that the aforementioned mine is cut to full @. In one embodiment, the "sawed edge" is defined as any uneven surface. For example, adjacent sawed semiconductor block 412 has a sawtooth edge formed by the above sawing method. It should also be understood that the manufacture of an external soldered joint can Electrostatic damage (esd) is minimized, and the ESD is caused by charge accumulation in interconnects within the semiconductor component. Charges are typically induced in semiconductor components in the process: for example, but not limited to, chemical mechanical polishing, interlayer Dielectric etching and plasma deposition or etching. In one embodiment, the fine protection can be achieved by forming a germanide layer in the drain region and embedding the antenna diode in the outer pad component. In general, the component is Conventional production with ESD protection is suitable for human operation (approx. 6kV) or mechanical model (approx. 2〇〇v). This is necessary for protection/production of the original system. The drawing j-line pad should be used in the scribe area. The available space for placing pads, snubber circuits, and ESD protection circuits is limited. The semiconductor wafers designated for simulation, the large ESD protection circuit in the scribe area can be reduced There is more room for the solder pads and supplemental circuits (buffer circuits and esd protection circuits). In one embodiment, the ESD protection circuit can be lower than the level of the production component. However, the reduction of ESD protection in the embodiment is for simulation. (Testing the die) is less important because the volume of the die used for testing is small relative to the large volume of the produced die. In various embodiments, the ESD protection circuit can be placed adjacent to the external pad or The position below the outer pad is such that ESD protection is provided. While the invention has been described in terms of the illustrated embodiments, those of ordinary skill in the art will readily appreciate that the embodiments can be modified and such changes are in the spirit and scope of the invention. -11- 200847258 is within the scope of the invention. Therefore, the general practitioner can make many modifications without departing from the scope and scope of the appended claims. Months [Simplified description of the drawings] The present invention is exemplified by examples and is not limited. In the drawings, like reference numerals indicate similar components and are in the drawings: Figure 1 shows a top view of a semiconductor wafer, characterized by small A plurality of semiconductor dies represented by squares. Θ , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The sawing line on the semiconductor block adjacent to the test/simulation die and the enlarged area of the corresponding external pad. Figure 4 shows a sawed semiconductor wafer structure characterized by a corresponding external pad, test circuit and Simulation/test die adjacent to the sawed semiconductor block. [Main component symbol description] 100 semiconductor wafer 101 semiconductor die 201 individual semiconductor block 202 external bond pad 203 scribe line 209 scribe region 210 semiconductor die block 301 semiconductor block 302 External solder pad 127214.doc -12- 200847258 304 Simulation / test die 305 sawing line 310 semiconductor die block 402 external bond pad 404 simulation / test die 411 sawed semiconductor wafer structure 412 adjacent sawed semiconductor block 413 Test Circuit 414 Serrated Edge 127214.doc -13-