US20090278124A1 - Scribe based bond pads for integrated circuits - Google Patents

Scribe based bond pads for integrated circuits Download PDF

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Publication number
US20090278124A1
US20090278124A1 US12/506,136 US50613609A US2009278124A1 US 20090278124 A1 US20090278124 A1 US 20090278124A1 US 50613609 A US50613609 A US 50613609A US 2009278124 A1 US2009278124 A1 US 2009278124A1
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Prior art keywords
semiconductor
sawn
die
semiconductor die
disposed
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US12/506,136
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Andrew Burnside
Albert Dye
Hugh Dick
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Atmel Corp
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Atmel Corp
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Priority to US12/506,136 priority Critical patent/US20090278124A1/en
Publication of US20090278124A1 publication Critical patent/US20090278124A1/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BURNSIDE, ANDREW, DICK, HUGH, DYE, ALBERT
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer.
  • microcontrollers and microprocessors contain embedded memories such as ROM. Typically, it is not possible to modify the memory of embedded ROM after manufacture. In the case of Write Once Memory, it is only possible to modify the memory once.
  • a method and system for utilizing a semiconductor wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between.
  • the method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die.
  • the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.
  • An apparatus including a semiconductor substrate is disclosed.
  • a first semiconductor die is disposed on the semiconductor substrate.
  • a first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die.
  • a first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.
  • FIG. 1 shows a top version of a semiconductor wafer which features a plurality of semiconductor die, represented by small squares.
  • FIG. 2 shows a magnified area of a 3 ⁇ 3 semiconductor die cluster and bond out pad circuitry in a scribe area on a semiconductor wafer.
  • FIG. 3 shows a magnified area of a 3 ⁇ 3 semiconductor die cluster, saw lines on semiconductor dice adjacent to a test/emulation die, and corresponding bond out pads.
  • FIG. 4 shows a sawn semiconductor wafer structure featuring an emulation/test die with corresponding bond out pads, test circuitry, and adjacent, sawn-semiconductor dice.
  • the present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer.
  • the following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and the generic principles and features described herein will be readily apparent to those skilled in the art.
  • the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • FIG. 1 shows a top view of a semiconductor wafer 100 that features a plurality of semiconductor die 101 , denoted by small squares.
  • Semiconductor 100 also features bond out pads and test circuitry (shown in subsequent figures).
  • a semiconductor wafer 100 may be designated as a product or test/development wafer. In the event semiconductor wafer 100 is designated for product, the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe area. Alternatively, in the event that a semiconductor wafer is designated for testing, test dice are separated by sawing through adjacent semiconductor dice while maintaining the integrity of the test circuitry and bond out pads.
  • the term “separating” refers to a process of partitioning a semiconductor wafer into individual, semiconductor die or dice.
  • the term may also be referred to as singulating, dividing, or severing.
  • each semiconductor die 101 disposed on semiconductor wafer 100 are identical and each contain memory circuitry for storing data securely.
  • semiconductor die 101 is a microcontroller and the memory circuit is provided in the form of read-only memory (ROM).
  • ROM read-only memory
  • semiconductor die 101 is a microprocessor.
  • semiconductor wafer 100 is processed using conventional semiconductor fabrication techniques to form semiconductor die 101 thereon.
  • test circuitry and bond out pads are also formed, according to an embodiment.
  • a semiconductor wafer may be designated as a product or test/development wafer.
  • the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe areas.
  • FIG. 2 shows an example layout of a 3.times.3 semiconductor die cluster 210 when a semiconductor wafer is designated for product.
  • this layout is not limited to a 3.times.3 semiconductor die cluster and that a semiconductor die cluster may incorporate more or less semiconductor dice thereon.
  • the semiconductor wafer is separated into individual semiconductor dice 201 . Separating a semiconductor wafer into individual semiconductor dice 201 may be achieved by use of a sawing technique, laser obliteration, diamond scribe or additional wafer processing techniques such as selective chemical etching.
  • a sawing technique is used to separate a semiconductor wafer into individual semiconductor dice for product.
  • a first sawing procedure is made along a set of scribe lines 203 in scribe area 209 .
  • scribe area 209 has a width of approximately 70 microns. In other words, the space between adjacent semiconductor die disposed on a semiconductor wafer is at least approximately 70 microns.
  • a saw blade having a width less than the width of scribe area 209 is used to cut a shallow depth sufficient to cut into the surface of a semiconductor wafer, but not so deep as to cut completely through the semiconductor wafer. For the embodiment, this sawing procedure destructively removes the test circuitry and bond out pads 202 in scribe area 209 .
  • a semiconductor wafer is subjected to a second sawing procedure such that a second cut is made along the path made by the first saw cut within scribe area 209 .
  • a saw blade having a narrow width is used to cut completely through the semiconductor wafer. The second sawing procedure thus completely severs and separates the wafer into individual semiconductor dice, which provides enhancing security against unauthorized access.
  • test circuitry and bond out pads 202 have been removed from their respective device dies, at this point no further testing of the device is ordinarily possible. It will be further appreciated that since the test circuitry and bond out pads 202 are destroyed in their removal, their visual inspection or reverse engineering is made practically impossible, further enhancing security of the devices against access by a hacker. It will also be appreciated that any remaining fragments of test circuitry and bond out pads cannot now be used to probe electrical activity or features of the devices since these fragments of inoperable test circuitry and bond out pads are rendered and remain isolated in the absence of the enabling signals from the test circuitry which was present but which has now been destroyed.
  • test circuitry and bond out pads are destructively removed to enhance the security of the finished device
  • security of the finished device could be alternatively or additionally enhanced by the destructive removal of other features such as expanded test mode circuitry or circuitry for unscrambling (otherwise scrambled) access to the devices' bus, central processing unit or memory.
  • a semiconductor wafer may be designated for testing or emulation.
  • FIG. 3 shows a magnified area of a 3 ⁇ 3 semiconductor die cluster 310 , saw lines 305 projected on semiconductor dice 301 adjacent to a test/emulation die 304 , and corresponding bond out pads 302 .
  • a semiconductor wafer designated for test or emulation undergoes a separation process relative to the separation process used to separate die disposed on product wafers, as described above.
  • a subsequent separation procedure is in accordance with the following: a first sawing procedure along saw lines 305 projected on semiconductor dice 301 to a pre-determined depth such that grooves are cut in adjacent semiconductor dice 301 ; a second sawing procedure along the grooves formed by the first sawing procedure such that the adjacent semiconductor dice 301 are severed in halves, fourths, or any fraction of the original size of semiconductor dice 301 .
  • FIG. 4 shows a sawn-semiconductor wafer structure 411 featuring an emulation/test die 404 with corresponding bond out pads 402 , test circuitry 413 , and adjacent, sawn-semiconductor dice 412 .
  • emulation/test die 404 is separated from its parent semiconductor wafer, while the structural integrity of bond out pads 402 and test circuitry 413 remain intact.
  • FIG. 4 shows a jagged edge 414 , which signifies the aforementioned sawing procedure.
  • a “jagged edge” is defined as any uneven surface.
  • adjacent, sawn-semiconductor dice 412 may have jagged edges due to the saw-cutting method described above.
  • the bond out pads may be manufactured such that electrostatic damage (ESD) is minimized.
  • ESD electrostatic damage
  • ESD is typically caused by charge build-up in interconnects within semiconductor devices.
  • charges are introduced within semiconductor devices during fabrication processes, such as, but not limited to chemical mechanical polishing, interlayer dielectric etch, and plasma deposition or etch.
  • ESD protection may be achieved by forming a salicide layer on drain regions and embedding antenna diodes within the bond out pad device.
  • ESD protection circuitry For the scribe bond pad application, there is limited available space in the scribe area for placement of bond pads, buffer circuit, and ESD protection circuitry. For semiconductor wafers that have been designated for emulation, the size of ESD protection circuitry can be reduced to allow more space for bond pads and complementary circuitry (buffer and ESD protection circuitry) within the scribe area. For an embodiment, the ESD protection circuitry may be lowered below a level that is acceptable for production devices. However, for embodiments, a reduction in ESD protection is a less critical for emulation (test die) as the volumes of die for testing is small relative to the large volume of production die.
  • ESD protection circuitry may be disposed adjacent to or under the bond out pads such that ESD protection is provided.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.

Description

    RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 11/607,564, filed on Dec. 1, 2006, which is incorporated herein by reference in its entirety.
    • FIELD OF THE INVENTION
  • The present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer.
    • BACKGROUND OF THE INVENTION
  • Many microcontrollers and microprocessors contain embedded memories such as ROM. Typically, it is not possible to modify the memory of embedded ROM after manufacture. In the case of Write Once Memory, it is only possible to modify the memory once.
  • It is standard in the industry to develop software applications for embedded processors. In order to develop and test software on real-time (or full speed) silicon it is necessary to bond out the read only memory on externally accessible bond out pads. The internal memory is isolated and replaced by external memory connected to the bond out pads.
  • Currently, manufacturers use bond out memory in development silicon. However, the standard approach requires that the provision of bond out pads occupy a significant amount of silicon area, resulting in a significant increase in product cost. Manufacturers have addressed this issue by either absorbing the costs or by manufacturing two variants of silicon, one for development purposes that includes bond out pads and a production version that does not include bond out pads. Both approaches lead to an increase cost of production.
  • Accordingly, what is desired is a cost-efficient method of manufacturing semiconductor wafers that can be used for both product and development purposes. The present invention addresses this need.
    • BRIEF SUMMARY OF THE INVENTION
  • A method and system for utilizing a semiconductor wafer is disclosed. The wafer comprises a plurality of semiconductor die and a plurality of scribe areas interspersed between. The method and system comprises forming bond out pads in the scribe areas such that the bond out pads are disposed on the semiconductor wafer between the plurality of semiconductor die. Additionally, the method and system comprises separating the semiconductor wafer into individual die such that when the semiconductor wafer is separated in a first manner at least one product die is provided. Furthermore, when the semiconductor wafer is separated in a second manner at least one test die is provided.
  • An apparatus including a semiconductor substrate is disclosed. A first semiconductor die is disposed on the semiconductor substrate. A first bond out pad is disposed on the semiconductor substrate adjacent to the first semiconductor die. A first sawn semiconductor die is disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.
  • Accordingly, it is an advantage of the present invention to provide separation methods that provide either a plurality of product die or a plurality of test die from a semiconductor wafer.
    • BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
  • The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which:
  • FIG. 1 shows a top version of a semiconductor wafer which features a plurality of semiconductor die, represented by small squares.
  • FIG. 2 shows a magnified area of a 3×3 semiconductor die cluster and bond out pad circuitry in a scribe area on a semiconductor wafer.
  • FIG. 3 shows a magnified area of a 3×3 semiconductor die cluster, saw lines on semiconductor dice adjacent to a test/emulation die, and corresponding bond out pads.
  • FIG. 4 shows a sawn semiconductor wafer structure featuring an emulation/test die with corresponding bond out pads, test circuitry, and adjacent, sawn-semiconductor dice.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • The present invention relates generally to semiconductor devices and specifically to a method of separating product and test die from a semiconductor wafer. The following description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and the generic principles and features described herein will be readily apparent to those skilled in the art. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features described herein.
  • FIG. 1 shows a top view of a semiconductor wafer 100 that features a plurality of semiconductor die 101, denoted by small squares. Semiconductor 100 also features bond out pads and test circuitry (shown in subsequent figures). A semiconductor wafer 100 may be designated as a product or test/development wafer. In the event semiconductor wafer 100 is designated for product, the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe area. Alternatively, in the event that a semiconductor wafer is designated for testing, test dice are separated by sawing through adjacent semiconductor dice while maintaining the integrity of the test circuitry and bond out pads.
  • According to an embodiment, the term “separating” (and other verb tenses of the term) refers to a process of partitioning a semiconductor wafer into individual, semiconductor die or dice. The term may also be referred to as singulating, dividing, or severing.
  • For an embodiment, each semiconductor die 101 disposed on semiconductor wafer 100 are identical and each contain memory circuitry for storing data securely. For the embodiment, semiconductor die 101 is a microcontroller and the memory circuit is provided in the form of read-only memory (ROM). For alternative embodiments, semiconductor die 101 is a microprocessor.
  • For an embodiment, semiconductor wafer 100 is processed using conventional semiconductor fabrication techniques to form semiconductor die 101 thereon. During the fabrication of semiconductor die 101, test circuitry and bond out pads are also formed, according to an embodiment.
  • As stated previously, a semiconductor wafer may be designated as a product or test/development wafer. In the event a semiconductor wafer is designated for product, the semiconductor die is subsequently separated into individual semiconductor die, which includes destructively removing the test circuitry and bond out pads disposed in the scribe areas.
  • FIG. 2 shows an example layout of a 3.times.3 semiconductor die cluster 210 when a semiconductor wafer is designated for product. Those having ordinary skill in the art will appreciate that this layout is not limited to a 3.times.3 semiconductor die cluster and that a semiconductor die cluster may incorporate more or less semiconductor dice thereon. For the embodiment when a semiconductor wafer is designated for product, the semiconductor wafer is separated into individual semiconductor dice 201. Separating a semiconductor wafer into individual semiconductor dice 201 may be achieved by use of a sawing technique, laser obliteration, diamond scribe or additional wafer processing techniques such as selective chemical etching. For an embodiment, a sawing technique is used to separate a semiconductor wafer into individual semiconductor dice for product.
  • For the embodiment when a sawing technique is used, a first sawing procedure is made along a set of scribe lines 203 in scribe area 209. For embodiments, scribe area 209 has a width of approximately 70 microns. In other words, the space between adjacent semiconductor die disposed on a semiconductor wafer is at least approximately 70 microns. In the first sawing procedure, a saw blade having a width less than the width of scribe area 209 is used to cut a shallow depth sufficient to cut into the surface of a semiconductor wafer, but not so deep as to cut completely through the semiconductor wafer. For the embodiment, this sawing procedure destructively removes the test circuitry and bond out pads 202 in scribe area 209.
  • Next, according to an embodiment, a semiconductor wafer is subjected to a second sawing procedure such that a second cut is made along the path made by the first saw cut within scribe area 209. For an embodiment, a saw blade having a narrow width is used to cut completely through the semiconductor wafer. The second sawing procedure thus completely severs and separates the wafer into individual semiconductor dice, which provides enhancing security against unauthorized access.
  • It will be appreciated that since the test circuitry and bond out pads 202 have been removed from their respective device dies, at this point no further testing of the device is ordinarily possible. It will be further appreciated that since the test circuitry and bond out pads 202 are destroyed in their removal, their visual inspection or reverse engineering is made practically impossible, further enhancing security of the devices against access by a hacker. It will also be appreciated that any remaining fragments of test circuitry and bond out pads cannot now be used to probe electrical activity or features of the devices since these fragments of inoperable test circuitry and bond out pads are rendered and remain isolated in the absence of the enabling signals from the test circuitry which was present but which has now been destroyed.
  • It will be appreciated that although in the above described embodiment features in the form of test circuitry and bond out pads are destructively removed to enhance the security of the finished device, the security of the finished device could be alternatively or additionally enhanced by the destructive removal of other features such as expanded test mode circuitry or circuitry for unscrambling (otherwise scrambled) access to the devices' bus, central processing unit or memory.
  • For an embodiment, a semiconductor wafer may be designated for testing or emulation. FIG. 3 shows a magnified area of a 3×3 semiconductor die cluster 310, saw lines 305 projected on semiconductor dice 301 adjacent to a test/emulation die 304, and corresponding bond out pads 302. For an embodiment, a semiconductor wafer designated for test or emulation undergoes a separation process relative to the separation process used to separate die disposed on product wafers, as described above.
  • For an embodiment when a semiconductor wafer is designated a test or emulation wafer, a subsequent separation procedure is in accordance with the following: a first sawing procedure along saw lines 305 projected on semiconductor dice 301 to a pre-determined depth such that grooves are cut in adjacent semiconductor dice 301; a second sawing procedure along the grooves formed by the first sawing procedure such that the adjacent semiconductor dice 301 are severed in halves, fourths, or any fraction of the original size of semiconductor dice 301.
  • FIG. 4 shows a sawn-semiconductor wafer structure 411 featuring an emulation/test die 404 with corresponding bond out pads 402, test circuitry 413, and adjacent, sawn-semiconductor dice 412. As shown, emulation/test die 404 is separated from its parent semiconductor wafer, while the structural integrity of bond out pads 402 and test circuitry 413 remain intact. Additionally, FIG. 4 shows a jagged edge 414, which signifies the aforementioned sawing procedure. For an embodiment, a “jagged edge” is defined as any uneven surface. For example, adjacent, sawn-semiconductor dice 412 may have jagged edges due to the saw-cutting method described above.
  • It will be further appreciated that the bond out pads may be manufactured such that electrostatic damage (ESD) is minimized. ESD is typically caused by charge build-up in interconnects within semiconductor devices. Often, charges are introduced within semiconductor devices during fabrication processes, such as, but not limited to chemical mechanical polishing, interlayer dielectric etch, and plasma deposition or etch. For an embodiment, ESD protection may be achieved by forming a salicide layer on drain regions and embedding antenna diodes within the bond out pad device.
  • Typically, devices are conventionally manufactured with ESD protection for human handling (approximately 6 kV), or machine model (approximately 200V). This is necessary for protection/yield reason. For the scribe bond pad application, there is limited available space in the scribe area for placement of bond pads, buffer circuit, and ESD protection circuitry. For semiconductor wafers that have been designated for emulation, the size of ESD protection circuitry can be reduced to allow more space for bond pads and complementary circuitry (buffer and ESD protection circuitry) within the scribe area. For an embodiment, the ESD protection circuitry may be lowered below a level that is acceptable for production devices. However, for embodiments, a reduction in ESD protection is a less critical for emulation (test die) as the volumes of die for testing is small relative to the large volume of production die.
  • For various embodiments, ESD protection circuitry may be disposed adjacent to or under the bond out pads such that ESD protection is provided.
  • Although the present invention has been described in accordance with the embodiments shown, one of ordinary skill in the art will readily recognize that there could be variations to the embodiments and those variations would be within the spirit and scope of the present invention. Accordingly, many modifications may be made by one of ordinary skill in the art without departing from the spirit and scope of the appended claims.

Claims (20)

1. An apparatus comprising:
a semiconductor substrate;
a first semiconductor die disposed on the semiconductor substrate;
a first bond out pad disposed on the semiconductor substrate adjacent to the first semiconductor die; and
a first sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die and the first bond out pad.
2. The apparatus of claim 1, wherein the first semiconductor die includes a test die.
3. The apparatus of claim 1, wherein the first semiconductor die includes an emulation die.
4. The apparatus of claim 1, wherein the bond out pad is disposed between the first semiconductor die and the first sawn semiconductor die.
5. The apparatus of claim 1, wherein the first bond out pad is disposed along a first scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate.
6. The apparatus of claim 1, comprising a second sawn semiconductor die disposed on the semiconductor substrate adjacent to the first semiconductor die.
7. The apparatus of claim 6, comprising a second bond out pad disposed on the semiconductor substrate between the first semiconductor die and the second sawn semiconductor die.
8. The apparatus of claim 6, wherein the second bond out pad is disposed along a second scribe line of the semiconductor substrate and completely within a scribe area of the semiconductor substrate.
9. The apparatus of claim 1, comprising test circuitry disposed on the semiconductor substrate outside the first semiconductor die.
10. The apparatus of claim 1, wherein the first semiconductor die includes a microprocessor.
11. The apparatus of claim 1, wherein the first semiconductor die includes read only memory.
12. The apparatus of claim 1, comprising electrostatic damage protection circuitry disposed under the first bond out pad.
13. An apparatus comprising:
a portion of a semiconductor wafer;
a first semiconductor die disposed on the portion of the semiconductor wafer;
a first bond out pad disposed adjacent to the first semiconductor die on the portion of the semiconductor wafer; and
a first sawn semiconductor die disposed adjacent to the first bond out pad and at a first edge of the portion of the semiconductor wafer, wherein a part of the first sawn semiconductor die forms at least a portion of the first edge.
14. The apparatus of claim 13, wherein the first semiconductor die includes a test die.
15. The apparatus of claim 13, comprising a second sawn semiconductor die disposed adjacent to the first semiconductor die and at a second edge of the portion of the semiconductor wafer, wherein a part of the second sawn semiconductor die forms at least a portion of the second edge.
16. The apparatus of claim 15, comprising a second bond out pad disposed between the first semiconductor die and the second sawn semiconductor die.
17. The apparatus of claim 13, comprising test circuitry disposed on the portion of a semiconductor wafer and adjacent the first semiconductor die.
18. A sawn semiconductor wafer structure comprising:
a first sawn edge and a second sawn edge;
a test die disposed between the first and second sawn edges;
a first bond out pad disposed adjacent to the test die; and
a first sawn semiconductor die disposed adjacent to the first bond out pad and at the first sawn edge, wherein at least a portion of the first sawn edge is a part of the first sawn semiconductor die.
19. The sawn semiconductor wafer structure of claim 18, comprising a second sawn semiconductor die disposed adjacent to the test die and at the second sawn edge, wherein at least a portion of the second sawn edge is a part of the second sawn semiconductor die.
20. The sawn semiconductor wafer structure of claim 19, comprising a second bond out pad disposed between the test die and the second sawn semiconductor die.
US12/506,136 2006-12-01 2009-07-20 Scribe based bond pads for integrated circuits Abandoned US20090278124A1 (en)

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US12/506,136 US20090278124A1 (en) 2006-12-01 2009-07-20 Scribe based bond pads for integrated circuits

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8049249B1 (en) * 2006-09-14 2011-11-01 Marvell International Ltd. Integrated circuit devices with ESD protection in scribe line, and methods for fabricating same
US7563694B2 (en) * 2006-12-01 2009-07-21 Atmel Corporation Scribe based bond pads for integrated circuits
JP2008311455A (en) * 2007-06-15 2008-12-25 Nec Electronics Corp Method for evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having evaluation element
JP5466820B2 (en) * 2007-10-18 2014-04-09 ピーエスフォー ルクスコ エスエイアールエル Semiconductor substrate and method for manufacturing semiconductor device
US8698139B2 (en) * 2008-11-25 2014-04-15 Qualcomm Incorporated Die-to-die power consumption optimization
CN102754208A (en) 2009-11-30 2012-10-24 飞思卡尔半导体公司 Bypass capacitor circuit and method of providing a bypass capacitance for an integrated circuit die
TWI464857B (en) * 2011-05-20 2014-12-11 Xintec Inc Chip package, method for forming the same, and package wafer
US9082832B2 (en) 2011-09-21 2015-07-14 Stats Chippac, Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US9484259B2 (en) 2011-09-21 2016-11-01 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming protection and support structure for conductive interconnect structure
US8648341B2 (en) * 2012-02-23 2014-02-11 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for testing pads on wafers
US10534554B2 (en) * 2017-10-13 2020-01-14 Silicon Storage Technology, Inc. Anti-hacking mechanisms for flash memory device
KR20190133964A (en) 2018-05-24 2019-12-04 삼성전자주식회사 A semiconductor device and a semiconductor package including the same

Citations (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721151A (en) * 1995-06-07 1998-02-24 Lsi Logic Corporation Method of fabricating a gate array integrated circuit including interconnectable macro-arrays
US5767565A (en) * 1996-07-22 1998-06-16 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US6054772A (en) * 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
US20010023979A1 (en) * 1998-02-27 2001-09-27 Brouvillette Donald W. Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
US6404217B1 (en) * 1995-09-30 2002-06-11 Atmel Research Enhanced security semiconductor device, semiconductor circuit arrangement and method or production thereof
US20020076840A1 (en) * 1999-04-09 2002-06-20 Dupont Photomasks, Inc. A Delaware Corporation Test wafer and method for investigating electrostatic discharge induced wafer defects
US20020130591A1 (en) * 2000-01-21 2002-09-19 Fraser John Douglas Hex packed two dimensional ultrasonic transducer arrays
US20030025116A1 (en) * 2001-08-01 2003-02-06 Motorola, Inc. Semiconductor laminate configured for dividing into predetermined parts and method of manufacture therefor
US20030032263A1 (en) * 2001-08-08 2003-02-13 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer, semiconductor device, and method for manufacturing the same
US20030049871A1 (en) * 2001-09-13 2003-03-13 Kunihiko Higashi Chip manufacturing method for cutting test pads from integrated circuits by sectioning circuit chips from circuit substrate
US20030215966A1 (en) * 2002-05-14 2003-11-20 Rolda Ruben A. Circular test pads on scribe street area
US6680484B1 (en) * 2002-10-22 2004-01-20 Texas Instruments Incorporated Space efficient interconnect test multi-structure
US20040089282A1 (en) * 1996-11-12 2004-05-13 Salman Akram Method for sawing wafers employing multiple indexing techniques for multiple die dimensions and dicing apparatus
US20040177298A1 (en) * 1995-12-22 2004-09-09 Farnworth Warren M. Device and method for testing integrated circuit dice in an integrated circuit module
US6829727B1 (en) * 2001-01-12 2004-12-07 Metalink Corp. In-circuit emulation of single chip microcontrollers
US20050230005A1 (en) * 2003-06-25 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Test pad for reducing die sawing damage
US20050239268A1 (en) * 2004-04-22 2005-10-27 Texas Instruments Incorporated Integrated circuit with removable scribe street trim and test pads
US6963511B2 (en) * 2004-03-10 2005-11-08 Fujitsu Limited Semiconductor integrated circuit
US6967111B1 (en) * 2003-08-28 2005-11-22 Altera Corporation Techniques for reticle layout to modify wafer test structure area
US20060001144A1 (en) * 2004-06-30 2006-01-05 Uehling Trent S Scribe street structure for backend interconnect semiconductor wafer integration
US20060103402A1 (en) * 2004-11-12 2006-05-18 Matsushita Electric Industrial Co., Ltd. Semiconductor apparatus
US7061256B2 (en) * 2004-07-26 2006-06-13 Nec Electronics Corporation Method and apparatus for contact resistance measurement
US7075107B2 (en) * 2004-05-06 2006-07-11 Advanced Analog Technology, Inc Semiconductor wafer and manufacturing process thereof
US7224176B2 (en) * 2002-07-26 2007-05-29 Samsung Electronics Co., Ltd. Semiconductor device having test element groups
US20080128690A1 (en) * 2006-12-01 2008-06-05 Andrew Burnside Scribe based bond pads for integrated circuits

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140303A (en) * 2004-11-12 2006-06-01 Mitsui Chemicals Inc Method for manufacturing semiconductor apparatus

Patent Citations (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5721151A (en) * 1995-06-07 1998-02-24 Lsi Logic Corporation Method of fabricating a gate array integrated circuit including interconnectable macro-arrays
US6404217B1 (en) * 1995-09-30 2002-06-11 Atmel Research Enhanced security semiconductor device, semiconductor circuit arrangement and method or production thereof
US20040177298A1 (en) * 1995-12-22 2004-09-09 Farnworth Warren M. Device and method for testing integrated circuit dice in an integrated circuit module
US5767565A (en) * 1996-07-22 1998-06-16 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US6403448B1 (en) * 1996-07-22 2002-06-11 Alliance Semiconductor Corporation Semiconductor devices having cooperative mode option at assembly stage and method thereof
US20040089282A1 (en) * 1996-11-12 2004-05-13 Salman Akram Method for sawing wafers employing multiple indexing techniques for multiple die dimensions and dicing apparatus
US20010023979A1 (en) * 1998-02-27 2001-09-27 Brouvillette Donald W. Method and system for dicing wafers, and semiconductor structures incorporating the products thereof
US6054772A (en) * 1998-04-29 2000-04-25 National Semiconductor Corporation Chip sized package
US20020076840A1 (en) * 1999-04-09 2002-06-20 Dupont Photomasks, Inc. A Delaware Corporation Test wafer and method for investigating electrostatic discharge induced wafer defects
US20020130591A1 (en) * 2000-01-21 2002-09-19 Fraser John Douglas Hex packed two dimensional ultrasonic transducer arrays
US6829727B1 (en) * 2001-01-12 2004-12-07 Metalink Corp. In-circuit emulation of single chip microcontrollers
US20030025116A1 (en) * 2001-08-01 2003-02-06 Motorola, Inc. Semiconductor laminate configured for dividing into predetermined parts and method of manufacture therefor
US20030032263A1 (en) * 2001-08-08 2003-02-13 Matsushita Electric Industrial Co., Ltd. Semiconductor wafer, semiconductor device, and method for manufacturing the same
US6686224B2 (en) * 2001-09-13 2004-02-03 Nec Electronics Corporation Chip manufacturing method for cutting test pads from integrated circuits by sectioning circuit chips from circuit substrate
US20030049871A1 (en) * 2001-09-13 2003-03-13 Kunihiko Higashi Chip manufacturing method for cutting test pads from integrated circuits by sectioning circuit chips from circuit substrate
US20030215966A1 (en) * 2002-05-14 2003-11-20 Rolda Ruben A. Circular test pads on scribe street area
US7224176B2 (en) * 2002-07-26 2007-05-29 Samsung Electronics Co., Ltd. Semiconductor device having test element groups
US6680484B1 (en) * 2002-10-22 2004-01-20 Texas Instruments Incorporated Space efficient interconnect test multi-structure
US20050230005A1 (en) * 2003-06-25 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Test pad for reducing die sawing damage
US6967111B1 (en) * 2003-08-28 2005-11-22 Altera Corporation Techniques for reticle layout to modify wafer test structure area
US7316935B1 (en) * 2003-08-28 2008-01-08 Altera Corporation Reticle for layout modification of wafer test structure areas
US6963511B2 (en) * 2004-03-10 2005-11-08 Fujitsu Limited Semiconductor integrated circuit
US20050239268A1 (en) * 2004-04-22 2005-10-27 Texas Instruments Incorporated Integrated circuit with removable scribe street trim and test pads
US7075107B2 (en) * 2004-05-06 2006-07-11 Advanced Analog Technology, Inc Semiconductor wafer and manufacturing process thereof
US20060001144A1 (en) * 2004-06-30 2006-01-05 Uehling Trent S Scribe street structure for backend interconnect semiconductor wafer integration
US7061256B2 (en) * 2004-07-26 2006-06-13 Nec Electronics Corporation Method and apparatus for contact resistance measurement
US20060103402A1 (en) * 2004-11-12 2006-05-18 Matsushita Electric Industrial Co., Ltd. Semiconductor apparatus
US20080128690A1 (en) * 2006-12-01 2008-06-05 Andrew Burnside Scribe based bond pads for integrated circuits
US7563694B2 (en) * 2006-12-01 2009-07-21 Atmel Corporation Scribe based bond pads for integrated circuits

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