TW200914919A - Display device and electronic apparatus including display device - Google Patents

Display device and electronic apparatus including display device Download PDF

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Publication number
TW200914919A
TW200914919A TW097116850A TW97116850A TW200914919A TW 200914919 A TW200914919 A TW 200914919A TW 097116850 A TW097116850 A TW 097116850A TW 97116850 A TW97116850 A TW 97116850A TW 200914919 A TW200914919 A TW 200914919A
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Taiwan
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wiring
potential
circuit
electrode
display device
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TW097116850A
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Chinese (zh)
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TWI402560B (en
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Yutaka Kobashi
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Epson Imaging Devices Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/03—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect
    • G02F1/0327—Operation of the cell; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Liquid Crystal (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

A display device includes an active matrix circuit for display, a plurality of bus lines which are connected to the active matrix circuit and which are used to transmit driving signals, driving circuits which supply the driving signals to the plurality of bus lines, the plurality of bus lines and the driving circuits being arranged on a substrate, and optical sensors arranged on the substrate. The optical sensors are arranged in a plurality of sub regions separated using the plurality of bus lines. The plurality of sub regions are arranged between the active matrix circuit and each of the driving circuits.

Description

200914919 九、發明說明 【發明所屬之技術領域】 本發明係關於例如顯示裝置及具備此裝置之電子機器 【先前技術】 近年來，於顯示裝置上，進行著特別是於使用薄膜電 晶體之液晶顯示裝置上搭載光感測器功能的技術之開發。 搭載光感測器的目的可以舉出3種：（1 )測定外光調整 亮度等以謀求耗電量的減低與畫質提高；（2 )測定背光 而調整亮度或色度；（3 )認識手指或光筆的位置而作爲 觸控鍵使用。作爲光感測器可以舉出薄膜電晶體、PIN ( p-intrinsic-n)二極體、PN二極體等。任一場合受光部都 是矽薄膜，爲了不使製造上的成本增大，最好是能夠與構 成顯示的開關元件之矽薄膜以相同的製造步驟來製造。 [專利文獻1]日本專利特開2006 - 1 1 8 96 5號公報 【發明內容】 [發明所欲解決之課題] 由光照度測定的精度或是設計上的觀點來看’光感測 器的設置位置最好是配置在接近顯示裝置的顯不區域’但 在驅動電路內藏型液晶顯示裝置，要在比驅動電路更內側 配置光感測器是有困難的。此外，在如此配置的場合，光 感測器容易受到顯示區域驅動的電氣雜訊的影響，此外來 -4- 200914919 自顯示區域的迷光所導致的影響也無法忽視，所以有光感 測器的精度低下的課題，特別是在液晶顯示裝置進行共通 電位反轉驅動的場合，此一問題變得顯著。 [供解決課題之手段] 本發明，係由具備光感測器、顯示用之主動矩陣電路 、被接續於前述主動矩陣電路而傳達驅動訊號之複數匯流 排線、以及對前述複數匯流排線輸出驅動訊號之驅動電路 的主動矩陣基板所構成之顯示裝置，前述光感測器，被配 置於以前述複數匯流排線區隔的複數次區域，前述複數次 區域被配置於前述主動矩陣電路與前述驅動電路之間。如 此配置的話，即使驅動電路內藏型顯示器，也因爲可以將 光感測器配置於顯示區域的附近，所以可正確測定外光照 度，搭載的電子機器之設計自由度也提高。 此外’本發明之特徵爲進而具備：被接續於前述主動 矩陣電路之複數畫素電極、在第1電位與第2電位之間被 反轉驅動的共通電極、對應於被施加在前述複數畫素電極 與前述共通電極之間的電場而改變配向狀態之液晶元件、 被接續於前述光感測器的感測器配線、以及被接續於前述 感測器配線而檢測出前述感測器配線的電位或者電流之檢 測電路；前述檢測電路，係前述共通電極以前述第1電位 或第2電位之任一方的計時，檢測前述感測器配線的電位 或者電流。如此構成的話，反轉驅動共通電極之所謂的共 同 AC驅動而使液晶顯示裝置之耗電量下降，可以防止共 -5- 200914919 通電極的反轉導致的電磁雜訊或與共通電極之結合 致的感測器配線電位的變動等所導致的精度降低。 此外’本發明之特徵爲前述檢測電路反覆進行 感測器配線的電位回到初期狀態之重設動作，前述 作結束之計時，係前述共通電極以前述第i電位或 第1電位更低的第2電位之任一方之計時。如此設 ，即使感測器配線係以與共通電極之結合電容決定 也因爲總是在電位回到原來的狀態下檢測電路才進 ，所以檢測精度不會降低。 此外’本發明之特徵爲前述感測器配線，係以 共通電極的電位相同的計時改變電位的。如此一來 必要去留意前述感測器配線與共通電極之間的結合 前述感測器配線之阻抗，所以提高配置上的自由度 縮小面板的外型。具體而言，特徵爲前述感測器配 前述共通電極短路。在此場合，感測器配線與共通 電位變成相等’可以忽視結合電容。或者，特徵爲 測器配線’僅在前述共通電位以前述不同的複數電 ，特定電位之計時’被連接於由外部供給電位的電 ，在其餘的期間成爲浮動（floating )狀態。如此 話，感測器配線係以與共通電極之結合電容決定振 使與共通電極之結合電容很大，或者感測器配線之 大的場合，也沒有關係。 此外’本發明具有被形成在與前述光感測器平 的區域的第1電極，在前述第1電極與前述匯流排 電容導 使前述 重設動 比前述 定的話 振幅， 行動作 與前述 ，沒有 電容或 ，可以 線係與 電極的 前述感 位之中 源配線 構成的 幅，即 電阻很 面重疊 線平面 -6- 200914919 重疊的區域配置第2電極。如此構成的話，即使因遮 遮蔽的目的而形成第1電極，也會使前述光感測器經 1電極而受到匯流排線（掃描線或資料線等）之電位 的影響變少，更爲提高精度。此外，本發明之特徵爲 第2電極係與共通電極接續。共通電極，爲了提高畫 將輸出阻抗或配線阻抗設計得較低，所以作爲第2電 電位固定目標而使用的話，提高遮蔽性能，此外沒有 多餘的配線所以可使顯示裝置的外型縮小。 此外本發明特徵爲具有與前述光感測器重疊的第 極，前述第1電極係供遮蔽背光之用的複數遮光電極 前述複數遮光電極間的間隙配置前述匯流排線或者前 2電極。使背光遮光電極與光感測器重疊時於其間隙 置匯流排線的話不會漏光，可以防止迷光。 此外本發明特徵爲前述複數之次區域係沿著前述 矩陣電路之外週部之複數邊配置的。因爲於複數邊配 感測器，所以液晶之顯示狀態所導致的迷光差異變少 外，特別是在對顯示裝置重疊上觸控面板等而使用的 ，因操作而手指接近而無法避免的光的影響也變少。 此外，本發明之特徵爲前述檢測電路係複數之檢 路，具備與前述複數檢測電路接續之多數決電路，前 數決電路，在來自前述複數之檢測電路之複數輸出結 中，2以上之輸出結果改變時，使輸出改變。如此構 話，即使如前所述因手指而導致陰影，或者相反的於 邊有外光所導致的強光點光，該區域之結果也被除外 光或 由第 變動 前述 質， 極之 必要 1電 ，於 述第 上配 主動 置光 ，此 場合 測電 述多 果之 成的 任一 所以 -7- 200914919 提高了檢測精度。進而，在本發明，也配合提出了於前述 複數檢測電路之一之第1檢測電路透過前述感測器配線接 續之前述複數次區域，沿著前述主動矩陣電路之外週部之 某個邊配置，於前述複數檢測電路之其他之一之第2檢測 電路透過前述感測器配線被連接的前述複數次區域，係沿 著前述主動矩陣電路之外週部之其他的邊而被配置的。如 此構成的話，因爲採用以邊爲單位之結果的多數決，所以 即使僅有特定的邊上有光影，或者相反的有光的時候也不 會誤動作，可以進而精度佳地檢測外光。 此外，本發明之特徵爲前述光感測器係使用薄膜多晶 矽之PIN接合二極體或者PN接合二極體，前述驅動電路 藉由使用薄膜多晶矽的電晶體來構成。如此構成的話，可 以使光感測器與薄膜電晶體以同一個製造步驟來形成’即 使內藏光感測器也不會增加成本。 此外，在本發明提案出使用這些顯示裝置之電子機器 。因爲內藏精度佳的光感測器所以容易配合外光而控制背 光，不會使耗電量無意義地增加，成本也不會上升。此外 ，可以在顯示區域附近配置光感測器’所以設計的自由度 也提商。 【實施方式】 以下，根據圖面說明將本發明具體化之實施型態。 [第1實施型態] -8- 200914919 圖1係相關於本實施例之液晶顯示裝置9 1 0 成圖（部分剖面圖）。液晶顯示裝置91 0，係藉 將主動矩陣基板101與對向基板912隔著一定間 夾持向列相液晶材料9 2 2。於主動矩陣基板1 0 1 圖示’但由聚醯亞胺等所構成的配向材料被塗布 施以摩擦處理的配向膜。此外，對向基板9 1 2， 雖未圖示但對應於畫素之彩色濾光片、防止光穿 提高之用的低反射/低透過率樹脂所構成的黑矩陣 主動矩陣基板101上之對向導通部3 3 0- 1〜3 3 0-ΙΤΟ膜所構成的作爲共通電極之對向電極930。 液晶材料922接觸之面上被塗布由聚醯亞胺等所 向材料，在與主動矩陣基板1 〇 1的配向膜的磨擦 直交的方向上被施以摩擦處理。 進而於對向基板9 1 2的外側，配置上偏光板 主動矩陣基板101的外側配置下偏光板92 5，以 光方向直交的方式（crossed Nichol狀）配置。 偏光板925，被配置背光單元926與導光板927 光單元926朝向導光板927照射，導光板927係 背光單元9 26的光朝向主動矩陣基板101而成爲 勻的面光源的方式使光反射曲折而作爲液晶顯示 的光源而發揮功能。背光單元926，在本實施例；| 元，但也可以是冷陰極管（CCFL )。背光單元 連接器929被接續於電子機器本體，供給電源， 施例具有藉由電源適宜適切地調整電流/電壓而 之立體構 由密封材 隔貼合， 上，雖未 而形成被 被形成： 透使對比 940、與 2短路的 與向列相 構成之配 處理方向 924，在 相互的偏 進而於下 ，光由背 以使來自 垂直且均 裝置 9 1 0 I LED 單 926通過 但在本實 調整來自 -9- 200914919 背光單元的光量的功能。 雖未圖示，但亦可進而應需要而以外殻覆蓋周圍 者在上偏光板924之上安裝保護用的玻璃或壓克力板 可貼上供改善視角之用的光學補償膜。 此外，主動矩陣基板101，被設有由對向基板91 出的伸出部 9 2 1，於位在該伸出部9 2 1的訊號輸入 3 20，被實裝作爲可撓性基板之FPC 928而被導電接 作爲可撓性基板之FPC 928被接續於電子機器本體， 給必要的電源、控制訊號等。 進而於液晶顯示裝置91 0上，第1個第1邊受光 部991-1〜第3個第1邊受光開口部991-3、第1個第 受光開口部992- 1〜第4個第2邊受光開口部992-4 ' 個第3邊受光開口部9 9 3 - 1〜第3個第3邊受光開 993-3、第1個第4邊受光開口部994-1〜第4個第4 光開口部994-4、分別藉由部分除去對向基板912上 矩陣940而被形成，外部之光通過這些開口部到達主 陣基板1 0 1上。 圖2爲主動矩陣基板101之方塊圖。於主動矩陣 1 〇 1上之顯示區域3 1 0，作爲主動矩陣電路，4 8 0條掃 201 (201-1〜201-480)與 1920 條資料線 202(202 2 0 2 - 1 9 2 0 )直交地形成，4 8 0條電容線2 0 3 ( 2 0 3 - 1〜 4 8 0 )與掃描線2 0 1 ( 2 0 1 - 1〜2 0 1 - 4 8 0 )平行地配置。 線203 ( 203 - 1〜203 -48 0 )相互被短路，與共通電位 335接續，進而與2個對向導通部330 ( 330-1〜330_2 ，或 ，亦 2伸 端子 繪。 被供 開口 2邊 第1 口部 邊受 之黑 動矩 基板 描線 -1〜 203- 電容 配線 )接 -10- 200914919 續而由訊號輸入!ijfij子320提供〇V-5V之反轉訊號、反轉時 間爲35μ秒之共通電位。掃描線201 ( 201-1〜201-480) 被接續於掃描線驅動電路301，此外資料線2〇2 ( 202」〜 202-1920)被接續於資料線驅動電路302及預充電電路 303’分別被適切地驅動。此外’掃描線驅動電路3〇1、資 料線驅動電路302、預充電電路303由訊號輸入端子302 供給驅動所必要的訊號。訊號輸入端子3 0 2被配置於伸出 部9 2 1上。掃描線驅動電路3 0 1、資料線驅動電路3 0 2、 預充電電路303係在主動矩陣基板1〇1上集積多晶矽薄膜 電晶體而形成的，以與後述之畫素開關元件40 1 ( 40 1 -n-m )相同的步驟所製造，成爲所謂的驅動電路內藏型液晶顯 示裝置。 此外，在掃描線驅動電路3 0 1與顯示區域3 1 0所夾的 區域作爲4 8 0個之光感測器之第1邊光感測器3 5 1 -1〜 351-480作爲光感測器351被配置。第η個之第n之第1 邊光感測器35 1-η分別被配置在掃描線20 1-η與掃描線 20 1-η+1之間的區域（次區域之一·例）。此處，第81個第 1邊光感測器351-81〜第160個第1邊光感測器351-160 與第1個第1邊受光開口部991-1平面重疊地配置’第 241個第1邊光感測器3 5 1 -24 1〜第3 20個第1邊光感測 器351-320與第2個第1邊受光開口部991-2平面重疊地 配置，第401個第1邊光感測器35 1-4〇1〜第4 8 0個第1 邊光感測器3 5 1 -4 80與第3個第1邊受光開口部991-3平 面重疊地配置。總稱與這些第1個第1邊受光開口部9 9 1 _ -11 - 200914919 1〜第3個第1邊受光開口部991-3之任一平面重疊的第n 個第1邊光感測器3 5 1 -η稱之爲第i邊受光感測器群。此 外，總稱與第1個第1邊受光開口部9 91 _ 1〜第3個第1 邊受光開口部99 1 -3之任一不重疊的第n個第1邊光感測 器3 5 1 - η稱之爲第1邊遮光感測器群。 同樣地，在預充電電路303與顯示區域310所夾的® 域作爲192〇個之光感測器之第2邊光感測器352-1〜352-192〇作爲光感測器3 52被配置。第η之第2邊光感測器 3 52-η分別被配置在資料線202-η與資料線202-n+l之間 的區域（次區域之一例）。此處，第1之第2邊光感測器 352-1〜第240個第2邊光感測器352-240與第1之第2邊 受光開口部992-1平面重疊地配置，第481個第2邊光感 測器3 5 2-48 1〜第720個第2邊光感測器3 52-72 0與第2 個第2邊受光開口部992-2平面重疊地配置，第961個第 2邊光感測器352-96 1〜第1 200個第2邊光感測器3 52-1200與第3個第2邊受光開口部992-3平面重疊地配置， 第1441個第2邊光感測器352-1441〜第1680個第2邊光 感測器352-1680與第4個第2邊受光開口部992-4平面重 疊地配置。總稱與這些第1個第2邊受光開口部992- 1〜 第4個第2邊受光開口部992-4之任一平面重疊的第η個 第2邊光感測器352-η稱之爲第2邊受光感測器群。此外 ，總稱與第1個第2邊受光開口部992- 1〜第4個第2邊 受光開口部9 92 -4之任一不重疊的第η個第2邊光感測器 3 52-η稱之爲第2邊遮光感測器群。 -12- 200914919 同樣地，在夾著掃描線驅動電路301與顯示區域310 而對向的週緣部作爲光感測器之480個之第3邊光感測器 3 5 3 - 1〜3 5 3 -480作爲光感測器3 5 3被配置。第η之第3邊 光感測器3 5 3 -η分別被配置在電容線203 -η與電容線203 -η+1之間的區域。此處，第1個第3邊光感測器3 5 3 - 1〜 第80個第3邊光感測器353-80與第1個第3邊受光開口 部9 93 - 1平面重疊地配置，第161個第3邊光感測器3 5 3 -161〜第240個第3邊光感測器3 5 3 -240與第2個第3邊 受光開口部993 -2平面重疊地配置，第321個第3邊光感 測器353-321〜第400個第3邊光感測器353-400與第3 個第3邊受光開口部993 _3平面重疊地配置。總稱與這些 第1個第3邊受光開口部993-1〜第3個第1邊受光開口 部993-3之任一平面重疊的第η個第3邊光感測器353-η 稱之爲第3邊受光感測器群。此外，總稱與第1個第3邊 受光開口部993-1〜第3個第1邊受光開口部993_3之任 一不重疊的第η個第3邊光感測器353-η稱之爲第3邊遮 光感測器群。 同樣地’在資料線驅動電路3 0 2與顯示區域3 1 0所夾 的區域作爲光感測器之192〇個之第4邊光感測器354-1〜 3 5 4 - 1 9 2 0作爲光感測器3 5 4被配置。第η之第4邊光感測 器3 5 4-η分別被配置在資料線2〇2_η與資料線202-n+l之 間的區域。此處’第241之第4邊光感測器3 54_241〜第 480個第4邊光感測器354_48〇與第1之第4邊受光開口 部994-1平面重疊地配置，第721個第4邊光感測器354- -13- 200914919 721〜第960個第4邊光感測器354-960與第2個第4邊 受光開口部994-2平面重疊地配置，第1201個第4邊光 感測器354-1201〜第1440個第4邊光感測器354-1440與 第3個第4邊受光開口部994-3平面重疊地配置，第1681 個第4邊光感測器3 54- 1 68 1〜第1 920個第4邊光感測器 3 54- 1 92〇與第4個第4邊受光開口部994-4平面重疊地配 置。總稱與這些第1個第4邊受光開口部994-1〜第4個 第4邊受光開口部994-4之任一平面重疊的第n個第4邊 光感測器3 54-η稱之爲第4邊受光感測器群。此外，總稱 與第1個第4邊受光開口部994-1〜第4個第4邊受光開 口部994-4之任一不重疊的第η個第4邊光感測器354-η 稱之爲第4邊遮光感測器群。 此處，第1邊受光感測器群被接續於配線SENSE ( SENSEI )與配線VSH ( VSH1 )。第1邊遮光感測器群被 接續於配線SENSEI與配線VSL ( VSL1 )與配線VDBT ( VDBT1 )。第2邊受光感測器群被接續於配線SENSE ( SENSE2)與配線VSH(VSH2)。第2邊遮光感測器群被 接續於配線SENSE2與配線VSL ( VSL2 )與配線VDBT ( VDBT2 )。第3邊受光感測器群被接續於配線SENSE ( SENSE3 )與配線VSH ( VSH3 )。第3邊遮光感測器群被 接續於配線SENSE3與配線VSL ( VSL3 )與配線VDBT ( VDBT3 )。第4邊受光感測器群被接續於配線SENSE ( SENSE4)與配線VSH ( VSH4)。第4邊遮光感測器群被 接續於配線SENSE4與配線VSL ( VSL4 )與配線VDBT ( -14- 200914919 VDBT4)。 配線 SENSEI與配線 VSH1與配線 VSL1與配線 VDBT1作爲檢測電路3 60被接續於第1檢測電路3 60- 1。 配線SENSE2與配線VSH2與配線VSL2與配線VDBT2作 爲檢測電路3 6 0被接續於第2檢測電路3 6 0 - 2。配線 SENSE3與配線VSH3與配線VSL3與配線VDBT3作爲檢 測電路3 60被接續於第3檢測電路3 60-3。配線SENSE4 與配線VSH4與配線VSL4與配線VDBT4作爲檢測電路 3 6 0被接續於第4檢測電路3 6 0 - 4。 來自第1檢測電路3 60- 1之輸出配線OUT1，與來自 第2檢測電路3 60-2的輸出配線OUT2，與來自第3檢測 電路3 60-3的輸出配線OUT3，與來自第4檢測電路3 60-4 的輸出配線OUT4被接續於多數決電路3 70，來自多數決 電路3 70的輸出配線OUT透過訊號輸入端子3 20之一被 接續於外部電路。 圖3係在顯示區域310之第m條資料線20 2-m與第η 條掃描線2 0 1 - η之父叉部附近之電路圖。於掃描線2 0 1 - η 與資料線202-m之各交點附近被形成由Ν通道型場效應多 晶矽薄膜電晶體所構成的畫素開關元件40 1 -n-m，其閘極 電極被連接於掃描線2〇 1 -η，源極·汲極電極被分別連接 於資料線202-m與畫素電極402 ( 402-n-m)。畫素電極 402-n-m以及被短路於同一電位的電極形成電容線203-n 與輔助電容量4 0 3 ( 4 0 3 - η - m )，此外作爲液晶顯示裝置被 組入時夾著液晶元件與對向電極9 3 0形成電容器。 -15- 200914919 圖4係顯示在本實施例之電子機器之具體構成之方塊 圖。s液晶顯示裝置9 1 0係圖1所說明之液晶顯示裝置， 外部電源電路784、影像處理電路780通過作爲可撓性基 板之FPC 928以及連接器929將必要的訊號與電源供給至 液晶顯示裝置910。中央演算電路781透過I/F電路782 取得來自輸出機器783的輸入資料。此處作爲輸出機器 783例如爲鍵盤、滑鼠、軌跡球、LED、喇叭、天線等。 中央演算電路7 8 1以來自外部的資料爲根本進行各種演算 處理，將結果作爲指令往影像處理電路78 0或外部I/F電 路782轉送。影像處理電路780根據來自中央演算電路 781的指令更新影像資訊，藉由變更往液晶顯示裝置910 之訊號，改變液晶顯示裝置9 1 0之顯示影像。此外，來自 液晶顯示裝置9 1 0上的多數決電路3 7 0之輸出配線0 U T 通過作爲可撓性基板之FPC 928被輸入至中央演算電路 781 ’中央演算電路781將二値輸出訊號（OUT )的脈衝 長變換爲對應的離散値。其次中央演算電路7 8 1存取由 EEPROM (可電性抹除可程式唯讀記憶體，Eiectronically Erasable and Programmable Read Only Memory )所構成之 參照表7 85 ’將變換的離散値再變換爲對應於適切的背光 單元9 2 6的電壓之値’送訊至外部電源電路7 8 4。外部電 源電路784通過連接器929將對應於此被送訊的値之電壓 的電位電源供給至液晶顯示裝置9 1 0內之背光單元9 2 6。 背光單元926的亮度係由從外部電源電路7 84供給的電壓 而改變的，所以液晶顯示裝置9 1 0之全白顯適時的亮度也 -16- 200914919 改變。此處所謂電子機器，具體而言可以舉出監, 、筆 S己型電腦、PDA ( Personal Digital ( Assistants )、數位相機、攝影機、行動電話、 播放器、可攜影帶播放器、可攜D V D播放器、 播放器等。 又’在本實施例，藉由電子機器上的中央 781控制背光單元926的亮度，但作爲例如在液 置910內具備驅動器1C以及EEPROM的構成， 驅動器1C具備由二値輸出訊號（OUT )往離散 功能、參照EEPROM之再變換功能、對背光單元 出電壓之調整功能等。此外，不使用參照表，而 値計算從離散値再變換爲對應於背光單元296的 的方式構成亦可。 圖5係顯示以圖3所示的畫素顯示區域的電 際構成之平面圖。如圖5之例所示，各網點不同 別爲不同的材料配線，相同的網點的部位係相同 線。鉻膜（C r )、多晶矽薄膜（P 〇 1 y - s i )、鉬f )、鋁鈸合金薄膜（AINd )、銦錫氧化物薄膜 Indium Tin Oxide)等5層薄膜所構成，分別之 成氧化矽、氮化矽、有機絕緣膜之任一或者這些 緣膜。具體而言，鉻膜（Cr )膜厚1 OOnm、多晶 Poly-Si)膜厚 50nm、鉬薄膜（Mo)膜厚 20 0nm 金薄膜（AINd)膜厚500nm、銦錫氧化物薄膜 Indium Tin Oxide)膜厚爲 1〇〇 nm。此外鉻膜（ 視器' TV :Data ) 可攜相片 可攜音樂 演算電路 晶顯示裝 亦可於此 値之變換 9 2 6的輸 以藉由數 電壓之値 路圖之實 的部位分 的材料配 奪膜（Mo (ITO， 層間被形 層積之絕 矽薄膜（ 、銘銳合 (ITO， Cr )與多 -17- 200914919 晶矽薄膜（P〇ly-Si)之間被形成層積100nm的氮化矽膜 與lOOnm的氧化矽膜之下底絕緣膜，多晶矽薄膜（Poly-Si)與鉬薄膜（Mo)之間被形成由lOOnm之氧化矽膜所 構成之閘極絕緣膜，鉬薄膜（Mo )與鋁銨合金薄膜（ AINd)之間被形成層積2 00nm的氮化矽膜與5 00nm的氧 化矽膜之層間絕緣膜，鋁钕合金薄膜（AINd )與銦錫氧化 物薄膜（ITO，Indium Tin Oxide)之間被形成層積200nm 之氮化矽膜與平均1 μηι的有機平坦化膜之保護絕緣膜，相 互之配線間爲絕緣，於適切的位置開口出接觸孔而使相互 接續。又，在圖5中不存在鉻薄膜（Cr)圖案。 如圖5所示，資料線202-m係由鋁鈸合金薄膜（AINd )所形成，透過接觸孔接續於畫素開關元件401-n-m的源 極電極。掃描線2 0 1 - η係以鉅薄膜（Μ 〇 )所構成，兼做畫 素開關元件40 1-n-m的閘極電極。電容線203 -η係由與掃 描線2 0 1 - η相同的配線材料所構成，畫素電極4 0 2 - η - m係 由銦錫氧化物薄膜所構成，通過接觸孔被接續於畫素開關 元件401-n-m之汲極電極。此外，畫素開關元件401-n-m 之汲極電極也被接續於由被高濃度摻雜磷的n +型多晶矽 薄膜所構成的電容部電極605，與電容線203-n平面重疊 構成補助電容電容器40 3-n-m。 圖6係供說明畫素開關元件401-n-m的構造之用的對 應於圖5之A - A ’線部的液晶顯不裝置9 1 0之部分剖面構 造圖。又，爲使圖容易辨認，比例尺並非固定。主動矩陣 基板1 〇 1係由無鹼玻璃所構成的厚度0 · 6 mm的絕緣基板， -18- 200914919 於其上中介著層積200nm的氮化矽膜與3 00nm的氧化矽 膜之下底絕緣膜而被配置由多晶矽薄膜所構成的矽島602 ，掃描線20 1-η挾著矽島602與前述之閘極絕緣膜被配置 於上方。在與掃描線201-η重疊的區域，矽島602係由完 全爲摻雜或者只低濃度摻雜很低濃度的磷離子的真性半導 體區域6021，於其左右存在磷離子被低濃度摻雜之薄膜電 阻爲20kn程度之η-區域602L，進而於其左右存在磷離子 被高濃度摻雜之薄膜電阻爲lkQ程度之η +區域602Ν之 LDD( Lightly Doped Drain，低摻雜汲極）構造。左右之 n +區域602N透過接觸孔而與源極電極603、汲極電極604 接續，源極電極603與資料線202-m接續，汲極電極604 與畫素電極402-n-m接續。在畫素電極402-n-m與對向基 板9 1 2上之作爲共通電極之對向電極9 3 0之間存在向列相 液晶材料922。此外，以與畫素電極402-n-m部分重疊的 方式在對向基板912上被形成黑矩陣940。又，在畫素開 關元件40 1 -n-m之光洩漏電流成爲問題的場合，於矽島 6 02下形成由鉻膜所構成的遮光層亦可。在本實施例因爲 光洩漏電流幾乎不成爲問題，且因採這樣的構造的話，畫 素開關元件401-n-m的移動度會降低，所以選擇除去矽島 602下之鉻膜的構成。 圖7係供說明輔助電容電容器403 -n-m的構造之用的 圖5的B-B’線部對應的液晶顯示裝置91〇的部分剖面構造 圖，與汲極電極604連結的電容部電極605與電容線203-n係以挾著閘極絕緣膜而重疊的方式形成蓄積電容。 -19- 200914919 圖8係第1邊受光感測器群之一之第η個第1邊光感 測器3 5 1 -η之平面擴大圖。凡例與圖5相同。此外，圖9 係顯示對應於圖8之C-C’線部的液晶顯示裝置910之部分 剖面構造圖。第η個第1邊光感測器35 1 -η係由陽極區域 610Ρ ( 610Ρ-η)、真性區域 6101 ( 610Ι-Π)、陰極區域 610Ν ( 610Ν-η )所形成的。陽極區域 610Ρ-η、真性區域 6101-η、陰極區域610Ν-η均係藉由對與形成畫素開關元 件41 0-n-m相同的多晶矽薄膜（Poly-Si )所構成的同一島 嶼圖案（island pattern)進行適切的不純物注入而分別形 成的。具體而言對陽極區域610P-η被注入高濃度的硼離 子使薄膜電阻被調整爲約21ίΩ，對陰極區域610Ν-Ι1被注 入高濃度的磷離子使薄膜電阻被調整爲約1 kQ。於真性區 域610I-n硼離子、磷離子都僅注入極微量，或者完全不注 入，被形成爲真性半導體。如此般第η個第1邊光感測器 35 1 -η被形成爲橫向（lateral )型PIN接合二極體。真性 區域6101-n之尺寸在平行於接合面的方向爲ΙΟΟμιη，在垂 直方向爲1 Ομηι。 此外，第η個第1邊光感測器3 5 1 -η係與全區域由鉻 薄膜（Cr)所構成的遮光電極61 1 ( 61 1-η)及與構成畫素 電極4〇2-n-m者相同的作爲銦錫氧化物薄膜（ITO)所構 成的透明遮蔽電極612之透明遮蔽電極612-n重疊而被形 成。遮光電極611-n係作爲防止背光926之光入射至第η 個第1邊光感測器35 1-η的遮光膜而發揮功能。此外，透 明遮蔽電極6 1 2 - η防止由於電磁雜訊導致照度檢測精度降 -20- 200914919 低。第η個第1邊光感測器351-n與第k個第1邊受光開 口部99 1-k重疊。在第k個第1邊受光開口部99l-k因爲 對向基板912上之黑矩陣94 0被除去’所以是以外光通過 第k個第1邊受光開口部991-k而到達第n個第1邊光感 測器3 5 1 - η的方式被形成。k係對應於n的數字，n = 8 1〜 160對應於k=l，n = 241〜320對應於k = 2 ’ n = 40 1〜80對 應於k = 3。 此處，陽極區域61〇P_n中介著接觸孔被接續於陽極 電極615(615-n)。此處，陰極區域610N-n中介著接觸 孔被接續於陰極電極616(616-n)。遮光電極611-n及透 明遮蔽電極6 1 2-n中介著接觸孔被接續於BT電極6 1 7 ( 6 17-n)。進而，雖未圖示，但陽極電極61 5·η被接續於配 線SENSEI，陰極電極616-η被接續於配線VSH1，ΒΤ電 極6 1 7 - η也被接續於配線V S Η 1。 又，除了第1邊遮光感測器群之一之第η ’個第〗邊光 感測器351-η’不與第k個第1邊受光開口部991-k重疊， 及陽極電極615(615-n)被接續於配線VSL1，陰極電極 616 (616-rT)被接續於配線 SENSEI，BT 電極 617 (617-n’）被接續於配線VDBT1以外，與第1邊受光感測器群 之一之第η個第1邊光感測器3 5 1 -η相同所以省略說明。 又，在本實施例，將遮光電極611-n、透明遮蔽電極 6 1 2 - η個別島嶼化，以相互間有間隙的方式形成，但因爲 第1邊受光感測器群與第1邊遮光感測器群相鄰的處所， 亦即除了 η = 80與η = 81之間、η=160與η=161之間、 -21 - 200914919 n=240 與 n=241 之間、n=320 與 n=321 之間、n=400 與 n = 4 0 1之間以外互爲相同電位，所以使其短路亦可。無論 如何，遮光電極間的間隙如本實施例這樣以某種金屬電極 覆蓋可以防止來自間隙的迷光，進而較佳者爲如果作爲金 屬電極使用匯流排線的話可以削減電路面積。 圖10係第2邊受光感測器群之一之第m個第2邊光 感測器3 52-m之平面擴大圖。凡例與圖5相同。第m個第 2邊光感測器352-m，係由陽極區域620P(620P-m)、真 性區域 6201 ( 620 I-m )、陰極區域 6 2 ON ( 6 2 ON - m )所形 成，被配置於資料線202-m與資料線2〇2-m + l之間，被形 成爲與第j個第2邊受光開口部9 92-j重疊。j係對應於m 的數字，m=l〜240對應於j = l，n = 481〜720對應於j=2 ，111==961 〜1200 對應於 j = 3，m=1441 〜1680 對應於 j=4。 除了陽極區域 620P-m、真性區域620I-m、陰極區域 62〇N-m分別之平行於接合面的長度爲25μηι以外，與圖8 之陽極區域 610Ρ-Π、真性區域 610Ι-η、陰極區域610Ν-η 係相同的構成所以省略其說明。此外，第m個第2邊光感 須〇器352-m係使全區域與遮光電極621 ( 62l-m)及透明 遮蔽電極622 ( 622-m )重疊而被形成，這些分別與圖8 之遮光電極6 1 1-n及透明遮蔽電極612-n爲相同的構成所 以省略說明。此外，陽極區域620P-m與陽極電極625 ( 625 -m)中介著接觸孔而被接續，陰極區域620N-m與陽 極電極626 ( 626-m)中介著接觸孔而被接續’遮光電極 621-m及透明遮蔽電極622-m係與BT電極627 ( 627-m) -22- 200914919 中介著接觸孔而被接續，這些也與圖8之陽極電極615-η 、陰極電極616-η、ΒΤ電極617-η爲相同的構成所以省略 說明。沿著圖10的D-D，之剖面圖也除了符號以外與圖9 之C-C’之剖面圖沒有不同，故省略說明。 又，除了第2邊遮光感測器群之一之第m’個第2邊 光感測器352-m’不與第j個第2邊受光開口部992-j重疊 ，及陽極電極62 5 ( 625 -m )被接續於配線VSL2，陰極電 極626 ( 626-m’）被接續於配線SENSE2，BT電極627 ( 627-m’）被接續於配線VDBT2以外，與第2邊受光感測 器群之一之第m個第2邊光感測器3 52-m相同。 第η個第3邊光感測器3 5 3 -η與第η個第1邊光感測 器351-η相比，除了位於電容線203 -n-l與電容線2〇3_η 之間，圖 8所示之配置旋轉1 8 0度，使連接於配線 SENSEI >配線VSH1、酉己線VSL1、配線BDBT1的部分接 續於配線SENSE3、配線VSH3、配線VSL3、配線VDBT3 是不同的以外其他都相同所以省略說明。此外，同樣的’ 第m個第4邊光感測器3 54-m與第m個第2邊光感測器 352-m相比，除了圖10所示之配置旋轉180度，使連接 於配線SENSE2、配線VSH2、配線VSL2、配線BDBT2的 部分接續於配線SENSE4、配線VSH4、配線VSL4、配線 VDBT4是不同的以外其他都相同所以省略說明。 圖1 1係作爲檢測電路3 6 0顯示第η個檢測電路3 6 0 - η (η=1〜4 )之電路圖。配線SMP、配線VCHG、配線RST 、配線V S L、配線V S Η係與訊號輸入端子3 2 0接續，由 -23- 200914919 外部電源電路7 8 4供給適切之電位/訊號。此處配線v C η G 供給電位VVCHG ( =2.0V )、配線VSL供給電位VVSL ( = 0.0V )、配線VSH供給電位VVSH ( =5_0V )。又，此處 配線V S L的電位V V S L係液晶顯示裝置9 1 0的接地（GN D )。輸出配線〇 UTn被接續於多數決電路3 70。 此外’配線VDBT ( VDBTn )被接續於第1開關SW1 之一端’配線VSL(VSLn)被接續於第2開關SW2之一 端，配線VSH ( VSHn)被接續於第3開關SW3之一端， 配線SENSE ( SENSEn)被接續於第4開關SW4之一端。 此處第1開關S W 1〜第4開關S W 4係以C Μ Ο S傳送閘所 構成。第1開關S W1之另一端被接續於配線ν C η G，第2 開關S W 2之另一端被接續於配線V S L，第3開關S W 3之 另一端被接續於配線C SH，第4開關S W4之另一端被接 續於節點SIN。構成第1開關SW1〜第4開關SW4的所有 的η通道型電晶體之閘極電極被接續於配線SMP，所有的 Ρ通道型電晶體之閘極電極被接續於反相器電路IN V 1之 輸出端子。此外反相器電路INV 1之輸入端子被接續於配 線 SMP。 節點S IN被接續於第1電容器C1之一端，第1電容 益C 1之另一端被接續於節點A。初期化電晶體N C之源極 電極被接續於配線V C H G，被供給電位V V C Η ( = 2 · 0 V ) 之電源。初期化電晶體NC之閘極電極被接續於配線RST ’汲極電極被接續於配線S EN S Εη。節點Α進而被接續於 第1之N型電晶體Ν1的閘極電極與第1之P型電晶體ρ 1 -24- 200914919 的閘極電極與重設（reset )電晶體NR的汲極電極，進而 被接續於第2電晶體C2的一端。第2電容器C2之另一端 被接續於配線R S T。第1之n型電晶體N1的汲極電極與 第1之P型電晶體P1的汲極電極與重設電晶體NR的源 極電極被接續於節點B，節點b進而被接續於第2之N型 電晶體N 2的閘極電極與第2之P型電晶體p 2的閘極電極 。第2之N型電晶體N 2的汲極電極與第2之P型電晶體 P 2的汲極電極被接續於節點c ’節點C進而被接續於第3 之N型電晶體N3的聞極電極與第3之P型電晶體P3的 閘極電極。第3之N型電晶體N 3的汲極電極與第3之P 型電晶體P 3的汲極電極被接續於節點D，節點〇進而被 接續於第4之N型電晶體N4的閘極電極與第4之P型電 晶體P 4的閘極電極。第4之N型電晶體N4的汲極電極 與第4之P型電晶體P4的汲極電極被接續於輸出配線 OUTn ’輸出配線OUTn進也被接續於第5之N型電晶體 Ν5的汲極電極。第5之Ν型電晶體Ν5的閘極電極與第5 之Ρ型電晶體Ρ5的閘極電極被接續於配線RST，第5之 Ρ型電晶體Ρ5的汲極電極被接續於第4之Ρ型電晶體Ρ4 的源極電極。第1之Ν型電晶體Ν1〜第5之Ν型電晶體 Ν5之源極電極被接續於配線VSL，被供給電位VVSL (= 〇V )。此外第1之Ρ型電晶體Ρ1〜第3之Ρ型電晶體Ρ3 以及第5之Ρ型電晶體Ρ5之源極電極被接續於配線VSH ，被供給電位V V S Η ( = + 5 V )。此外，反相器電路IN V 1 被供給+9V與-4V之電源。 -25- 200914919 此處在本實施例，第1之N型電晶體N1的通道寬幅 爲ΙΟμπι，第2之N型電晶體N2的通道寬幅爲35μιη，第 3之Ν型電晶體Ν3的通道寬幅爲ΙΟΟμηι，第4之Ν型電 晶體Ν4的通道寬幅爲150μιη，第5之Ν型電晶體Ν5的 通道寬幅爲150μιη，第6之Ν型電晶體Nil的通道寬幅爲 4μιη，第7之N型電晶體N21的通道寬幅爲200μηι，第1 之Ρ型電晶體Ρ1的通道寬幅爲ΙΟμιη，第2之Ρ型電晶體 Ρ2的通道寬幅爲35μηι，第3之Ρ型電晶體Ρ3的通道寬 幅爲ΙΟΟμιη，第4之Ρ型電晶體Ρ4的通道寬幅爲300μιη ，第5之Ρ型電晶體Ρ5的通道寬幅爲300μηι，第6之Ρ 型電晶體PI 1的通道寬幅爲200μπι，第7之Ρ型電晶體 Ρ21的通道寬幅爲4μηι，重設電晶體NR的通道寬幅爲 2μηι，初期化電晶體NC之通道寬幅爲50μηι，構成第1開 關S W 1〜第4開關S W4之Ν型電晶體及Ρ型電晶體之通 道寬幅爲1〇〇μηι，構成反相器電路INV1及反相器電路 INV2之型電晶體及Ρ型電晶體之通道寬幅爲50μηι，所有 的Ν型電晶體之通道長爲8μηι，所有的Ρ型電晶體之通道 長爲6μηι，所有的Ν型電晶體之移動度爲80cm2/Vsec，所 有的P型電晶體之移動度爲60cm2/Vsec，所有的N型電 晶體之閾値電壓（Vth)爲+1.0V，所有的P型電晶體之閾 値電壓（Vth)爲-1.0V，第1電容器C1之電容爲1PF，第 2電容器C2的電容爲38fF。 圖1 2係被施加至配線RST、配線SMP、共通電位配 線3 3 5、掃描線201-1、掃描線201-2的訊號之計時圖。又 -26- 200914919 ，以圖之易辨認性爲優先’縱橫軸之尺度並非固定。掃描 線2 0 1 - 1、掃描線2 0 1 - 2係藉由掃描線驅動電路3 0 1所驅 動，每1 6.7 m秒被選擇3 1.2 μ秒鐘。掃描線2 0 1 - 2在掃描 線2 ο 1 -1被選擇起3 4.6 μ秒後被選擇’以下掃描線2 01 _ 3 、20 1-4、...係以34.6μ秒的間隔依次被選擇。共通電位配 線3 3 5於每3 4.6 μ秒在H i g h電位（=5 V )與L 〇 w電位（ =〇 V )間反轉，但每1 6 · 7 m秒相位偏移半個週期。因此’ 掃描線201-n每次被選擇時被施加於共通電位配線335的 極性會反轉’亦即所謂的進行1 H共同反轉驅動。RST訊 號在掃描線2 0 1 - 1被選擇的3 2.9 μ秒前被選擇2 7.7 μ秒鐘 。此時，共通電位配線3 3 5的電位必爲L 〇 w電位（=0 V ) ，所有的掃描線201-1〜20 1 -48 0未被選擇。SMP訊號在 共通電位配線3 3 5爲L 〇 w的期間’藉由共通電位配線3 3 5 之反轉計時而在3·5μ秒後被選擇27.7μ秒鐘。RST訊號爲 ◦ Ν的期間SMP訊號必爲ON。此處’ RST訊號、SMP訊 號、掃描線201-n選擇時，亦即High電位爲+ 9V，非選擇 時，亦即Low電位爲-4V。 如此構成的話，在配線RST爲High ( = + 9V )的計時 於配線SENSEn及節點SIN被充電電位VVCHG ( =2.0V ) 。此外，於配線 VDBTn被充電電位 VVCHG，於配線 VSLn被充電電位VVSL，於配線VSH被充電VVSH。此外 ，重設電晶體NR打開（ON )，所以節點A與節點B短 路，於本實施例，兩節點被充電於2.5 V。又，配線R S T 爲High ( =9V )的期間第5之N型電晶體N5打開（ON ) -27- 200914919 ，第5之P型電晶體P5關閉（OFF )，所以輸出配線 OUTn 爲 0V。 配線RST於2 7·7μ秒後成爲Low ( =-4V )時，重設電 晶體NR關閉，節點A與節點B電氣切離，節點A藉由第 2電容器C 2的結合而電位與配線R s T同時下降0 · 5 V成爲 2.0V。配線RST於27·7μ秒後成爲Low ( =-4V )的瞬間， 配線SENSEn爲電位VVCHG ( =2.0V )，配線VSLn爲電 位 VVSL(=0.0V)，配線 VSHn 爲電位 VVSH(=5.0V) 。亦即’由第1邊之受光感測器群對第4邊之受光感測器 群爲被施加逆向偏壓3.0V，由第1邊之遮光感測器群對第 4邊之遮光感測器群爲被施加逆向偏壓2.0V。此外，由輸 出配線OUTn被輸出電位VVSL。此時，由第1邊之受光 感測器群往第4邊之受光感測器群，與由第丨邊之遮光感 測器群往第4邊之遮光感測器群流動的熱電流大致變得相 等，於配線SENSEn流入比例於從第1邊之受光感測器群 往第4邊之受光感測器群照射的外光照度之光電流Iphoto ，配線SENSEn的電位以比例於光電流Iphot〇的速度上升 。於配線V S Η η、配線V S L η也有電流流過，都些許接近 配線SENSEn的電位，每69.2μ秒以配線SMP成爲High (=9V )的計時使第開關SW2及第3開關SW3成爲打開 (ON )而回到原來的電位，幾乎沒有變化。 又，配線SENSEn的電位變化的速度與被照射至第η 邊的受光感測器群之光量的關係以一次式表示，顯示其斜 率的係數係由配線SENSΕη及被接續於其之第^邊的受光 • 28 - 200914919 感測器群之陽極電極及第n邊之遮光感測器群之陰極電極 的負荷電容的總和所決定，在本實施例顯示此斜率之係數 係以從第1邊至第4邊（η= 1〜4 )沒有差異’亦即由第1 邊之受光感測器群在第4邊之受光感測器群之一定光量之 「光電流Iphotoj +「配線SENSEn」之電容係以在各邊成 爲相等的方式調整的。 如此般配線R s T爲L 〇 w ( = - 4 V )的期間，節點A成 爲浮動狀態，所以藉由與第1電容器C1之電容結合而與 節點 SIN結合電位同時上升，節點 A及節點SIN成爲 2.5V時輸出配線OUTn的電位反轉爲High ( =5V )。 在本實施例由第1邊之受光感測器群起第4邊之受光 感測器群被配置爲接近顯示區域310，陽極電極615-Π、 陰極電極6 1 6 - η、B T電極6 1 7 - η與共通電位配線3 3 5交叉 。此外，掃描線201-η'資料線202-m、電容線203 -η之 任一都存在著與經由遮光電極的電容，通過這些電容容易 混入電磁雜訊。特別是共通電位配線3 3 5與配線SENS Εη 藉由無法忽視的電容而結合，由於共通電位配線3 3 5的極 性使得配線 SENS Εη的電位上上下下。作爲一例於圖1 2 顯示配線SENS Εη之計時圖。如此般，配線SENS Εη在共 通電位配線335反轉爲Low(=〇V) —High(=5V)時藉由 電容結合使Δν電位上升，反轉爲High (=5V) —Low ( =0 V )時Δ V電位下降。但是，在本實施例，s Μ P訊號僅 在ON之計時導通節點SIN與配線SENSEn，所以如圖1 2 所示’在節點SIN’極性反轉時不變動。亦即不會產生由 -29- 200914919 於共通電位配線3 3 5之反轉所導致的誤動作。 同樣地在本實施例，配線VDBTn、配線VSLn、配線 VSHn ( n=l〜4 )也僅在SMP訊號爲打開（on )的計時分 別與配線V C H G、配線V S L、配線V S Η導通，在S Μ P訊 號關閉（OFF )的計時成爲浮動狀態。如此構成的話，配 線VDBTn、配線VSLn、配線VSHn(n=l〜4)也在共通 電位配線3 3 5之極性反轉時因電容結合而僅變動Δ v之電 位。亦即’即使共通電位配線3 3 5之極性反轉由第1邊之 受光感測器群對第4邊之受光感測器群施加的偏壓與由第 1邊之遮光感測器群對第4邊之遮光感測器群施加的偏壓 不會改變’亦即由第1邊之受光感測器群往第4邊之受光 感測器群流動的光電流Ipho to與熱電流及由第1邊之遮光 感測器群往第4邊之遮光感測器群流動的熱電流不隨共通 電位配線3 3 5的極性改變而維持一定。 在本實施例因爲A V比較大所以採這樣的構成，但在 △ V比較小之不滿IV的場合，亦可除去第1開關SW1、 第2開關SW2、第4開關SW4。作爲這樣的場合之檢測電 路之其他構成例之檢測電路3 60’的第η檢測電路3 60，-n 之電路圖顯示於圖13。在本其他實施例與圖11所示之第 η個檢測電路360-n相比，第1開關SW1〜第4開關SW4 被除去，配線VDBTn與配線VCHG短路，配線VSLn與 配線 VSL短路，配線 VSHn與配線 VSH短路，配線 SENSEn與節點SIN短路。採這樣的構成的話，節點SIN 顯示因應於共通電位配線3 3 5的極性之振幅（成爲正好如 -30- 200914919 圖12的配線SENSEn所示之圖）。因此，維持原狀跨全 期間進行檢測動作的話，共通電位配線3 3 5反轉爲High ( =5V )時會引起誤動作。在此，除去第3之N型電晶體N3 〜第5之N型電晶體及第3之P型電晶體〜第5之P型電 晶體P 5，替代地將第2N型電晶體N2與第2P型電晶體 P2之汲極電極接續於第1NAND電路NAND1之輸入端子 之一，將第1NAND電路NAND1之輸入端子之另一方接續 於SMP訊號，將第1NAND電路NAND1之輸出端子接續 於第 2NAND電路 NAND2之輸入端子之一方，將第 2NAND電路 NAND2之輸入端子之另一方接續於第 3NAND電路 NAND3之輸出端子，將第 3NAND電路 NAND3之輸入端子之一方接續於第2NAND電路NAND2 之輸出端子，將第3NAND電路NAND3之輸入端子之另一 方接續於反相器電路INV3之輸出端子，將反相器電路 INV3之輸入端子接續於配線 RST。第 1NAND電路 NAND1〜第3NAND電路NAND3以及反相器電路INV3之 電源接續於配線VSH及配線VSL。其他之電路構成與動 作與圖1 1相同所以賦予相同符號而省略說明。如此構成 的話，節點SIN的電位爲2.5V以上且僅在SMP訊號爲 High時，第 1NAND電路NAND1的輸出成爲 Low。第 2NAND電路NAND2與第3NAND電路NAND3成爲RS觸 發器電路（flip-fl〇P) ’第1NAND電路NANDI的輸出成 爲負極性之設定（set )訊號，反相器電路INV3之輸出成 爲負極性之重設（reset)訊號。亦即重設（RESET )訊號 -31 - 200914919 成爲High ( =9V )時對輸出配線OUΤη之輸出被閂鎖於 Low，節點SIN的電位爲2.5V以上且SMP訊號成爲High 之最初的計時往輸出配線〇UTn之輸出被閂鎖於High。亦 即，共通電位配線3 3 5在High ( =5V)之期間之檢測結果 被視爲無效，不會引起誤動作。 圖14係多數決電路3 70之電路圖。於第4NAND電路 NAND11 、第 5NAND 電路 NAND12 、第 6NAND 電路 NAND13 、第 7NAND 電路 NAND14 、第 8NAND 電路 NAND15、第 9NAND電路N A N D 1 6之輸入端子分別順歹丨J 組合而接續輸出配線 OUT 1〜OUT4之中的任兩條。第 4NAND 電路 NAND11 、第 5NAND 電路 NAND12 、第 6NAND電路NAND13之輸出端子被接續於第10NAND電 路NAND21的輸入端子，第 7NAND電路NAND14、第 8NAND電路NAND15、第9NAND電路NAND16之輸出端 子被接續於第 11NAND電路 NAND22的輸入端子，第 10NAND 電路 NAND21、第 1 1NAND 電路 NAND22 之輸出 端子被接續於第1NOR電路30的輸入端子，第1NOR電 路30之輸出端子被接續於反相器電路in V4之輸入端子， 反相器電路INV4之輸出端子被接續往輸出配線OUT。於 第 4NAND 電路 NAND11 、第 5NAND 電路 NAND12、 第 6NAND 電 路 NAND13、 第 7NAND 電路 NAND14、 第 8NAND 電 路 NAND15 、 第 9NAND 電路 NAND16 、 第 1 0NAND 電路 NAND21 、 第 1 1NAND 電路 NAND22、 第 1NOR電路30之電源被接續於配線VSH及配線VSL。此 -32- 200914919 電路，是對輸出配線〇UT1〜0υτ4之中’任何二以上 線成爲High (=5V)時往輸出配線OUT輸出High (= ，輸出配線OUT1〜OUT4之全部爲Low(=〇V)或是 任一爲High (=5V)時往輸出配線OUT輸出Low (= 之電路。如此構成的話，配線RST成爲Low(=-4V) 直到輸出配線OUT反轉爲High (=5V)爲止的時間 爲反比例於由第1邊之受光感測器群起第4邊之受光 器群之中，光之照射量第2大的邊之光照射量。在本 例如此般搭載多數決電路3 7 0 ’各邊之照度檢測結果 ，排除照度最高的結果以防止在該邊由於有很強的光 時發生誤動作。此外，原本就排除照度低的結果以及 第2低的結果，例如即使在4邊之中有兩邊有手指等 子也可以得到正確的結果。 圖1 5係本實施例之根據來自輸出配線OUT之輸 外部光檢測照度與背光亮度之設定例。被設定爲在外 度非常低時使背光亮度和緩變化，徐徐使變化增大在 照度5 00Lux時使亮度變化達到最大之後，再使其和 變化之S字形曲線，在1 5 00LUX以上以保持最大亮度 式設定。因應於電子機器的特性此曲線亦可自由設定 了防止亮度的明滅以一定期間之平均値使其和緩地改 可，亦可以使亮度與照度之關係具有滯後現象（hyste )。此外，亦可因應於等待時與操作時等，電子機器 作狀態等而使曲線改變。 如此般，在本實施例即使讓受光開口部極爲接近 之配 5V ) 僅有 0V ) 之後 ，成 感測 實施 之中 點光 照度 之影 出的 部照 外部 緩地 的方 ，爲 變亦 r e s i s 之操 顯不 -33- 200914919 區域，使用共同反轉驅動法也不會有誤動作’因 的精度很高總是可以把顯示裝置設定於最適當的 以提高視覺確認性同時對降低耗電量也有貢獻。 1邊〜2邊以手指蓋住，或是光點光照到某一處 以正確測定外環境光，使背光亮度總是保持於最1 [第2實施型態] 圖16係相關於第2實施例之第1邊受光感 一之第η個第1邊光感測器351-n的平面擴大圖 於第1實施例之圖8之圖。凡例與圖5相同。以 8之不同點爲中心說明圖1 6。 在圖16與圖8不同，掃描線201-n係在與 6 1 1 _n平面重疊的區域中介著接觸孔以鋁銨合: A1N d )所形成的配線來構成，在掃描線2 0 1 - η與 6 1 hn之間被形成以鉬（Mo )構成的共通電位 6 1 8 。共通電位分枝配線6 1 8 -η係中介著接觸孔 電位配線接續，被提供共通電位（COM )。其他 1 6與圖8沒有不同所以賦予相同符號而省略說明 圖1 7係相關於第2實施例之第2邊受光感 一之第η個第2邊光感測器352-n的平面擴大圖 於第1實施例之圖1 〇之圖。凡例與圖5相同。 圖1 0之不同點爲中心說明圖1 7。 在圖17與圖10不同，資料線202-n與遮光 (62 1 -η )在平面重疊的區域間被形成以鉬薄膜 爲光檢測 売度，可 此外，有 所時也可 測器群之 ，係對應 下以與圖 遮光電極 薄膜（ 遮光電極 汗枝配線 而與共通 之點’圖 〇 測器群之 ，係對應 以下以與 電極621 :Mo )構 -34- 200914919 成的共通電位分枝配線6 2 8 - η。共通電位分枝配練6 2 8 係中介著接觸孔而與共通電位配線接續，被提供共通胃& (COM)。其他之點，圖17與圖1 〇沒有不同所以賦予相 同符號而省略說明。 本實施例之主動矩陣基板101、液晶顯示裝置91〇白勺 構成與第1實施例同樣，電子機器的構成、外光照度與离 度之設定也與第1實施例相同所以省略說明。 在本實施例與第1實施例比較，掃描線2 0 1 - η與@ % 電極611-η平面重疊的部分，以及資料線202-η與遮光電 極6 2 1 - η平面重疊的部分，隔著間隔被配置連接於共通電 位配線3 3 5之共通電位分枝配線6 1 8 - η、6 2 8 - η，所以不具 有直接之交叉電容。因此，掃描線201-η、資料線2〇2_η 的電位改變時，亦即掃描線2 0 1 - η以掃描線驅動電路3 〇 1 選擇的計時或是資料線202-η以資料線驅動電路3 02或預 充電電路3 03而被寫入不同的電位（影像）時遮光電極 61卜η與遮光電極621-η的電位也不易變動。遮光電極 61 1-η以及遮光電極621 -η之電位改變時配線SENSEI、配 線SENS E2之電位也隨著電容結合而改變，本實施例與第 1實施例相比，可以進行精度更高的照度測定。此外，夾 於間隙供遮蔽之用的配線連接於共通電位配線3 3 5，所以 不需要新配線遮蔽用的電源。共通電位配線3 3 5爲了維持 畫質原本即已低阻抗來配置，所以作爲遮蔽電位使用極爲 有效。共通電位配線3 3 5因爲被反轉驅動所以有成爲對遮 光電極之雜訊的問題，但在本實施例因爲進行與第1實施 -35- 200914919 例同樣的驅動，所以不會有因爲與共通電 合而導致電位變動之精度降低。另一方面 共通電位配線3 3 5之電容增大，所以會有 問題。若要選擇第1實施例的構成或第2 任一，只要考量以上所述之優點、缺點再 使用用途來選擇即可。 又，在本實施例僅關於重疊於第n之 3 5 1 - η、第η之第2邊光感測器3 5 2 - η的遮 ，因應需要將同樣的對策應用於第η之| 353-η、第η之第4邊光感測器354-η的遮 [第3實施型態] 圖1 8係相關於第3實施例之主動矩 塊圖，以下，說明與第1實施例之圖2所 板101之差異，針對與第1實施例之圖2 予同一記號而省略說明。在本實施例，替 第1邊光感測器351-1〜3 5 1 -480作爲光感 感測器351’-1〜351’-4 80作爲光感測器3: 第2邊光感測器352_1〜352-1920作爲光 光感測器3 5 2’-1〜3 52’· 1 920作爲光感測: 替代第3邊光感測器3 5 3 - 1〜3 5 3 -48 0作爲 邊光感測器3 5 3 ’ -1〜3 5 3，-4 8 0作爲光感測 替代第4邊光感測器3 5 4 - 1〜3 54- 1 920作 4邊光感測器354’-1〜354’-1920作爲光！ 位配線之電容結 ，本實施例因爲 ‘耗電量增大等的 實施例之構成之 因應電子機器的 第1邊光感測器 :光電極尋求對策 春3邊光感測器 光電極亦可。 陣基板1 0 2之方 示的主動矩陣基 相同的構成者賦 代第1實施例之 測器之第1邊光 5 Γ被配置，替代 感測器之第2邊 器3 5 2 ’被配置， 丨光感測器之第3 器3 5 3 ’被配置， 爲光感測器之第 惑測器3 54’被配 -36 - 200914919 置。此外替代第1檢測電路3 6 0 - 1〜第4檢測電路3 6 0 - 4 配置檢測電路3 6 1。 第1邊光感測器351’-1〜351’-4 80之中，與第1之第 1邊受光開口部991-1〜第3之第1邊受光開口部991-3重 疊者（第1邊受光感測器群）與配線SENSE(SENSEP) 接續’均沒有重疊者（第1邊遮光感測器群）與配線 SENSE ( SENSED )接續。同樣地第2邊光感測器3 5 2，-1 〜352’-1920之中，與第1之第2邊受光開口部992-1〜第 4之第2邊受光開口部9 92-4重疊者（第2邊受光感測器 群）與配線SEN SEP接續，均沒有重疊者（第2邊遮光感 測器群）與配線SENSED接續；第3邊光感測器3 5 3 ’-1〜 3 5 3’-48 0之中，與第1之第3邊受光開口部993 - 1〜第3 之第3邊受光開口部993 -3重疊者（第3邊受光感測器群 )與配線SENSEP接續，均沒有重疊者（第3邊遮光感測 器群）與配線SENSED接續；第4邊光感測器3 54’-1〜 354’-1920之中，與第1之第4邊受光開口部994-1〜第4 之第4邊受光開口部994-4重疊者（第4邊受光感測器群 )與配線SENSEP接續，均沒有重疊者（第4邊遮光感測 器群）與配線 SENSED接續。配線 SENSED與配線 S EN S E P被接續於檢測電路3 6 1，檢測電路3 6 1之輸出配 線OUT通過訊號輸入端子3 20往外部連接。 圖1 9係相關於第3實施例之第1邊受光感測器群之 一之第η個第1邊光感測器351，-η的平面擴大圖’係對應 於第1實施例之圖8之圖。凡例與圖5相同。以下以與圖 -37- 200914919 8之不同點爲中心說明圖1 9。 圖19之第η之第1邊光感測器351’-η係由陽極區域 610Ρ，（610Ρ’-η)、真性區域 610Ι’（610Ι’-η)、陰極區 域61 ON，（610Ν’-η)所構成之橫向（lateral)型PIN二極 體，這些分別與第1實施例之圖8所說明的陽極區域 610P-n、真性區域6101-n、陰極區域610N-n爲相同構成 所以省略說明。陽極區域6 1 0P ’ -η中介著接觸孔被接續於 陽極電極615’（615’- η)，陽極電極615’-η被接續於配線 8£>^£?。陰極區域61(^’-]1、遮光電極611’（611’-11)、 作爲透明遮蔽電極612 ’之透明遮蔽電極612’-η分別透過 接觸孔被接續於共通電位配線3 3 5 ’被提供共通電位（ COM )。其他之點，圖1 9與圖8沒有不同所以賦予相同 符號而省略說明。 針對第1邊遮光感測器群之一之第η’之第1邊光感測 器35 1，-η’，除了與第1之第1邊受光開口部991-1〜第3 之第1邊受光開口部991 _3之任一均不重疊，與陽極電極 615,（ 61 5’-η’）被連接於配線SENSED以外與圖19所說 明的相同所以省略。 圖20係相關於第3實施例之第2邊受光感測器群之 一之第m個第2邊光感測器352’-m的平面擴大圖’係對 應於第1實施例之圖1〇之圖。凡例與圖5相同。以下以 與圖1 〇之不同點爲中心說明圖2 0。 圖20之第m之第2邊光感測器3 52’-m係由陽極區域 620P，（62〇P’-m) ' 真性區域 620I’（ 620I’-m)、陰極區 -38- 200914919 域 620N，（ 620N’-m)所構成之橫向（lateral)型 PIN 二 極體，這些分別與第1實施例之圖1 〇所說明的陽極區域 620P-m、真性區域620I-m、陰極區域620N-m爲相同構成 所以省略說明。陽極區域62 OP’-m中介著接觸孔被接續於 陽極電極625’（ 625’- m)，陽極電極625’- m被接續於配 線 SENSEP。陰極區域 620N’-m、透明遮蔽電極 622’（ 622’·η )、遮光電極621 ’（ 621 ’-η )分別透過接觸孔被接 續於共通電位配線3 3 5，被提供共通電位（COM )。其他 之點，圖20與圖1 0沒有不同所以賦予相同符號而省略說 明。 針對第2邊遮光感測器群之一之第η ’之第2邊光感測 器352,-η’，除了與第1之第2邊受光開口部992-1〜第4 之第2邊受光開口部992-4之任一均不重疊’與陽極電極 625,（ 625’-ιΓ )被連接於配線SENSED以外與圖19所說 明的相同所以省略。 第η之第3邊光感測器3 5 3 ’ -η與第η之第1邊光感測 器3 5 1，- η比較，除了位於電容線2 0 3 -η -1與電容線2 0 3 - η 之間，圖20所示之配置旋轉1 8〇度以外餘皆相同所以省 略說明。此外，第η之第4邊光感測器3 54’ — η與第η之第 2邊光感測器3 5 2 ’ - η比較’除了圖2 0所示之配置旋轉1 8 0 度以外餘皆相同所以省略說明° 圖21係檢測電路3 61之電路圖。配線SMP1、配線 S Μ P 2、配線R S T、配線V C H G、配線V S L、配線V S Η係 與訊號輸入端子3 2 〇接續，由外部電源電路7 8 4供給適切 -39- 200914919 之電位/訊號。此處配線 VCHG供給電位 VVCHG (=-2.0V )、配線VSL供給電位VVSL ( =0.0V )、配線VSH 供給電位 V V S Η ( = 5 · 0 V )。又，此處配線 V S L的電位 VVSL係液晶顯示裝置910的接地（GND )。輸出配線 ◦ UTn與訊號輸入端子3 20接續，往外部電路輸出。 配線SENSED被接續於第5開關SW5之一端，配線 SENSEP被接續於第6開關SW6之一端。第5開關SW5 及第6開關S W6之另一端都被接續至節點S IN ’。此處第 5開關SW5〜第6開關SW6係以CMOS傳送閘所構成。構 成第5開關SW5的η通道型電晶體之閘極電極被接續於 配線SMP 1，P通道型電晶體之閘極電極被接續於反相器 電路IN V 5之輸出端子。反相器電路IN V5之輸入端子被 接續於配線SMP1。此外構成第6開關SW6的η通道型電 晶體之閘極電極被接續於配線S ΜΡ2，ρ通道型電晶體之 閘極電極被接續於反相器電路IN V 6之輸出端子。反相器 電路INV6之輸入端子被接續於配線SMP2。 此外，節點S IN ’被接續於第3電容器C 3之一端與初 期化電晶體NC’之汲極電極，第3電容器C3之另一端被 接續於節點A ’。初期化電晶體NC ’之源極電極被接續於配 線V C H G ’被供給電位V V C H G ( = - 2 · 0 V )之電源。初期 化電晶體N C ’之閘極電極被連接於配線r s Τ。節點A，進而 被接續於第6之N型電晶體N，1的閘極電極與第6之P型 電晶體P ’ 1的閘極電極與重設（r e s e t )電晶體N R，的汲極 電極，進而被接續於第4電晶體C4的一端。第4電容器 -40- 200914919 C4之另一端被接續於配線RST。 第6之N型電晶體N ’1的汲極電極與第6之P型電晶 體P’l的汲極電極與重設電晶體NR’的源極電極被接續於 節點B’ ’節點B’進而被接續於第7之n型電晶體n，2的 閘極電極與第7之P型電晶體P ’ 2的閘極電極。第7之N 型電晶體N ’ 2的汲極電極與第7之P型電晶體P ’ 2的汲極 電極被接續於節點C ’’節點C ’進而被接續於第8之N型 電晶體Ν’3的閘極電極與第8之P型電晶體P’3的閘極電 極。第8之N型電晶體N ’ 3的汲極電極與第8之P型電晶 體P ’ 3的汲極電極被接續於節點D ’，節點D，進而被接續 於第9之N型電晶體N ’ 4的閘極電極與第9之P型電晶體 P ’ 4的閘極電極。第9之N型電晶體N ’ 4的汲極電極與第 9之P型電晶體P’4的汲極電極被接續於輸出配線ουτ， 輸出配線OUT進也被接續於第10之N型電晶體N’5的汲 極電極。第10之N型電晶體N’5的閘極電極與第1〇之p 型電晶體P ’ 5的閘極電極被接續於配線R s T，第1 0之p 型電晶體P’5的汲極電極被接續於第9之P型電晶體P’4 的源極電極。第6之N型電晶體Ν’1〜第10之N型電晶 體Ν ’ 5之源極電極被接續於配線V S L，被供給電位V V S L (=0V )。此外第6之Ρ型電晶體p’l〜第8之Ρ型電晶 體P’3以及第10之P型電晶體P’5之源極電極被接續於 配線V S Η，被供給電位V V S Η ( = + 5 V )。此外，反相器 電路INV5及反相器電路INV6被供給+9V與-4V之電源。 此處在本實施例，第6之Ν型電晶體ν ’ 1的通道寬幅 -41 - 200914919 爲ΙΟμιη，第7之N型電晶體N’2的通道寬幅爲35μηι，第 8之Ν型電晶體Ν’3的通道寬幅爲ΙΟΟμιη，第9之Ν型電 晶體Ν’4的通道寬幅爲150μηι，第10之Ν型電晶體Ν’5 的通道寬幅爲150μπι，第6之Ρ型電晶體P’l的通道寬幅 爲ΙΟμιη，第7之P型電晶體P’2的通道寬幅爲35μπι，第 8之Ρ型電晶體P’3的通道寬幅爲ΙΟΟμιη，第9之Ρ型電 晶體P’4的通道寬幅爲3 00μηι，第10之Ρ型電晶體P’5 的通道寬幅爲300μηι，重設電晶體 NR’的通道寬幅爲 ΙΟμηι，初期化電晶體NC’之通道寬幅爲150μπι，構成第5 開關S W5〜第6開關SW6的Ν型電晶體及Ρ型電晶體之 通道寬幅爲1〇〇8μιη，構成反相器電路INV5及反相器電路 INV6的Ν型電晶體及Ρ型電晶體之通道寬幅爲50μιη，這 些所有的Ν型電晶體之通道長爲8 μηι，所有的Ρ型電晶體 之通道長爲 6μηι，所有的 Ν型電晶體之移動度爲 80cm2/Vsec，所有的Ρ型電晶體之移動度爲60cm5/Vsec， 所有的N型電晶體之閾値電壓（Vth )爲+ 1 . 0 V，所有的P 型電晶體之閾値電壓（Vth)爲-1.0V，第3電容器C3之 電容爲lpF，第4電容器C4的電容爲38fF。 其次圖22本實施例之計時圖。以圖之易辨認性爲優 先，縱橫軸之尺度並非固定。針對共通電位配線3 3 5、掃 描線201 -1、掃描線201 -2、配線RST如同在第1實施例 之圖12所說明的，因此省略說明。配線SMP1在共通配 線3 3 5爲Low ( =0V )時被選擇13.8μ秒，週期爲69·2μ 秒。配線SMP2同樣在共通配線3 3 5爲Low時接著配線 -42 - 200914919 SMP1被選擇13·8μ秒。配線SMPl、配線SMP2在選擇時 ，亦即電位爲High時係+9V之訊號，而在非選擇時，亦 即電位爲Low時爲-4V之訊號。 如此般構成電路的話，共通電位配線3 3 5在Low ( = 〇V)的期間首先配線SMP1被選擇，配線SENSED與節 點SIN’接續，同時節點A’與節點B’藉由重設電晶體NR’ 而短路，被充電至2 · 5 V。此間往輸出配線OUT之輸出必 爲Low ( =〇V )。其次13·8μ秒後配線SMP1成爲非選擇 同時配線SMP2被選擇’配線SEN SEP與節點SIN’接續， 節點1與節點B’被電氣分離同時藉由第4電容器C4使節 點A’之電位降低至2·〇ν。此後’通過第5開關SW5節點 SIN’的電位由配線SENSED的電位朝向配線SENSEP變動 ，藉由電容結合使得節點 A ’的電位也改變。亦即，配線 SMP2在成爲非選擇之前’節點A之電位爲「2.0V」+「 配線SENSEP的電位」-「配線SENSED的電位」，此値 超過2.5V的話檢測電路361往輸出配線OUT輸出High。 配線S EN S E D之電位以比例於由第1邊之遮光感測器群往 第4邊之遮光感測器群流過的熱電流成比例之斜率改變’ 配線SENSEP的電位以與由第1邊之受光感測器群往第4 邊之受光感測器群流動的「熱電流」+「光電流1Photo」 成比例的斜率改變，所以配線S E N S E P與配線S E N S E D之 電位差以與光電流Iph〇t〇成比例的斜率改變。由此’與第 1實施例同樣，配線RST成爲非選擇起直到輸出配線OUT 最初成爲H i g h爲止的期間成爲比例於外光照度的倒數。 -43- 200914919 其次共通電位配線3 3 5反轉至High ( =5 V )之前配線 S Μ P 1、配線S Μ Ρ 2都成爲非選擇，共通電位配線3 3 5爲 High ( =5 V )之期間沒有被選擇。作爲圖1 2之圖’如配線 SENSED、配線 SENSEP 所示配線 SENSED、配線 SENSEP 在共通電位配線3 3 5反轉爲High ( =5V )時，因電容結合 而電位上升約5 V。但是，同樣地如圖1 2所示’此期間第 開關SW5及第6開關SW6關閉，所以節點SIN’的電位不 受到影響。亦即，與第1實施例同樣不會受到共通電位配 線3 3 5的反轉的影響，可以高精度地檢測。 本實施例之檢測電路3 6 1的構成，與第1實施例的檢 測電路3 60之構成相比，電路內之節點A成爲浮動的期間 很短，具有對雜訊比較不受影響之優點。另一方面，容易 受到第開關SW5與第6開關SW6之開關雜訊的影響，而 有精度變差的情形。要採用哪種構成只要考慮兩者的優點 再選擇即可。於任一種構成，都是重設動作結束（在實施 例爲配線RST的電位回到Low)的計時之共通電位（COM )’與檢測電路3 6 1動作（在實施例爲配線S MP、配線 SMP1、配線SMP2成爲High)的期間之共通電位（COM )一致是很重要的’只要是成爲那樣的構成之電路，也可 以採用與本說明書所舉例之電路以外的已知的各種電路來 構成檢測電路3 6 1。 本實施例之液晶顯示裝置與圖1所示之第1實施例之 液晶顯示裝置9 1 0相比除了把主動矩陣基板1 〇丨置換爲主 動矩陣基板1 0 2以外沒有不同’所以省略說明。此外，電 -44- 200914919 子機器之構成、外光照度與亮度的設定等也與第1實施例 相同，所以省略。 在本實施例接續於光感測器的電源使用共通電位配線 3 3 5之共通電位（COM )。在本實施例遮光電極/透明電極 也接續於共通電位配線33 5，所以光感測器幾乎完全被結 合至共通電位配線3 3 5之共通電位（COM )，配線 SEN SEP及配線SENSED成爲與共通電位配線335相同的 週期/相位而以約略相同的電位振盪。因此，被施加於二 極體的偏壓幾乎不會隨著共通電位配線3 3 5的極性而改變 。此外，與第1實施例相比，可以大幅削減配線數，所以 可以縮小液晶顯示裝置的外型尺寸。另一方面’檢測電路 3 6 1之電源電位可以爲D C電位，所以可以與掃描線驅動 電路3 0 1或資料線驅動電路3 0 2之電源電位共用，不會使 供給的電源數無效益地增加。又，在有共通電位配線3 3 5 的電位變動或由於雜訊增大而影響畫質的顧慮時，亦可採 用把其他的電源電位供給往光感測器的構成。 此外，在本實施例接續全邊之配線SENSEP與配線 SENSED，與一個檢測電路361接續，但如第1實施例那 樣在各邊分離配線SENSEP與配線SENSED而於各邊配置 檢測電路3 6 1 -1〜3 6 1 -4，使其輸出以第1實施例所示之多 數決電路3 70來判定亦可。此外，相反的以在第1實施例 之第η之檢測電路3 60-n爲一個，使各邊之配線短路亦可 。如本實施例這樣短路各邊使檢測電路爲一個的話，可以 大幅削減電路規模，可以縮小液晶顯示裝置9 1 0的外型° -45- 200914919 另一方面，可以檢測的外光照度爲各邊的外光照度的平均 ，所在手指等大幅遮蔽外光的場合會把外光照度檢測爲比 實際更暗。無論選擇哪一種，只要決定電子機器的構成、 操作方法、液晶顯示裝置的尺寸等即可。 此外，本說明書之各實施例係於顯示區域3 1 〇之4邊 配置光感測器，但有外型等限制的場合，當然亦可於3邊 或者更少邊配置光感測器。 [產業上利用可能性] 本發明並不以實施型態爲限，不限利用於TN模式， 亦可利用於垂直配向模式（V A模式）、利用橫電場之I p s 模式、或利用邊緣電場的FFS模式等液晶顯示裝置。此外 ，不僅全透過型而已，亦可爲全反射型或反射透過兼用型 。此外’不僅液晶顯示裝置，亦可使用於有機EL顯示器 、場發射型顯示器’亦可使用於液晶顯示裝置以外之半導 體裝置。 此外，不僅如本實施例所示的配合外光之顯示亮度的 控制，亦可用於測定顯示裝置之亮度或色度而將其反饋之 沒有色偏或經年老化的顯示裝置。 【圖式簡單說明】 圖1係本發明之實施例之液晶顯示裝置9 1 0之立體圖 〇 圖2係相關於本發明之第丨及第2實施型態之主動矩 -46- 200914919 陣基板1 0 1之構成圖。 圖3係本發明之實施例之主動矩陣基板1 0 1之畫素電 路圖。 圖4係顯示本發明之電子機器之實施例之方塊圖。 圖5係本發明之實施例之主動矩陣基板ιοί之畫素部 之平面圖。 圖6係圖5之A - A ’剖面圖。 圖7係圖5之B-B’剖面圖。 圖8係相關於本發明之第1實施例之第丨邊受光感測 器群之一之第η個第1邊光感測器351-n的平面擴大圖。 圖9係圖8之C - C ’剖面圖。 圖10係相關於本發明之第1實施例之第2邊受光感 測器群之一之第η個第2邊光感測器3 52-n的平面擴大圖 〇 圖1 1係相關於本發明之實施例之第η個檢測電路 3 60-η之電路圖。 圖1 2係相關於本發明之實施例之計時圖。 圖1 3係相關於本發明之其他實施例之第η個檢測電 路360’-η之電路圖。 圖1 4係相關於本發明的實施例之多數決電路3 7 0之 電路圖。 圖1 5係相關於本發明之實施例之外部光的檢出照度 與背光亮度之設定圖。 圖1 6係相關於本發明之第2實施例之第丨邊受光感 -47- 200914919 測器群之一之第n個第1邊光感測器3 5 1 -η的平面擴大圖 〇 圖1 7係相關於本發明之第2實施例之第2邊受光感 測器群之一之第η個第2邊光感測器352-η的平面擴大圖 〇 圖18係相關於本發明之第3實施型態之主動矩陣基 板1 0 2之構成圖。 圖19係相關於本發明之第3實施例之第1邊受光感 測器群之一之第η個第1邊光感測器351-η的平面擴大圖 〇 圖2 0係相關於本發明之第3實施例之第2邊受光感 測器群之—之第η個第2邊光感測器3 5 2 - η的平面擴大圖 〇 圖21係相關於本發明之第3實施型態之檢測電路3 6 1 之電路圖。 圖2 2係相關於本發明之第3實施例之計時圖。 【主要元件符號說明】 ' 101，102 :主動矩陣基板 201，201-1〜201-480 :掃描線 202.202- 1 〜202- 1 920:資料線 203.203- 1〜203-480:電容線 3 〇 1 :掃描線驅動電路 3 〇2 :資料線驅動電路 -48- 200914919 3 03 :充電電路 3 1 0 :顯示區域 3 20 :訊號輸入端子 3 3 0 :對向導通部 3 3 5 :共通電位配線 351，351'352,352’，353,353，，354,354，：光感測器 351- 1 〜351-480,351’-1 〜351’-480:作爲光感測器之 第1邊光感測器 352- 1 〜352-1920,352’-1 〜352’-1920 :作爲光感測器 之第2邊光感測器 353- 1 〜353-480,353’-1 〜353’-480 :作爲光感測器之 第3邊光感測器 3 5 4- 1 〜3 5 4- 1 920,3 5 4’-1 〜3 5 4’- 1 920 ··作爲光感測器 之第4邊光感測器 3 60,3 60’，361 :檢測電路 3 70 :多數決電路 401 :畫素開關元件 4 0 2 :畫素電極 403 :輔助電容電容器 602 :石夕島（silicon island) 6 0 3 :源極電極 6 0 4 :汲極電極 610P,610P’，620P，620P’ ：陽極區域 610N，610N’，620N，62 0N’ ：陰極區域 -49- 200914919 6101，6101，，6201,6201’ ：真性區域 611,611’，621，621 ’ ：遮光電極 6 1 2,622,622’ ：透明遮蔽電極 615,615’，625,625’ ：陽極電極 616,626:陰極電極 6 1 7,627 ： BT 電極 7 8 0 :影像處理電路 7 8 1 :中央演算電路 7 82 :外部I/F電路 7 84 :外部電源電路 7 8 5 :參照表 7 8 3 :輸出入機器 9 1 0 _·液晶顯示裝置 9 1 2 :對向基板 921 :伸出部 922 :向列相液晶材料 9 2 3 :密封材 924 :上偏光板 925 :下偏光板 926 :背光單元 927 :導光板 92 8 :作爲可撓性基板之FPC 929 :連接器 9 3 0 :作爲共通電極之對向電極 -50- 200914919 940 :黑矩陣 991- 1〜991-3:第1個第1邊受光開口部〜第3個第 1邊受光開口部 992- 1〜992-4:第1個第2邊受光開口部〜第4個第 2邊受光開口部 993- 1〜993-3:第1個第3邊受光開口部〜第3個第 3邊受光開口部 994- 1〜994-4 :第1個第4邊受光開口部〜第4個第 4邊受光開口部 SENSE,VSH,VSL,VDBT，VCHG:配線 -51 -200914919 IX. [Technical Field] The present invention relates to, for example, a display device and an electronic device having the same. [Prior Art] In recent years, On the display device, The development of a technology in which a photosensor function is mounted on a liquid crystal display device using a thin film transistor is carried out.  The purpose of carrying a light sensor can be exemplified by three types: (1) Measuring external light adjustment, brightness, etc., in order to reduce power consumption and improve image quality; (2) measuring the backlight and adjusting the brightness or chromaticity; (3) Know the position of the finger or the light pen and use it as a touch key. As a photosensor, a thin film transistor can be cited, PIN ( p-intrinsic-n) diode, PN diode and so on. In any case, the light receiving part is a film of tantalum. In order not to increase the cost of manufacturing, Preferably, it can be fabricated in the same manufacturing steps as the tantalum film of the switching element constituting the display.  [Patent Document 1] Japanese Laid-Open Patent Publication No. 2006-1 1 8 96 5 SUMMARY OF THE INVENTION [Problems to be Solved by the Invention] From the viewpoint of accuracy of illuminance measurement or design point of view, the setting of the light sensor Preferably, the position is disposed in a display area adjacent to the display device, but in the drive circuit built-in type liquid crystal display device, It is difficult to configure the photo sensor inside the drive circuit. In addition, In such a configuration, The light sensor is susceptible to electrical noise driven by the display area. In addition -4- 200914919 The impact caused by the fascination of the display area cannot be ignored. Therefore, there is a problem that the accuracy of the light sensor is low. In particular, when the liquid crystal display device performs common potential inversion driving, This problem has become significant.  [Means for Solving the Problem] The present invention, It is equipped with a light sensor, Active matrix circuit for display, a plurality of bus lines that are connected to the active matrix circuit to convey a driving signal, And a display device comprising an active matrix substrate for driving a drive circuit for outputting a driving signal to the plurality of bus bars, The aforementioned photo sensor, It is assigned to a plurality of sub-areas separated by the aforementioned plurality of bus bars, The plurality of sub-regions are disposed between the active matrix circuit and the driver circuit. With this configuration, Even if the drive circuit has a built-in display, Also because the light sensor can be placed near the display area, Therefore, the external illumination can be correctly measured. The design freedom of the mounted electronic equipment has also increased.  Further, the present invention is characterized by further comprising: a plurality of pixel electrodes connected to the active matrix circuit, a common electrode that is driven in reverse between the first potential and the second potential, a liquid crystal element that changes an alignment state corresponding to an electric field applied between the complex pixel electrode and the common electrode,  The sensor wiring connected to the aforementioned photo sensor, And a detecting circuit that detects the potential or current of the sensor wiring by being connected to the sensor wiring; The aforementioned detection circuit, The common electrode is timed by either one of the first potential or the second potential. The potential or current of the aforementioned sensor wiring is detected. So constituted, Inverting the so-called common AC drive of the common electrode to reduce the power consumption of the liquid crystal display device, It is possible to prevent the accuracy caused by electromagnetic noise caused by the inversion of the common electrode or the variation of the sensor wiring potential due to the combination with the common electrode.  Further, the present invention is characterized in that the detecting circuit repeatedly performs a resetting operation of returning the potential of the sensor wiring to an initial state, The timing of the end, The common electrode is counted by either one of the ith potential or the second potential lower than the first potential. So set up, Even if the sensor wiring is determined by the combined capacitance with the common electrode, the detection circuit is always in the state where the potential returns to the original state. Therefore, the detection accuracy will not be reduced.  Further, the present invention is characterized by the aforementioned sensor wiring, The potential is changed by the same timing of the potential of the common electrode. Therefore, it is necessary to pay attention to the impedance between the aforementioned sensor wiring and the common electrode, and the impedance of the aforementioned sensor wiring. So increase the freedom of configuration and reduce the appearance of the panel. in particular, The sensor is characterized in that the aforementioned common electrode is short-circuited with the aforementioned common electrode. On this occasion, The sensor wiring and the common potential become equal', and the combined capacitance can be ignored. or, The characteristic is that the detector wiring 'only has the aforementioned complex electric potential in the aforementioned common potential, The timing of a specific potential is connected to the electricity supplied from the outside, It becomes a floating state during the rest of the period. In this case, The sensor wiring is determined by the combined capacitance with the common electrode, and the combined capacitance of the common electrode and the common electrode is large. Or where the sensor wiring is large, It doesn't matter.  Further, the present invention has a first electrode formed in a region flat with the aforementioned photo sensor, The first electrode and the bus bar capacitance are caused to increase the amplitude of the reset signal as described above.  Action and the above, No capacitor or , A frame formed by the source wiring among the aforementioned senses of the line system and the electrode, That is, the resistance overlaps the line plane -6- 200914919 The second electrode is placed in the overlapping area. So constituted, Even if the first electrode is formed for the purpose of shielding, The light sensor is also less affected by the potential of the bus bar (scanning line, data line, etc.) via the 1 electrode. Improve accuracy. In addition, The present invention is characterized in that the second electrode system is connected to the common electrode. Common electrode, In order to improve the drawing, the output impedance or wiring impedance is designed to be low. Therefore, if it is used as a fixed target of the second electric potential, Improve the shielding performance, In addition, there is no extra wiring, so the appearance of the display device can be reduced.  Further, the present invention is characterized by having a first electrode overlapping the aforementioned photo sensor, The first electrode is a plurality of light-shielding electrodes for shielding the backlight. The bus bar line or the front electrode is disposed in a gap between the plurality of light-shielding electrodes. When the backlight light-shielding electrode is overlapped with the photo sensor, the bus line is not disposed in the gap, and the light is not leaked. Can prevent stray.  Further, the present invention is characterized in that the plurality of sub-regions are arranged along a plurality of sides of the outer peripheral portion of the matrix circuit. Because the sensor is used in the plural side, Therefore, the difference in the brightness caused by the display state of the liquid crystal is small, In particular, when the display device is overlapped with a touch panel or the like, The influence of light that cannot be avoided by the finger approaching due to the operation is also reduced.  In addition, The invention is characterized in that the foregoing detection circuit is a plurality of inspection paths, Having a majority circuit connected to the aforementioned complex detection circuit, The first few circuits, In the complex output junction from the aforementioned plurality of detection circuits, When the output of 2 or more changes, Make the output change. So structured, Even if the shadow is caused by a finger as described above, Or on the contrary, there is a strong light spot caused by external light. The results of this area are also excluded from the light or by the first change,  Extremely necessary 1 electricity, Actively set the light on the first In this case, any of the test results can be improved. Therefore, -7-200914919 improves the detection accuracy. and then, In the present invention, Further, the first detection circuit which is one of the plurality of detection circuits is connected to the plurality of sub-regions which are connected to the sensor wiring. Arranged along one side of the outer periphery of the aforementioned active matrix circuit, a second detection circuit in which the other one of the plurality of detection circuits is connected to the plurality of sub-regions through which the sensor wiring is connected, It is arranged along the other sides of the outer periphery of the aforementioned active matrix circuit. If it is constituted, Because of the majority decision using the results of the side, So even if there is only light on the specific side, Or when there is light in the opposite direction, it will not malfunction. External light can be detected with high precision.  In addition, The present invention is characterized in that the photosensor uses a PIN junction diode or a PN junction diode of a thin film polysilicon. The above drive circuit is constructed by using a transistor of a thin film polysilicon. So constituted, The photosensor can be formed in the same manufacturing step as the thin film transistor, even if the built-in photosensor does not increase the cost.  In addition, An electronic machine using these display devices is proposed in the present invention. Because of the built-in precision light sensor, it is easy to control the backlight with the external light. Will not make the power consumption increase insignificantly, The cost will not rise. In addition, The light sensor can be placed near the display area, so the freedom of design is also mentioned.  [Embodiment] Hereinafter, The embodiment of the invention will be described in accordance with the drawings.  [First Embodiment] -8- 200914919 Fig. 1 is a diagram (partial cross-sectional view) of a liquid crystal display device 9 1 0 according to the present embodiment. Liquid crystal display device 91 0, The nematic liquid crystal material 9 2 2 is sandwiched between the active matrix substrate 101 and the counter substrate 912 with a certain interval therebetween. The alignment material composed of the polyimine or the like is applied to the active matrix substrate 1 0 1 , but the alignment film of the rubbing treatment is applied. In addition, Opposite substrate 9 1 2,  Although not shown, it corresponds to the color filter of the pixel, A pair of common electrodes formed on the black matrix active matrix substrate 101 of the low-reflection/low-transmittance resin for preventing light penetration enhancement, which is formed by the opposite-passing portions 3 3 0 - 1 to 3 3 0-ΙΤΟ film Electrode 930.  The surface on which the liquid crystal material 922 is contacted is coated with a material such as polyimide or the like. A rubbing treatment is applied in a direction orthogonal to the friction of the alignment film of the active matrix substrate 1 〇 1 .  Further on the outer side of the counter substrate 9 1 2 Configuring the upper polarizing plate The lower polarizing plate 92 5 is disposed outside the active matrix substrate 101, It is arranged in a way that the light direction is orthogonal (crossed Nichol shape).  Polarizer 925, The backlight unit 926 and the light guide plate 927 are configured to be illuminated toward the light guide plate 927. The light guide plate 927 is configured such that the light of the backlight unit 926 is directed toward the active matrix substrate 101 to form a uniform surface light source, and the light is reflected and bent to function as a light source for liquid crystal display. Backlight unit 926, In this embodiment; | Yuan, But it can also be a cold cathode tube (CCFL). The backlight unit connector 929 is connected to the electronic machine body. Supply power,  The embodiment has a three-dimensional structure in which the current/voltage is appropriately adjusted by the power source, and is sealed by a sealing material.  on, Although not formed, it is formed:  Through contrast 940, And short-circuited with the nematic phase, the processing direction 924, In the mutual bias, and then The light is backed by the back so that the vertical and uniform devices 9 1 0 I LED single 926 pass but the actual amount of light from the -9-200914919 backlight unit is adjusted.  Although not shown, However, it is also possible to attach a protective glass or acrylic plate to the upper polarizer 924 as needed to cover the surroundings, and to attach an optical compensation film for improving the viewing angle.  In addition, Active matrix substrate 101, An extension 9 2 1 provided by the opposite substrate 91 is provided At the signal input 3 20 of the protrusion 9 2 1 , The FPC 928, which is mounted as a flexible substrate, is electrically connected to the FPC 928 as a flexible substrate, and is connected to the electronic device body.  Give the necessary power, Control signals, etc.  Further, on the liquid crystal display device 91 0, The first first side light receiving portion 991-1 to the third first side light receiving opening portion 991-3, The first light-receiving opening portion 992-1 to the fourth second-side light-receiving opening portion 992-4', the third-side light-receiving opening portion 9 9 3 - 1 to the third third-side light-receiving opening 993-3, The first fourth side light receiving opening portion 994-1 to the fourth fourth light opening portion 994-4, Formed by partially removing the matrix 940 on the opposite substrate 912, The external light passes through the openings to reach the main array substrate 110.  2 is a block diagram of the active matrix substrate 101. In the display area 3 1 0 on the active matrix 1 〇 1, As an active matrix circuit, 4 8 0 sweep 201 (201-1~201-480) is formed directly with 1920 data lines 202 (202 2 0 2 - 1 9 2 0), 4 80 0 capacitor lines 2 0 3 ( 2 0 3 - 1 to 4 8 0 ) are arranged in parallel with the scanning lines 2 0 1 ( 2 0 1 - 1 to 2 0 1 - 4 8 0 ).  Lines 203 (203 - 1 to 203 - 48 0 ) are shorted to each other, Continued with the common potential 335, Further with the two pairs of guides 330 (330-1~330_2, Or , Also 2 extension terminal painted.  The opening is provided on the side of the opening. The first part of the edge is subjected to the black moment. The substrate is drawn -1~ 203- Capacitor wiring) -10- 200914919 Continued and input by signal! Ijfij sub-320 provides a reversal signal of 〇V-5V, The inversion time is a common potential of 35 μsec. The scan lines 201 (201-1 to 201-480) are connected to the scan line drive circuit 301, Further, the data lines 2〇2 (202" to 202-1920) are connected to the data line drive circuit 302 and the precharge circuit 303', respectively, and are appropriately driven. In addition, the scanning line driving circuit 3〇1 a data line driving circuit 302, The precharge circuit 303 supplies a signal necessary for driving by the signal input terminal 302. The signal input terminal 306 is disposed on the extension portion 92. Scan line drive circuit 3 0 1. Data line drive circuit 3 0 2  The precharge circuit 303 is formed by collecting polycrystalline germanium film transistors on the active matrix substrate 1? It is manufactured in the same steps as the pixel switching element 40 1 ( 40 1 -n-m ) described later, It is a so-called drive circuit built-in type liquid crystal display device.  In addition, The area sandwiched by the scanning line driving circuit 310 and the display area 3 1 0 serves as a photo sensor of the first side photo sensor 3 5 1 -1 to 351-480 of the 680 photosensors. The 351 is configured. The nth first side photosensors 35 1-n of the nth are respectively arranged in a region between the scanning line 20 1-n and the scanning line 20 1-n+1 (one example of the sub-region). Here, The eleventh first side photo sensor 351-81 to the 160th first side photo sensor 351-160 are disposed so as to overlap the plane of the first first side light receiving opening 991-1. The side light sensors 3 5 1 - 24 1 to the 3rd 20th first side photosensors 351-320 are arranged to overlap the second first side light receiving opening portion 991-2. The 401th first side photo sensor 35 1-4〇1 to the 480th first side photo sensor 3 5 1 -4 80 overlaps with the third first side light receiving opening portion 991-3 Ground configuration. The nth first side photosensor overlapping the plane of any of the first first side light receiving openings 9 9 1 _ -11 - 200914919 1 to the third first side light receiving opening 991-3 3 5 1 -η is called the i-th edge received sensor group. In addition, The nth first side photosensor 3 5 1 - η which does not overlap with any of the first first side light receiving opening 9 91 _ 1 to the third first side light receiving opening 99 1 -3 It is called the first side shading sensor group.  Similarly, The second side photosensors 352-1 to 352-192, which are the 192 side photosensors in the ® field sandwiched between the precharge circuit 303 and the display area 310, are disposed as the photo sensor 352. The second side photosensors 3 52-n of the nth are respectively arranged in a region between the data line 202-n and the data line 202-n+1 (an example of the sub-region). Here, The first second side optical sensor 352-1 to the 240th second side photo sensor 352-240 are disposed so as to overlap the first and second side light receiving openings 992-1. The 481th second side photosensor 3 5 2-48 1 to the 720th second side photo sensor 3 52-72 0 are disposed so as to overlap the second second side light receiving opening portion 992-2. The 961th second side optical sensor 352-96 1 to the 1 200th second side photo sensor 3 52-1200 are disposed so as to overlap the third second side light receiving opening portion 992-3.  The 1441th second side photosensors 352-44-1 to 1680th second side light sensors 352-1680 are arranged in a plane overlapping the fourth second side light receiving opening portion 992-4. The n-th second side photosensor 352-η which is superimposed on any one of the first second side light receiving opening 992-1 to the fourth second side light receiving opening 992-4 is called The second side receives the sensor group. In addition, The n-th second side photo sensor 3 52-η which is not overlapped with any of the first second side light receiving opening portion 992-1 to the fourth second side light receiving opening portion 9 92 -4 It is the second side shading sensor group.  -12- 200914919 Similarly, A peripheral sensor portion that faces the scanning line driving circuit 301 and the display region 310 as a photo sensor is used as a photosensor of 480 third side photo sensors 3 5 3 - 1 to 3 5 3 - 480. 3 5 3 is configured. The third side of the ηth photo sensor 3 5 3 -η is disposed in a region between the capacitance line 203 -η and the capacitance line 203 -η+1, respectively. Here, The first third side photo sensor 3 5 3 - 1 to the 80th third side photo sensor 353-80 are disposed so as to overlap the first third side light receiving opening portion 9 93 -1 . The 161rd third side photo sensor 3 5 3 - 161 to the 240th third side photo sensor 3 5 3 - 240 are disposed so as to overlap the second third side light receiving opening portion 993 - 2 . The 321rd third side photosensors 353-321 to 400th third side photosensors 353-400 are arranged to overlap the third third side light receiving opening portion 993_3 plane. The n-th third-side photosensor 353-η which is superimposed on any one of the first third-side light-receiving opening 933-1 to the third first-side light-receiving opening 993-3 is called The third side receives the sensor group. In addition, The n-th third-side photosensor 353-η, which is not overlapped with any of the first third-side light-receiving opening 993-1 to the third first-side light-receiving opening 993_3, is referred to as a third side. Shading sensor group.  Similarly, the area sandwiched between the data line driving circuit 312 and the display area 3 1 0 serves as the 192 第 fourth side photo sensor 354-1 to 3 5 4 - 1 9 2 0 of the photo sensor. It is configured as a photo sensor 3 5 4 . The fourth side photosensors 3 5 4-n of the nth are respectively arranged in a region between the data line 2〇2_η and the data line 202-n+1. Here, the fourth side optical sensor 3 54_241 to the 480th fourth side photo sensor 354_48 of the 241st are disposed so as to overlap the first fourth side light receiving opening portion 994-1. The 721th fourth side photo sensor 354--13-200914919 721 to 960th fourth side photo sensor 354-960 are arranged in a plane overlapping with the second fourth side light receiving opening portion 994-2. The 1201th fourth side optical sensor 354-10-1 to the 1440th fourth side optical sensor 354-1440 are arranged to overlap the third fourth side light receiving opening portion 994-3. The 1681th fourth side photo sensor 3 54- 1 68 1 to the 1 920th 4th side photo sensor 3 54- 1 92〇 overlaps the 4th 4th side light receiving opening portion 994-4 plane Configuration. The nth fourth side photosensor 3 54-η which is superimposed on any one of the first fourth side light receiving opening 994-1 to the fourth fourth side light receiving opening 994-4 is called It is the fourth side of the light sensor group. In addition, The n-th fourth-side photosensor 354-η, which is not overlapped with any of the first fourth-side light-receiving opening 994-1 to the fourth fourth-side light-receiving opening 994-4, is called a 4 side shading sensor group.  Here, The first side photodetector group is connected to the wiring SENSE (SENSEI) and the wiring VSH (VSH1). The first side shading sensor group is connected to the wiring SENSEI and the wiring VSL (VSL1) and the wiring VDBT (VDBT1). The second side photodetector group is connected to the wiring SENSE (SENSE2) and the wiring VSH (VSH2). The second side shading sensor group is connected to the wiring SENSE2 and the wiring VSL (VSL2) and the wiring VDBT (VDBT2). The third side photodetector group is connected to the wiring SENSE (SENSE3) and the wiring VSH (VSH3). The third side shading sensor group is connected to the wiring SENSE3 and the wiring VSL (VSL3) and the wiring VDBT (VDBT3). The fourth side photodetector group is connected to the wiring SENSE (SENSE4) and the wiring VSH (VSH4). The fourth side shading sensor group is connected to the wiring SENSE4 and the wiring VSL (VSL4) and the wiring VDBT (-14-200914919 VDBT4).  Wiring SENSEI and wiring VSH1 and wiring VSL1 and wiring VDBT1 are connected to the first detecting circuit 3 60-1 as the detecting circuit 3 60.  The wiring SENSE2 and the wiring VSH2 and the wiring VSL2 and the wiring VDBT2 are connected to the second detecting circuit 3 6 0 - 2 as the detecting circuit 360. The wiring SENSE3 and the wiring VSH3 and the wiring VSL3 and the wiring VDBT3 are connected to the third detecting circuit 3 60-3 as the detecting circuit 3 60. The wiring SENSE4 and the wiring VSH4, the wiring VSL4, and the wiring VDBT4 are connected to the fourth detecting circuit 3 6 0 - 4 as the detecting circuit 306.  Output wiring OUT1 from the first detecting circuit 3 60-1, With the output wiring OUT2 from the second detecting circuit 3 60-2, With the output wiring OUT3 from the third detecting circuit 3 60-3, The output wiring OUT4 from the fourth detecting circuit 3 60-4 is connected to the majority circuit 3 70, The output wiring OUT from the majority circuit 3 70 is connected to the external circuit through one of the signal input terminals 3 20.  3 is a circuit diagram of the vicinity of the parent fork of the mth data line 20 2-m and the nth scanning line 2 0 1 - η of the display area 310. A pixel switching element 40 1 -n-m formed of a germanium channel type field effect polycrystalline germanium film transistor is formed in the vicinity of each intersection of the scanning line 2 0 1 - η and the data line 202-m, The gate electrode is connected to the scan line 2〇 1 -η, The source and drain electrodes are connected to the data line 202-m and the pixel electrode 402 (402-n-m), respectively. The pixel electrode 402-n-m and the electrode short-circuited at the same potential form a capacitance line 203-n and an auxiliary capacitance 4 0 3 ( 4 0 3 - η - m ), Further, when the liquid crystal display device is incorporated, a capacitor is formed between the liquid crystal element and the counter electrode 930.  -15- 200914919 Fig. 4 is a block diagram showing the specific constitution of the electronic apparatus of the present embodiment. s liquid crystal display device 9 10 is a liquid crystal display device illustrated in FIG.  External power supply circuit 784, The image processing circuit 780 supplies necessary signals and power to the liquid crystal display device 910 through the FPC 928 as a flexible substrate and the connector 929. The central calculation circuit 781 acquires input data from the output device 783 through the I/F circuit 782. Here, as an output machine 783, for example, a keyboard, mouse, Trackball, LED, horn, Antennas, etc.  The central calculus circuit 7 8 1 performs various arithmetic processing based on external data. The result is transferred to the image processing circuit 78 0 or the external I/F circuit 782 as a command. The image processing circuit 780 updates the image information according to an instruction from the central calculation circuit 781. By changing the signal to the liquid crystal display device 910, The display image of the liquid crystal display device 910 is changed. In addition, The output wiring 0 UT of the majority circuit 307 from the liquid crystal display device 910 is input to the central calculation circuit 781 by the FPC 928 as a flexible substrate. The central processing circuit 781 outputs the signal (OUT). The pulse length is transformed into a corresponding discrete 値. Secondly, the central calculus circuit 7 8 1 accesses the EEPROM (electrically erasable programmable read-only memory, The reference table 7 85 ' constructed by Eiectronically Erasable and Programmable Read Only Memory) is converted into a voltage corresponding to the voltage of the appropriate backlight unit 926 to the external power supply circuit 784. The external power supply circuit 784 supplies the potential power corresponding to the signaled voltage of the cesium to the backlight unit 916 in the liquid crystal display device 910 via the connector 929.  The brightness of the backlight unit 926 is changed by the voltage supplied from the external power supply circuit 784, Therefore, the brightness of the white display of the liquid crystal display device 9 10 is also changed from -16 to 200914919. The so-called electronic machine here, Specifically, it can be mentioned that  , Pen S computer, PDA ( Personal Digital ( Assistants ), Digital camera, camera, mobile phone,  player, Portable video player, Portable D V D player,  Player, etc.  In the present embodiment, The brightness of the backlight unit 926 is controlled by the center 781 on the electronic device, However, for example, a configuration in which the driver 1C and the EEPROM are provided in the liquid tank 910 is provided.  The driver 1C has a binary output signal (OUT) to a discrete function, Refer to the EEPROM retransform function, Adjusting the voltage of the backlight unit, etc. In addition, Do not use a reference table, The 値 calculation may be performed by converting the discrete 値 to the corresponding backlight unit 296.  Fig. 5 is a plan view showing the electrical configuration of the pixel display region shown in Fig. 3. As shown in the example in Figure 5, Different outlets are wired for different materials. The parts of the same dot are the same line. Chrome film (C r ), Polycrystalline germanium film (P 〇 1 y - s i ), Molybdenum f), Aluminum-bismuth alloy film (AINd), Indium Tin Oxide (Indium Tin Oxide) is composed of five layers of film. Separate into cerium oxide, Tantalum nitride, Any one of these organic insulating films or these. in particular, Chrome film (Cr) film thickness is OOnm, Polycrystalline Poly-Si) film thickness 50nm, Molybdenum film (Mo) film thickness 20 0nm gold film (AINd) film thickness 500nm, Indium Tin Oxide film has a film thickness of 1 〇〇 nm. In addition to the chrome film (viewer 'TV: Data ) Portable photo Portable music calculation circuit Crystal display device can also be used here to change the output of 9 2 6 by means of the voltage of the road. The material of the road map is matched with the film (Mo (ITO,  An interlayer film laminated between layers ( Ming Ruihe (ITO,  Cr) and -17- 200914919 A germanium film (P〇ly-Si) is formed by laminating a tantalum nitride film of 100 nm and a bottom insulating film of a tantalum oxide film of 100 nm. A gate insulating film composed of a tantalum oxide film of 100 nm is formed between the polycrystalline germanium film (Poly-Si) and the molybdenum film (Mo). An interlayer insulating film of a tantalum nitride film of 200 nm and a ruthenium oxide film of 500 nm is formed between the molybdenum thin film (Mo) and the aluminum ammonium alloy thin film (AINd). Aluminum-bismuth alloy film (AINd) and indium tin oxide film (ITO, Indium Tin Oxide) is formed with a protective insulating film of a 200 nm tantalum nitride film and an average 1 μm organic planarization film. The wiring rooms of each other are insulated. The contact holes are opened at appropriate positions to be connected to each other. also, There is no chrome film (Cr) pattern in Figure 5.  As shown in Figure 5, The data line 202-m is formed of an aluminum-bismuth alloy film (AINd). The source electrode of the pixel switching element 401-n-m is connected through the contact hole. The scanning line 2 0 1 - η is composed of a giant film (Μ 〇 ). It also serves as the gate electrode of the pixel switching element 40 1-n-m. The capacitance line 203 - η is composed of the same wiring material as the scanning line 2 0 1 - η. The pixel electrode 4 0 2 - η - m is composed of an indium tin oxide film. The drain electrode is connected to the drain electrode of the pixel switch element 401-n-m through the contact hole. In addition, The drain electrode of the pixel switching element 401-n-m is also connected to the capacitor portion electrode 605 composed of an n + -type polysilicon film doped with phosphorus at a high concentration. The plane of the capacitance line 203-n is overlapped to form a supplementary capacitor capacitor 40 3-n-m.  Fig. 6 is a partial cross-sectional structural view showing a configuration of the pixel switching element 401-n-m for the liquid crystal display device 910 corresponding to the A - A ' line portion of Fig. 5. also, In order to make the picture easy to identify, The scale is not fixed. Active matrix substrate 1 〇 1 is an insulating substrate composed of alkali-free glass and having a thickness of 0 · 6 mm.  -18- 200914919 矽 602 602, which is composed of a polycrystalline tantalum film, is formed by laminating a 200 nm tantalum nitride film and a 300 nm yttrium oxide underlayer insulating film. The scanning line 20 1-n is disposed above the erbium island 602 and the aforementioned gate insulating film. In an area overlapping the scan line 201-n, The Yeouido 602 system consists of a true semiconductor region 6021 that is fully doped or only doped with very low concentrations of phosphorus ions at low concentrations. Η-region 602L having a film resistance of 20 kn to which the phosphorus ion is doped at a low concentration is present, Further, a thin film resistor having a high concentration of doped phosphorus ions is ΔQ + 602 Ν LDD (Lightly Doped Drain, Low doped bungee) construction. The left and right n + regions 602N pass through the contact holes and the source electrode 603, The drain electrode 604 is connected, The source electrode 603 is connected to the data line 202-m. The drain electrode 604 is connected to the pixel electrode 402-n-m. A nematic liquid crystal material 922 is present between the pixel electrode 402-n-m and the counter electrode 930 as a common electrode on the counter substrate 9 1 2 . In addition, A black matrix 940 is formed on the opposite substrate 912 in a manner partially overlapping the pixel electrodes 402-n-m. also, In the case where the light leakage current of the pixel switching element 40 1 -n-m becomes a problem, A light-shielding layer made of a chromium film may be formed under the 6 Island 62 02. In this embodiment, since the light leakage current hardly becomes a problem, And because of this structure, The mobility of the pixel switching element 401-n-m is lowered, Therefore, the composition of the chrome film under the 矽 island 602 was selected.  Fig. 7 is a partial cross-sectional structural view of the liquid crystal display device 91A corresponding to the line B-B' of Fig. 5 for explaining the structure of the auxiliary capacitor 403-n-m. The capacitor portion electrode 605 and the capacitor line 203-n connected to the drain electrode 604 form a storage capacitor so as to overlap with the gate insulating film.  -19- 200914919 Fig. 8 is a plan enlarged view of the nth first side photosensor 3 5 1 -η of one of the first side light receiving sensor groups. The example is the same as in Figure 5. In addition, Fig. 9 is a partial cross-sectional structural view showing a liquid crystal display device 910 corresponding to the line C-C' of Fig. 8. The nth first side photosensor 35 1 -η is composed of an anode region 610 Ρ ( 610 Ρ - η), Authentic area 6101 ( 610Ι-Π), The cathode region is formed by 610 Ν (610Ν-η). Anode region 610Ρ-η, Authentic area 6101-η, The cathode regions 610Ν-η are each formed by appropriate impurity implantation of the same island pattern formed by the same polycrystalline silicon film (Poly-Si) forming the pixel switching elements 41 0-n-m. Specifically, the anode region 610P-η is implanted with a high concentration of boron ions to adjust the sheet resistance to about 21 ίΩ. The cathode region 610Ν-Ι1 was injected with a high concentration of phosphorus ions to adjust the sheet resistance to about 1 kQ. In the true region 610I-n boron ion, Phosphorus ions are only injected into very small amounts. Or not at all, Formed as a true semiconductor. The nth first side photo sensor 35 1 -η is thus formed as a lateral type PIN junction diode. The size of the true region 6101-n is ΙΟΟμιη in a direction parallel to the joint surface. It is 1 Ομηι in the vertical direction.  In addition, The nth first side photosensor 3 5 1 -η system and the light-shielding electrode 61 1 ( 61 1-η) composed of a chromium thin film (Cr) and the pixel electrode 4〇2-nm The same transparent shielding electrode 612-n of the transparent shielding electrode 612 which is formed of an indium tin oxide film (ITO) is formed to overlap. The light-shielding electrode 611-n functions as a light-shielding film that prevents light of the backlight 926 from entering the n-th first side photosensor 35 1-n. In addition, The transparent shielding electrode 6 1 2 - η prevents the illumination detection accuracy from being lowered due to electromagnetic noise -20- 200914919 Low. The nth first side photosensor 351-n overlaps with the kth first side light receiving opening portion 99 1-k. In the kth first side light receiving opening portion 99l-k, since the black matrix 94 0 on the counter substrate 912 is removed, the external light passes through the kth first side light receiving opening portion 991-k to reach the nth number. A side photosensor 3 5 1 - η is formed. k is a number corresponding to n, n = 8 1~160 corresponds to k=l, n = 241~320 corresponds to k = 2 ′ n = 40 1~80 corresponds to k = 3.  Here, The anode region 61〇P_n is interposed with the contact hole being connected to the anode electrode 615 (615-n). Here, Cathode regions 610N-n are interposed with contact holes that are connected to cathode electrode 616 (616-n). The light-shielding electrode 611-n and the transparent shielding electrode 6 1 2-n are connected to the BT electrode 6 1 7 ( 6 17-n) via the contact hole. and then, Although not shown, However, the anode electrode 61 5·η is connected to the wiring SENSEI, The cathode electrode 616-η is connected to the wiring VSH1, The 6 electrode 6 1 7 - η is also connected to the wiring V S Η 1.  also, The nth side optical sensor 351-n' except one of the first side shading sensor groups does not overlap with the kth first side light receiving opening portion 991-k.  And the anode electrode 615 (615-n) is connected to the wiring VSL1, The cathode electrode 616 (616-rT) is connected to the wiring SENSEI, The BT electrode 617 (617-n') is connected to the wiring VDBT1. The nth first side photosensors 3 5 1 -η of one of the first side light receiving sensor groups are the same, and therefore the description thereof is omitted.  also, In this embodiment, The shading electrode 611-n, Transparent shielding electrode 6 1 2 - η individual islanding, Formed in such a way that there is a gap between them, However, because the first side of the photosensor group is adjacent to the first side shading sensor group,  That is, except η = 80 and η = 81, η=160 and η=161,  -21 - 200914919 n=240 and n=241, Between n=320 and n=321, n=400 and n = 4 0 1 are mutually the same potential, So it can also be short-circuited. Anyway, The gap between the shading electrodes can be prevented from being lost from the gap by covering with a certain metal electrode as in the present embodiment. Further, it is preferable that the circuit area can be reduced by using a bus bar as a metal electrode.  Fig. 10 is a plan enlarged view of the mth second side optical sensor 3 52-m of one of the second side light receiving sensor groups. The example is the same as in Figure 5. The mth second side photo sensor 352-m, By the anode region 620P (620P-m), Authentic area 6201 ( 620 I-m ), The cathode region is formed by 6 2 ON ( 6 2 ON - m ), It is disposed between the data line 202-m and the data line 2〇2-m + l, It is formed to overlap the j-th second side light receiving opening portion 92-j. j is a number corresponding to m, m=l~240 corresponds to j = l, n = 481~720 corresponds to j=2, 111==961 ~1200 corresponds to j = 3, m=1441 ～1680 corresponds to j=4.  Except the anode area 620P-m, Authentic area 620I-m, The cathode region 62〇N-m is respectively parallel to the length of the joint surface of 25 μm. With the anode region of Figure 8 610Ρ-Π, Authentic area 610Ι-η, Since the cathode regions 610Ν-η have the same configuration, the description thereof will be omitted. In addition, The mth second side optical susceptor 352-m is formed by overlapping the entire area with the shading electrode 621 (62l-m) and the transparent shielding electrode 622 (622-m). These are the same configurations as those of the shading electrodes 6 1 1-n and the transparent shielding electrodes 612-n of Fig. 8, respectively, and the description thereof is omitted. In addition, The anode region 620P-m and the anode electrode 625 (625-m) are connected by a contact hole, The cathode region 620N-m and the anode electrode 626 (626-m) are connected by a contact hole and are connected by the 'shading electrode 621-m and the transparent shielding electrode 622-m and the BT electrode 627 (627-m) -22-200914919. Contact holes are connected, These are also related to the anode electrode 615-η of Figure 8, Cathode electrode 616-η, Since the ruthenium electrode 617-η has the same configuration, the description thereof will be omitted. Along the D-D of Figure 10, The cross-sectional view is also different from the cross-sectional view of C-C' of Fig. 9 except for the symbols. Therefore, the description is omitted.  also, The m'th second side photo sensor 352-m' excluding one of the second side shading sensor groups does not overlap with the jth second side light receiving opening portion 992-j. And the anode electrode 62 5 ( 625 -m ) is connected to the wiring VSL2, Cathode electrode 626 (626-m') is connected to wiring SENSE2, The BT electrode 627 (627-m') is connected to the outside of the wiring VDBT2. It is the same as the mth second side photo sensor 3 52-m of one of the second side light receiving sensor groups.  The nth third side photo sensor 3 5 3 -η is compared with the nth first side photo sensor 351-η, Except that it is located between the capacitance line 203 -n-l and the capacitance line 2〇3_η, The configuration shown in Figure 8 is rotated by 180 degrees. Connect to wiring SENSEI > Wiring VSH1 酉自线VSL1 The part of the wiring BDBT1 is connected to the wiring SENSE3, Wiring VSH3, Wiring VSL3, The wiring VDBT3 is the same except that it is the same, and therefore the description is omitted. In addition, The same 'mth fourth side photosensor 3 54-m is compared with the mth second side photo sensor 352-m, Except for the configuration shown in Figure 10, rotated 180 degrees, Connect to the wiring SENSE2 Wiring VSH2 Wiring VSL2 The part of the wiring BDBT2 is connected to the wiring SENSE4, Wiring VSH4, Wiring VSL4, The wiring VDBT4 is the same except that it is the same, and therefore the description is omitted.  Fig. 11 is a circuit diagram showing the nth detecting circuit 3 6 0 - η (η = 1 to 4) as the detecting circuit 306. Wiring SMP, Wiring VCHG, Wiring RST, Wiring V S L, The wiring V S is connected to the signal input terminal 3 2 0, From -23- 200914919 external power supply circuit 7 8 4 supplies the appropriate potential / signal. Here the wiring v C η G is supplied to the potential VVCHG (=2. 0V), wiring VSL supply potential VVSL ( = 0. 0V), wiring VSH is supplied to potential VVSH (=5_0V). Further, here, the potential V V S L of the wiring V S L is the ground (GN D ) of the liquid crystal display device 910. The output wiring 〇 UTn is connected to the majority circuit 3 70. Further, the wiring VDBT (VDBTn) is connected to one end of the first switch SW1. The wiring VSL (VSLn) is connected to one end of the second switch SW2, and the wiring VSH (VSHn) is connected to one end of the third switch SW3, and the wiring SENSE ( SENSEn) is connected to one end of the fourth switch SW4. Here, the first switch S W 1 to the fourth switch S W 4 are constituted by C Μ Ο S transfer gates. The other end of the first switch S W1 is connected to the wiring ν C η G , the other end of the second switch SW 2 is connected to the wiring VSL, and the other end of the third switch SW 3 is connected to the wiring C SH , and the fourth switch S The other end of W4 is connected to node SIN. The gate electrodes of all the n-channel transistors constituting the first switch SW1 to the fourth switch SW4 are connected to the wiring SMP, and the gate electrodes of all the Ρ channel type transistors are connected to the inverter circuit IN V 1 Output terminal. Further, the input terminal of the inverter circuit INV 1 is connected to the wiring line SMP. The node S IN is connected to one end of the first capacitor C1, and the other end of the first capacitor C 1 is connected to the node A. The source electrode of the initializing transistor N C is connected to the wiring V C H G and supplied with a power source of a potential V V C Η (= 2 · 0 V ). The gate electrode of the initial transistor NC is connected to the wiring RST', and the drain electrode is connected to the wiring S EN S Εη. The node is further connected to the gate electrode of the first N-type transistor 与1 and the gate electrode of the first P-type transistor ρ 1 -24- 200914919 and the gate electrode of the reset transistor NR. Further, it is connected to one end of the second transistor C2. The other end of the second capacitor C2 is connected to the wiring R S T . The drain electrode of the first n-type transistor N1 and the drain electrode of the first P-type transistor P1 and the source electrode of the reset transistor NR are connected to the node B, and the node b is further connected to the second The gate electrode of the N-type transistor N 2 and the gate electrode of the P-type transistor p 2 of the second type. The drain electrode of the second N-type transistor N 2 and the drain electrode of the second P-type transistor P 2 are connected to the node c 'node C and then connected to the third N-type transistor N3. The electrode and the gate electrode of the P-type transistor P3 of the third. The drain electrode of the Nth N-type transistor N 3 and the drain electrode of the 3rd P-type transistor P 3 are connected to the node D, and the node is further connected to the gate of the 4th N-type transistor N4. The electrode is the gate electrode of the P-type transistor P 4 of the fourth. The drain electrode of the fourth N-type transistor N4 and the drain electrode of the fourth P-type transistor P4 are connected to the output wiring OUTn'. The output wiring OUTn is also connected to the drain of the fifth N-type transistor Ν5. electrode. The gate electrode of the fifth 电-type transistor Ν5 and the gate electrode of the fifth 电-type transistor Ρ5 are connected to the wiring RST, and the drain electrode of the fifth 电-type transistor Ρ5 is connected to the fourth Ρ The source electrode of the transistor Ρ4. The source electrode of the first type of transistor Ν1 to the fifth type of transistor Ν5 is connected to the wiring VSL, and is supplied with the potential VVSL (= 〇V). Further, the source electrodes of the first type of transistor Ρ1 to the third type of transistor Ρ3 and the fifth type of transistor Ρ5 are connected to the wiring VSH, and the potential V V S Η (= + 5 V ) is supplied. In addition, the inverter circuit IN V 1 is supplied with a power supply of +9V and -4V. -25- 200914919 Here, in the present embodiment, the first N-type transistor N1 has a channel width of ΙΟμπι, and the second N-type transistor N2 has a channel width of 35 μm, and the third N-type transistor Ν3 The width of the channel is ΙΟΟμηι, the channel width of the fourth 电-type transistor Ν4 is 150μηη, the channel width of the fifth 电-type transistor Ν5 is 150μηη, and the channel width of the sixth 电-type transistor Nil is 4μιη. The seventh N-type transistor N21 has a channel width of 200 μm, the first channel-type transistor Ρ1 has a channel width of ΙΟμιη, and the second Ρ-type transistor Ρ2 has a channel width of 35 μm, and the third has a width of 35 μm. The channel width of the transistor Ρ3 is ΙΟΟμιη, the channel width of the fourth transistor Ρ4 is 300μηη, and the channel width of the fifth transistor Ρ5 is 300μηι, the sixth 电 transistor PI 1 The width of the channel is 200μπι, the channel width of the 7th 电 transistor Ρ21 is 4μηι, the channel width of the reset transistor NR is 2μηι, and the channel width of the initial transistor NC is 50μηι, which constitutes the first switch. SW 1 ~ 4th switch S W4 Ν type transistor and Ρ type transistor channel width is 1〇〇 Ηι, the type of transistor forming the inverter circuit INV1 and the inverter circuit INV2 and the channel of the Ρ-type transistor are 50 μηι wide, and the channel length of all the Ν-type transistors is 8 μm, and all the channels of the 电-type transistor are The length is 6μηι, the mobility of all the Ν-type transistors is 80cm2/Vsec, the mobility of all P-type transistors is 60cm2/Vsec, and the threshold 値 voltage (Vth) of all N-type transistors is +1. 0V, the threshold voltage (Vth) of all P-type transistors is -1. At 0 V, the capacitance of the first capacitor C1 is 1 PF, and the capacitance of the second capacitor C2 is 38 fF. Fig. 1 is a timing chart of signals applied to the wiring RST, the wiring SMP, the common potential wiring 335, the scanning line 201-1, and the scanning line 201-2. Also -26- 200914919, the priority of the map is given priority. The scale of the vertical and horizontal axis is not fixed. The scanning line 2 0 1 -1 and the scanning line 2 0 1 - 2 are driven by the scanning line driving circuit 310, each of which is 1. 7 m seconds is selected 3 1. 2 μsec. Scan line 2 0 1 - 2 is selected on scan line 2 ο 1 -1 3 4. After 6 μsec, it is selected 'The following scan lines 2 01 _ 3 , 20 1-4,. . . Is tied to 34. The interval of 6 μsec is selected in turn. Common potential wiring 3 3 5 for every 3 4. 6 μsec is inverted between the H i g h potential (=5 V ) and the L 〇 w potential (=〇 V ), but the phase is shifted by half a cycle every 1 6 · 7 m seconds. Therefore, the polarity of the common potential wiring 335 applied when the scanning line 201-n is selected is reversed, that is, the so-called 1 H common inversion driving is performed. The RST signal is selected 3 on the scan line 2 0 1 - 1. 2 μ seconds ago was selected 2 7. 7 μsec. At this time, the potential of the common potential wiring 3 3 5 must be L 〇 w potential (=0 V ), and all the scanning lines 201-1 to 20 1 - 48 0 are not selected. The SMP signal is selected after 3·5 μsec by the inversion timing of the common potential wiring 3 3 5 during the period in which the common potential wiring 3 3 5 is L 〇 w. 7μ seconds. The SMP signal must be ON during the period when the RST signal is ◦ 。. Here, when the RST signal, SMP signal, and scan line 201-n are selected, the High potential is +9V, and when not selected, the Low potential is -4V. In this case, when the wiring RST is High (= + 9V), the wiring SENSEn and the node SIN are charged with the potential VVCHG (=2. 0V). Further, the wiring VDBTn is charged with the potential VVCHG, and the wiring VSLn is charged with the potential VVSL, and the wiring VSH is charged with VVSH. In addition, the reset transistor NR is turned on (ON), so the node A and the node B are short-circuited. In this embodiment, the two nodes are charged at 2. 5 V. Further, during the period in which the wiring R S T is High (=9V), the fifth N-type transistor N5 is turned on (ON) -27-200914919, and the fifth P-type transistor P5 is turned off (OFF), so the output wiring OUTn is 0V. When the wiring RST becomes Low (=-4V) after 2 7·7 μsec, the reset transistor NR is turned off, the node A and the node B are electrically disconnected, and the node A is connected to the potential and the wiring R by the combination of the second capacitor C 2 . s T simultaneously drops 0 · 5 V becomes 2. 0V. The wiring RST is at a moment of Low (=-4V) after 27·7 μsec, and the wiring SENSEn is the potential VVCHG (=2. 0V), wiring VSLn is the potential VVSL (=0. 0V), wiring VSHn is potential VVSH (=5. 0V). That is, the group of the photosensors of the first side is oppositely biased by the photosensor group of the fourth side. 0V, by the first side of the shading sensor group, the fourth side of the shading sensor group is reverse biased. 0V. Further, the potential VVSL is output from the output wiring OUTn. At this time, the photosensor group from the first side of the photodetector group to the fourth side of the photosensor group and the fourth side of the shading sensor group to the fourth side of the shading sensor group It becomes equal, and the wiring SENSEn flows into the photocurrent Iphoto of the external illuminance which is irradiated from the photodetector group of the first side to the photodetector group of the fourth side, and the potential of the wiring SENSEn is proportional to the photocurrent Iphot〇 The speed is rising. There is also a current flowing through the wiring V S Η η and the wiring V S L η, which is somewhat close to the potential of the wiring SENSEn, every 69. When the wiring SMP is High (=9 V) for 2 μsec, the switch SW2 and the third switch SW3 are turned ON (ON) and returned to the original potential, and there is almost no change. Further, the relationship between the speed of the potential change of the wiring SENSEn and the amount of light of the light receiving sensor group irradiated to the nth side is expressed in a one-time expression, and the coefficient indicating the slope is the wiring SENSΕn and the spliced side thereof. According to the sum of the load capacitances of the anode electrodes of the sensor group and the cathode electrodes of the n-side shading sensor group, the coefficient of the slope is shown in this embodiment from the first side to the first side. 4 sides (η= 1~4) have no difference', that is, the capacitance of the photocurrent Iphotoj + "wiring SENSEn" of a certain amount of light from the photosensor group of the 4th side of the photosensor group of the 1st side Adjusted in such a way that each side becomes equal. When the wiring R s T is L 〇w ( = - 4 V ), the node A is in a floating state. Therefore, by combining with the capacitance of the first capacitor C1, the potential is increased simultaneously with the node SIN, and the node A and the node SIN are simultaneously raised. Become 2. At 5V, the potential of the output wiring OUTn is inverted to High (=5V). In the present embodiment, the photosensor group of the fourth side from the photosensor group of the first side is disposed close to the display region 310, and the anode electrode 615-Π, the cathode electrode 6 1 6 - η, and the BT electrode 6 1 7 - η intersects with the common potential wiring 3 3 5 . Further, any one of the scanning line 201-η' data line 202-m and the capacitance line 203-η has a capacitance passing through the light-shielding electrode, and electromagnetic noise is easily mixed by these capacitances. In particular, the common potential wiring 3 3 5 and the wiring SENS Εη are combined by a capacitor which cannot be ignored, and the potential of the wiring SENS Εη is up and down due to the polarity of the common potential wiring 3 3 5 . As an example, a timing chart of the wiring SENS Εη is shown in FIG. In this manner, when the common potential wiring 335 is inverted to Low (= 〇V) - High (= 5 V), the wiring SENS Ε η increases the Δν potential by capacitance coupling, and is inverted to High (= 5 V) - Low ( =0 V When ΔV potential drops. However, in the present embodiment, the s Μ P signal turns on the node SIN and the wiring SENSEn only at the time of ON, so that the state of the node SIN does not change when the polarity of the node SIN is reversed as shown in Fig. 12 . That is, the malfunction caused by the inversion of the common potential wiring 3 3 5 by -29-200914919 does not occur. Similarly, in the present embodiment, the wiring VDBTn, the wiring VSLn, and the wiring VSHn (n = 1 to 4) are also electrically connected to the wiring VCHG, the wiring VSL, and the wiring VS 仅 only when the SMP signal is turned on (on), at S Μ The timing of the P signal off (OFF) becomes floating. In this way, the wiring VDBTn, the wiring VSLn, and the wiring VSHn (n = 1 to 4) are also shifted by the capacitance of the Δv due to the capacitance coupling when the polarity of the common potential wiring 3 3 5 is reversed. That is, even if the polarity of the common potential wiring 3 3 5 is reversed, the bias voltage applied by the light receiving sensor group of the first side to the light receiving sensor group of the fourth side is opposite to the light shielding sensor group of the first side. The bias voltage applied by the fourth side of the shading sensor group does not change, that is, the photocurrent Ipho to and the thermal current flowing from the photosensor group of the first side to the photosensor group of the fourth side The thermal current flowing from the shading sensor group of the first side to the shading sensor group of the fourth side is not maintained constant as the polarity of the common potential wiring 3 3 5 is changed. In the present embodiment, since A V is relatively large, such a configuration is adopted. However, when ΔV is relatively small and less than IV, the first switch SW1, the second switch SW2, and the fourth switch SW4 may be removed. A circuit diagram of the nth detecting circuit 3 60, -n of the detecting circuit 3 60' as another configuration example of the detecting circuit in such a case is shown in Fig. 13 . In the other embodiment, the first switch SW1 to the fourth switch SW4 are removed, the wiring VDBTn is short-circuited to the wiring VCHG, and the wiring VSLn is short-circuited to the wiring VSL, and the wiring VSHn is removed from the n-th detecting circuit 360-n shown in FIG. Shorted to the wiring VSH, the wiring SENSEn is short-circuited to the node SIN. With this configuration, the node SIN displays the amplitude of the polarity of the common potential wiring 3 3 5 (it is exactly the diagram shown by the wiring SENSEn of Fig. 12 of -30-200914919). Therefore, if the detection operation is performed while maintaining the original period, the common potential wiring 3 3 5 is inverted to High (=5V), which may cause malfunction. Here, the third N-type transistor N3 to the fifth N-type transistor and the third P-type transistor to the fifth P-type transistor P 5 are removed, and the second N-type transistor N2 and the second are replaced. The drain electrode of the 2P-type transistor P2 is connected to one of the input terminals of the first NAND circuit NAND1, and the other of the input terminals of the first NAND circuit NAND1 is connected to the SMP signal, and the output terminal of the first NAND circuit NAND1 is connected to the second NAND circuit. One of the input terminals of the NAND2 connects the other of the input terminals of the second NAND circuit NAND2 to the output terminal of the third NAND circuit NAND3, and connects one of the input terminals of the third NAND circuit NAND3 to the output terminal of the second NAND circuit NAND2. The other of the input terminals of the NAND circuit NAND3 is connected to the output terminal of the inverter circuit INV3, and the input terminal of the inverter circuit INV3 is connected to the wiring RST. The power supplies of the first NAND circuit NAND1 to the third NAND circuit NAND3 and the inverter circuit INV3 are connected to the wiring VSH and the wiring VSL. The other circuit configurations and operations are the same as those in Fig. 11. Therefore, the same reference numerals will be given thereto, and description thereof will be omitted. In this way, the potential of the node SIN is 2. When the SMP signal is 5 V or higher and the SMP signal is High, the output of the first NAND circuit NAND1 becomes Low. The second NAND circuit NAND2 and the third NAND circuit NAND3 are RS flip-flop circuits (flip-fl〇P). The output of the first NAND circuit NANDI is set to a negative polarity (set) signal, and the output of the inverter circuit INV3 becomes a negative polarity. Set (reset) signal. That is, the reset (RESET) signal -31 - 200914919 becomes High (=9V), the output of the output wiring OUΤη is latched to Low, and the potential of the node SIN is 2. The output of the output wiring 〇UTn is latched to High at 5V or higher and the SMP signal becomes the first timing of High. That is, the detection result of the common potential wiring 3 3 5 during High (= 5 V) is regarded as invalid and does not cause malfunction. Figure 14 is a circuit diagram of a majority circuit 3 70. The input terminals of the fourth NAND circuit NAND11, the fifth NAND circuit NAND12, the sixth NAND circuit NAND13, the seventh NAND circuit NAND14, the eighth NAND circuit NAND15, and the ninth NAND circuit NAND1 are respectively combined with the output wirings OUT1 to OUT4. Any two of them. The output terminals of the fourth NAND circuit NAND11, the fifth NAND circuit NAND12, and the sixth NAND circuit NAND13 are connected to the input terminal of the tenth NAND circuit NAND21, and the output terminals of the seventh NAND circuit NAND14, the eighth NAND circuit NAND15, and the ninth NAND circuit NAND16 are connected to the 11th NAND. The input terminals of the circuit NAND22, the output terminals of the 10th NAND circuit NAND21 and the 1st NAND circuit NAND22 are connected to the input terminal of the first NOR circuit 30, and the output terminal of the first NOR circuit 30 is connected to the input terminal of the inverter circuit in V4. The output terminal of the inverter circuit INV4 is connected to the output wiring OUT. The power supply of the fourth NAND circuit NAND11, the fifth NAND circuit NAND12, the sixth NAND circuit NAND13, the seventh NAND circuit NAND14, the eighth NAND circuit NAND15, the ninth NAND circuit NAND16, the tenth NAND circuit NAND21, the first NAND circuit NAND22, and the first NOR circuit 30 are It is connected to the wiring VSH and the wiring VSL. In the -32-200914919 circuit, when any of the output lines 〇UT1 to 0υτ4 becomes High (=5V), the output wiring OUT outputs High (=, and all of the output wirings OUT1 to OUT4 are Low (=〇). V) When either High (=5V), the circuit of Low (= is output to the output wiring OUT. When this is configured, the wiring RST becomes Low (=-4V) until the output wiring OUT is inverted to High (=5V). The time is inversely proportional to the amount of light irradiation of the second largest side of the amount of light irradiation among the photoreceptor groups of the fourth side from the photosensor group of the first side. In this case, for example, a majority circuit 3 7 is mounted. 0 'The illuminance detection result of each side excludes the result with the highest illuminance to prevent malfunction due to strong light on the side. In addition, the result of low illuminance and the second low result are excluded, for example, even on 4 sides The correct result can be obtained by having fingers on both sides. Fig. 1 is an example of setting the external light detection illuminance and backlight brightness from the output wiring OUT in the present embodiment. It is set such that when the externality is very low Backlight brightness and slow change, slowly increase the change When the brightness is changed to the maximum when the illumination is 500 lux, and then the S-shaped curve of the change is made, the maximum brightness setting is maintained above 1 500 LUX. The curve can also be freely set to prevent the brightness according to the characteristics of the electronic device. The annihilation of a certain period of time makes it possible to change it gently, and it is also possible to make the relationship between brightness and illuminance hysteric (hyste). In addition, it is also possible to make the state of the electronic machine, etc., depending on the waiting time and the operation time. In this way, even in the present embodiment, even if the light-receiving opening portion is extremely close to 5V (only 0V), the portion of the illuminance that is reflected by the sensitization of the light-sensing portion is changed to the outside. The resis operation is not -33- 200914919 area, using the common inversion drive method, there will be no malfunctions. Because of the high precision, the display device can be set to the most appropriate to improve visual confirmation and reduce power consumption. Also contributed. 1 to 2 sides are covered with a finger, or the light is illuminated to a certain place to correctly measure the external ambient light, so that the backlight brightness is always kept at the maximum 1 [Second Embodiment] FIG. 16 is related to the second embodiment. The plane enlarged view of the nth first side photosensor 351-n, which is the first side of the light receiving light, is shown in Fig. 8 of the first embodiment. The example is the same as in Figure 5. Figure 16 is centered on the difference of 8. In Fig. 16 and Fig. 8, the scanning line 201-n is formed by interposing a contact hole with a wiring formed by aluminum ammonium: A1N d ) in a region overlapping the plane of the 6 1 1 — n plane, at the scanning line 2 0 1 - A common potential 6 1 8 composed of molybdenum (Mo ) is formed between η and 6 1 hn . The common potential branch wiring 6 1 8 -η is interposed by the contact hole potential wiring connection, and a common potential (COM) is supplied. The other 16 is different from that of FIG. 8, and the same reference numerals are given to the same, and the explanation is omitted. FIG. 1 is a plan enlarged view of the n-th second-side photosensor 352-n related to the second-side light-receiving feeling of the second embodiment. Figure 1 is a diagram of the first embodiment. The example is the same as in Figure 5. Figure 1 shows the difference between Figure 10 and the center. 17 and FIG. 10, the data line 202-n and the light-shielding (62 1 -η ) are formed in a plane overlapping area, and the molybdenum film is used as the light detecting intensity, and in addition, sometimes the detector group is Corresponding to the common potential branching of the light-shielding electrode film (the light-shielding electrode line and the common point 'the detector group, corresponding to the following electrode 621:Mo)-34-200914919 Wiring 6 2 8 - η. The common potential branching and cultivating 6 2 8 system is connected to the common potential wiring by interposing the contact hole, and is provided with a common stomach & (COM). In the other points, Fig. 17 and Fig. 1 are not different, so the same reference numerals are given and the description is omitted. The configuration of the active matrix substrate 101 and the liquid crystal display device 91 of the present embodiment is the same as that of the first embodiment, and the configuration of the electronic device, the setting of the external illuminance and the degree of deviation are also the same as those of the first embodiment, and thus the description thereof is omitted. In the present embodiment, compared with the first embodiment, the portion where the scanning line 2 0 1 - η overlaps the plane of the @ % electrode 611-η, and the portion where the data line 202-η overlaps the plane of the shading electrode 6 2 1 - η, Since the interval is arranged to be connected to the common potential branch wirings 6 1 8 - η, 6 2 8 - η of the common potential wiring 3 3 5, there is no direct cross capacitance. Therefore, when the potentials of the scan lines 201-n and the data lines 2〇2_n are changed, that is, the scan lines 2 0 1 -η are selected by the scan line drive circuit 3 〇1 or the data lines 202-η are driven by the data lines. When the potentials (images) are written to 3 02 or the precharge circuit 303, the potentials of the light-shielding electrodes 61 and the light-shielding electrodes 621-n are not easily changed. When the potentials of the light-shielding electrodes 61 1-n and the light-shielding electrodes 621 - η are changed, the potentials of the wiring SENSEI and the wiring SENS E2 are also changed in accordance with the capacitance. This embodiment can perform higher-accuracy illuminance than the first embodiment. Determination. Further, the wiring for shielding from the gap is connected to the common potential wiring 3 3 5, so that a power supply for shielding the new wiring is not required. The common potential wiring 3 3 5 is extremely effective as a shielding potential in order to maintain the image quality as it is originally low impedance. The common potential wiring 3 3 5 has a problem of being a noise to the light-shielding electrode because it is driven in reverse. However, in the present embodiment, since the same driving as in the first embodiment -35-200914919 is performed, there is no common cause. The accuracy of the potential variation is reduced by the electrical connection. On the other hand, the capacitance of the common potential wiring 3 3 5 is increased, so there is a problem. In order to select the configuration of the first embodiment or the second one, it is only necessary to select the advantages and disadvantages described above and select the use. Further, in the present embodiment, only the mask of the second side photosensors 3 5 2 - η superimposed on the nth 3 5 1 - η and the nth is applied to the η 353 as needed. - η, nth fourth side photo sensor 354-η shielding [third embodiment] FIG. 18 is related to the active moment block diagram of the third embodiment, and the following description is made with the first embodiment. The difference between the board 101 of Fig. 2 and the same reference numerals as those of Fig. 2 of the first embodiment will be omitted. In the present embodiment, the first side photo sensors 351-1 to 3 5 1 -480 are used as the photo sensor 351'-1 to 351'-4 80 as the photo sensor 3: the second side light sensation 352_1~352-1920 as light photosensors 3 5 2'-1~3 52'· 1 920 as light sensing: instead of 3rd side photo sensor 3 5 3 - 1~3 5 3 -48 0 as side light sensor 3 5 3 ' -1~3 5 3,-4 8 0 as light sensing instead of 4th side light sensor 3 5 4 - 1~3 54- 1 920 for 4 side light sense 354'-1~354'-1920 as light! In the present embodiment, the first side photosensor of the electronic device is used for the configuration of the embodiment in which the power consumption is increased, etc.: the photoelectrode seeks the spring 3 side photosensor photoelectrode. . The same constituents of the active matrix base shown in the matrix substrate 1 0 2 are configured to configure the first side light 5 Γ of the detector of the first embodiment, and the second edger 3 5 2 ' of the sensor instead of the sensor is configured. The third sensor of the Twilight Sensor 3 5 3 ' is configured, and the first Detector 3 54' of the photo sensor is equipped with -36 - 200914919. Further, instead of the first detecting circuit 3 6 0 - 1 to the fourth detecting circuit 3 6 0 - 4, the detecting circuit 3 6 1 is disposed. Among the first side photosensors 351'-1 to 351'-4 80, the first side light receiving opening 991-1 to the third one side light receiving opening 991-3 overlap. One side of the light sensor group) and the wiring SENSE (SENSEP) continue to overlap (the first side shading sensor group) and the wiring SENSE (SENSED). Similarly, among the second side photosensors 3 5 2, -1 to 352'-1920, the first and second side light receiving openings 992-1 to the fourth side second light receiving openings 9 92-4 The overlap (the second side photodetector group) is connected to the wiring SEN SEP, and there is no overlap (the second side shading sensor group) is connected to the wiring SENSED; the third side photo sensor 3 5 3 '-1 Among the 3 3 3'-48 0, the third light receiving opening portion 993 -1 to the third third light receiving opening portion 993 -3 overlaps (the third side light receiving sensor group) and Wiring SENSEP continues, no overlap (3rd side shading sensor group) and wiring SENSED; 4th side photo sensor 3 54'-1~ 354'-1920, and 1st 4th side The light-receiving opening portion 994-1 to the fourth fourth-side light-receiving opening portion 994-4 overlap (the fourth-side light receiving sensor group) and the wiring SENSEP are connected, and there is no overlap (fourth side light-shielding sensor group) Connected to the wiring SENSED. Wiring SENSED and wiring S EN S E P is connected to the detecting circuit 3 6 1 , and the output wiring OUT of the detecting circuit 3 6 1 is externally connected through the signal input terminal 3 20 . Fig. 19 is an n-th first side photosensor 351 related to one of the first side light receiving sensor groups of the third embodiment, and a plane enlarged view of -n corresponds to the first embodiment. Figure 8 The example is the same as in Figure 5. The following is a description of Fig. 19 centering on the difference from Fig. 37-200914919. The first side photosensor 351'-n of the nth portion of Fig. 19 is composed of an anode region 610, (610 Ρ '-η), a true region 610 Ι ' (610 Ι '-η), and a cathode region 61 ON, (610 Ν '- The lateral type PIN diode composed of η) is the same as the anode region 610P-n, the true region 6101-n, and the cathode region 610N-n described in FIG. 8 of the first embodiment, and thus is omitted. Description. The anode region 6 1 0P '-η intervenes with contact holes connected to the anode electrode 615' (615'-η), and the anode electrode 615'-η is connected to the wiring 8£>. The cathode region 61 (^'-]1, the light-shielding electrode 611' (611'-11), and the transparent shielding electrode 612'-η as the transparent shielding electrode 612' are respectively connected to the common potential wiring 3 3 5 ' through the contact hole. The common potential (COM) is provided. Other points are not the same as those in Fig. 8. Therefore, the same reference numerals will be given, and the description will be omitted. The first side photosensor of the first η' for one of the first side shading sensor groups. 35, -η', and the anode opening electrode 991_3 are not overlapped with any of the first first light receiving opening 991-1 to the third one, and the anode electrode 615, (61 5'- η') is the same as that illustrated in Fig. 19 except for being connected to the wiring SENSED. Fig. 20 is the mth second side photosensor of one of the second side light receiving sensor groups of the third embodiment. The plane enlarged view of 352'-m corresponds to the figure of Fig. 1 of the first embodiment. The example is the same as Fig. 5. Hereinafter, Fig. 20 will be described centering on the difference from Fig. 1 。. The second side photosensor 3 52'-m is composed of an anode region 620P, (62〇P'-m) 'true region 620I' (620I'-m), cathode region -38- 20091491 9 lateral PIN diodes of the domain 620N, (620N'-m), which are respectively associated with the anode region 620P-m, the true region 620I-m, and the cathode illustrated in Fig. 1 of the first embodiment. Since the region 620N-m has the same configuration, the description thereof will be omitted. The anode region 62 OP'-m is interposed with the contact hole being connected to the anode electrode 625' (625'-m), and the anode electrode 625'-m is connected to the wiring SENSEP. The 620N'-m, the transparent shielding electrode 622' (622'·n), and the light-shielding electrode 621' (621'-η) are respectively connected to the common potential wiring 3 3 5 through the contact hole, and are supplied with a common potential (COM). 20 is different from FIG. 10, and therefore the same reference numerals will be given, and the description will be omitted. The second side photo sensor 352, -η' of the η' of one of the second side shading sensor groups, except The first second light receiving opening 992-1 to the fourth second light receiving opening 992-4 are not overlapped with the anode electrode 625, and (625'-ι) is connected to the wiring SENSED. The same as described in Fig. 19, the description is omitted. The third side photo sensor of the η 3 5 3 '-η and the ηth 1 side photo sensor 3 5 1,- η comparison, except for the capacitance line 2 0 3 -η -1 and the capacitance line 2 0 3 - η, the configuration shown in Figure 20 is rotated by 18 degrees. The description is omitted, and the fourth side photo sensor 3 54'-n of the nth is compared with the second side photo sensor 3 5 2 '-n of the nth' except for the configuration rotation shown in FIG. The remainder is the same as 1 to 80 degrees, so the description is omitted. Fig. 21 is a circuit diagram of the detecting circuit 3 61. Wiring SMP1, wiring S Μ P 2, wiring R S T, wiring V C H G, wiring V S L, wiring V S Η is connected to the signal input terminal 3 2 ,, and the potential/signal of the appropriate -39- 200914919 is supplied from the external power supply circuit 784. Here wiring VCHG supply potential VVCHG (=-2. 0V), wiring VSL supply potential VVSL (=0. 0V), wiring VSH supply potential V V S Η ( = 5 · 0 V ). Further, the potential VVSL of the wiring V S L is the ground (GND) of the liquid crystal display device 910. Output wiring ◦ UTn is connected to the signal input terminal 3 20 and output to an external circuit. The wiring SENSED is connected to one end of the fifth switch SW5, and the wiring SENSEP is connected to one end of the sixth switch SW6. The other ends of the fifth switch SW5 and the sixth switch S W6 are connected to the node S IN '. Here, the fifth switch SW5 to the sixth switch SW6 are constituted by CMOS transfer gates. The gate electrode of the n-channel type transistor constituting the fifth switch SW5 is connected to the wiring SMP 1, and the gate electrode of the P-channel type transistor is connected to the output terminal of the inverter circuit IN V 5 . The input terminal of the inverter circuit IN V5 is connected to the wiring SMP1. Further, the gate electrode of the n-channel type transistor constituting the sixth switch SW6 is connected to the wiring S ΜΡ 2, and the gate electrode of the p-channel type transistor is connected to the output terminal of the inverter circuit IN V 6 . The input terminal of the inverter circuit INV6 is connected to the wiring SMP2. Further, the node S IN ' is connected to one end of the third capacitor C 3 and the gate electrode of the initializing transistor NC', and the other end of the third capacitor C3 is connected to the node A '. The source electrode of the initializing transistor NC' is connected to the power supply of the potential V V C H G (= - 2 · 0 V ) to the wiring V C H G '. The gate electrode of the initial transistor N C ' is connected to the wiring r s Τ. The node A is further connected to the gate electrode of the Nth N-type transistor N, 1 and the gate electrode of the P-type transistor P'1 of the 6th and the gate electrode of the reset transistor NR. Further, it is connected to one end of the fourth transistor C4. The fourth capacitor -40- 200914919 The other end of the C4 is connected to the wiring RST. The drain electrode of the sixth N-type transistor N '1 and the drain electrode of the sixth P-type transistor P'1 and the source electrode of the reset transistor NR' are connected to the node B' 'node B' Further, it is connected to the gate electrode of the seventh n-type transistor n, 2 and the gate electrode of the seventh P-type transistor P' 2 . The drain electrode of the seventh N-type transistor N'2 and the drain electrode of the seventh P-type transistor P'2 are connected to the node C'' node C' and are then connected to the eighth N-type transistor. The gate electrode of Ν'3 and the gate electrode of the P-type transistor P'3 of the eighth. The drain electrode of the eighth N-type transistor N'3 and the drain electrode of the eighth P-type transistor P'3 are connected to the node D', node D, and then connected to the ninth N-type transistor. The gate electrode of N ' 4 and the gate electrode of the P-type transistor P ' 4 of the ninth. The drain electrode of the ninth N-type transistor N'4 and the drain electrode of the ninth P-type transistor P'4 are connected to the output wiring ουτ, and the output wiring OUT is also connected to the tenth N-type transistor. N'5's drain electrode. The gate electrode of the Nth transistor N'5 of the 10th and the gate electrode of the p-type transistor P'5 of the 1st electrode are connected to the wiring RsT, the p-type transistor P'5 of the 10th The drain electrode is connected to the source electrode of the P-type transistor P'4 of the ninth. The source electrode of the sixth N-type transistor Ν'1 to the 10th N-type transistor Ν '5 is connected to the wiring V S L and supplied with the potential V V S L (=0 V ). Further, the source electrodes of the sixth 电-type transistor p'1 to the eighth 电-type transistor P'3 and the tenth P-type transistor P'5 are connected to the wiring VS Η, and are supplied with the potential VVS Η ( = + 5 V ). Further, the inverter circuit INV5 and the inverter circuit INV6 are supplied with power supplies of +9V and -4V. Here, in the present embodiment, the channel width -41 - 200914919 of the 6th type of transistor ν ' 1 is ΙΟμιη, and the channel width of the 7th N-type transistor N'2 is 35μηι, the 8th type The channel width of the transistor Ν'3 is ΙΟΟμιη, the channel width of the ninth type transistor Ν'4 is 150μηι, and the channel width of the 10th 电 transistor Ν'5 is 150μπι, the sixth Ρ The channel width of the type transistor P'l is ΙΟμιη, the channel width of the P-type transistor P'2 of the seventh type is 35 μm, and the channel width of the eighth type of transistor P'3 is ΙΟΟμιη, the ninth The channel width of the 电-type transistor P'4 is 300 ηηι, the channel width of the 10th 电 transistor P'5 is 300μηι, and the channel width of the reset transistor NR' is ΙΟμηι, the initial transistor NC The channel width of the channel is 150 μm, and the channel width of the Ν-type transistor and the Ρ-type transistor constituting the fifth switch S W5 to the sixth switch SW6 is 1 〇〇 8 μm, and constitutes the inverter circuit INV5 and the inverter circuit. The channel width of the INV6 Ν-type transistor and the Ρ-type transistor is 50μηη, and the channel length of all the Ν-type transistors is 8 μηι. The channel length of all 电-type transistors is 6μηι, the mobility of all Ν-type transistors is 80cm2/Vsec, the mobility of all Ρ-type transistors is 60cm5/Vsec, and the threshold voltage of all N-type transistors ( Vth ) is + 1 .  0 V, the threshold voltage (Vth) of all P-type transistors is -1. At 0V, the capacitance of the third capacitor C3 is lpF, and the capacitance of the fourth capacitor C4 is 38fF. Next, Fig. 22 is a timing chart of this embodiment. Taking the visibility of the map as a priority, the scale of the vertical and horizontal axes is not fixed. The common potential wiring 3 3 5, the scanning line 201 -1, the scanning line 201-2, and the wiring RST are as described in Fig. 12 of the first embodiment, and thus the description thereof is omitted. The wiring SMP1 is selected when the common wiring 3 3 5 is Low (=0V). 8 μsec, the period is 69·2 μsec. The wiring SMP2 is also wired when the common wiring 3 3 5 is Low - 42 - 200914919 SMP1 is selected for 13·8 μsec. When the wiring SMP1 and the wiring SMP2 are selected, that is, the signal of +9V when the potential is High, and the signal of -4V when the potential is Low, that is, when the potential is Low. When the circuit is configured as such, the common potential wiring 3 3 5 is in the middle of Low (= 〇V), the wiring SMP1 is selected first, the wiring SENSED is connected to the node SIN', and the node A' and the node B' are reset by the transistor NR. ' And short circuit, is charged to 2 · 5 V. The output to the output wiring OUT must be Low (=〇V). After 13·8 μsec, the wiring SMP1 becomes non-selected and the wiring SMP2 is selected. The wiring SEN SEP is connected to the node SIN. The node 1 and the node B' are electrically separated, and the potential of the node A' is lowered by the fourth capacitor C4. 2·〇ν. Thereafter, the potential passing through the fifth switch SW5 node SIN' is changed by the potential of the wiring SENSED toward the wiring SENSEP, and the potential of the node A' is also changed by capacitive coupling. That is, before the wiring SMP2 becomes non-selected, the potential of the node A is "2. 0V"+"potential of wiring SENSEP" - "potential of wiring SENSED", this 超过 exceeds 2. The 5V detection circuit 361 outputs High to the output wiring OUT. The potential of the wiring S EN SED is proportional to the slope of the thermal current flowing from the shading sensor group of the first side to the shading sensor group of the fourth side, and the potential of the wiring SENSEP is compared with the first side. The slope of the "thermal current" + "photocurrent 1Photo" flowing through the photosensor group on the 4th side of the photosensor group changes, so the potential difference between the wiring SENSEP and the wiring SENSED is the same as the photocurrent Iph〇t〇 The proportional slope changes. Thus, as in the first embodiment, the period from when the wiring RST is not selected until the output wiring OUT first becomes H i g h becomes a reciprocal ratio of the external illuminance. -43- 200914919 Next, the common potential wiring 3 3 5 is reversed to High (=5 V ) before the wiring S Μ P 1 and the wiring S Μ Ρ 2 are not selected, and the common potential wiring 3 3 5 is High (=5 V ) It was not selected during the period. As shown in Fig. 12, the wiring SENSED and the wiring SENSEP shown by the wiring SENSEP are reversed to High (=5V) when the common potential wiring 3 3 5 is inverted, and the potential is increased by about 5 V due to the capacitance coupling. However, similarly, as shown in Fig. 12, the first switch SW5 and the sixth switch SW6 are turned off during this period, so the potential of the node SIN' is not affected. In other words, similarly to the first embodiment, it is not affected by the inversion of the common potential wiring 3 3 5 and can be detected with high precision. The configuration of the detecting circuit 361 of the present embodiment is shorter than the configuration of the detecting circuit 360 of the first embodiment in that the node A in the circuit is floating, and has an advantage that the noise is not affected. On the other hand, it is easy to be affected by the switching noise of the switch SW5 and the sixth switch SW6, and the accuracy is deteriorated. To choose which component to use, just consider the advantages of both and then choose. In either configuration, the common potential (COM) of the timing of the reset operation (in the embodiment, the potential of the wiring RST returns to Low) and the detection circuit 361 operate (in the embodiment, the wiring S MP, the wiring) It is important that the common potential (COM) of the period in which the SMP1 and the wiring SMP2 are in the high state are the same. 'As long as the circuit has such a configuration, various circuits other than the circuits exemplified in the present specification may be used for the detection. Circuit 3 6 1. The liquid crystal display device of the present embodiment is not different from the liquid crystal display device 910 of the first embodiment shown in Fig. 1 except that the active matrix substrate 1 〇丨 is replaced by the main matrix substrate 1200. Further, the configuration of the sub-machine, the setting of the external illuminance and the brightness, and the like are also the same as those of the first embodiment, and therefore will not be described. In the present embodiment, the common potential (COM) of the common potential wiring 3 3 5 is used in the power supply of the photo sensor. In the present embodiment, the light-shielding electrode/transparent electrode is also connected to the common potential wiring 33 5, so that the photo sensor is almost completely integrated to the common potential (COM) of the common potential wiring 3 3 5 , and the wiring SEN SEP and the wiring SENSED become common to each other. The potential wiring 335 oscillates at approximately the same potential in the same cycle/phase. Therefore, the bias voltage applied to the diode hardly changes with the polarity of the common potential wiring 3 3 5 . Further, since the number of wirings can be significantly reduced as compared with the first embodiment, the outer dimensions of the liquid crystal display device can be reduced. On the other hand, the power supply potential of the detection circuit 361 can be a DC potential, so it can be shared with the power supply potential of the scanning line driving circuit 301 or the data line driving circuit 306, without making the number of supplied power supplies unprofitable. increase. Further, when there is a possibility that the potential of the common potential wiring 3 3 5 fluctuates or the image quality is affected by the increase in noise, a configuration in which another power source potential is supplied to the photo sensor may be employed. Further, in the present embodiment, the wiring SENSEP and the wiring SENSED which are connected to the entire side are connected to one detection circuit 361. However, as in the first embodiment, the wiring SENSEP and the wiring SENSED are separated on each side, and the detection circuit 3 6 1 is disposed on each side. 1 to 3 6 1 -4, the output may be determined by the majority circuit 3 70 shown in the first embodiment. Further, in contrast, in the case of the nth detecting circuit 3 60-n of the first embodiment, the wiring of each side may be short-circuited. If the short-circuiting sides of the present embodiment are such that the detection circuit is one, the circuit scale can be greatly reduced, and the appearance of the liquid crystal display device 9 10 can be reduced. -45-200914919 On the other hand, the external illuminance that can be detected is on each side. The average of the external illuminance, when the finger or the like greatly shields the external light, the external illuminance is detected to be darker than the actual. Regardless of which one is selected, the configuration of the electronic device, the method of operation, the size of the liquid crystal display device, and the like may be determined. Further, in each of the embodiments of the present specification, the photosensor is disposed on the four sides of the display area 3 1 ,. However, when there is a limitation such as an outer shape, the photo sensor may be disposed on three or less sides. [Industrial Applicability] The present invention is not limited to the implementation type, and is not limited to the TN mode, and may be used in a vertical alignment mode (VA mode), an I ps mode using a lateral electric field, or a fringe electric field. A liquid crystal display device such as an FFS mode. In addition, it is not only a full transmission type, but also a total reflection type or a reflection type. Further, not only a liquid crystal display device but also an organic EL display or a field emission type display can be used for a semiconductor device other than the liquid crystal display device. Further, not only the control of the display brightness of the external light as shown in the present embodiment but also the brightness or chromaticity of the display device can be used to feed back the display device without color shift or ageing. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of a liquid crystal display device 9 10 according to an embodiment of the present invention. FIG. 2 is a second embodiment of a second embodiment of the present invention, and the active moment-46-200914919 array substrate 1 is related to the present invention. The composition of 0 1 . Fig. 3 is a diagram showing a pixel circuit of the active matrix substrate 101 of the embodiment of the present invention. 4 is a block diagram showing an embodiment of an electronic machine of the present invention. Fig. 5 is a plan view showing a pixel portion of an active matrix substrate ιοί according to an embodiment of the present invention. Figure 6 is a cross-sectional view taken along line A - A' of Figure 5. Figure 7 is a cross-sectional view taken along line B-B' of Figure 5. Fig. 8 is a plan enlarged view of the nth first side photosensor 351-n which is one of the first side light receiving sensor groups according to the first embodiment of the present invention. Figure 9 is a cross-sectional view taken along line C - C ' of Figure 8. Figure 10 is a plan enlarged view of the n-th second-side photosensor 3 52-n of one of the second-side light-receiving sensor groups according to the first embodiment of the present invention. A circuit diagram of the nth detecting circuit 3 60-n of the embodiment of the invention. Figure 12 is a timing diagram relating to an embodiment of the present invention. Figure 13 is a circuit diagram of an nth detection circuit 360'-η associated with other embodiments of the present invention. Fig. 14 is a circuit diagram of a majority circuit 370 related to an embodiment of the present invention. Fig. 15 is a diagram showing the setting of the detected illuminance and the backlight luminance of the external light according to the embodiment of the present invention. Figure 16 is a plan enlarged view of the nth first side photosensor 3 5 1 -η of one of the detector groups of the second embodiment of the present invention. Fig. 18 is a plan enlarged view of the nth second side photosensor 352-n of one of the second side light receiving sensor groups according to the second embodiment of the present invention. Fig. 18 is related to the present invention. A configuration diagram of the active matrix substrate 110 of the third embodiment. 19 is a plan enlarged view of the n-th first side photosensor 351-n of one of the first side light receiving sensor groups according to the third embodiment of the present invention. FIG. 20 is related to the present invention. FIG. 21 is a plan view of the third n-th photosensor 3 5 2 - η of the second side light receiving sensor group of the third embodiment. FIG. 21 is related to the third embodiment of the present invention. The circuit diagram of the detection circuit 3 6 1 . Fig. 2 is a timing chart relating to a third embodiment of the present invention. [Description of main component symbols] '101,102: Active matrix substrate 201, 201-1~201-480: Scanning line 202. 202- 1 ~ 202- 1 920: data line 203. 203- 1~203-480: Capacitor line 3 〇1: Scanning line drive circuit 3 〇2 : Data line drive circuit -48- 200914919 3 03 : Charging circuit 3 1 0 : Display area 3 20 : Signal input terminal 3 3 0 : Pair of guides 3 3 5 : Common potential wirings 351, 351'352, 352', 353, 353, 354, 354,: Photosensors 351-1 to 351-480, 351'-1 to 351'-480: as photosensors The first side light sensor 352- 1 ~ 352-1920, 352'-1 ~ 352'-1920: as the second side light sensor of the light sensor 353-1 to 353-480, 353'-1 ~ 353'-480: 3rd side light sensor as photo sensor 3 5 4- 1 ~ 3 5 4- 1 920, 3 5 4'-1 〜 3 5 4'- 1 920 ·· as light perception The fourth side photo sensor of the detector 3 60, 3 60', 361: detection circuit 3 70: majority circuit 401: pixel switching element 4 0 2 : pixel electrode 403: auxiliary capacitor capacitor 602: Shixia Island (silicon island) 6 0 3 : source electrode 6 0 4 : drain electrode 610P, 610P', 620P, 620P': anode region 610N, 610N', 620N, 62 0N': cathode region -49- 200914919 6101,6101 ,,6201,6201': the true area 611,611', 621,621 ': shading electrode 6 1 2,622,622': transparent shielding electrode 615, 615', 625, 625': anode electrode 616, 626: cathode electrode 6 1 7, 627: BT electrode 7 8 0: image processing circuit 7 8 1 : central calculation circuit 7 82: External I/F circuit 7 84 : External power supply circuit 7 8 5 : Refer to Table 7 8 3 : Input/output device 9 1 0 — Liquid crystal display device 9 1 2 : Counter substrate 921 : Extension portion 922 : Nematic liquid crystal Material 9 2 3 : Sealing material 924 : Upper polarizing plate 925 : Lower polarizing plate 926 : Backlight unit 927 : Light guide plate 92 8 : FPC 929 as a flexible substrate : Connector 9 3 0 : Counter electrode as a common electrode -50- 200914919 940: Black matrix 991-1 to 991-3: first first side light receiving opening part - third first side light receiving opening part 992-1 to 992-4: first second side receiving light The opening portion to the fourth second side light receiving opening portion 993-1 to 993-3: the first third side light receiving opening portion to the third third side light receiving opening portion 994-1 to 994-4: the first The fourth side light receiving opening portion - the fourth fourth side light receiving opening portion SENSE, VSH, VSL, VDBT, VCHG: wiring - 51 -

Claims (1)

200914919 十、申請專利範圍 1_ 一種顯示裝置’係於基板上具備 顯示用之主動矩陣電路、 被接續於前述主動矩陣電路而傳達驅動訊號之複數匯 流排線、以及 對前述複數匯流排線輸出驅動訊號之驅動電路之顯示 裝置，其特徵爲： 於前述基板上具備光感測器， 前述光感測器， 被配置於以前述複數匯流排線區隔的複數次區域， 前述複數次區域被配置於前述主動矩陣電路與前述驅 動電路之間。 2 ·如申請專利範圍第1項之顯示裝置，其中具備： 被接續於前述主動矩陣電路之複數畫素電極、 在第1電位與電位比前述第1電位更低的第2電位之 間被反轉驅動的共通電極、 藉由對前述複數畫素電極與前述共通電極之間施加的 電場而改變配向狀態之液晶元件、 被接續於前述光感測器的感測器配線、以及 被接續於前述感測器配線而檢測出前述感測器配線的 電位或者電流之檢測電路； 前述檢測電路，係前述共通電極以前述第1電位或第 2電位之任一方的計時，檢測前述感測器配線的電位或者 電流。 -52 - 200914919 3 ·如申請專利範圍第2項之顯示裝置，其中 前述檢測電路反覆進行使前述感測器配線的電位回到 初期狀態之重設動作， fill述重設動作，係前述共通電極以前述第1電位或第 2電位之前述任一方之他方的計時進行的。 4.如申請專利範圍第2或3項之顯示裝置，其中 前述感測器配線，係以與前述共通電極相同之計時改 變電位。 5 _如申請專利範圍第3或4項之顯示裝置，其中 前述感測器配線，係與前述共通電極短路。 6 _如申請專利範圍第3至5項之任一項之顯示裝置， 其中 前述感測器配線， 在前述共通電極於前述第1電位或第2電位之前述任 一方之他方的期間中’被接續至由外部供給電位之電源配 線，而於一方之期間成爲浮動狀態。 7_如申請專利軔圍第1至6項之任一項之顯示裝置， 其中 在與前述光感測器平面重疊的區域形成第1電極， 於前述第1電極與前述匯流排線平面重疊的區域，配 置第2電極。 8 ·如申請專利範圍第7項之顯示裝置，其中 前述第2電極與共通電極接續。 9.如申請專利範圍第8項之顯示裝置，其中 -53- 200914919 前述第1電極係供遮住背光之用的複數遮光電極， 於前述複數遮光電極間之間隙，配置前述匯流排線$ 前述第2電極。 1 0 如申請專利範圍第1至9項之任一項之顯示裝_ ，其中 前述複數次區域係沿著前述主動矩陣電路之外周部$ 邊配置的。 1 1 ·如申請專利範圍第2至9項之任一項之顯示裝 ，其中 前述檢測電路係由複數檢測電路所構成， 具備與前述複數檢測電路接續之多數決電路，前述多 數決電路， 在來自前述複數之檢測電路之複數輸出結果之中，2 以上之輸出結果改變時’使輸出改變。 12.如申請專利範圍第10項之顯示裝置，其中 前述複數檢測電路’具備第1檢測電路與第2檢測電 路， 前述第1檢測電路之次區域與前述第2檢測電路之次 區域，被配置於前述主動矩陣電路之外周部之不同的邊。 1 3 .如申請專利範圍第1至1 2之任一項之顯示裝置， 其中 前述光感測器係使用薄膜多晶矽之PIN接合二極體或 者PN接合二極體’ 前述驅動電路藉由使用薄膜多晶矽的電晶體來構成。 -54- 200914919 1 4 · 一種電子機器，其特徵爲使用申請專利範圍第1 至1 3項之任一項所記載的顯示裝置。 -55-200914919 X. Patent Application Scope 1_ A display device is provided with an active matrix circuit for display on a substrate, a plurality of bus bars connected to the active matrix circuit to transmit a driving signal, and a driving signal for outputting the plurality of bus bars The display device of the driving circuit is characterized in that: the substrate is provided with a photo sensor, and the photo sensor is disposed in a plurality of sub-regions separated by the plurality of bus bars, and the plurality of sub-regions are arranged The foregoing active matrix circuit is connected to the aforementioned driving circuit. 2. The display device according to claim 1, wherein the plurality of pixel electrodes connected to the active matrix circuit are reversed between a first potential and a second potential lower than a potential of the first potential a common electrode for driving, a liquid crystal element that changes an alignment state by an electric field applied between the plurality of pixel electrodes and the common electrode, a sensor wiring connected to the photosensor, and is connected to the foregoing a detection circuit for detecting a potential or a current of the sensor wiring by the sensor wiring; wherein the detection circuit detects the sensor wiring by using one of the first potential or the second potential Potential or current. The display device of claim 2, wherein the detection circuit repeatedly performs a reset operation for returning the potential of the sensor wiring to an initial state, and the reset operation is the common electrode It is carried out by the other of the first potential or the second potential. 4. The display device of claim 2, wherein the sensor wiring is changed in time by the same timing as the common electrode. The display device of claim 3, wherein the sensor wiring is short-circuited with the common electrode. The display device according to any one of claims 3 to 5, wherein the sensor wiring is 'in the period in which the common electrode is in the other of the first potential or the second potential The power supply wiring is supplied to the external potential, and is in a floating state during one period. The display device according to any one of claims 1 to 6, wherein the first electrode is formed in a region overlapping the plane of the photosensor, and the first electrode overlaps with the bus bar plane. In the area, the second electrode is placed. 8. The display device of claim 7, wherein the second electrode is connected to the common electrode. 9. The display device of claim 8, wherein -53-200914919, the first electrode is a plurality of light-shielding electrodes for shielding a backlight, and the bus bar line is disposed in a gap between the plurality of light-shielding electrodes The second electrode. The display device according to any one of claims 1 to 9, wherein the plurality of sub-areas are disposed along the outer side of the active matrix circuit. The display device according to any one of claims 2 to 9, wherein the detection circuit is constituted by a plurality of detection circuits, and has a plurality of circuit blocks connected to the plurality of detection circuits, and the plurality of circuit blocks are Among the complex output results from the above-described plurality of detection circuits, when the output result of 2 or more is changed, the output is changed. 12. The display device according to claim 10, wherein the complex detection circuit ' includes a first detection circuit and a second detection circuit, and a sub-region of the first detection circuit and a sub-region of the second detection circuit are arranged Different sides of the outer periphery of the aforementioned active matrix circuit. The display device according to any one of claims 1 to 12, wherein the photosensor is a PIN-bonded diode or a PN-bonded diode of a thin film polysilicon. The driving circuit is formed by using a thin film. Polycrystalline germanium is formed by a transistor. -54-200914919 1 4 - An electronic device characterized by using the display device according to any one of claims 1 to 13. -55-
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