CN101303497A - Display device and electronic apparatus including display device - Google Patents

Display device and electronic apparatus including display device Download PDF

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Publication number
CN101303497A
CN101303497A CNA2008100985084A CN200810098508A CN101303497A CN 101303497 A CN101303497 A CN 101303497A CN A2008100985084 A CNA2008100985084 A CN A2008100985084A CN 200810098508 A CN200810098508 A CN 200810098508A CN 101303497 A CN101303497 A CN 101303497A
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China
Prior art keywords
aforementioned
wiring
circuit
sensor
electrode
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Granted
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CNA2008100985084A
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Chinese (zh)
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CN101303497B (en
Inventor
小桥裕
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Japan Display West Inc
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Sanyo Epson Imaging Devices Corp
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Publication of CN101303497A publication Critical patent/CN101303497A/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/03—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on ceramics or electro-optical crystals, e.g. exhibiting Pockels effect or Kerr effect
    • G02F1/0327—Operation of the cell; Circuit arrangements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line

Abstract

A display device includes an active matrix circuit for display, a plurality of bus lines which are connected to the active matrix circuit and which are used to transmit driving signals, driving circuits which supply the driving signals to the plurality of bus lines, the plurality of bus lines and the driving circuits being arranged on a substrate, and optical sensors arranged on the substrate. The optical sensors are arranged in a plurality of sub regions separated using the plurality of bus lines. The plurality of sub regions are arranged between the active matrix circuit and each of the driving circuits.

Description

Display device and possess the electronic equipment of this display device
Technical field
The present invention relates to display device for example and possess the electronic equipment of this display device.
Background technology
In recent years, developing on the display device, especially adopted the technology (for example patent documentation 1) of carrying the optical sensor function in the liquid crystal indicator of thin film transistor (TFT).The purpose of carrying optical sensor can be enumerated 3: (1) is measured the back by external light brightness etc. is adjusted, and seeks to consume that electric power reduces, picture element improves; (2) backlight is measured, brightness or colourity are adjusted; (3) position of finger, light pen is distinguished and used as membrane keyboard.Can enumerate thin film transistor (TFT), PIN (p-intrinsic-n, p-intrinsic-n) diode, PN diode etc. as optical sensor.Under any circumstance photographic department all is a silicon thin film, for the cost that does not make manufacturing increases, preferably makes in same manufacturing process with the silicon thin film that constitutes the on-off element that shows.
2,006 one No. 118965 communiques of [patent documentation 1] TOHKEMY
The precision of measuring from illuminance, the viewpoint in the design, the preferred light sensor the viewing area that display device is approached in the position is set, but in driving circuit internally-arranged type liquid crystal indicator, be difficult to dispose optical sensor in the inboard of driving circuit.And, under the situation of configuration like this, optical sensor is subjected to the influence of the electrical noise of viewing area driving easily, and can not ignore the influence that produces by parasitic light from the viewing area, so there is the problem of the precise decreasing of optical sensor, it is particularly remarkable to carry out under the situation of the anti-phase driving of common potential this problem in liquid crystal indicator.
Summary of the invention
Display device of the present invention is made of active-matrix substrate, and this active-matrix substrate possesses optical sensor, show the active matrix circuit of usefulness, be connected in aforementioned active matrix circuit and transmit the multiple bus of drive signal and to the driving circuit of aforementioned multiple bus output drive signal; This display device is characterised in that the aforementioned lights sensor configuration is being divided a plurality of subregions that form by aforementioned multiple bus; Aforementioned a plurality of subregion is disposed between aforementioned active matrix circuit and the aforementioned driving circuit.If like this configuration, even driving circuit internally-arranged type display then, also optical sensor can be disposed at the viewing area near, so can correctly measure outer illuminance, the design of electronic devices degree of freedom of lift-launch also improves.
And, the invention is characterized in: also possess a plurality of pixel electrodes that are connected in aforementioned active matrix circuit, between the 1st current potential and the 2nd current potential by the common electrode of anti-phase driving, and put on the electric field liquid crystal cell that changes of state of orientation accordingly between aforementioned a plurality of pixel electrode and the aforementioned common electrode, the testing circuit that is connected in the sensor wiring of aforementioned lights sensor and is connected in sensor as aforementioned wiring, the current potential or the electric current of sensor as aforementioned wiring detected; Aforementioned testing circuit is that either party timing in aforementioned the 1st current potential or the 2nd current potential detects the current potential or the electric current of sensor as aforementioned wiring at aforementioned common electrode.If constitute like this, then can either drive (common AC driving) and reduce the consumption electric power of liquid crystal indicator, thereby can prevent from again to cause the sensor wiring potential change to cause precision to reduce by the electromagnetic noise of the anti-phase generation of common electrode with by coupling capacitance with common electrode by common electrode being carried out shared AC anti-phase driving, so-called.
And of the present invention being characterized as: aforementioned testing circuit makes the current potential of sensor as aforementioned wiring turn back to the work that resets of original state repeatedly; The timing that the aforementioned work that resets is finished is that aforementioned common electrode is aforementioned the 1st current potential and current potential than either party timing in the 2nd low current potential of aforementioned the 1st current potential.Set if so, though then sensor wiring because of with the coupling capacitance luffing of common electrode carry out work under the initial state because testing circuit turns back to often at current potential, so accuracy of detection does not descend.
And of the present invention being characterized as: the current potential of sensor as aforementioned wiring and the current potential of aforementioned common electrode change in same timing.Like this, the impedance of the coupling capacitance between the sensor as aforementioned of forgetting it wiring and the common electrode, sensor as aforementioned wiring, thus the degree of freedom of arranging raising, and the profile that can dwindle panel.Particularly, be characterized as sensor as aforementioned wiring and aforementioned common electrode short circuit.Coupling capacitance in this case,, sensor wiring equates, so can be ignored because becoming with the current potential of common electrode.Perhaps, be characterized as: sensor as aforementioned wiring, only the timing of the specific potential among aforementioned common electrode is aforementioned different a plurality of current potentials is connected in the power-supply wiring of supplying with current potential from the outside, becomes (floating) state of floating during remaining.If constitute like this, then sensor wiring because of with the coupling capacitance luffing of common electrode, so even with the coupling capacitance of common electrode greatly or the big situation of the resistance of sensor wiring also harmless.
And of the present invention being characterized as: have and be formed at the 1st electrode of overlooking overlapping areas with the aforementioned lights sensor; Overlook overlapping areas in aforementioned the 1st electrode and aforementioned bus and dispose the 2nd electrode.If constitute like this, even then form the 1st electrode, also can reduce the aforementioned lights sensor and be subjected to the influence of the potential change of bus (sweep trace, data line etc.) by the 1st electrode for the purpose of shading, shielding, precision further improves.And feature of the present invention also is: aforementioned the 2nd electrode is connected with common electrode.Because common electrode designs output impedance, wiring impedance low in order to improve picture element, thus if as the current potential stiff end of the 2nd electrode shielding properties improve, so and do not need unnecessary wiring can reduce the profile of display device.
And of the present invention being characterized as: have 1st electrode overlapping with the aforementioned lights sensor, aforementioned the 1st electrode is a plurality of shading electrodes that are used for backlight is carried out shading; At aforementioned bus of the interelectrode gap configuration of aforementioned a plurality of shadings or aforementioned the 2nd electrode.If configuration bus on the crack betwixt when making backlight shading electrode and optical sensor overlapping, then unglazed leakage can prevent parasitic light.
And of the present invention being characterized as: aforementioned a plurality of subregions are along many limit configurations of the peripheral part of aforementioned active matrix circuit.Because at many limit configuration optical sensors, so the difference of the parasitic light that is caused by the show state of liquid crystal is little, and, especially touch panel is overlapped under the situation that display device uses, thereby, influence also less even when pointing close shut out the light etc. for operation.
And of the present invention being characterized as: aforementioned testing circuit is a plurality of testing circuits; Possesses the majority decision circuit that is connected with aforementioned a plurality of testing circuits; Aforementioned majority decision circuit when variation has taken place the output result more than 2 among a plurality of output results at aforementioned a plurality of testing circuits, changes output.If constitute like this, even otherwise then occurring the shade that produces because of finger as described above or have spot light on arbitrary limit than outer light intensity, this regional result also can be excluded, so accuracy of detection further improves.And then in the present invention, also propose in the lump: be connected in aforementioned a plurality of subregions by the sensor as aforementioned wiring, along certain bar limit configuration of the peripheral part of aforementioned active matrix circuit as the 1st testing circuit of one of aforementioned a plurality of testing circuits; Be connected in another aforementioned a plurality of subregions of the 2nd testing circuit by sensor as aforementioned wiring, along other limits configurations of the peripheral part of aforementioned active matrix circuit as aforementioned a plurality of testing circuits.If constitute like this, then because get with the limit result's who is unit majority decision, so even can not delay work when only otherwise shade or irradiation light occurring on specific limit yet, can be more externally light detect.
And of the present invention being characterized as: the aforementioned lights sensor is PIN junction diode or the PN junction diode that has adopted membrane polysilicon, and aforementioned driving circuit constitutes by the transistor that has adopted membrane polysilicon.If constitute like this, then can form optical sensor and thin film transistor (TFT) with same manufacturing process, so even built-in optical sensors, cost does not increase yet.
And the electronic equipment of these display device has been adopted in proposition in the present invention.Because built-in high-precision optical sensor so can easily control backlight corresponding to outer light, can not make consumption electric power increase invalidly, cost can not rise yet.And, because can be near ground, viewing area configuration optical sensor, so the degree of freedom of design also can improve.
Description of drawings
Fig. 1 is the stereographic map of the liquid crystal indicator 910 in the embodiments of the invention.
Fig. 2 is the pie graph of the active-matrix substrate 101 among the of the present invention the 1st and the 2nd embodiment.
Fig. 3 is the image element circuit figure of the active-matrix substrate 101 in the embodiments of the invention.
Fig. 4 is the block diagram of the embodiment of expression electronic equipment of the present invention.
Fig. 5 is the vertical view of the pixel portions of the active-matrix substrate 101 in the embodiments of the invention.
Fig. 6 is the sectional view along Fig. 5 A-A '.
Fig. 7 is the sectional view along Fig. 5 B-B '.
Fig. 8 be a sensor in conduct the 1st limit photosensitive sensor group of the 1st embodiment of the present invention n the 1st marginal ray sensor 351-n overlook enlarged drawing.
Fig. 9 is the sectional view along Fig. 8 C-C '.
Figure 10 be a sensor in conduct the 2nd limit photosensitive sensor group of the 1st embodiment of the present invention n the 2nd marginal ray sensor 352-n overlook enlarged drawing.
Figure 11 is the circuit diagram of n testing circuit 360-n in the embodiments of the invention.
Figure 12 is the sequential chart in the embodiments of the invention.
Figure 13 is the circuit diagram of n testing circuit 360 '-n among other embodiment of the present invention.
Figure 14 is the circuit diagram of the majority decision circuit 370 in the embodiments of the invention.
Figure 15 is the detection illumination of the exterior light in the embodiments of the invention and the setting figure of back light source brightness.
Figure 16 be a sensor in conduct the 1st limit photosensitive sensor group of the 2nd embodiment of the present invention n the 1st marginal ray sensor 351-n overlook enlarged drawing.
Figure 17 be a sensor in conduct the 2nd limit photosensitive sensor group of the 2nd embodiment of the present invention n the 2nd marginal ray sensor 352-n overlook enlarged drawing.
Figure 18 is the pie graph of the active-matrix substrate 102 among the 3rd embodiment of the present invention.
Figure 19 be a sensor in conduct the 1st limit photosensitive sensor group of the 3rd embodiment of the present invention n the 1st marginal ray sensor 351 '-n overlook enlarged drawing.
Figure 20 be a sensor in conduct the 2nd limit photosensitive sensor group of the 3rd embodiment of the present invention n the 2nd marginal ray sensor 352 '-n overlook enlarged drawing.
Figure 21 is the circuit diagram of the testing circuit 361 among the 3rd embodiment of the present invention.
Figure 22 is the sequential chart among the 3rd embodiment of the present invention.
Symbol description
101,102... active-matrix substrate, 201,201-1～201-480... sweep trace, 202,202-1～202-1920... data line, 203,203-1～203-480... electric capacity line, 301... scan line drive circuit, 302... data line drive circuit, 303... pre-charge circuit, 310... viewing area, 320... signal input terminal, 330... subtend conducting portion, 335... common potential wiring, 351,351 ', 352,352 ', 353,353 ', 354,354 ' ... optical sensor, 351-1～351-480,351 '-1～351 '-480... is as the 1st marginal ray sensor of optical sensor, 352-1～352-1920,352 '-1～352 '-1920... is as the 2nd marginal ray sensor of optical sensor, 353-1～353-480,353 '-1～353 '-480... is as the 3rd marginal ray sensor of optical sensor, 354-1～354-1920,354 '-1～354 '-1920... is as the 4th marginal ray sensor of optical sensor, 360,360 ', 361... testing circuit, 370... majority decision circuit, 401... pixel switch element, 402... pixel electrode, 403... auxiliary capacitor capacitor, 602... silicon island, 603... source electrode, 604... drain electrode, 610P, 610P ', 620P, 620P ' ... anode region, 610N, 610N ', 620N, 620N ' ... cathode zone, 610I, 610I ', 620I, 620I ' ... intrinsic region, 611,611 ', 621,621 ' ... the shading electrode, 612,622,622 ' ... transparent guarded electrode, 615,615 ', 625,625 ' ... positive electrode, 616,626... negative electrode, 617,627...BT electrode, 780... image processing circuit, 781... central computing circuit, 782... exterior I/F circuit, 784... external power source circuit, 785... reference table, 783... input-output device, 910... liquid crystal indicator, 912... subtend substrate, 921... extension, 922... nematic liquid crystal material, 923... encapsulant, 924... upper deflection board, 925... lower polarizing plate, 926... backlight unit, 927... light guide plate, 928... FPC as flexible base, board, 929... connector, 930... counter electrode as common electrode, 940... black matrix, the 1st the 1st limit sensitization peristome～3rd of 991-1～991-3... the 1st limit sensitization peristome, the 1st the 2nd limit sensitization peristome～4th of 992-1～992-4... the 2nd limit sensitization peristome, the 1st the 3rd limit sensitization peristome～3rd of 993-1～993-3... the 3rd limit sensitization peristome, the 1st the 4th limit sensitization peristome～4th of 994-1～994-4... the 4th limit sensitization peristome, SENSE, VSH, VSL, VDBT, VCHG... wiring.
Embodiment
Below, based on description of drawings the specific embodiment of the present invention.
The 1st embodiment
Fig. 1 is the three-dimensional composition figure (part sectioned view) of the liquid crystal indicator 910 of present embodiment.Liquid crystal indicator 910 constitutes, with active-matrix substrate 101 and subtend substrate 912 by encapsulant 923 with certain interval fit, clamping nematic liquid crystal material 922.The oriented material that coating is made of polyimide etc. on active-matrix substrate 101 also rubs (rubbing) thereby handles and form alignment films (not shown).And, subtend substrate 912, be formed with: corresponding to the color filter (not shown) of pixel, be used to prevent light leak, make black matrix 940 that contrast improves is made of low reflection, low transmissivity resin and with active-matrix substrate 101 on subtend conducting portion 330 (330-1,330-2) short circuit by the film formed counter electrode 930 of ITO as common electrode.With 922 contacted of nematic liquid crystal materials on the oriented material that constitutes by polyimide etc. of coating, with the direction of the friction treatment of the alignment films of active-matrix substrate 101 mutually the direction of quadrature be implemented friction treatment.
And then at the outside of subtend substrate 912 configuration upper deflection board 924, at the outside of active-matrix substrate 101 configuration lower polarizing plate 925, and make mutual polarization direction mutually orthogonally (cross Nicols (cross nicol) shape) be configured.And then below lower polarizing plate 925, configuration backlight unit 926 and light guide plate 927, from backlight unit 926 towards light guide plate 927 irradiates lights, light guide plate 927 becomes towards active-matrix substrate 101 vertical and uniform surface light source the feasible light from backlight unit 926 of light reflected refraction, and the light source as liquid crystal indicator 910 works thus.Backlight unit 926 is the LED unit in the present embodiment, but also can be cold-cathode tube (CCFL).Backlight unit 926 is connected in the electronic equipment body by connector 929, thereby is supplied to power supply, has in the present embodiment by power supply being adjusted into suitable appropriate electric current, voltage to adjust function from the light quantity of backlight unit 926.
Though not shown, but and then around can also be as required covering with shell, glass, the acrylic panel of protection usefulness perhaps are installed on upper deflection board 924, can also attach optical compensation films in order to improve field angle.
And active-matrix substrate 101 is provided with the extension 921 that stretches out from subtend substrate 912, installs and be electrically connected FPC928 as flexible base, board at the signal input terminal 320 that is positioned at this extension 921.FPC928 as flexible base, board is connected in the electronic equipment body, is supplied to essential power supply, control signal etc.
And then on liquid crystal indicator 910, the black matrix of removing on the subtend substrate 912 by part 940 forms the 1st the 1st limit sensitization peristome 991-1～3rd the 1st a limit sensitization peristome 991-3, the 1st the 2nd limit sensitization peristome 992-1～4th the 2nd a limit sensitization peristome 992-4, the 1st the 3rd limit sensitization peristome 993-1～3rd the 3rd a limit sensitization peristome 993-3, the 1st the 4th limit sensitization peristome 994-1～4th the 4th a limit sensitization peristome 994-4 respectively, makes outside light arrive on the active-matrix substrate 101 by these peristomes.
Fig. 2 is the block diagram of active-matrix substrate 101.Viewing area 310 on active-matrix substrate 101, as active matrix circuit, be formed with 480 sweep traces 201 (201-1～201-480) and 1920 data lines 202 (202-1～202-1920), 480 electric capacity lines 203 (203-1～203-480) and sweep trace 201 (201-1～201-480) configuration concurrently orthogonally.Electric capacity line 203 (203-1～203-480) short circuit mutually, be connected with common potential wiring 335, and then with 2 subtend conducting portions 330 (thereby 330-1～330-2) is connected by signal input terminal 320 common potential is provided, this common potential is the inversion signal of 0V～5V, anti-phase time to be 35 microseconds (μ seconds).(201-1～201-480) be connected in scan line drive circuit 301, (202-1～202-1920) be connected in data line drive circuit 302 and pre-charge circuit 303 suitably is driven respectively data line 202 sweep trace 201.And scan line drive circuit 301, data line drive circuit 302, pre-charge circuit 303 are supplied with from signal input terminal 320 and are driven necessary signal.Signal input terminal 320 is disposed on the extension 921.Scan line drive circuit 301, data line drive circuit 302, pre-charge circuit 303 form by integrated polycrystalline SiTFT on active-matrix substrate 101, make in same operation with pixel switch element 401 described later (401-n-m), thereby become the liquid crystal indicator of so-called driving circuit internally-arranged type.
And, in the zone that is held on scan line drive circuit 301 and viewing area 310, dispose 480 the 1st marginal ray sensor 351-1～351-480 as optical sensor as optical sensor 351.Sequence number is that n the 1st marginal ray sensor 351-n of n is disposed at the zone (example of subregion) between sweep trace 201-n and the sweep trace 201-n+1 respectively.At this, the 81st the 1st marginal ray sensor 351-81～160th the 1st a marginal ray sensor 351-160 and the 1st the 1st limit sensitization peristome 991-1 overlook overlay configuration, the 241st the 1st marginal ray sensor 351-241～320th the 1st a marginal ray sensor 351-320 and the 2nd the 1st limit sensitization peristome 991-2 overlook overlay configuration, and the 401st the 1st marginal ray sensor 351-401～480th the 1st a marginal ray sensor 351-480 and the 3rd the 1st limit sensitization peristome 991-3 overlook overlay configuration.It is the 1st limit photosensitive sensor group that among general name these and the 1st the 1st limit sensitization peristome 991-1～3rd the 1st limit sensitization peristome 991-3 certain is overlooked overlapping n the 1st marginal ray sensor 351-n.And, general name not with the 1st the 1st limit sensitization peristome 991-1～3rd the 1st a limit sensitization peristome 991-3 in any equitant n the 1st marginal ray sensor 351-n be the 1st limit shading sensor groups.
Similarly, in the zone that is held on pre-charge circuit 303 and viewing area 310, dispose 1920 the 2nd marginal ray sensor 352-1～352-1920 as optical sensor as optical sensor 352.Individual the 2nd marginal ray sensor 352-n of n is disposed at the zone (example of subregion) between data line 202-n and the data line 202-n+1 respectively.At this, the 1st the 2nd marginal ray sensor 352-1～240th the 2nd a marginal ray sensor 352-240 and the 1st the 2nd limit sensitization peristome 992-1 overlook overlay configuration, the 481st the 2nd marginal ray sensor 352-481～720th the 2nd a marginal ray sensor 352-720 and the 2nd the 2nd limit sensitization peristome 992-2 overlook overlay configuration, the 961st the 2nd marginal ray sensor 352-961～1200th the 2nd a marginal ray sensor 352-1200 and the 3rd the 2nd limit sensitization peristome 992-3 overlook overlay configuration, and the 1441st the 2nd marginal ray sensor 352-1441～1680th the 2nd a marginal ray sensor 352-1680 and the 4th the 2nd limit sensitization peristome 992-4 overlook overlay configuration.It is the 2nd limit photosensitive sensor group that some among general name these and the 1st the 2nd limit sensitization peristome 992-1～4th the 2nd limit sensitization peristome 992-4 overlooked overlapping n the 2nd marginal ray sensor 352-n.And, general name not with the 1st the 2nd limit sensitization peristome 992-1～4th the 2nd a limit sensitization peristome 992-4 in any equitant n the 2nd marginal ray sensor 352-n be the 2nd limit shading sensor groups.
Similarly, viewing area 310 with scan line drive circuit 301 clampings relative to circumference in, dispose 480 the 3rd marginal ray sensor 353-1～353-480 as optical sensor 353 as optical sensor.Individual the 3rd marginal ray sensor 353-n of n is disposed at the zone between electric capacity line 203-n and the electric capacity line 203-n-1 respectively.At this, the 1st the 3rd marginal ray sensor 353-1～80th the 3rd a marginal ray sensor 353-80 and the 1st the 3rd limit sensitization peristome 993-1 overlook overlay configuration, the 161st the 3rd marginal ray sensor 353-161～240th the 3rd a marginal ray sensor 353-240 and the 2nd the 3rd limit sensitization peristome 993-2 overlook overlay configuration, and the 321st the 3rd marginal ray sensor 353-321～400th the 3rd a marginal ray sensor 353-400 and the 3rd the 3rd limit sensitization peristome 993-3 overlook overlay configuration.It is the 3rd limit photosensitive sensor group that among general name these and the 1st the 3rd limit sensitization peristome 993-1～3rd the 3rd limit sensitization peristome 993-3 certain is overlooked overlapping n the 3rd marginal ray sensor 353-n.And, general name not with the 1st the 3rd limit sensitization peristome 993-1～3rd the 3rd a limit sensitization peristome 993-3 in any equitant n the 3rd marginal ray sensor 353-n be the 3rd limit shading sensor groups.
Similarly, in being held on the zone of data line drive circuit 302 and viewing area 310, dispose 1920 the 4th marginal ray sensor 354-1～354-1920 as optical sensor as optical sensor 354.Individual the 4th marginal ray sensor 354-n of n is disposed at the zone between data line 202-n and the data line 202-n+1 respectively.At this, the 241st the 4th marginal ray sensor 354-241～480th the 4th a marginal ray sensor 354-480 and the 1st the 4th limit sensitization peristome 994-1 overlook overlay configuration, the 721st the 4th marginal ray sensor 354-721～960th the 4th a marginal ray sensor 354-960 and the 2nd the 4th limit sensitization peristome 994-2 overlook overlay configuration, the 1201st the 4th marginal ray sensor 354-1201～1440th the 4th a marginal ray sensor 354-1440 and the 3rd the 4th limit sensitization peristome 994-3 overlook overlay configuration, and the 1681st the 4th marginal ray sensor 354-1681～1920th the 4th a marginal ray sensor 354-1920 and the 4th the 4th limit sensitization peristome 994-4 overlook overlay configuration.It is the 4th limit photosensitive sensor group that among general name these and the 1st the 4th limit sensitization peristome 994-1～4th the 4th limit sensitization peristome 994-4 certain is overlooked overlapping n the 4th marginal ray sensor 354-n.And, general name not with the 1st the 4th limit sensitization peristome 994-1～4th the 4th a limit sensitization peristome 994-4 in any equitant n the 4th marginal ray sensor 354-n be the 4th limit shading sensor groups.
At this, the 1st limit photosensitive sensor group is connected in wiring SENSE (SENSE1) and wiring VSH (VSH1).The 1st limit shading sensor groups is connected in wiring SENSE1, wiring VSL (VSL1) and wiring VDBT (VDBT1).The 2nd limit photosensitive sensor group is connected in wiring SENSE (SENSE2) and wiring VSH (VSH2).The 2nd limit shading sensor groups is connected in wiring SENSE2, wiring VSL (VSL2) and wiring VDBT (VDBT2).The 3rd limit photosensitive sensor group is connected in wiring SENSE (SENSE3) and wiring VSH (VSH3).The 3rd limit shading sensor groups is connected in wiring SENSE3, wiring VSL (VSL3) and wiring VDBT (VDBT3).The 4th limit photosensitive sensor group is connected in wiring SENSE (SENSE4) and wiring VSH (VSH4).The 4th limit shading sensor groups is connected in wiring SENSE4, wiring VSL (VSL4) and wiring VDBT (VDBT4).
Wiring SENSE1, wiring VSH1, wiring VSL1 and wiring VDBT1 are connected in the 1st testing circuit 360-1 as testing circuit 360.Wiring SENSE2, wiring VSH2, wiring VSL2 and wiring VDBT2 are connected in the 2nd testing circuit 360-2 as testing circuit 360.Wiring SENSE3, wiring VSH3, wiring VSL3 and wiring VDBT3 are connected in the 3rd testing circuit 360-3 as testing circuit 360.Wiring SENSE4, wiring VSH4, wiring VSL4 and wiring VDBT4 are connected in the 4th testing circuit 360-4 as testing circuit 360.
From the output of the 1st testing circuit 360-1 wiring OUT1, from the output wiring OUT2 of the 2nd testing circuit 360-2, be connected in majority decision circuit 370, be connected in external circuit by one of signal input terminal 320 from the output wiring OUT of majority decision circuit 370 from the output wiring OUT3 of the 3rd testing circuit 360-3 and output wiring OUT4 from the 4th testing circuit 360-4.
Fig. 3 is that the sequence number in the viewing area 310 is near the circuit diagram of cross part of the data line 202-m of m and the sweep trace 201-n that sequence number is n.Each intersection point at sweep trace 201-n and data line 202-m forms the pixel switch element 401-n-m that is made of N channel-type field effect polycrystalline SiTFT, its gate electrode is connected in sweep trace 201-n, and source, drain electrode are connected to data line 202-m and pixel electrode 402 (402-n-m).Pixel electrode 402-n-m and form auxiliary capacitor capacitor 403 (403-n-m) at the electrode of same current potential and this pixel electrode short circuit and electric capacity line 203-n, and when being assembled into liquid crystal indicator and counter electrode 930 clampings liquid crystal cell and form capacitor.
Fig. 4 is the block diagram of concrete formation of the electronic equipment of expression present embodiment.Liquid crystal indicator 910 is the liquid crystal indicators that are illustrated with Fig. 1, and external power source circuit 784, image processing circuit 780 supply to liquid crystal indicator 910 by FPC928 and the connector 929 as flexible base, board with essential signal and power supply.Central authorities' computing circuit 781 is obtained input data from input-output device 783 by exterior I/F circuit 782.Be meant for example keyboard, mouse, trace ball, LED, loudspeaker, antenna etc. at this input-output device 783.Central authorities' computing circuit 781 carries out various calculation process based on the data from the outside, and the result is transmitted to image processing circuit 780 or exterior I/F circuit 782 as instruction.Image processing circuit 780 changes the signal that sends to liquid crystal indicator 910 based on from the instruction of central computing circuit 781 image information being upgraded, and the display image of liquid crystal indicator 910 changes thus.And, output wiring OUT from the majority decision circuit on the liquid crystal indicator 910 370 is input into central computing circuit 781 by the FPC928 as flexible base, board, and central computing circuit 781 is transformed into corresponding discrete value with the pulse length of binary output signal (OUT).Follow central computing circuit 781 visits by EEPROM (Electronically Erasable and Programmable Read Only Memory, Electrically Erasable Read Only Memory) constitute with reference to table 785, the discrete value that conversion is obtained is transformed into the suitable corresponding value of the voltage with backlight unit 926 again, and is sent in external power source circuit 784.External power source circuit 784 will be corresponding with this transmission value the current potential power supply of voltage be supplied in backlight unit 926 in the liquid crystal indicator 910 by connector 929.Because the brightness of backlight unit 926 changes according to the voltage of being supplied with from external power source circuit 784, so brightness also changes when complete white demonstration of liquid crystal indicator 910.Specifically be meant monitor, TV, notebook personal computer, PDA (Personal Digital (Data) Assistants, individual digital (data) assistant), digital camera, video camera, portable telephone, portable Photo Browser, portable video player, portable dvd player, portable audio player etc. at this electronic equipment.
Also have, though control by the brightness of the 781 pairs of backlight units 926 of central computing circuit on the electronic equipment in the present embodiment, but also can be for for example in liquid crystal indicator 910, possessing the formation that driver IC and EEPROM are arranged, and the mapping function again that this driver IC is had carry out to the mapping function of discrete value conversion, with reference to EEPROM from binary output signal (OUT), adjust adjustment function to the output voltage of backlight unit 926.And, also can be transformed into the value corresponding by numerical evaluation again from discrete value without reference table with the voltage of backlight unit 926.
Fig. 5 is the vertical view of actual formation of the circuit diagram in the pixel display area territory shown in the presentation graphs 3.Shown in the legend of Fig. 5, the different position of each shade is expressed as different respectively material wirings, is expressed as the identical materials wiring with the position shown in the identical shade.Constituted by chromium thin film (Cr), polysilicon membrane (Poly-Si), molybdenum film (Mo), aluminium neodymium alloy film (AlNd), this 5 layer film of indium tin oxide films (Indium tin Oxiced=ITO), between each layer, form any dielectric film in monox, silicon nitride, the organic insulating film or form they have been carried out lamination and dielectric film.Particularly, chromium thin film (Cr) thickness is that 100nm, polysilicon membrane (Poly-Si) thickness are that 50nm, molybdenum film (Mo) thickness are that 200nm, aluminium neodymium alloy film (AlNd) thickness are that 500nm, indium tin oxide films (ITO) thickness are 100nm.And; the underlying insulation film that the silicon oxide film of the silicon nitride film of formation lamination 100nm and 100nm forms between chromium thin film (Cr) and polysilicon membrane (Poly-Si); between polysilicon membrane (Poly-Si) and molybdenum film (Mo), form the gate insulating film that the silicon oxide film by 100nm constitutes; the interlayer dielectric that the silicon oxide film of the silicon nitride film of formation lamination 200nm and 500nm forms between molybdenum film (Mo) and aluminium neodymium alloy film (AlNd); the protection dielectric film that organic planarization film of the silicon nitride film of formation lamination 200nm and average 1 μ m forms between aluminium neodymium alloy film (AlNd) and indium tin oxide films (ITO); make between the mutual wiring and insulate, offer contact hole in position and make it to be connected to each other.Also have, in Fig. 5, do not have chromium thin film (Cr) figure.
As shown in Figure 5, data line 202-m forms by aluminium neodymium alloy film (AlNd), is connected in the source electrode of pixel switch element 401-n-m by contact hole.Sweep trace 201-n is made of molybdenum film (Mo), is also used as the gate electrode of pixel switch element 401-n-m.Electric capacity line 203-n is made of the wiring material identical with sweep trace 201-n, and pixel electrode 402-n-m is made of indium tin oxide films, is connected in the drain electrode of pixel switch element 401-n-m by contact hole.And the drain electrode of pixel switch element 401-n-m also is connected in by high concentration mixes the capacitance part electrode 605 that the n+ type polysilicon membrane of phosphorus constitutes, and overlooks overlapping with electric capacity line 203-n and constitutes auxiliary capacitor capacitor 403-n-m.
Fig. 6 is used for expression that the structure to pixel switch element 401-n-m the describes figure corresponding to the part section structure of the liquid crystal indicator 910 of A-A ' the line part of Fig. 5.Also have, engineer's scale is unfixing for figure is easily seen.Active-matrix substrate 101 is the insulated substrate of 0.6mm for the thickness that is made of alkali-free glass, clip the underlying insulation film that the silicon oxide film of the silicon nitride film of lamination 200nm and 300nm forms thereon and dispose the silicon island 602 that constitutes by polysilicon membrane, sweep trace 201-n and the aforesaid gate insulating film of silicon island 602 clampings and be disposed at the top.Silicon island 602 is LDD (Lightly Doped Drain, lightly doped drain) structure, promptly, with the equitant zone of sweep trace 201-n in for not mixing phosphonium ion fully or only mixing the intrinsic semiconductor region 602I of extremely low concentration phosphonium ion, about the 602I of this zone, exist low concentration ground to mix the n-zone 602L of the sheet resistance of phosphonium ion (sheetresistance), and then the sheet resistance that exists high concentration ground to mix phosphonium ion about the 602I of this zone is the n+ zone 602N of 1k Ω degree for 20k Ω degree.About n+ zone 602N be connected with source electrode 603, drain electrode 604 by contact hole, source electrode 603 is connected with data line 202-m, drain electrode 604 is connected with pixel electrode 402-n-m.Between the counter electrode 930 on pixel electrode 402-n-m and the subtend substrate 912, there is nematic liquid crystal material 922 as common electrode.And black matrix 940 is to be formed on the subtend substrate 912 with the partly overlapping mode of pixel electrode 402-n-m.Also have, become at the light leakage current of pixel switch element 401-n-m under the situation of problem also and can be in the silicon island to form the light shield layer that constitutes by the Cr film 602 times.Because the light leakage current is out of question basically in the present embodiment, and if take so structure, then the mobility of pixel switch element 401-n-m descends, so selected to remove the formation of the Cr film under the silicon island 602.
Fig. 7 is used for expression that the structure to auxiliary capacitor capacitor 403-n-m the describes figure corresponding to the part section structure of the liquid crystal indicator 910 of B-B ' the line part of Fig. 5, and capacitance part electrode 605 that is connected with drain electrode 604 and electric capacity line 203-n clamping gate insulating film overlaid form memory capacitance thus.
Fig. 8 is the enlarged drawing of overlooking as n the 1st marginal ray sensor 351-n of a sensor in the 1st limit photosensitive sensor group.Legend and Fig. 5 are same.Fig. 9 is the figure of expression corresponding to the part section structure of the liquid crystal indicator 910 of line C-C ' the line part of Fig. 8.N the 1st marginal ray sensor 351-n forms by anode region 610P (610P-n), intrinsic region 610I (610I-n), cathode zone 610N (610N-n).Anode region 610P-n, intrinsic region 610I-n, cathode zone 610N-n all be by by with form same island figure that the employed identical polysilicon membrane (Poly-Si) of pixel switch element 401-n-m constitutes and carry out suitable impurity and inject and form.Particularly, inject the boron ion on anode region 610P-n high concentration ground and trimmer resistance is about 2k Ω, inject phosphonium ion on cathode zone 610N-n high concentration ground and trimmer resistance is about 1k Ω.Intrinsic region 610I-n boron ion, phosphonium ion all only denier inject or do not inject fully, form intrinsic semiconductor.So n the 1st marginal ray sensor 351-n forms as lateral type PIN junction diode.The size of intrinsic region 610I-n is to be 100 μ m in the direction that is parallel to the knot face, is 10 μ m in vertical direction.
And, n the 1st marginal ray sensor 351-n is whole with the shading electrode 611 (611-n) that is made of chromium (Cr) film and as the transparent guarded electrode 612-n overlaid of the transparent guarded electrode 612 that is made of indium tin oxide films (ITO), wherein, the indium tin oxide films that constitutes transparent guarded electrode with constitute the identical of pixel electrode 402-n-m.Shading electrode 611-n is incident in the photomask of n the 1st marginal ray sensor 351-n as the light that prevents backlight unit 926 and works.And transparent guarded electrode 612-n prevents that the luminance detection precision that is caused by electromagnetic noise from reducing.N the 1st marginal ray sensor 351-n and k the 1st limit sensitization peristome 991-k overlaid.Because the black matrix 940 on k the 1st limit sensitization peristome 991-k removal subtend substrate 912, so form: outer light arrives n the 1st marginal ray sensor 351-n by k the 1st limit sensitization peristome 991-k.K is the numeral corresponding to n, and n=81～16 are corresponding to k=1, and n=241～320 are corresponding to k=2, and n=401～80 are corresponding to k=3.
Be connected in positive electrode 615 (615-n) at this anode region 610P-n by contact hole.And cathode zone 610N-n is connected in negative electrode 616 (616-n) by contact hole.Shading electrode 611-n and transparent guarded electrode 612-n are connected in BT electrode 617 (617-n) by contact hole.Though not shown, positive electrode 615-n is connected in wiring SENSE1, negative electrode 616-n is connected in wiring VSH1, and BT electrode 617-n also is connected in wiring VSH1.
Also have, as individual the 1st marginal ray sensor 351-n ' of the n ' of a sensor in the 1st limit shading sensor groups except not with k the 1st limit sensitization peristome 991-k overlaid, being connected in wiring VSL1, negative electrode 616 (616-n ') with positive electrode 615 (615-n ') is connected in wiring SENSE1, BT electrode 617 (617-n ') and is connected in outside the wiring VDBT1, identical with n the 1st marginal ray sensor 351-n as a sensor in the 1st limit photosensitive sensor group, so explanation is omitted.
Also have, though make individually islandization of shading electrode 611-n, transparent guarded electrode 612-n in the present embodiment, and form mutual formation gap, but also can be except that the 1st limit photosensitive sensor group and the 1st limit shading sensor groups adjacent, promptly between n=80 and n=81, between n=160 and the n=161, between n=240 and the n=241, between n=320 and the n=321, between n=400 and the n=401, shading electrode 611-n, transparent guarded electrode 612-n are mutually same potential, so short circuit.In a word in any case, the interelectrode gap of shading is if cover the parasitic light that then can prevent from the gap with some metal electrodes as present embodiment, and then preferably as metal electrode employing bus, can reduce circuit area like this.
Figure 10 is the enlarged drawing of overlooking as m the 2nd marginal ray sensor 352-m of a sensor in the 2nd limit photosensitive sensor group.Legend and Fig. 5 are same.M the 2nd marginal ray sensor 352-m, form by anode region 620P (620P-m), intrinsic region 620I (620I-m), cathode zone 620N (620N-m), be disposed between data line 202-m and the data line 202-m+1, form with j the 2nd limit sensitization peristome 992-j overlaid.J is the numeral corresponding to m, and m=1～240, m=481～720, m=961～1200, m=1441～1680 correspond respectively to j=1, j=2, j=3, j=4.
Anode region 620P-m, intrinsic region 620I-m, cathode zone 620N-m except the length that is parallel to the knot face is 25 μ m structure all anode region 610P-n, intrinsic region 610I-n, the cathode zone 610N-n with Fig. 8 is identical, so explanation is omitted.And, m the 2nd marginal ray sensor 352-m whole and shading electrode 621 (621-m) and the formation of transparent guarded electrode 622 (622-m) overlaid ground are so these formations are omitted with shading electrode 611-n and the identical explanation of transparent guarded electrode 612-n of Fig. 8 respectively.And, anode region 620P-m is connected by contact hole respectively with BT electrode 627 (627-m) with negative electrode 626 (626-m), shading electrode 621-m and transparent guarded electrode 622-m with positive electrode 625 (625-m), cathode zone 620N-m, so these formations also are omitted with the identical explanation of positive electrode 615-n, negative electrode 616-n, BT electrode 617-n of Fig. 8 respectively.Because Figure 10 along the sectional view of D-D ' except symbol with the C-C ' of Fig. 9 sectional view there is no the different explanations of also omitting.
Also have, as individual the 2nd marginal ray sensor 352-m ' of the m ' of a sensor in the 2nd limit shading sensor groups except not with j the 2nd limit sensitization peristome 992-j overlaid, be connected in wiring VSL2, negative electrode 626 (626-m ') with positive electrode 625 (625-m ') and be connected in wiring SENSE2, BT electrode 627 (627-m ') and be connected in outside the wiring VDBT2, identical with m the 2nd marginal ray sensor 352-m as a sensor in the 2nd limit photosensitive sensor group.
N the 3rd marginal ray sensor 353-n, the difference of comparing with n the 1st marginal ray sensor 351-n is, between electric capacity line 203-n-1 and electric capacity line 203-n, be shown in the layout Rotate 180 degree of Fig. 8, and make the part that is connected in wiring SENSE1, wiring VSH1, wiring VSL1, wiring VDBT1 be connected in wiring SENSE3, wiring VSH3, wiring VSL3, wiring VDBT3, in addition identical, so omission will be described.And, similarly, m the 4th marginal ray sensor 354-m, the difference of comparing with m the 2nd marginal ray sensor 352-m is, be shown in the layout Rotate 180 degree of Figure 10, and make the part that is connected in wiring SENSE2, wiring VSH2, wiring VSL2, wiring VDBT2 be connected in wiring SENSE4, wiring VSH4, wiring VSL4, wiring VDBT4, and in addition identical, so omission will be described.
Figure 11 is the circuit diagram of expression as n the testing circuit 360-n (n=1～4) of testing circuit 360.Wiring SMP, wiring VCHG, wiring RST, wiring VSL, wiring VSH are connected with signal input terminal 320, supply with suitable current potential, signal by external power source circuit 784.At this, the wiring VCHG be supplied to current potential VVCHG (=2.0V), the wiring VSL be supplied to current potential VVSL (=0.0V), the wiring VSH be supplied to current potential VVSH (=5.0V).Also having, is the GND of liquid crystal indicator 910 at the current potential VVSL of this wiring VSL.Output wiring OUTn is connected in majority decision circuit 370.
And wiring VDBT (VDBTn), wiring VSL (VSLn), wiring VSH (VSHn), wiring SENSE (SENSEn) are connected to an end of the 1st switch SW 1, an end of the 2nd switch SW 2, an end of the 3rd switch SW 3, an end of the 4th switch SW 4.Constitute by CMOS transmission grid in this 1st switch SW 1～the 4th switch SW 4.The other end of the other end of the other end of the other end of the 1st switch SW 1, the 2nd switch SW 2, the 3rd switch SW 3, the 4th switch SW 4 is connected to wiring VCHG, wiring VSL, wiring CSH, node (node) SIN.The gate electrode that constitutes all n channel transistors of the 1st switch SW 1～the 4th switch SW 4 is connected in wiring SMP, and the gate electrode of all p channel transistors is connected in the lead-out terminal of negative circuit INV1.And the input terminal of negative circuit INV1 is connected in wiring SMP.
Node SIN is connected in the end of the 1st capacitor C1, and the other end of the 1st capacitor C1 is connected in node A.The source electrode of initialization transistor NC is connected in wiring VCHG, is supplied to current potential VVCH (=2.0V) power supply.The gate electrode of initialization transistor NC is connected in wiring RST, and drain electrode is connected in wiring SENSEn.Node A also is connected in the gate electrode of the gate electrode of the 1st N transistor npn npn N1, the 1st P transistor npn npn P1 and the drain electrode of reset transistor NR, also is connected in the end of the 2nd capacitor C2.The other end of the 2nd capacitor C2 is connected in wiring RST.The drain electrode of the drain electrode of the 1st N transistor npn npn N1, the 1st P transistor npn npn P1 and the source electrode of reset transistor NR are connected in Node B, and Node B also is connected in the gate electrode of the 2nd N transistor npn npn N2 and the gate electrode of the 2nd P transistor npn npn P2.The drain electrode of the drain electrode of the 2nd N transistor npn npn N2 and the 2nd P transistor npn npn P2 is connected in node C, and node C also is connected in the gate electrode of the 3rd N transistor npn npn N3, the gate electrode of the 3rd P transistor npn npn P3.The drain electrode of the drain electrode of the 3rd N transistor npn npn N3 and the 3rd P transistor npn npn P3 is connected in node D, and node D also is connected in the gate electrode of the 4th N transistor npn npn N4 and the gate electrode of the 4th P transistor npn npn P4.The drain electrode of the drain electrode of the 4th N transistor npn npn N4 and the 4th P transistor npn npn P4 is connected in output wiring OUTn, and output wiring OUTn also is connected in the drain electrode of the 5th N transistor npn npn N5.The gate electrode of the gate electrode of the 5th N transistor npn npn N5 and the 5th P transistor npn npn P5 is connected in wiring RST, and the drain electrode of the 5th P transistor npn npn P5 is connected in the source electrode of the 4th P transistor npn npn P4.The source electrode of the 1st N transistor npn npn N1～5th a N transistor npn npn N5 be connected in the wiring VSL, be supplied to current potential VVSL (=0V).And the source electrode of the 1st P transistor npn npn P1～3rd P transistor npn npn P3 and the 5th P transistor npn npn P5 be connected in the wiring VSH, be supplied to current potential VVSH (=+ 5V).And, to the power supply of negative circuit INV1 supply+9V with-4V.
This in the present embodiment the channel width of the 1st N transistor npn npn N1 be 10 μ m, the channel width of the 2nd N transistor npn npn N2 is 35 μ m, the channel width of the 3rd N transistor npn npn N3 is 100 μ m, the channel width of the 4th N transistor npn npn N4 is 150 μ m, the channel width of the 5th N transistor npn npn N5 is 150 μ m, the channel width of the 6th N transistor npn npn N11 is 4 μ m, the channel width of the 7th N transistor npn npn N21 is 200 μ m, the channel width of the 1st P transistor npn npn P1 is 10 μ m, the channel width of the 2nd P transistor npn npn P2 is 35 μ m, the channel width of the 3rd P transistor npn npn P3 is 100 μ m, the channel width of the 4th P transistor npn npn P4 is 300 μ m, the channel width of the 5th P transistor npn npn P5 is 300 μ m, the channel width of the 6th P transistor npn npn P11 is 200 μ m, the channel width of the 7th P transistor npn npn P21 is 4 μ m, the channel width of reset transistor NR is 2 μ m, the channel width of initialization transistor NC is 50 μ m, constituting the 1st switch SW 1～N transistor npn npn of the 4th switch SW 4 and the channel width of P transistor npn npn is 100 μ m, constituting negative circuit INV1 and the N transistor npn npn of negative circuit INV2 and the channel width of P transistor npn npn is 50 μ m, these whole N transistor npn npn channel lengths are 8 μ m, the channel length of the P transistor npn npn that these are whole is 6 μ m, and the mobility of whole N transistor npn npns is 80cm 2/ Vsec, the mobility of whole P transistor npn npns is 60cm 2/ Vsec, the threshold voltage (Vth) of whole N transistor npn npns be+1.0V, and the threshold voltage (Vth) of whole P transistor npn npns is-1.0V, and the capacitance of the 1st capacitor C1 is 1pF, and the capacitance of the 2nd capacitor C2 is 38fF.
Figure 12 is the sequential chart that puts on the signal of wiring RST, wiring SMP, common potential wiring 335, sweep trace 201-1, sweep trace 201-2.Also have, check accompanying drawing for convenience, make the scale of longitudinal axis transverse axis unfixing.Sweep trace 201-1, sweep trace 201-2 drive by scan line drive circuit 301, every 16.7 milliseconds of selected 31.2 microseconds.Sweep trace 201-2 is selected after 34.6 microseconds after having selected sweep trace 201-1, below with 34.6 microseconds serve as select at interval sweep trace 201-3,201-4 ....Common potential wiring 335, every 34.6 microseconds noble potential (=5V) with electronegative potential (=anti-phase between 0V), still every 16.7 milliseconds of phase deviation half period.Therefore, anti-phase, the anti-phase driving of so-called 1H shared (common) takes place in the polarity of carrying out putting on common potential wiring 335 when selecting sweep trace 201-n.The RST signal is selected 27.7 microseconds before 32.9 microseconds of selecting sweep trace 201-1.At this moment, the current potential of common potential wiring 335 must be electronegative potential (=0V), all sweep trace 201-1～201-480 can be not selected.The SMP signal be between lowstand in common potential wiring 335, selected 27.7 microseconds after 335 anti-phase constant time lag 3.5 microseconds of connecting up than common potential.The RST signal be conducting during the SMP signal also must be conducting.At this RST signal, SMP signal, sweep trace 201-n noble potential when selecting be+9V, electronegative potential is-4V during in non-selection.
Constitute if so, then wiring RST for high (=+ 9V) timing current potential VVCHG (=2.0V) charge in wiring SENSEn and node SIN.And current potential VVCHG, current potential VVSL, current potential VVSH charge respectively in wiring VDBTn, wiring VSLn, wiring VSH.And because reset transistor NR conducting, so node A and Node B short circuit, in the present embodiment, two contacts are charged as 2.5V.Also have, wiring RST for high (=9V) during the 5th N transistor npn npn N5 conducting and the 5th P transistor npn npn P5 end, so output wiring OUTn is 0V.
If that wiring RST becomes after 27.7 microseconds is low (=-4V), then reset transistor NR is by, node A and the disconnection of Node B electricity, and node A is current potential and the wiring RST 0.5V that descends simultaneously by the coupling of the 2nd capacitor C2, becomes 2.0V.Wiring RST after 27.7 microseconds, become low (=-4V) moment, wiring SENSEn be current potential VVCHG (=2.0V), wiring VSLn be current potential VVSL (=0.0V), wiring VSHn be current potential VVSH (=5.0V).Thereby, applying reverse biased 3.0V in the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit, the shading sensor groups on shading sensor groups to the 4 limits on the 1st limit applies reverse biased 2.0V.And, from output wiring OUTn output potential VVSL.At this moment, the thermocurrent that flows through in the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit becomes with the thermocurrent that flows through in the shading sensor groups on shading sensor groups to the 4 limits on the 1st limit and equates substantially, flow into and shine the photocurrent Iphoto that is directly proportional in the illumination of the outer light of the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit at wiring SENSEn, the current potential of wiring SENSEn is to be proportional to the speed rising of photocurrent Iphoto.Though also flow through electric current, equal approach a little to connect up current potentials of SENSEn at wiring VSHn, wiring VSLn, but becoming height (=9V) timing every 69.2 microseconds wirings SMP, the 2nd switch SW 2 and the 3rd switch SW 3 become conducting, thereby turn back to original current potential, do not change basically.
Also have, the speed that changes of current potential of wiring SENSEn is represented with expression of first degree with the relation of shining in the light quantity of the photosensitive sensor group on n limit, the coefficient of representing its slope is by wiring SENSEn, determine with the summation of the load capacity of the negative electrode of the shading sensor groups on the positive electrode of the photosensitive sensor group on the n limit that is connected in this wiring and n limit, but the coefficient of representing this slope in the present embodiment is in 4 limits, the 1st limit to the and indifference, that is, be adjusted to equal on each limit at the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit capacitance that obtains by " photocurrent Iphoto " ÷ " wiring SENSEn " during for fixing light quantity.
Like this, the wiring RST be low (4V) during, node A becomes floating state, thus by rising simultaneously with the capacitive coupling of the 1st capacitor C1 and node SIN coupling, current potential, when node A and node SIN become 2.5V the current potential of output wiring OUTn anti-phase for high (=5V).
The photosensitive sensor winding on photosensitive sensor group to the 4 limits on the 1st limit in the present embodiment is bordering on viewing area 310 configurations, and positive electrode 615-n, negative electrode 616-n, BT electrode 617-n and common potential wiring 335 intersect.And, have the electric capacity that is connected with the either party of sweep trace 201-n, data line 202-m, electric capacity line 203-n via the shading electrode, because of these electric capacity cause electromagnetic noise easily.Especially common potential wiring 335 is coupled by the electric capacity that can not ignore with wiring SENSEn, and the current potential of wiring SENSEn changes up and down owing to the polarity of common potential wiring 335.With an example with the wiring SENSEn sequential chart be shown in Figure 12.Like this, wiring SENSEn, when common electrode wiring 335 from low (=0V) → high (=carry out when anti-phase 5V) because capacitive coupling and current potential rising Δ V, when from high (=5V) → low (=carry out current potential decline Δ V when anti-phase 0V).But, because node SIN is the timing conducting of conducting at the SMP signal only with wiring SENSEn, so as shown in figure 12, in node SIN, when polarity is anti-phase, do not change in the present embodiment.Thereby, do not produce anti-phase delaying work of causing by common potential wiring 335.
Similarly connect up in the present embodiment VDBTn, wiring VSLn, wiring VSHn (n=1～4) also only the SMP signal be conducting timing respectively with wiring VCHG, wiring VSL, wiring VSH conducting, be to be in floating state in the timing that ends at the SMP signal.Constitute if so, the VDBTn that then connects up, wiring VSLn, wiring VSHn (n=1～4) also change Δ V because of the capacitive coupling current potential approximately when the polarity of common potential wiring 335 is anti-phase.Anti-phase thereby even the polarity of common potential wiring 335 takes place, the bias voltage of shading sensor groups that puts on shading sensor groups to the 4 limits on the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit and the 1st limit does not change yet.Thereby, photocurrent Iphoto that in the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit, flows through and thermocurrent, have nothing to do with the thermocurrent that in the shading sensor groups on shading sensor groups to the 4 limits on the 1st limit, flows through and to fix in the polarity of common potential wiring 335.
So because bigger the taking of Δ V so constitutes, still under the situation of the smaller not enough 1V of Δ V, also can remove the 1st switch SW the 1, the 2nd switch SW the 2, the 4th switch SW 4 at present embodiment.Figure 13 illustrates the circuit diagram under the situation like this as n testing circuit 360 '-n in the testing circuit 360 ' of the other configuration example of testing circuit.In these other embodiment, than n the testing circuit 360-n that is shown in Figure 11, remove the 1st switch SW 1～the 4th switch SW 4, wiring VDBTn and wiring VCHG, wiring VSLn and wiring VSL, wiring VSHn and wiring VSH, wiring SEBSEn and node SIN short circuit respectively.If take so to constitute, then node SIN presents amplitude (the sequential chart that the wiring SEBSEn as Figure 12 of becoming represents) corresponding to the polarity of common potential wiring 335.Therefore, if during whole, carry out testing like this, then when common potential connect up 335 anti-phase for height (=cause 5V) time and delay work.Therefore, remove the 3rd N transistor npn npn N3～5th a N transistor npn npn N5 and the 3rd P transistor npn npn P3～5th a P transistor npn npn P5, the drain electrode that replaces the 2nd N transistor npn npn N2 and the 2nd P transistor npn npn P2 is connected in one of input terminal of the 1st NAND circuit NAND1, the opposing party of the input terminal of the 1st NAND circuit NAND1 is connected in the SMP signal, the lead-out terminal of the 1st NAND circuit NAND1 is connected in a side of the input terminal of the 2nd NAND circuit NAND2, the opposing party of the input terminal of the 2nd NAND circuit NAND2 is connected in the lead-out terminal of the 3rd NAND circuit NAND3, one side of the input terminal of the 3rd NAND circuit NAND3 is connected in the lead-out terminal of the 2nd NAND circuit NAND2, the opposing party of the input terminal of the 3rd NAND circuit NAND3 is connected in the lead-out terminal of negative circuit INV3, the input terminal of negative circuit INV3 is connected in wiring RST.The power supply of the 1st NAND circuit NAND1～the 3rd NAND circuit NAND3 and negative circuit INV3 is connected in wiring VSH and wiring VSL.So the formation of other circuit, the identical additional phase of work with Figure 11 with symbol and omission is described.Constitute if so, then only when the current potential of node SIN be more than the 2.5V and SMP signal when being high, the output of the 1st NAND circuit NAND1 becomes low.The 2nd NAND circuit NAND2 and the 3rd NAND circuit NAND3 become rest-set flip-flop, and the output of the 1st NAND circuit NAND1 becomes the asserts signal of negative polarity, and the output of negative circuit INV3 becomes the reset signal of negative polarity.That is, when the RESET signal become height (=output latch to output wiring OUTn 9V) time is low, the current potential of node SIN be more than the 2.5V and the SMP signal become high initial timing to the output latch of output wiring OUTn for high.Thereby, common potential wiring 335 for high (=5V) during testing result be invalid, do not delay work so can not cause.
Figure 14 is the circuit diagram of majority decision circuit 370.Press the permutation and combination connection for any 2 among the input terminal of the 4th NAND circuit NAND11, the 5th NAND circuit NAND12, the 6th NAND circuit NAND13, the 7th NAND circuit NAND14, the 8th NAND circuit NAND15, the 9th NAND circuit NAND16 will be exported wiring OUT1～OUT4 respectively.The 4th NAND circuit NAND11, the 5th NAND circuit NAND12, the lead-out terminal of the 6th NAND circuit NAND13 is connected in the input terminal of the 10th NAND circuit NAND21, the 7th NAND circuit NAND14, the 8th NAND circuit NAND15, the lead-out terminal of the 9th NAND circuit NAND16 is connected in the input terminal of the 11st NAND circuit NAND22, the 10th NAND circuit NAND21, the lead-out terminal of the 11st NAND circuit NAND22 is connected in the input terminal of the 1st NOR circuit 30, the lead-out terminal of the 1st NOR circuit 30 is connected in the input terminal of negative circuit INV4, and the lead-out terminal of negative circuit INV4 connects to output wiring OUT.The power supply of the 4th NAND circuit NAND11, the 5th NAND circuit NAND12, the 6th NAND circuit NAND13, the 7th NAND circuit NAND14, the 8th NAND circuit NAND15, the 9th NAND circuit NAND16, the 10th NAND circuit NAND21, the 11st NAND circuit NAND22, the 1st NOR circuit 30 is connected in wiring VSH and wiring VSL.This circuit be when among output wiring OUT1～OUT4, any wiring more than 2 become height (=5V) time to output wiring OUT output high (=5V), and when output wiring OUT1～OUT4 all be low (=0V) or only any 1 for high (=export low (=0V) circuit to the output OUT that connects up 5V) time.Constitute if so, then from wiring RST become low (=-4V) be height (the rayed amount on the limit that=5V) time is inversely proportional among the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit, the irradiation flow control of light 2 is big to output wiring OUT is anti-phase.In the present embodiment, carry so majority decision circuit 370, the result who remove among the luminance detection result on each limit, illumination is the highest prevents thus when there is some light (spot light) time than external environment light intensity to delay work in this limit irradiation.And, because the minimum result of illumination, and illumination the 2nd low result also be removed, so even 2 limits also can obtain correct result among for example the shade of finger etc. came across 4 limits.
Figure 15 be in the present embodiment based on from the detection illumination of the exterior light of the output of output wiring OUT and the setting example of back light source brightness.Externally illumination extremely low during be set at: back light source brightness is changed lentamente, make gradually to change and when accelerating externally illumination 500 luxs brightness is changed to become maximum, and then the S word curve that changes lentamente, and more than 1500 luxs, be set at and keep high-high brightness.This curve both can freely be set corresponding to the characteristic of electronic equipment, also can make it to change lentamente with the mean value during certain for the flicker that prevents brightness, also can make the relation of brightness and illumination have hysteresis quality.And, in the time of also can be corresponding to standby during with operation etc. the mode of operation of electronic equipment etc. curve is changed.
Like this, although make sensitization peristome and viewing area very approaching in the present embodiment, even but adopt the precision height that shared anti-phase driving does not delay work yet, light detects, so can always display device be set at best brightness, visual raising also helps to consume the electric power reduction.And, even cover 1 limit～2 limits or some illumination in 1 place, also external surround lighting is correctly measured with finger, back light source brightness always is maintained the best.
The 2nd embodiment
Figure 16 be a sensor in conduct the 1st marginal ray sensor groups among the 2nd embodiment n the 1st marginal ray sensor 351-n overlook enlarged drawing, be figure corresponding to Fig. 8 of the 1st embodiment.Legend and Fig. 5 are same.Below, be that the center describes to Figure 16 with difference with Fig. 8.
Different with Fig. 8 in Figure 16, sweep trace 201-n overlooks the wiring formation that is formed by aluminium neodymium alloy film (AlNd) by contact hole in the overlapping areas with shading electrode 611-n, the wiring 618-n of common potential branch that formation is made of molybdenum film (Mo) between sweep trace 201-n and shading electrode 611-n.Common potential branch wiring 618-n and common potential connect up and 335 are connected by contact hole, are supplied to common potential (COM).In other respects, it is different that Figure 16 and Fig. 8 there is no, thus additional phase with symbol and omission is described.
Figure 17 be a sensor in conduct the 2nd marginal ray sensor groups of the 2nd embodiment n the 2nd marginal ray sensor 352-n overlook enlarged drawing, be figure corresponding to Figure 10 of the 1st embodiment.Legend and Fig. 5 are same.Below, be that the center describes to Figure 17 with difference with Figure 10.
Different with Figure 10 in Figure 17, overlook the wiring 628-n of common potential branch that forms between overlapping areas by molybdenum film (Mo) formation at data line 202-n and shading electrode 621-n.Common potential branch wiring 628-n and common potential connect up and 335 are connected by contact hole, are supplied to common potential (COM).In other respects, it is different that Figure 17 and Figure 10 there is no, thus additional phase with symbol and omission is described.
Active-matrix substrate 101 in the present embodiment, the formation of liquid crystal indicator 910 are identical with the 1st embodiment, and the setting of the formation of electronic equipment, outer illuminance and brightness etc. are also identical with the 1st embodiment, so explanation is omitted.
Compare with the 1st embodiment in the present embodiment, overlook in the overlapping part, reach and overlook in the overlapping part at sweep trace 201-n and shading electrode 611-n at data line 202-n and shading electrode 621-n, disposing common potential branch wiring 618-n, the 628-n that is connected in common potential wiring 335 between sweep trace 201-n and the shading electrode 611-n and between data line 202-n and the shading electrode 621-n respectively, so do not have direct cross capacitance.Therefore, even when variation has taken place in the current potential of sweep trace 201-n, data line 202-n, promptly, be scanned timing that line drive circuit 301 selects at sweep trace 201-n, undertaken writing fashionable at data line 202-n by data line drive circuit 302 or 303 pairs of different current potentials of pre-charge circuit (image), the current potential of shading electrode 611-n and shading electrode 621-n also is difficult to change.When the current potential of shading electrode 611-n and shading electrode 621-n changed, the current potential of wiring SENSE1, wiring SENSE2 was also because of the capacitive coupling change, so present embodiment than the 1st embodiment, can carry out the higher illumination photometry of precision.And, be connected in common potential wiring 335 by the wiring that is used to shield that will be sandwiched in therebetween, the power supply of shielding usefulness needn't newly be set.Common potential wiring 335 is in order to keep picture element originally with the Low ESR configuration, so extremely effective when using as screen potential.Because of so there is the noise that becomes the shading electrode in common potential wiring 335 by anti-phase driving, but, carry out described same driving in the present embodiment, so thereby can not cause that potential change causes precision to reduce because of capacitive coupling with the common potential wiring with the 1st embodiment.On the other hand, in the present embodiment, because the electric capacity of common potential wiring 335 increases, so the problem of existence consumption electric power increase etc.The formation of selecting the 1st embodiment on earth still is the formation of the 2nd embodiment, can be on the basis of the relative merits more than having considered as one feels fit selects according to use of electronic equipment etc.
Also have, though only taked measure in the present embodiment, also can take same measure to n the 3rd marginal ray sensor 353-n, n the 4th marginal ray sensor 354-n as required about the shading electrode that is overlapped in n the 1st marginal ray sensor 351-n, n the 2nd marginal ray sensor 352-n.
The 3rd embodiment
Figure 18 is the block diagram of the active-matrix substrate 102 among the 3rd embodiment, below, the difference with the active-matrix substrate 101 of the Fig. 2 that is shown in the 1st embodiment is described, to the formation additional phase identical with Fig. 2 of the 1st embodiment with symbol and omission is described.In the present embodiment, replace the 1st marginal ray sensor 351-1～351-480 configuration among the 1st embodiment as the 1st marginal ray sensor 351 '-1～351 '-480 of optical sensor, replace the 2nd marginal ray sensor 352 '-1～352 '-1920 of the 2nd marginal ray sensor 352-1～352-1920 configuration as optical sensor, replace the 3rd marginal ray sensor 353 '-1～353 '-480 of the 3rd marginal ray sensor 353-1～353-480 configuration as optical sensor, replace the 4th marginal ray sensor 354 '-1～354 '-1920 of the 4th marginal ray sensor 354-1～354-1920 configuration, respectively as optical sensor 351 ' as optical sensor, 352 ', 353 ', 354 '.And, replace the 1st testing circuit 360-1～the 4th testing circuit 360-4 and configuration detection circuit 361.
Among the 1st marginal ray sensor 351 '-1～351 '-480, (the 1st limit photosensitive sensor group) overlapping with the 1st the 1st limit sensitization peristome 991-1～3rd the 1st limit sensitization peristome 991-3 is connected with wiring SENSE (SENSEP), is not connected with the SENSE (SENSED) that connects up with any overlapping (the 1st limit shading sensor groups).Similarly among the 2nd marginal ray sensor 352 '-1～352 '-1920, (the 2nd limit photosensitive sensor group) overlapping with the 1st the 2nd limit sensitization peristome 992-1～4th the 2nd limit sensitization peristome 992-4 is connected with wiring SENSEP, is not connected with the SENSED that connects up with any overlapping (the 2nd limit shading sensor groups).Among the 3rd marginal ray sensor 353 '-1～353 '-480, (the 3rd limit photosensitive sensor group) overlapping with the 1st the 3rd limit sensitization peristome 993-1～3rd the 3rd limit sensitization peristome 993-3 is connected with wiring SENSEP, is not connected with the SENSED that connects up with any overlapping (the 3rd limit shading sensor groups).Among the 4th marginal ray sensor 354 '-1～354 '-1920, (the 4th limit photosensitive sensor group) overlapping with the 1st the 4th limit sensitization peristome 994-1～4th the 4th limit sensitization peristome 994-4 is connected with wiring SENSEP, is not connected with the SENSED that connects up with any overlapping (the 4th limit shading sensor groups).Wiring SENSED and wiring SENSEP are connected in testing circuit 361, and the output wiring OUT of testing circuit 361 connects to the outside by signal input terminal 320.
Figure 19 be a sensor in conduct the 1st limit photosensitive sensor group of the 3rd embodiment n the 1st marginal ray sensor 351 '-n overlook enlarged drawing, be figure corresponding to Fig. 8 of the 1st embodiment.Legend is identical with Fig. 5.Below, be that the center describes to Figure 19 with difference with Fig. 8.
The n of Figure 19 the 1st marginal ray sensor 351 '-n for by anode region 610P ' (610P '-n), intrinsic region 610I ' (610I '-n), cathode zone 610N ' (610N '-the lateral type PIN diode that n) constituted, because their formation is identical with illustrated anode region 610P-n, intrinsic region 610I-n, the cathode zone 610N-n of Fig. 8 of the 1st embodiment respectively, explanation is omitted.Anode region 610P '-n is connected in positive electrode 615 ' by contact hole, and (615 '-n), positive electrode 615 '-n is connected in wiring SENSEP.Cathode zone 610N '-n, shading electrode 611 ' (611 '-n), be connected in common potential wiring 335 by contact hole respectively as transparent the guarded electrode 612 '-n of transparent guarded electrode 612 ', be supplied to common potential (COM).In other respects, it is different that Figure 19 and Fig. 8 there is no, thus additional phase with symbol and omission is described.
About as individual the 1st marginal ray the sensor 351 '-n ' of the n ' of a sensor in the 1st limit shading sensor groups, except not overlapping, positive electrode 615 ' (615 '-n ') with any of the 1st the 1st limit sensitization peristome 991-1～3rd the 1st a limit sensitization peristome 991-3 be connected in the wiring SENSED identical with the explanation of Figure 19, so omit explanation.
Figure 20 be a sensor in conduct the 2nd limit photosensitive sensor group of the 3rd embodiment m the 2nd marginal ray sensor 352 '-m overlook enlarged drawing, be figure corresponding to Figure 10 of the 1st embodiment.Legend is identical with Fig. 5.Below, be that the center describes to Figure 20 with difference with Figure 10.
The m of Figure 20 the 2nd marginal ray sensor 352 '-m for by anode region 620P ' (620P '-m), intrinsic region 620I ' (620I '-m), cathode zone 620N ' (620N '-the lateral type PIN diode that m) constituted, because their formation is identical with illustrated anode region 620P-m, intrinsic region 620I-m, the cathode zone 620N-m of Figure 10 of the 1st embodiment respectively, explanation is omitted.Anode region 620P '-m is connected in positive electrode 625 ' by contact hole, and (625 '-m), positive electrode 625 '-m is connected in wiring SENSEP.Cathode zone 620N '-m, transparent guarded electrode 622 ' (612 '-m), (621 '-m) is connected in common potential wiring 335 by contact hole respectively to shading electrode 621 ', is supplied to common potential (COM).In other respects Figure 20 and Figure 10 there is no different, so additional phase with symbol and omission is described.
About as individual the 2nd marginal ray the sensor 352 '-n ' of the n ' of a sensor in the 2nd limit shading sensor groups, except not overlapping, positive electrode 625 ' (625 '-n ') with any of the 1st the 2nd limit sensitization peristome 992-1～4th the 2nd a limit sensitization peristome 992-4 be connected in the wiring SENSED identical with the explanation of Figure 19, so omit explanation.
N the 3rd marginal ray sensor 353 '-n compares with n the 1st marginal ray sensor 351 '-n, between electric capacity line 203-n-1 and electric capacity line 203-n, is shown in the layout Rotate 180 degree of Figure 20, and be in addition all identical, so explanation is omitted.N the 4th marginal ray sensor 354 '-n compares with n the 2nd marginal ray sensor 352 '-n, and other are identical except the layout Rotate 180 degree that is shown in Figure 20, so explanation is omitted.
Figure 21 is the circuit diagram of testing circuit 361.Wiring SMP1, wiring SMP2, wiring RST, wiring VCHG, wiring VSL, wiring VSH are connected with signal input terminal 320, supply with suitable current potential, signal by external power source circuit 784.At this, the wiring VCHG be supplied to current potential VVCHG (=-2.0V), the wiring VSL be supplied to current potential VVSL (=0.0V), the wiring VSH be supplied to current potential VVSH (=5.0V).Also having, is the GND of liquid crystal indicator 910 at the current potential VVSL of this wiring VSL.Output wiring OUTn is connected with signal input terminal 320, exports to external circuit.
Wiring SENSED is connected in an end of the 5th switch SW 5, and wiring SENSEP is connected in an end of the 6th switch SW 6.The other end of the 5th switch SW 5 and the 6th switch SW 6 all is connected in node SIN '.Constitute by CMOS transmission grid in this 5th switch SW 5～the 6th switch SW 6.The gate electrode that constitutes the n channel transistor of the 5th switch SW 5 is connected in wiring SMP1, and the gate electrode of p channel transistor is connected in the lead-out terminal of negative circuit INV5.The input terminal of negative circuit INV5 is connected in wiring SMP1.The gate electrode that constitutes the n channel transistor of the 6th switch SW 6 is connected in wiring SMP2, and the gate electrode of p channel transistor is connected in the lead-out terminal of negative circuit INV6.The input terminal of negative circuit INV6 is connected in wiring SMP2.
And node SIN ' is connected in the end of the 3rd capacitor C3 and the drain electrode of initialization transistor NC ', and the other end of the 3rd capacitor C3 is connected in node A '.The source electrode of initialization transistor NC ' is connected in wiring VCHG, be supplied to current potential VVCH (=-2.0V) power supply.The gate electrode of initialization transistor NC ' is connected in wiring RST.Node A ' also is connected in the gate electrode of the gate electrode of the 6th N transistor npn npn N ' 1, the 6th P transistor npn npn P ' 1 and the drain electrode of reset transistor NR ', and is connected in the end of the 4th capacitor C4.The other end of the 4th capacitor C4 is connected in wiring RST.
The drain electrode of the drain electrode of the 6th N transistor npn npn N ' 1, the 6th P transistor npn npn P ' 1 and the source electrode of reset transistor NR ' are connected in Node B ', Node B ' also is connected in the gate electrode of the 7th N transistor npn npn N ' 2 and the gate electrode of the 7th P transistor npn npn P ' 2.The drain electrode of the drain electrode of the 7th N transistor npn npn N ' 2 and the 7th P transistor npn npn P ' 2 is connected in node C ', and node C ' also is connected in the gate electrode of the 8th N transistor npn npn N ' 3 and the gate electrode of the 8th P transistor npn npn P ' 3.The drain electrode of the drain electrode of the 8th N transistor npn npn N ' 3 and the 8th P transistor npn npn P ' 3 is connected in node D ', and node D ' also is connected in the gate electrode of the 9th N transistor npn npn N ' 4 and the gate electrode of the 9th P transistor npn npn P ' 4.The drain electrode of the drain electrode of the 9th N transistor npn npn N ' 4 and the 9th P transistor npn npn P ' 4 is connected in output wiring OUT, and output wiring OUT also is connected in the drain electrode of the 10th N transistor npn npn N ' 5.The gate electrode of the gate electrode of the 10th N transistor npn npn N ' 5 and the 10th P transistor npn npn P ' 5 is connected in wiring RST, and the drain electrode of the 10th P transistor npn npn P ' 5 is connected in the source electrode of the 9th P transistor npn npn P ' 4.The source electrode of the 1～10th N transistor npn npn N ' 5 of the 6th N transistor npn npn N ' be connected in the wiring VSL, be supplied to current potential VVSL (=0V).And the source electrode of the 1～8th P transistor npn npn P ' 3 of the 6th P transistor npn npn P ' and the 10th P transistor npn npn P ' 5 be connected in the wiring VSH, be supplied to current potential VVSH (=+ 5V).And, to negative circuit INV5 and negative circuit INV6 supply+9V power supply with-4V.
At this in the present embodiment, the channel width of the 6th N transistor npn npn N ' 1 is 10 μ m, the channel width of the 7th N transistor npn npn N ' 2 is 35 μ m, the channel width of the 8th N transistor npn npn N ' 3 is 100 μ m, the channel width of the 9th N transistor npn npn N ' 4 is 150 μ m, the channel width of the 10th N transistor npn npn N ' 5 is 150 μ m, the channel width of the 6th P transistor npn npn P ' 1 is 10 μ m, the channel width of the 7th P transistor npn npn P ' 2 is 35 μ m, the channel width of the 8th P transistor npn npn P ' 3 is 100 μ m, the channel width of the 9th P transistor npn npn P ' 4 is 300 μ m, the channel width of the 10th P transistor npn npn P ' 5 is 300 μ m, the channel width of reset transistor NR ' is 10 μ m, the channel width of initialization transistor NC ' is 150 μ m, constituting the 5th switch SW 5～N transistor npn npn of the 6th switch SW 6 and the channel width of P transistor npn npn is 100 μ m, constituting negative circuit INV5 and the N transistor npn npn of negative circuit INV6 and the channel width of P transistor npn npn is 50 μ m, the channel length of the N transistor npn npn that these are whole is 8 μ m, the channel length of the P transistor npn npn that these are whole is 6 μ m, and the mobility of whole N transistor npn npns is 80cm 2/ Vsec, the mobility of whole P transistor npn npns is 60cm 2/ Vsec, the threshold voltage (Vth) of whole N transistor npn npns be+1.0V, and the threshold voltage (Vth) of whole P transistor npn npns is-1.0V, and the capacitance of the 3rd capacitor C3 is 1pF, and the capacitance of the 4th capacitor C4 is 38fF.
Next, Figure 22 is the sequential chart of present embodiment.For the ease of watching accompanying drawing, the scale of longitudinal axis transverse axis is unfixing.About common potential wiring 335, sweep trace 201-1, sweep trace 201-2, wiring RST, with in the 1st embodiment by illustrated identical of Figure 12, so explanation is omitted.Wiring SMP1 is when common potential wiring 335 is that low (=selected 13.8 microseconds 0V) time, the cycle is 69.2 microseconds.Wiring SMP2 similarly when common potential wiring 335 when low, continue in connecting up SMP1 and selected 13.8 microseconds.Wiring SMP1, wiring SMP2 are that current potential is Gao Shiwei+9V but not is the signal of-4V when current potential is low when selecting when selecting.
Forming circuit if so, then common potential wiring 335 be low (=0V) during, selective interconnection SMP1 at first, wiring SENSED is connected with node SIN ', while node A ' and Node B ' pass through reset transistor NR ' short circuit, be charged as 2.5V.Therebetween to the output of output wiring OUT must for low (=0V).Then after 13.8 microseconds, it is selected that wiring SMP1 becomes the non-selection SMP2 that connects up simultaneously, and wiring SENSEP is connected node A ' and Node B with node SIN ' ' the electric separation, the current potential of node A ' is reduced to 2.0V by the 4th capacitor C4 simultaneously.After this, the current potential of node SIN ' changes towards wiring SENSEP from the current potential of wiring SENSED by the 5th switch SW 5, and also changes because of the current potential of capacitive coupling node A '.That is, before wiring SMP2 will become non-selection, the current potential of node A ' became " 2.0V "+" current potential of wiring SENSEP "-" current potential of wiring SENSED ", and then testing circuit 361 is high to output wiring OUT output if it surpasses 2.5V.The current potential of wiring SENSED changes with the slope that is directly proportional with the thermocurrent that flows through in the shading sensor groups on shading sensor groups to the 4 limits on the 1st limit, the current potential of wiring SENSEP with the photosensitive sensor group on photosensitive sensor group to the 4 limits on the 1st limit in the slope that " thermocurrent "+" photocurrent Iphoto " is directly proportional that flows through change, so the potential difference (PD) of wiring SENSEP and wiring SENSED changes with the slope that is proportional to photocurrent Iphoto.Thus, with the 1st embodiment in the same manner, from wiring RST become non-selection begin till output wiring OUT becomes height at first time with outside the inverse of illuminance be directly proportional.
Next common potential connect up 335 anti-phase for high (=5V) before, wiring SMP1, wiring SMP2 become non-selection together, common potential wiring 335 be height (=5V) during not selected.Shown in the sequential chart of Figure 12, if common potential connect up 335 anti-phase for high (=5V), the SENSED that then connects up, wiring SENSEP are because of the capacitive coupling current potential 5V that rises approximately.But, equally as shown in figure 12, because in the 5th switch SW 5 and 6 shutoffs of the 6th switch SW during this period, so the current potential of node SIN ' is unaffected.Thereby, can not be subjected to the anti-phase influence ground of common potential wiring 335 to carry out high-precision test equally with the 1st embodiment.
The formation of the testing circuit 361 of present embodiment is than the formation of the testing circuit 360 of the 1st embodiment, short during existing node A in the circuit to become to float, the advantage of noise resistance relatively.On the other hand, be subject to the influence of the switching noise of the 5th switch SW 5 and the 6th switch SW 6, the situation of deterioration in accuracy may occur.Can consider as one sees fit that as for taking which kind of formation on earth both advantages select.No matter in which kind of constitutes importantly the common potential (COM) of the timing that finishes the work that resets (turning back to low) if then be meant the current potential of wiring RST with embodiment, with carry out at testing circuit 361 work (if being meant then that with embodiment connect up SMP, SMP1, SMP2 become height) during common potential (COM) consistent, so long as become the circuit of formation like this, then testing circuit 360 can constitute with the known all circuit except that illustrational in this manual circuit.
The liquid crystal indicator 910 of liquid crystal indicator in the present embodiment and the 1st embodiment shown in Figure 1 except active-matrix substrate 101 is changed into there is no the active-matrix substrate 102 different, so explanation is omitted.And the setting of the formation of electronic equipment, outer illuminance and brightness etc. are also identical with the 1st embodiment, so explanation is omitted.
The power supply that is connected in optical sensor in the present embodiment uses the common potential (COM) of common potential wiring 335.Because shading electrode, transparency electrode also are connected in common potential wiring 335 in the present embodiment, so optical sensor is connected in the common potential (COM) of common potential wiring 335 basically fully, wiring SENSEP and wiring SENSED are to connect up 335 identical cycles, phase place and with essentially identical electrical oscillation with common potential.Therefore, the bias voltage that puts on diode owing to the polarity of common potential wiring 335 does not change basically.And than the 1st embodiment, the wiring number reduces significantly, so can dwindle the physical dimension of liquid crystal indicator.On the other hand, because the power supply potential of testing circuit 361 can be the DC current potential, thus can be shared with the power supply potential of scan line drive circuit 301, data line drive circuit 302, can not make the futile increase of the power supply number of supplying with.Also have, because the potential change of common potential wiring 335, noise increases and may influence under the situation of picture element etc. and certainly adopt formation from other power supply potential to optical sensor that supply with.
Wiring SENSEP with all limits is connected with wiring SENSED in the present embodiment, be connected with a testing circuit 361 then, but also can be as the 1st embodiment on each limit wiring SENSEP and wiring SENSED be separated and, this output be judged by the majority decision circuit 370 shown in the 1st embodiment at each limit configuration detection circuit 361-1～361-4.Otherwise, also can make n the testing circuit 360-n of the 1st embodiment become a testing circuit, with the short-circuit on each limit.If as present embodiment each limit short circuit being made testing circuit is one, then circuit scale can be cut down in a large number, can dwindle the size of liquid crystal indicator 910.On the other hand, because the outer illuminance that can detect is the mean value of the outer illuminance on each limit, be detected as outer illuminance darker than reality so under the situation of blocking outer light because of finger etc. in a large number, understand.As for which kind of selects then can be by size of the constituting of electronic equipment, method of operating, liquid crystal indicator etc. and determine on earth.
Though 4 limits of 310 have disposed optical sensor in the viewing area in each embodiment of this instructions, under the situation of the restriction that has profile etc., can certainly be 3 below the limit.
The present invention is not the mode that is defined in embodiment, also can not be used in the liquid crystal indicator of TN pattern and be used in vertical alignment mode (VA pattern), utilized transverse electric field the IPS pattern, utilized in the liquid crystal indicator of FFS pattern etc. of fringe field.And being not only the total transmissivity type also can be fully-reflected type, reflection and transmission dual-purpose type.And, except that liquid crystal indicator, can also be used for OLED display, field emission display, also can be used for liquid crystal indicator semiconductor device in addition.
And, not only can be used for control shown in the present embodiment and display brightness outer photophase, thereby and can be used for that brightness, colourity to display device is measured and this is fed back can not produce inhomogeneous, through the time display device that changes.

Claims (14)

1. display device possesses the active matrix circuit that shows usefulness on substrate, be connected in the multiple bus of aforementioned active matrix circuit, transmission drive signal and to the driving circuit of aforementioned multiple bus output drive signal; It is characterized in that:
On aforesaid base plate, possesses optical sensor;
The aforementioned lights sensor configuration is in a plurality of subregions of being divided by aforementioned multiple bus;
Aforementioned a plurality of subregion is disposed between aforementioned active matrix circuit and the aforementioned driving circuit.
2. according to the described display device of claim 1, it is characterized in that possessing:
Be connected in a plurality of pixel electrodes of aforementioned active matrix circuit,
At the 1st current potential and between than the 2nd low current potential of aforementioned the 1st current potential by the common electrode of anti-phase driving,
The liquid crystal cell that state of orientation changes by putting on the electric field between aforementioned a plurality of pixel electrode and the aforementioned common electrode,
Be connected in the aforementioned lights sensor sensor wiring and
The testing circuit that is connected in sensor as aforementioned wiring, the current potential or the electric current of sensor as aforementioned wiring detected;
Aforementioned testing circuit is either party timing in aforementioned the 1st current potential or the 2nd current potential at aforementioned common electrode, and the current potential or the electric current of sensor as aforementioned wiring detected.
3. according to the described display device of claim 2, it is characterized in that:
Aforementioned testing circuit makes the current potential of sensor as aforementioned wiring turn back to the work that resets of original state repeatedly;
Aforementionedly reset that to be operated in aforementioned common electrode be that the timing of any the opposing party in aforementioned the 1st current potential or the 2nd current potential is carried out.
4. according to claim 2 or 3 described display device, it is characterized in that:
Sensor as aforementioned wiring, with aforementioned common electrode at same timing potential change.
5. according to claim 3 or 4 described display device, it is characterized in that:
Sensor as aforementioned wiring and aforementioned common electrode short circuit.
6. according to any one the described display device in the claim 3～5, it is characterized in that:
Sensor as aforementioned wiring, aforementioned common electrode be in aforementioned the 1st current potential or the 2nd current potential any the opposing party during be connected in the power-supply wiring of supplying with current potential by the outside, in aforementioned the 1st current potential or the 2nd current potential either party during become floating state.
7. according to any one the described display device in the claim 1～6, it is characterized in that:
Have and be formed at the 1st electrode of overlooking overlapping areas with the aforementioned lights sensor;
Overlook overlapping areas in aforementioned the 1st electrode and aforementioned bus and dispose the 2nd electrode.
8. according to the described display device of claim 7, it is characterized in that:
Aforementioned the 2nd electrode is connected with common electrode.
9. according to the described display device of claim 8, it is characterized in that:
Aforementioned the 1st electrode is a plurality of shading electrodes that are used for backlight is carried out shading;
In aforementioned a plurality of shading gaps between electrodes, dispose aforementioned bus or aforementioned the 2nd electrode.
10. according to any one the described display device in the claim 1～9, it is characterized in that:
Aforementioned a plurality of subregion is along the limit configuration of the peripheral part of aforementioned active matrix circuit.
11. any one the described display device according in the claim 2～9 is characterized in that:
Aforementioned testing circuit is made of a plurality of testing circuits;
This display device possesses the majority decision circuit that is connected with aforementioned a plurality of testing circuits;
Aforementioned majority decision circuit when variation has taken place the output result more than 2 among from a plurality of output results of aforementioned a plurality of testing circuits, changes output.
12., it is characterized in that according to the described display device of claim 10:
Aforementioned a plurality of testing circuit possesses the 1st testing circuit and the 2nd testing circuit;
The subregion of the subregion of aforementioned the 1st testing circuit and aforementioned the 2nd testing circuit is along the different limit configuration of the peripheral part of aforementioned active matrix circuit.
13. any one the described display device according in the claim 1～12 is characterized in that:
The aforementioned lights sensor is PIN junction diode or the PN junction diode that has adopted membrane polysilicon, and aforementioned driving circuit is made of the transistor that has adopted membrane polysilicon.
14. an electronic equipment is characterized in that:
Adopt any one the described display device in the claim 1～13.
CN2008100985084A 2007-05-08 2008-05-08 Display device and electronic apparatus including display device Expired - Fee Related CN101303497B (en)

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TW200914919A (en) 2009-04-01
TWI402560B (en) 2013-07-21

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