200910578 ryouu /1 z^o/9twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於-種記憶體結構及其降列，且特別是 有關於一種非揮發記憶體結構及其陣列。 【先前技術】 非揮發性§己憶體中的可電抹除可程式唯讀記憶體 (electrically erasable programmable read only mem〇ry 5 Γ EEPROM)具有可進行多次資料之存入、讀取、抹除等動 作，且存入之資料在斷電後也不會消失之優點，所以已成 為個人電腦和電子設備所廣泛採用的—種記憶體元件。 典型的可電抹除且可程式唯讀記憶體是以摻雜的多晶 矽衣作夺置閘極(floating gate)與控制間極(c她〇1购 記憶體進行程式化(pn)gfam)時，注人浮 ^ 勻分布於整個多晶石夕浮置閘極層之中。 ㈣·^均 产體=二!!習知的還有—種可電抹除且可程式唯讀記 ，體疋抓用g何陷人層取代多晶料置閘極，此電荷陷入 例如技切。這種氮切電荷陷人層上下通常 石夕’而形成一種包含氧化石夕/氮化矽/氧化矽 )複。，|電層在内的堆疊式(stacked)開極結構。 以隔憶體之通道區四周的基底上，具有用 於==鄰兩條字元線的氧化石夕隔離圖案，其位 ϋ 條字元線之間的基底上1而，上 =知的^憶體在電性的表現上具有讀取電流低、互導 con uctance’GM)較差、程式化速度慢及資料保存時 200910578 rvouu/i /9twf.doc/p 間短等缺點。 此外’位於摻雜區上方的氧化石夕隔離圖案在製造上需 要使___ft_offmethod)等複雜的製造方法，因此會 降低產品的生產效率及良率。 【發明内容】 有鑑於此’本發明的目的就是在提供一種非揮發記情 體結構，可有效地降低製程的複雜度。 C') 本發明的另一目的是提供一種非揮發記憶體陣列，具 有較佳的電性表現。 、 本發明提出-種非揮發記憶體結構，包括基底、多個 堆疊圖案及多個應力圖案。堆叠圖案配置於基底上，各個 堆疊圖案由下而上包括電荷儲存結構及閘極，其中電荷儲 存結構至少包括電荷儲存層。應力圖案分別配置於相鄰兩 個堆疊圖案之間的基底上。 依照本發明的-實施例所述’在上述之非揮發記憶體 結構中’更包括多個摻雜區，其分別配置於各個堆疊 兩側的基底中。 ’' 依照本發明的-實施例所述，在上述之非揮發記憶體 結構中，當摻雜區為N型摻雜時，應力圖案的材料包括拉 伸應力（tensile stress)材料。 依照本發明的一實施例所述，在上述之非揮發記憶體 結構中，當摻雜區為P型摻雜時’應力圖案的材料包括麗 縮應力（compressive stress)材料。 依照本發明的一實施例所述，在上述之非揮發記憶體 200910578 ryuw/1 zho / ^twfdoc/p 結構中，電荷儲存層的材料包括摻 依照本發明的—實施例所述，化石夕。 結構中，應力圖案的材料包括氮切f述之非揮發記憶體 ㈣t照ί發明的—實施例所述，在上述之非揮發辦體 :構中，應力圖案的寬度等於相鄰兩個堆疊圖 本發明提種轉發記,胃料列， 隔離圖案、多個摻籠、多條字元線 ^ ^ Ρ·圖案彼此平行配置於基底 圖案。 隔離圖案刪為-應卿。摻===二 ί=;Γ字;線彼此平行配置於隔離圖案= 耆第一方向延伸’而弟一方向與第 == 線下方的相鄰兩個隔離圖案之二= 上的t目鄰兩個堆疊圖案之間具有開口：各個 存結構至少包括一電荷儲存層。 /、甲电何儲 陳二照明的一實施例所述’在上述之非揮發記憶體 陣列中，電荷儲存層的材料包括摻雜多晶石夕或氮化石夕。體 依照本發明的一實施例所述，在 陣列中’應力材料包括氮化矽。 剛4體 依照本發明的-實施例所述，在 =中’當摻雜區為Ν型摻雜時，應力材料二3 材料。 〜 依照本發明的-實施例所述，在上述之非揮發記憶體 200910578 r /1 z-^to / 9twf.d〇c/p 陣列中，當摻雜區為p型換雜時，應力材料包括_應为 材料。 〜 陆二照ίΓ月的—實施例所述，在上述之非揮發記憶體 陣列中，更包括介電層，其配置於基底上並填滿開口。 明的〜實施例所述’在上述之非揮發記憶體 車1中，W電層的材料包括應力材料。 〇200910578 ryouu /1 z^o/9twf.doc/p IX. Description of the invention: [Technical field of the invention] The present invention relates to a memory structure and its de-listing, and in particular to a non-volatile memory Structure and its array. [Prior Art] The electrically erasable programmable read only mem〇ry 5 Γ EEPROM has the ability to store, read, and erase multiple data. In addition to the actions, and the stored data will not disappear after power off, it has become a kind of memory component widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory is a doped polysilicon coat for the floating gate and the control electrode (c her memory for stylized (pn) gfam) The injection float is evenly distributed throughout the polycrystalline slab floating gate layer. (4)·^All products = two!! There are also known kinds of electric erasable and programmable reading, body grabbing g, the human layer replaces the polycrystalline material to set the gate, this charge is trapped, for example. cut. This nitrogen-cutting charge traps the upper and lower layers of the layer and forms a complex containing oxidized oxide/tantalum nitride/yttria. , | Stacked open structure inside the electrical layer. On the substrate around the channel region of the memory layer, there is an oxide oxide isolation pattern for == adjacent two word lines, which is located on the substrate between the word lines 1 and is upper = knowing ^ In the electrical performance, the memory has the disadvantages of low read current, poor mutual conduction con uctance 'GM), slow programming speed and short data between 200910578 rvouu/i /9twf.doc/p. In addition, the oxidized stone isolation pattern located above the doped region requires a complicated manufacturing method such as ___ft_offmethod, which reduces the production efficiency and yield of the product. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a non-volatile character structure that can effectively reduce the complexity of the process. C') Another object of the present invention is to provide a non-volatile memory array having better electrical performance. The invention proposes a non-volatile memory structure comprising a substrate, a plurality of stacked patterns and a plurality of stress patterns. The stacked pattern is disposed on the substrate, and each of the stacked patterns includes a charge storage structure and a gate from bottom to top, wherein the charge storage structure includes at least a charge storage layer. The stress patterns are respectively disposed on the substrate between the adjacent two stacked patterns. The 'in the non-volatile memory structure' described above in accordance with the embodiment of the present invention further includes a plurality of doped regions which are respectively disposed in the substrates on both sides of each of the stacks. According to the embodiment of the present invention, in the above non-volatile memory structure, when the doped region is N-type doped, the material of the stress pattern includes a tensile stress material. According to an embodiment of the present invention, in the above non-volatile memory structure, when the doped region is P-type doped, the material of the stress pattern includes a compressive stress material. In accordance with an embodiment of the present invention, in the above non-volatile memory 200910578 ryuw/1 zho / ^twfdoc/p structure, the material of the charge storage layer comprises a fossil as described in the embodiment of the present invention. In the structure, the material of the stress pattern comprises a non-volatile memory of nitrogen, and the width of the stress pattern is equal to two adjacent stacked patterns in the non-volatile body structure described above. According to the present invention, the forwarding code, the gastric material column, the isolation pattern, the plurality of cages, and the plurality of character lines are arranged in parallel with each other in the base pattern. The isolation pattern was deleted as - Ying Qing. Doped === two ί=; Γ word; the lines are arranged parallel to each other in the isolation pattern = 耆 first direction extension 'and the other direction of the brother and the second = 2 lines below the == line = t neighbor There is an opening between the two stacked patterns: each of the storage structures includes at least one charge storage layer. In an embodiment of the above non-volatile memory array, the material of the charge storage layer comprises doped polycrystalline or nitrite. Body In accordance with an embodiment of the invention, the stress material in the array comprises tantalum nitride. Just 4 body In accordance with the embodiment of the present invention, the stress material is 3 material when the doped region is doped with yttrium. ~ In accordance with the embodiment of the present invention, in the above non-volatile memory 200910578 r /1 z-^to / 9twf.d〇c/p array, when the doped region is p-type, the stress material Including _ should be material. ~ The second embodiment of the invention, in the non-volatile memory array described above, further comprising a dielectric layer disposed on the substrate and filling the opening. In the non-volatile memory vehicle 1 described above, the material of the W electrical layer includes a stress material. 〇
C 陣列實施—述’在上述之非揮發記憶體 =之的寬度等於在第二方向上的相鄰兩個堆 個隔一種非揮發記憶體陣列’包括基底、多 區、多條字元線、多_ 向⑽^離圖案彼此平行配置於基底上且沿著第一方 線彼!^雜區分別配置於隔離圖案下方的基底中。字元 -方向與;=:離圖=著第二方向延伸，而第 電荷m之間具有開口。各鱗疊圖料η上包括 儲存層。;;〇閘極’其#電荷儲存結構至少包括-電荷 料為應力材^配置於基底上並填關口，且介電層的材 體陣：本一實施例所述，在上述之非揮發記憶 依昭太欲何绪存層的材料包括摻雜多晶石夕或氮化石夕。 體障列ΪΪΓΓ—實施例所述，在上述之非揮發記憶 應力材料包括氮化矽。 200910578 / i ^H〇/9twf.doc/p 力材料 依照本發明的另一實施例所述，在上述之非揮 ，陣列中，當摻雜區為㈣摻雜時，應力材料包括^^ 依照本發明的另—實施例所述，在上述之非揮 二中’當摻雜區為p型摻雜時’應力材料包括▲縮； 力材料。 基於上述，在本發明所提出的非揮發記憶體及其陣列 t ’由於在相鄰兩個堆疊_之_基底上配置有應力圖 案，而此應力随會施加應力於基底上，會 言土己憶體及其_在紐的表現上具有讀取電流高、互綠 佳、程式化速度快及資料保存時間長等優點。 此外，藉由本發明所提出的非揮發記憶體及其陣列可 有效地降低製程的複雜度，進而提升產品的生產效率。 “為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂’下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖1所繪示為本發明第一實施例到第三實施例之非揮 發δ己憶體陣列的上視圖。圖2所緣示為本發明第一實施例 及第二實施例沿圖1中Α_Α，剖面線之非揮發記憶體結構的 剖面圖。圖3所緣示為本發明第一實施例及第三實施例沿 圖1中Β-Β’剖面線之非揮發記憶體結構的剖面圖。圖1中 的非揮發記憶體陣列包括基底1〇〇、隔離圖案1〇2、摻雜區 104、子元線1〇6、堆疊圖案1〇8以及介電層η〇。圖2中 200910578 r / ι / 9twf.doc/p 的非揮lx記k'體結構包括基底 ……衫、雅跑 104、字元線106、堆疊圖案108以及介電層110。圖3中 的非揮發記憶體結構包括基底100、字元線1〇6、堆疊圖案 108以及介電層11〇。 f c 請同時參照圖1至圖3，在第一實施例中，隔離圖案 1〇2彼此平行配置於基底1〇〇上且沿著第一方向延伸，第 一方向例如是X-Y座標平面上的γ方向。隔離圖案工犯 的材料為應力材料，如具有應力的氮化矽材料，而使 ^圖案1G2成為具有應力的應力_。另外，#摻雜區^ =型?Γ夺，應力材料例如是具有拉申應力的拉伸應力 屨給虛I雜區1()4為？型摻雜時，應力材料例如是具有 壓縮應力的壓縮應力材料。 、肩 此外，51離圖案102的寬度w 102的高产 ' 方向除此之外，關於隔離圖案 件及需求域具㈣f知識者可依照製程條 中。==H=ri02下方的基底刚 或是摻雜。 〜體類里的不同需求可為N型摻雜 二方向延於隔離圖案102上且沿著第 材料例如是接雜多晶發 '第二方向相交。字元線106的 堆疊圖案108分別配w a — 置子7L線下方的相鄰兩個 隔 10C Array implementation - described in the above non-volatile memory = width equal to two adjacent non-volatile memory arrays in the second direction - including substrate, multi-region, multiple word lines, The plurality of patterns are disposed on the substrate in parallel with each other and are disposed in the substrate below the isolation pattern along the first square line. Character - direction and ; =: from the picture = extending in the second direction, and there is an opening between the first charges m. Each of the scales η includes a storage layer. ; 〇 极 ' 其 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷 电荷The material of the Yizhao Taixu layer includes doped polycrystalline or nitrite. Body Barriers - As described in the Examples, the non-volatile memory stress material described above includes tantalum nitride. 200910578 / i ^H〇/9twf.doc/p force material according to another embodiment of the present invention, in the above non-volatile, array, when the doped region is (four) doped, the stress material includes ^^ According to another embodiment of the present invention, in the above-mentioned non-volatile two, when the doped region is p-type doped, the stress material includes a yoke; a force material. Based on the above, the non-volatile memory and the array t′ proposed by the present invention are arranged on the substrate of the adjacent two stacks, and the stress is applied to the substrate. The memory and its _ in the performance of New Zealand have the advantages of high reading current, good mutual green, fast programming speed and long data storage time. In addition, the non-volatile memory and the array thereof proposed by the invention can effectively reduce the complexity of the process, thereby improving the production efficiency of the product. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; 1 is a top view of a non-volatile δ-resonance array of the first embodiment to the third embodiment of the present invention. FIG. 2 is a view showing the first embodiment and the second embodiment of the present invention along the Α_Α of FIG. A cross-sectional view of the structure of the volatile memory. Figure 3 is a cross-sectional view showing the non-volatile memory structure of the first embodiment and the third embodiment of the present invention along the Β-Β' section line of Figure 1. The volatile memory array includes a substrate 1 , an isolation pattern 1 , 2 , a doping region 104 , a sub-line 1 〇 6 , a stacked pattern 1 〇 8 , and a dielectric layer η 〇. In FIG. 2 , 200910578 r / ι / 9 twf. The non-volatile x' structure of doc/p includes a substrate, a shirt, a run 104, a word line 106, a stacked pattern 108, and a dielectric layer 110. The non-volatile memory structure in FIG. 3 includes a substrate 100, a word The upper line 1〇6, the stacked pattern 108, and the dielectric layer 11〇. fc Please refer to FIG. 1 to FIG. 3 simultaneously, in the first real In an example, the isolation patterns 1〇2 are arranged parallel to each other on the substrate 1〇〇 and extend along the first direction, for example, the γ direction on the XY coordinate plane. The material of the isolation pattern is a stress material, such as having The stress of the tantalum nitride material causes the pattern 1G2 to become a stress with stress _. In addition, the #doped region ^=type?, the stress material is, for example, a tensile stress with a tensile stress 屦 to the virtual I region When 1()4 is a doping type, the stress material is, for example, a compressive stress material having a compressive stress. In addition, the shoulder 51 is spaced apart from the width of the pattern 102 by a high yield '102 direction, in addition to the isolation pattern member and the demand. The knowledge of the domain (4) f can be in accordance with the process bar. =========================================================== The material is, for example, a hybrid polycrystalline hair 'the second direction intersects. The stacked pattern 108 of the word line 106 is respectively assigned a wa - the adjacent two compartments below the 7L line.
200910578 ^〇/9twf.doc/p 图案102之間的基底wo上， 一 個堆疊圖荦108夕„目士Ba 在弟方向上的相鄰兩 上間具有開口 112。堆疊_ 1〇8由下而 二二儲存結構114及閘極U6。閘極ΐΐ6在第 是摻I ^線刚互相電性連接，· 116的材料料 儲存層St:;: = 、電荷 電荇，包層以電何儲存層120可用以儲存 電荷雜多晶料導體材料或是氮化料 雷二底介電層118與頂介電層122可用以阻幹 何=電何儲存層12〇中流失，其材料例如是氧化石夕。田 ^介電層110配置於基底100上並填滿開口 112，且人 包層^〇的材料為應力材料，如具有應力的氮切 ， 而使件介電層1Η)成為具有應力的應力圖案。另外，當換 雜區104為Ν型摻雜時，應力材料例如是具有拉申應^ 拉，應力材料；當摻雜區刚為Ρ型摻雜時，應力材料例 如疋/、有壓應力的壓縮應力材料。此外，位於開口 Η] 申的介電層110位於第一方向上的相鄰兩個堆疊圖案1〇8 之間的基底100上，且位於開口 112中的介電層11〇的寬 又W2專於在弟—方向上的相鄰兩個堆疊圖案1 〇8之間的 距離D2。 、 在上述第一實施例中，於相鄰兩個堆疊圖案1 〇8之間 的基底100上配置有應力圖案(隔離圖案102及位於開口 U2中的J電層110),由於應力圖案可對基底1〇〇施加應 力’會使得非揮發性記憶體及其陣列在電性的表現上具有 11 200910578 »9twf.doc/p 讀取電流高 等優點。 互導較佳、程式化速度快及資料保存時間長 此外，第一眘 ΐΛ〇 丨施例中以位於摻雜區104上的隔離g素 102取代習知技術中位於摻雜區上的氧切隔圖ΐ 以有效地簡化製程，進而提升產品的=崎，可 ㈣實施例中是以隔離圖案102與介電層110200910578 ^〇/9twf.doc/p On the substrate wo between the patterns 102, a stacking pattern 荦108 目 目 Ba Ba has an opening 112 between the adjacent two in the direction of the brother. Stack _ 1 〇 8 from the bottom The second storage structure 114 and the gate U6. The gate electrode 6 is electrically connected to each other at the first I-line, and the material storage layer of the material material is St:;::, charge electric charge, and the cladding layer is electrically charged. 120 may be used to store the charge heteropolysilicon conductor material or the nitride dielectric bottom dielectric layer 118 and the top dielectric layer 122 may be used to resist the draining of the storage layer 12, such as an oxidized stone. The dielectric layer 110 is disposed on the substrate 100 and fills the opening 112, and the material of the human cladding layer is a stress material, such as a nitrogen cut with stress, so that the dielectric layer of the device becomes stress-resistant. In addition, when the impurity-doping region 104 is doped-type doped, the stress material has, for example, a tensile stress, a stress material; when the doped region is just doped, the stress material is, for example, 疋/, Compressive stress material of compressive stress. Further, the adjacent dielectric layer 110 located in the opening direction is located in the first direction On the substrate 100 between the stacked patterns 1〇8, the width W2 of the dielectric layer 11〇 located in the opening 112 is specific to the distance D2 between the adjacent two stacked patterns 1 〇8 in the young-direction. In the first embodiment described above, the stress pattern (the isolation pattern 102 and the J-electrode layer 110 located in the opening U2) is disposed on the substrate 100 between the adjacent two stacked patterns 1 〇 8 because the stress pattern can be The stress applied to the substrate 1〇〇 makes the non-volatile memory and its array have the advantages of high electrical reading performance. 2009-017878-9wf.doc/p High reading current. Better mutual conduction, fast programming and data saving In addition, in the first embodiment, the isolation g-crystal 102 located on the doping region 104 is substituted for the oxygen-cutting pattern on the doped region in the prior art to effectively simplify the process, thereby improving the product. = Saki, (4) In the embodiment, the isolation pattern 102 and the dielectric layer 110 are
Γ〇 J 目 兩者的其中之一的材料為應力材料，在 獲得明顯地改善。以下，以第二實施例及 弟二μ %例繼績進行說明。 明同日守參知圖1及圖2，在第二實施例中，隔離圖案 二”應力材料，使得隔離圖案102成為具有應力 的應力圖案，而介電層11()的材料為氧化發等一般介電材 料。另外’#二實施狀轉發性記題結構巾的其他構 件的材料、配置方式及功效與第—實施例中所揭露的内容 大致相同，故於此不再贅述。 田由於隔離圖案102分別配置於第二方向上的相鄰兩個 堆豐圖案108之間的基底100上，因此隔離圖帛1〇2可對 基底10 0施加應力’進而提升非揮發性記憶體的電性效能。 此外，第二實施例中以位於摻雜區1〇4上的隔離圖案 102取代習知技術中位於摻雜區上的氧化矽隔離圖案，可 以有效地降低製程複雜度，進而提升產品的生產效率。 請同時參照圖1及圖3,在第三實施例中，介電層u〇 的材料為應力材料，使得介電層11〇成為具有應力的應力 12 200910578 ryouu/L ^H〇/9twf.doc/p 圖案，而隔離圖案l〇2的材料為氧化石夕等人 另外’第三實_之轉發性記賴結構。 材料、配置方式及功效與第—實施例中所揭露的==的 相同，故於此不再贅述。 、内各大致 由於位於開口 112中的介電層11〇位於 相鄰兩個堆疊圖案議之間的基底⑽上，因此位=的 ⑴中的介電層110可對基底⑽施加 提= 揮發性記Μ的電性效能。 ㈣&升非 综上所述，上述實施例至少具有下列優點： ^ 1.本發明所提出的非揮發記憶體結構及 地簡化製程，進而提升產品的生產效率。 2·本發明所提出的非揮發記憶體結構及 佳的電性表現。 其陣列可有效 其陣列具有較 —雖然本發明已以較佳實施例揭露如上’然其並非用以 限=本發明，任何熟習此技藝者，在不脫離本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 二圖1所繪示為本發明第一實施例到第三實施例之非揮 發5己彳思體陣列的上視圖。 圖2所緣示為本發明第一實施例及第二實施例沿圖1 中Α-Α’剖面線之非揮發記憶體結構的剖面圖。 圖3所繪示為本發明第一實施例及第三實施例沿圖1 中剖面線之非揮發記憶體結構的剖面圖。 13 200910578 a y \j\j\j t x I ^twf.doc/p 【主要元件符號說明】 100 :基底 102 :隔離圖案 104 :摻雜區 106 :字元線 108 :堆疊結構 110 :介電層 112 :開口 114:電荷儲存結構 116 :閘極 118 :底介電層 120 :電荷儲存層 122 :頂介電層 Dl、D2 :距離 Wl、W2 :寬度 14Γ〇 J The material of either of them is a stress material, which is significantly improved. Hereinafter, the second embodiment and the second example of the second example will be described. In the second embodiment, the isolation pattern is made of two stress materials, so that the isolation pattern 102 becomes a stress pattern with stress, and the material of the dielectric layer 11 is oxidized. Dielectric material. The material, arrangement and function of the other components of the '#2 embodiment-transferable character structure structure towel are substantially the same as those disclosed in the first embodiment, and therefore will not be described here. 102 is respectively disposed on the substrate 100 between the two adjacent stack patterns 108 in the second direction, so the isolation pattern 帛1〇2 can stress the substrate 10 0 to improve the electrical performance of the non-volatile memory. In addition, in the second embodiment, the isolation pattern 102 located on the doping region 1〇4 is substituted for the yttrium oxide isolation pattern on the doped region in the prior art, which can effectively reduce the process complexity and further improve the production of the product. Referring to FIG. 1 and FIG. 3 simultaneously, in the third embodiment, the material of the dielectric layer u is a stress material, so that the dielectric layer 11 becomes a stress with stress 12 200910578 ryouu/L ^H〇/9twf .doc/p pattern The material of the isolation pattern l〇2 is the same as the 'third real_transferability record structure of the oxidized stone Xi et al. The material, the arrangement and the effect are the same as the == disclosed in the first embodiment, so Therefore, the dielectric layer 11 located in the opening 112 is located on the substrate (10) between the adjacent two stacked patterns, so that the dielectric layer 110 in the (1) can be opposite to the substrate (10). Applying the electrical performance of the volatility record. (4) & liters In summary, the above embodiments have at least the following advantages: 1. The non-volatile memory structure proposed by the present invention simplifies the process and improves the product. Production efficiency 2. The non-volatile memory structure and good electrical performance of the present invention are provided. The array can be effectively arrayed. Although the present invention has been disclosed in the preferred embodiment, it is not intended to limit the In the present invention, it is to be understood that the scope of the invention is defined by the scope of the appended claims. 【figure BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2 is a top view of a non-volatile 5 bismuth array of the first embodiment to the third embodiment of the present invention. FIG. 2 is a first embodiment and a second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a cross-sectional view showing the structure of a non-volatile memory along the line Α-Α' in FIG. 1. FIG. 3 is a view showing a non-volatile memory structure along the line of FIG. 1 according to the first embodiment and the third embodiment of the present invention. 13 200910578 ay \j\j\jtx I ^twf.doc / p [Main component symbol description] 100: substrate 102: isolation pattern 104: doped region 106: word line 108: stacked structure 110: Electrical layer 112: opening 114: charge storage structure 116: gate 118: bottom dielectric layer 120: charge storage layer 122: top dielectric layer D1, D2: distance Wl, W2: width 14