CN115036291A - Three-dimensional memory, preparation method thereof and storage system - Google Patents
Three-dimensional memory, preparation method thereof and storage system Download PDFInfo
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
The application provides a three-dimensional memory, a preparation method thereof and a storage system. The three-dimensional memory comprises a laminated structure, a storage channel structure and a top selection gate contact structure. A stacked structure is formed on the substrate, and the stacked structure includes a top select gate. A plurality of storage channel structures extend through the stack structure and to the substrate. The top selection gate contact structure is positioned between two adjacent storage channel structures in the first direction, extends to the top selection gate in a penetrating mode and is electrically connected with the top selection gate. Wherein the first direction is an extension direction of the substrate. According to the three-dimensional memory and the preparation method thereof, the top selection gate contact structure is also arranged in the core area, so that the driving length of the top selection gate can be effectively reduced, and the switching rate of the top selection gate can be controlled.
Description
Technical Field
The present application relates to the field of semiconductor design and manufacturing, and more particularly, to a structure of a three-dimensional memory and a method for fabricating the same.
Background
The increase in the storage density of the memory is closely related to the progress of the semiconductor manufacturing process. To further increase the storage density, three-dimensional memories have been developed. The three-dimensional memory includes a stacked structure formed by alternately stacking a plurality of gate layers and a plurality of dielectric layers, and a plurality of storage channel structures passing through the stacked structure. The memory channel structure may include a memory string, a portion of the memory string corresponding to the gate layer and the corresponding gate layer forming a memory cell.
The gate layers at the top of the stack structure typically serve as top select gates for controlling the top select transistors to select the memory strings. The other gate layers can be used as control gates for controlling the memory cells to realize the memory function.
It is to be appreciated that this background section is intended in part to provide a useful background for understanding the technology, however, it is not necessary for these matters to be within the knowledge or understanding of those skilled in the art prior to the filing date of the present application.
Disclosure of Invention
One aspect of the present application provides a three-dimensional memory. The three-dimensional memory includes: a stacked structure formed on the substrate, the stacked structure including a top select gate; a plurality of storage channel structures penetrating the stacked structure and extending to the substrate; the top selection gate contact structure is positioned between two adjacent storage channel structures in the first direction, penetrates through the top selection gate, extends to the top selection gate and is electrically connected with the top selection gate; wherein the first direction is an extension direction of the substrate.
In some embodiments, the laminate structure has a core region and a plateau region; the plurality of top selection grid contact structures are positioned in the core area; alternatively, a plurality of top select gate contact structures are located in the core region and the step region.
In some embodiments, the three-dimensional memory further includes a top select gate cut line penetrating the top select gate and extending in the first direction to divide the top select gate into a plurality of regions insulated from each other; a plurality of top select gate contact structures and a plurality of storage channel structures are located in each region.
In some embodiments, the stacked structure includes gate layers and dielectric layers that are alternately stacked; the top selection gate tangent line penetrates through at least one gate layer, and the top selection gate contact structure extends to the at least one gate layer; wherein at least one of the gate layers constitutes a top select gate.
In some embodiments, the stacked structure includes a first stacked structure and a second stacked structure, which respectively include gate layers and dielectric layers alternately stacked; the memory channel structure comprises a first memory channel structure and a second memory channel structure respectively penetrating through the first laminated structure and the second laminated structure, and a first channel layer of the first memory channel structure is electrically communicated with a second channel layer of the second memory channel structure; the top selection gate tangent line penetrates through the at least one gate layer of the second laminated structure, and the top selection gate contact structure extends to the at least one gate layer of the second laminated structure; wherein at least one gate layer of the second stacked structure constitutes a top select gate.
In some embodiments, the stacked structure includes a first stacked structure including a first gate layer and a first dielectric layer which are alternately stacked, and a second stacked structure including a second gate layer and a second dielectric layer which are stacked, the storage channel structure including a first storage channel structure and a second storage channel structure which extend through the first stacked structure and the second stacked structure, respectively, the first channel layer of the first storage channel structure and the second channel layer of the second storage channel structure being in electrical communication; the top selection gate tangent line penetrates through the second laminated structure, and the top selection gate contact structure extends to the second gate layer; wherein the second gate layer constitutes a top select gate.
In some embodiments, the material of the first gate layer is different from the material of the second gate layer.
In some embodiments, the first gate layer comprises a metal conductive material and the second gate layer comprises doped polysilicon.
In some embodiments, the radial dimension of the second storage channel structure is smaller than the radial dimension of the first storage channel structure.
In some embodiments, at least a portion of the top select gate tangent is undulating in the first direction.
In some embodiments, the three-dimensional memory further comprises: and the interconnection structure is electrically connected with the top selection gate contact structure and is used for carrying out signal transmission with an external control circuit.
In some embodiments, a dummy channel structure is further included through a portion of the stack structure and extending to the substrate at a location corresponding to the top select gate contact structure.
A method for preparing a three-dimensional memory comprises the following steps: forming a stacked structure including a top select gate and a storage channel structure on a substrate; and forming a top select gate contact structure between adjacent memory channel structures in the first direction, the top select gate contact structure extending to and in electrical contact with the top select gate; wherein the first direction is an extension direction of the substrate.
In some embodiments, the laminate structure comprises a first laminate structure and a second laminate structure; wherein the step of forming a stacked structure including a top select gate and a storage channel structure on a substrate comprises: forming a first stacked structure including a first storage channel structure on a substrate, the first stacked structure including first dielectric layers and first gate layers which are alternately stacked; and forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; wherein the channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure, and the at least one second gate layer constitutes a top select gate.
In some embodiments, the laminate structure comprises a first laminate structure and a second laminate structure; wherein the step of forming a stacked structure including a top select gate and a storage channel structure on a substrate comprises: forming a first stack structure including a first storage channel structure on a substrate, the first stack structure including first dielectric layers and gate sacrificial layers alternately stacked; forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; replacing the grid sacrificial layer in the first stacked structure with a first grid layer; wherein the first dielectric layers and the first gate layers alternately stacked constitute a first stacked structure, the channel layer of the first storage channel structure is electrically connected with the channel layer of the second storage channel structure, and at least one of the second gate layers constitutes a top select gate.
In some embodiments, the method of making further comprises: forming a top select gate tangent line penetrating the top select gate, wherein the top select gate tangent line extends in a first direction and divides the top select gate into a plurality of regions insulated from each other, and a plurality of top select gate contact structures and a plurality of storage channel structures are located in each region.
In some embodiments, the material of the first gate layer is different from the material of the second gate layer.
In some embodiments, the first gate layer comprises a metal conductive material and the second gate layer comprises doped polysilicon.
In some embodiments, the method of making further comprises: an interconnect structure is formed in electrical contact with the top select gate contact structure for signal transmission to an external control circuit.
A storage system, comprising: the three-dimensional memory as above; and the controller is electrically connected with the three-dimensional memory and is used for controlling the three-dimensional memory.
According to the three-dimensional memory and the manufacturing method thereof, the top selection gate contact structure is also arranged in the core region including the memory string, so that the driving length of the top selection gate can be effectively reduced, and the switching rate of the top selection gate can be controlled.
Drawings
Other features, objects, and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, with reference to the accompanying drawings. In the drawings:
FIG. 1 is a schematic partial top view of a three-dimensional memory according to some embodiments of the related art;
2-4 are schematic partial cross-sectional views of a three-dimensional memory according to some embodiments of the related art taken along line AA' of FIG. 1;
FIG. 5 is a schematic partial top view of a three-dimensional memory according to some embodiments of the present application;
FIG. 6 is a schematic partial cross-sectional view of a three-dimensional memory according to some embodiments of the present application, taken along line BB' of FIG. 5;
FIG. 7 is a flow chart of a method of fabricating a three-dimensional memory according to some embodiments of the present application;
FIG. 8 is a flowchart of step S1 according to some embodiments of the present application;
fig. 9A to 9D are partial schematic views of the device structure in the step shown in fig. 8;
FIG. 10 is a flowchart of step S1 according to other embodiments of the present application;
FIGS. 11A to 11C are partial schematic views of the device structure in the steps shown in FIG. 10;
FIG. 12 is a partial schematic diagram of a device structure in step S2 according to some embodiments of the present application; and
fig. 13A and 13B are schematic structural diagrams of a storage system according to an exemplary embodiment of the present application.
Detailed Description
The present application will hereinafter be described in detail with reference to the accompanying drawings, and the exemplary embodiments mentioned herein are only for explaining the present application and do not limit the scope of the present application. Like reference numerals refer to like elements throughout the specification.
In the drawings, the thickness, size and shape of the components have been slightly adjusted for convenience of explanation. The figures are purely diagrammatic and not drawn to scale. As used herein, the terms "approximately," "about," and the like are used as approximations, not as degrees of expression, and are intended to account for inherent deviations in measured or calculated values that will be recognized by those of ordinary skill in the art.
It should also be understood that the expression "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising," "including," "having," "including," and/or "containing" are open rather than closed expressions in this specification that indicate the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof. Furthermore, when a statement such as "at least one of" appears after a list of listed features, it modifies that entire list of features rather than merely individual elements of the list. When describing embodiments of the present application, the use of "may" mean "one or more embodiments of the present application. Also, the term "exemplary" is intended to indicate either an example or an illustration.
Further, in this application, when expressions such as "connected," "covered," and/or "formed at …" are used, direct or indirect contact between the respective components may be meant, unless there is an explicit other limitation or can be inferred from the context.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. Furthermore, unless otherwise indicated herein, words defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense.
The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic partial top view of a three-dimensional memory 10 according to some embodiments of the related art. Referring to fig. 1, a three-dimensional memory 10 may include a plurality of Gate Line Slit structures (GLS) 11 extending in a Y-axis direction. Two adjacent gate line slit structures 11 divide the plurality of memory channel structures 12 into one block region 13. One block region 13 includes a plurality of Top Selective Gate cuts (TSG cuts) 14 extending in the Y-axis direction, the Top Selective Gate cuts 14 dividing the block region 13 into a plurality of finger areas 13a, and thus a Top select Gate (described below) of each finger area 13a can be individually controlled. When a bit line 15 is selected, the top select transistor in a finger memory region 13a is turned on, and the memory channel structure 12 in the finger memory region 13a to which the bit line 15 is connected is selected; when a word line (not shown) of one layer is selected, a memory cell in the memory channel structure 12 can be selected, and thus, the memory function of a single memory cell can be realized. For clarity, only one bit line 15 is shown in FIG. 1, it being understood that there may be multiple bit lines 15.
Fig. 2 is a schematic partial cross-sectional view of the three-dimensional memory 10 according to some embodiments of the related art, taken along line AA' of fig. 1.
Referring to fig. 2, the three-dimensional memory 10 includes a stacked structure 18 in which a plurality of gate layers 16 and a plurality of dielectric layers 17 are alternately stacked, and a memory channel structure 12 penetrating the stacked structure 18. In the three-dimensional memory 10, at least one Gate layer 16 (shown as 4 Gate layers 16 in fig. 2) on Top of the stacked structure 18 may serve as a Top Selective Gate (TSG), and at least one field effect transistor (also referred to as a "Top select transistor") may be formed in each storage channel structure 12 at a position corresponding to the Top select Gate.
In the three-dimensional memory 10, the remaining gate layer 16 in the stacked structure 18 may serve as a control gate. The memory channel structure 12 may form a memory cell at a location corresponding to each control gate. The portion of the storage channel structure 12 surrounded by the control gate and the portion surrounded by the top select gate may have the same structure and radial dimensions.
Top select gate cut lines 14 pass through the top select gates and the dielectric layer 17 adjacent thereto to partition the top select gates so that the top select gates in each finger area 13a (see fig. 1) can be driven separately. As shown in fig. 2, the top selection gate tangent 14 may be disposed between adjacent memory channel structures 12, but the embodiment is not limited thereto. For example, dummy channel structures (not shown) may be added below the top select gate tangent 14.
Fig. 3 is a schematic partial cross-sectional view of the three-dimensional memory 20 according to some embodiments of the related art, taken along line AA' of fig. 1.
The three-dimensional memory 20 differs from the three-dimensional memory 10 in that the top select gate is formed in a sub-stack structure. Specifically, as shown in fig. 3, the three-dimensional memory 20 includes a first stacked structure 21 and a second stacked structure 22, and a first storage channel structure 23 and a second storage channel structure 24 respectively penetrating the first stacked structure 21 and the second stacked structure 22. The first and second storage channel structures 23 and 24 may include first and second channel layers 25 and 26, respectively, and the first and second channel layers 25 and 26 may be in contact to achieve electrical communication. The top selection gate tangent 14 is located between two adjacent second storage channel structures 24 and passes through at least one gate layer 16 of the second stacked structure 22, so as to form a top selection gate in the second stacked structure 22 (in fig. 3, the top selection gate tangent 14 passes through 5 gate layers 16, in practical applications, the number of layers of the gate layers 16 in the top selection gate may be adjusted as needed, which is not limited in the present application), so as to be capable of driving each of the finger areas 13a (fig. 1) respectively.
Fig. 4 is a schematic partial cross-sectional view of a three-dimensional memory 30 according to some embodiments of the related art, taken along line AA' of fig. 1.
The three-dimensional memory 30 differs from the three-dimensional memory 20 in that the second stacked structure 31 includes only one gate layer 32 (top select gate) and two dielectric layers 33 adjacent to both sides thereof, and the gate layer 32 in the second stacked structure 31 may include a different material from the gate layer 35 in the first stacked structure 34. The top selection gate cut line 14 is located between two adjacent second memory channel structures 24 and penetrates through the second stacked structure 31 to partition the top selection gate (gate layer 32) so as to be able to drive the top selection gate in each of the memory cell regions 13a (fig. 1) respectively.
It should be understood that the embodiments illustrated in fig. 2 to 4 are merely examples, and the embodiments of the memory channel structure and the stack structure are not limited thereto.
Referring again to fig. 1, a top select gate cut line 14 divides the top select gate into a plurality of finger areas 13a to individually control the plurality of finger areas 13 a. The three-dimensional memory 10 may further include a core region CA for forming a plurality of memory channel structures 12 and a step region SS for forming various connection structures and word lines, etc., without including the memory channel structures 12. The plurality of storage channel structures 12 may be arranged in a two-dimensional array on a plane formed parallel to the X-axis and the Y-axis. In the step region SS, the three-dimensional memory 10 may include a top select gate contact structure 19. The top select gate contact structure 19 passes through a portion of the stacked structure 18 (see fig. 2) or a portion of the second stacked structure 22 (see fig. 3), or a portion of the second stacked structure 31 (see fig. 4) and is in electrical contact with the top select gate (see gate layer 16 of fig. 2 and 3 and gate layer 32 of fig. 4). The three-dimensional memory 10 may further include an interconnect structure (not shown) in electrical contact with the top select gate contact structure 19 for signal transmission with an external control circuit to drive the top select gates of the respective finger areas 13 a. According to the related art embodiment, in order to control the top select gate in one finger storage region 13a, the driving length of the top select gate contact structure 19 is DL 0 . Currently, to improve the storage capacity of three-dimensional memories, the DL is usually adopted 0 A plurality of memory channel structures are arranged in the direction of (a). In other words, relatively long DL 0 It needs to be driven by a top select gate contact structure 19 located in the SS. While relatively longer DL 0 The top select gate is made to have a relatively high resistance, which results in a reduced switching rate and reduced memory performance. This further reduces the switching rate, especially when the top select gate comprises a material such as polysilicon, since the resistivity of polysilicon is roughly 20 times greater than that of metal (e.g., tungsten).
In view of this, exemplary embodiments of the present application provide a three-dimensional memory including a stack structure, a memory channel structure, and a top select gate contact structure. A stacked structure is formed on the substrate, and the stacked structure includes a top select gate. A plurality of storage channel structures extend through the stack structure and to the substrate. The top selection gate contact structure is positioned between two adjacent storage channel structures in the first direction, extends to the top selection gate in a penetrating mode and is electrically connected with the top selection gate. Wherein the first direction is an extension direction of the substrate. In the scheme, the top selection gate contact structure is arranged between two adjacent storage channel structures, so that the length of the top selection gate between the adjacent top selection gate contact structures is shorter, and the driving length of the top selection gate contact structure can be reduced when the top selection gate of the laminated structure is controlled, so that the top selection gate correspondingly has relatively smaller resistance, the switching rate of the storage is improved, and the performance of the storage is further improved.
The above-described aspects of the present application are applicable to various forms of stacked structures, such as the stacked structure 18 shown in fig. 2, or the stacked structure includes the first stacked structure 21 and the second stacked structure 22 shown in fig. 3, or the stacked structure includes the first stacked structure 34 and the second stacked structure 31 shown in fig. 4. The present application will hereinafter describe the technical solution of the present application in detail in the form of a laminate structure including a first laminate structure 34 (hereinafter, referred to as a first laminate structure 120) and a second laminate structure 31 (hereinafter, referred to as a first laminate structure 140) as illustrated in fig. 4.
Fig. 5 is a schematic partial top view of a three-dimensional memory 100 according to some embodiments of the present application.
Referring to fig. 5, the three-dimensional memory 100 may include a plurality of top select gate contact structures 110 in a core region CA, and the top select gate contact structures 110 are distributed in each of the finger storage regions F to reduce a driving length DL of the top select gate contact structures 110 when the top select gates in the finger storage regions F are respectively controlled 1 . As shown in fig. 5, DL may be implemented by providing a plurality of top select gate contact structures 110 in each finger pad region F 1 <DL 0 . It should be understood that the arrangement of the plurality of top select gate contact structures 110 is not limited to the arrangement shown in fig. 5, but may be in any manner capable of reducing the driving lengthThe formula (I) is arranged.
Fig. 6 is a schematic partial cross-sectional view of three-dimensional memory 100 according to some embodiments of the present application, taken along line BB' of fig. 5.
Referring to fig. 6, the three-dimensional memory 100 may include a first stack structure 120 on a substrate 101. In some embodiments, the substrate 101 may comprise polysilicon. The first stacked structure 120 may include a plurality of first dielectric layers 121 and a plurality of first gate layers 122 stacked alternately, wherein the first gate layers 122 may serve as a control gate for extracting a word line (not shown), for example. In some embodiments, the first gate layer 122 may include a metal conductive material of W, Co, Cu, Al, Ti, Ta, Ni, or the like. In some embodiments, the first gate layer 122 may include polysilicon, doped silicon, metal silicide (e.g., NiSi) x 、WSi x 、CoSi x And/or TiSi x ) Or any combination thereof. In some embodiments, the first dielectric layer 121 may include silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first stacked layer structure 120 may include a plurality of pairs of the first dielectric layer 121 and the first gate layer 122, and the number of pairs may be selected according to various application scenarios, for example, the number of pairs may be 32, 64, 96, 128, 160, 192, 224, 256 or more.
In some embodiments, the three-dimensional memory 100 may include a first storage channel structure 130 extending through the first stack structure 120. The first storage channel structure 130 may include, for example, a pillar shape (e.g., a cylinder) or a contour shape similar to an "inverted cone" shape. The first storage channel structure 130 may include, for example, a functional layer, a first channel layer 131, and a first filler core 132, which are sequentially disposed from the outside to the inside. The functional layers may include, for example, a first barrier layer 133, a storage layer 134, and a tunneling layer 135 disposed in this order from the outside to the inside. The first barrier layer 133 may include, for example, silicon oxide, silicon oxynitride, a high dielectric constant material, or any combination thereof. Storage layer 134 may comprise, for example, silicon nitride, silicon oxynitride, silicon, or any combination thereof. The tunneling layer 135 may comprise, for example, silicon oxide, silicon oxynitride, or any combination thereof. In some embodiments, the functional layer may be, for example, a composite layer including silicon oxide/silicon oxynitride/silicon oxide (ONO). The first channel layer 131 may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or single crystal silicon, for example. The first filled core 132 may comprise, for example, an insulating material such as silicon oxide or the like.
In some embodiments, the first channel layers 131 may be in contact with the substrate 101 such that the first channel layers 131 of the respective first storage channel structures 130 are interconnected. The first channel layer 131 may have a similar profile shape to the first storage channel structure 130, for example. The first filling core portion 132 may be disposed, for example, in a space defined by the first channel layer 131 and occupy a bottom portion of the space near the substrate 101.
The first storage channel structure 130 may further include a first channel plug 136 at an upper portion thereof, for example. A first channel plug 136 may be located on a side of the first filler core 132 away from the substrate 101, wherein the first channel plug 136 may be in contact with an end of the first channel layer 131. The first channel plug 136 may also be in contact with a sidewall of the first channel layer 131, for example. The first channel plug 136 may include the same material as that of the first channel layer 131.
In some embodiments, the three-dimensional memory 100 may include a second stacked structure 140 on the first stacked structure 120. The second stacked structure 140 may include at least one second gate layer 142 and at least two second dielectric layers 141 adjacent thereto, which are alternately stacked. In some embodiments, the second gate layer 142 may serve as a top select gate. It is to be understood that the number of the second gate layer 142 and the second dielectric layer 141 adjacent thereto may be set as desired. For example, the number of second gate layers 142 may be 1, 2, 4, or more.
In some embodiments, one second dielectric layer 141 of the second stacked structure 140 close to the substrate 101 may be adjacent to one first dielectric layer 121 of the first stacked structure 120 far from the substrate 101. In some embodiments, the second dielectric layer 141 may include the same material as that of the first dielectric layer 121.
In some embodiments, the second gate layer 142 may include a metal conductive material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., and the work function of the metal is such that when the second gate layer 142 is used as a top select gate, the threshold voltage of the top select transistor is positive, for example, so that the controlled memory channel structure can be turned off.
In some embodiments, the second gate layer 142 may also include materials such as polysilicon, doped silicon, metal silicide (e.g., NiSi) x 、WSi x 、CoSi x And/or TiSi x ) Or any combination thereof, and the like. In some embodiments, the second gate layer 142 may include polysilicon doped P-type (e.g., boron doped) such that when the second gate layer 142 is used as a top select gate, the threshold voltage of the top select transistor is positive, thereby turning off the controlled storage channel structure. In addition, when the second gate layer 142 is a semiconductor material, since the resistance of the semiconductor material is about 20 times that of the metal material, the driving length DL of the top selection gate contact structure 110 is reduced 1 The method is particularly beneficial to enabling the top selection grid of the semiconductor material to have relatively small resistance correspondingly, improving the switching rate of the top selection grid, and further improving the performance of the three-dimensional memory.
In some embodiments, the material of the first gate layer 122 may be different from the material of the second gate layer 142. For example, the first gate layer 122 may include a metal material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., and the second gate layer 142 may include a semiconductor material such as undoped polysilicon or doped polysilicon or metal silicide, etc. In some embodiments, the first gate layer 122 may include W, and the second gate layer 142 may include boron doped polysilicon. In some embodiments, the material of the first gate layer 122 may be the same as the material of the second gate layer 142.
In some embodiments, the three-dimensional memory 100 may further include a second storage channel structure 150 extending through the second stack structure 140. In some embodiments, the second memory channel structure 150 may pass through the second stacked structure 140 and stop at a surface of the second dielectric layer 141 contacting the first stacked structure 120. The second storage channel structure 150 may include a similar profile shape as the first storage channel structure 130, for example. The radial dimension of the second memory channel structure 150 may be smaller than the radial dimension of the first memory channel structure 130. The second storage channel structure 150 may include a second barrier layer 151, a second channel layer 152, and a second filler core 153, which are sequentially disposed from the outside to the inside. The second channel layer 152 may have a similar profile shape to the second storage channel structure 150, for example. In some embodiments, the second channel layer 152 may extend into the first storage channel structure 130 and be electrically connected with the first channel layer 131. In some embodiments, the material of the second channel layer 152 may be the same as the material of the first channel layer 131. In one embodiment, the second channel layer 152 may be in contact with the first channel plug 136, thereby being electrically connected to the first channel layer 131 through the first channel plug 136. The second filler core 153 may be disposed, for example, in a space defined by the second channel layer 152 and occupy a bottom portion of the space near the substrate 101.
The three-dimensional memory 100 may further include a second channel plug 154 positioned at an upper portion of the second memory channel structure 150. A second channel plug 154 may be located on a side of the second filler core 153 remote from the substrate 101, wherein the second channel plug 154 may be in contact with an end of the second channel layer 152. The second channel plug 154 may also be in contact with a sidewall of the second channel layer 152. In some embodiments, the second channel plug 154 can increase a contact area and a process window of a bit line contact, and can also serve as a portion of a drain of a corresponding memory channel structure. In some embodiments, the material of the second channel plug 154 may be the same as the material of the second channel layer 152.
Referring to fig. 5 and 6, the three-dimensional memory 100 may further include a top select gate cut line 170 between adjacent gate line slit structures 160. The top select gate tangent 170 may be disposed between two adjacent second memory channel structures 150, for example, and pass through the second gate layer 142 and stop in one second dielectric layer 141 in contact with the first stacked structure 120, for dividing the top select gate (at least one second gate layer 142) into a plurality of mutually insulated regions, thereby individually controlling the regions. It should be noted that the top select gate tangent line 170 divides the top select gate into a plurality of mutually insulated regions, which are referred to as the memory regions F herein. The top select gate cut 170 may comprise any suitable insulating material, for example.
Referring to fig. 5 and 6, the three-dimensional memory 100 may further include a plurality of top select gate contact structures 110. In some embodiments, the top selection gate contact structure 110 may be disposed in each of the core region CA and the terrace region SS, and a plurality of top selection gate contact structures 110 may be included in the core region CA of each of the finger regions F. Alternatively, the plurality of top select gate contact structures 110 may be located only in the core area CA.
The top select gate contact structure 110 may, for example, pass through an upper portion of the second stack structure 140 remote from the substrate 101 and stop in one second gate layer 142 (top select gate) to be electrically connected with the top select gate. The top select gate contact structure 110 may, for example, comprise the same material as the second gate layer 142. In some embodiments, the top select gate contact structure 110 may comprise any suitable conductive material.
In some embodiments, the three-dimensional memory 100 may further include an interconnect structure 180 of the top select gate contact structure 110. The interconnect structure 180 is in electrical contact with the top select gate contact structure 110 for signal transmission to external control circuitry to drive the top select gates in each finger pad region F, respectively. The interconnect structure 180 may comprise, for example, the same material as the top select gate contact structure 110. In some embodiments, interconnect structure 180 may include any suitable conductive material. In some embodiments, a dummy channel structure 190 may be further included through the first stack structure 120 at a position corresponding to the top select gate contact structure 110. It is understood that in some other embodiments, dummy channel structure 190 may be omitted.
According to the exemplary embodiment of the present application, since the top selection gate contact structure 110 is disposed in the core area CA of each finger-storing area F, and the top selection gate contact structure 11 in the core area CA of each finger-storing area F0 can be set to be plural, thereby reducing the effective Drive Length (DL) of the control top select gate 1 <DL 0 ) The problem of reduced switching rate caused by the need to drive a longer length top select gate (higher resistivity) is avoided, and the performance of the three-dimensional memory is improved.
Exemplary embodiments of the present application may also provide a method of manufacturing a three-dimensional memory. Fig. 7 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to some embodiments of the present application. As shown in fig. 7, the method 1000 for manufacturing a three-dimensional memory may include the following steps:
s1, forming a laminated structure comprising a top selection gate and a storage channel structure on the substrate;
s2, forming a top selection gate contact structure between adjacent storage channel structures in a first direction, wherein the top selection gate contact structure extends to the top selection gate and is electrically contacted with the top selection gate, and the first direction is the extending direction of the substrate; and
and S3, forming an interconnection structure of the top selection gate contact structure.
In addition, the embodiments and the features of the embodiments in the present application may be combined with each other without conflict. Further, unless explicitly defined or contradicted by context, the specific steps included in the methods described herein need not be limited to the order described, but rather can be performed in any order or in parallel. Fig. 8 to 12 are partial schematic views of device structures formed at various stages of a method 1000 for fabricating a three-dimensional memory according to some embodiments of the present application, and furthermore, fig. 9A to 9D and fig. 11A to 11C are partial sectional views of the structure illustrated in fig. 5 in an X direction, and fig. 12 is a partial sectional view of the structure illustrated in fig. 5 in a Y direction. The preparation method 1000 will be described in detail below with reference to fig. 8 to 12 and fig. 6.
S1，Forming a stack structure including a top select gate and a storage channel structure on a substrate。
In some embodiments, the laminate structure comprises a first laminate structure and a second laminate structure. As shown in fig. 8, step S1 includes:
s101, forming a first laminated structure comprising a first storage channel structure on a substrate, wherein the first laminated structure comprises a first dielectric layer and a first gate layer which are alternately laminated; and
and S102, forming a second stacked structure comprising a second storage channel structure on the first stacked structure, wherein the second stacked structure comprises at least one second gate layer and at least two second dielectric layers adjacent to the second gate layer.
Wherein the channel layer of the first memory channel structure is electrically connected to the channel layer of the second memory channel structure, and the at least one second gate layer constitutes a top select gate.
Referring to fig. 9A, in step S101, a first stacked structure 120 ' is formed on a substrate 101, the first stacked structure 120 ' including first dielectric layers 121 and gate sacrificial layers 122 ' alternately stacked. A plurality of first storage channel structures 130 are then formed through the first stacked structure 120'. Subsequently, a gate line slit 160 'penetrating the first stacked structure 120' is formed, referring to fig. 9B, and the gate sacrificial layer 122 'of the first stacked structure 120' is replaced with the first gate layer 122 via the gate line slit 160 'and then the gate line slit 160' is filled to form the gate line slit structure 160, referring to fig. 9C. To this end, the first dielectric layers 121 and the first gate layers 122 alternately stacked constitute the first stacked structure 120.
Referring to fig. 9D, in step S102, the second stacked structure 140 is formed on a side of the first stacked structure 120 away from the substrate 101, where the second stacked structure 140 includes at least one second gate layer 142 and at least two second dielectric layers 141 adjacent thereto. Illustratively, the second dielectric layer 141, the second gate layer 142, and the second dielectric layer 141 are sequentially formed using a thin film deposition process. A plurality of second memory channel structures 150 are then formed through the second stack structure 140. The channel layer of the first memory channel structure 130 is electrically connected to the channel layer of the second memory channel structure 150, and the second gate layer 142 constitutes the top select gate.
The material of the first gate layer 122 may be different from the material of the second gate layer 142, for example. For example, the first gate layer 122 may include a metal material such as W, Co, Cu, Al, Ti, Ta, Ni, etc., and the second gate layer 142 may include a semiconductor material such as undoped polysilicon or doped polysilicon or metal silicide, etc. In some embodiments, the first gate layer 122 may include W, and the second gate layer 142 may include boron doped polysilicon. In some embodiments, the material of the first gate layer 122 may be the same as the material of the second gate layer 142, and both include a metal material such as W.
Alternatively, the step of "gate replacement" may be performed after the second stacked structure is formed to replace the gate sacrificial layer with the first gate layer.
Specifically, as shown in fig. 10, step S1 includes:
s101', forming a first stacked structure comprising a first storage channel structure on a substrate, wherein the first stacked structure comprises a first dielectric layer and a gate sacrificial layer which are alternately stacked;
s102', forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; and
s103', replacing the grid sacrificial layer in the first stacked structure with a first grid layer;
wherein the first dielectric layers and the first gate layers, which are alternately stacked, constitute a first stack structure, the channel layer of the first storage channel structure is electrically connected with the channel layer of the second storage channel structure, and at least one of the second gate layers constitutes a top select gate.
Referring also to fig. 9A, in step S101 ', a first stacked structure 120 ' including alternately stacked first dielectric layers 121 and gate sacrificial layers 122 ' is formed on a substrate. A plurality of first storage channel structures 130 are then formed through the first stacked structure 120'.
Referring to fig. 11A, in step S102 ', the second stacked structure 140 is formed on a side of the first stacked structure 120' away from the substrate 101, where the second stacked structure 140 includes at least one second gate layer 142 and at least two second dielectric layers 141 adjacent thereto. Illustratively, the second dielectric layer 141, the second gate layer 142, and the second dielectric layer 141 are sequentially formed using a thin film deposition process. A plurality of second memory channel structures 150 are then formed through the second stack structure 140. The channel layer of the first storage channel structure 130 is electrically connected to the channel layer of the second storage channel structure 150, and the second gate layer 142 constitutes the top select gate.
Subsequently, a gate line slit 160 'penetrating the first stacked structure 120' and the second stacked structure 140 is formed in step S103 ', referring to fig. 11B, and the gate line slit 160' is formed by filling the gate line slit 160 'after the gate sacrificial layer 122' of the first stacked structure 120 'is replaced with the first gate layer 122 via the gate line slit 160', referring to fig. 11C. To this end, the first dielectric layers 121 and the first gate layers 122 alternately stacked constitute a first stacked structure 120.
In some embodiments, step S101 or S101' may further include forming a dummy channel structure 190 penetrating the first stacked structure 120.
The gate line slit structure divides the plurality of first storage channel structures into one block region. In some embodiments, forming the stacked structure further includes forming a top select gate tangent line extending through the top select gate, the top select gate tangent line dividing the block area into a plurality of finger areas F, and thus the top select gate (described below) of each finger area F can be individually controlled. Wherein the top select gate tangent line extends along the first direction and divides the top select gate into a plurality of regions (finger storage regions F) insulated from each other, a plurality of the top select gate contact structures and a plurality of the storage channel structures being located in each of the regions.
S2, forming a top selection gate contact structure between adjacent storage channel structures。
Referring to fig. 9, in step S2, forming a top select gate contact structure may include, but is not limited to: forming an insulating layer 200 on the second stack structure 140; and forming a top select gate contact structure 110 penetrating the insulating layer 200 and portions of the second stack structure 140 and stopping in one second gate layer 142 at a plurality of preset locations between adjacent second memory channel structures 150 in the core region CA (refer to fig. 5). In some embodiments, the top select gate contact structure 110 may also be formed at the step region SS. In some embodiments, step S2 may further include forming a contact structure 201 that penetrates the insulating layer 200 and is in electrical contact with the second channel plug 154 or the second channel layer 152.
And S3, forming an interconnection structure of the top selection gate contact structure.
Referring again to fig. 6, in step S3, forming an interconnect structure may include, but is not limited to, forming an interconnect layer 210 of the interconnect structure 180 including the top select gate contact structure 110 on the insulating layer 200. In some embodiments, interconnect layer 210 may include contacts 202 connected with contact structures 201 and an insulating material that electrically isolates interconnect structures 180 from contacts 202.
Table 1 shows the relationship between the number N of top select gate contact structures located in the same finger area F and the loss length L (μm) and the effective driving length DL of the memory region according to some embodiments of the present application.
| N | L | DL |
| 3 | 0 | 1L 0 |
| 5 | 0.6 | 1/2L 0 |
| 9 | 1.8 | 1/ |
| 17 | 4.2 | 1/ |
| 33 | 9 | 1/16L 0 |
Referring to table 1, if the same storage region F includes three top select gate contact structures spaced apart by the same distance along the Y-axis direction (refer to fig. 5) (N ═ 3), it is considered that the loss length L is 0 and the effective driving length DL is 1L 0 Then, the case of N being 5 corresponds to a loss of two more memory areas of unit length (0.3 μm) (L being 0.6 μm) compared to the case of N being 3, but the effective drive length DL can be reduced to 1/2L 0 . By analogy, the case of N being 9 corresponds to a loss of 6 unit length (0.3 μm) more storage area (L being 1.8 μm) than the case of N being 3, but the effective drive length DL can be reduced to 1/4L 0 . It should be understood that the data listed in table 1 are merely examples and are merely used to illustrate the effect that providing a plurality of top select gate contact structures in the core area CA may reduce the effective driving length.
According to the three-dimensional memory and the preparation method thereof, the top selection gate contact structure is also arranged in the core region, so that the effective driving length of the top selection gate can be effectively reduced, the switching rate of the top selection gate is increased, and the memory performance is improved.
It should be understood that although the three-dimensional memory device including two sub-stack structures is illustrated in fig. 9A to 9D and fig. 11A to 11C, the concept of adding a top select gate contact structure in the core region to reduce the effective driving length of the memory device of the present application may be applied to any three-dimensional memory device.
Fig. 13A and 13B are schematic structural diagrams of a storage system according to an exemplary embodiment of the present application. As shown in fig. 13A and 13B, the storage system 500 includes a three-dimensional memory 510 and a controller 520. The three-dimensional memory 510 is the three-dimensional memory 100 as mentioned in the above embodiments. The controller 520 is electrically connected to the three-dimensional memory 510 for controlling the three-dimensional memory 510.
In the example shown in fig. 13A, the controller 520 and the single three-dimensional memory 510 may be integrated into a memory card. The memory card may include a PC card (PCMCIA, personal computer memory card international association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), and the like. The memory card may also include a memory card connector 530 that couples the memory card with a host (not shown).
In another example as shown in fig. 13B, the controller 520 and the plurality of three-dimensional memories 510 may be integrated into a Solid State Drive (SSD). The solid state drive may also include an SSD connector 530 that couples the solid state drive with a host (not shown). In some embodiments, the storage capacity and/or operating speed of the solid state drive is higher than that of the memory card shown in fig. 13A.
The above description is only an embodiment of the present application and an illustration of the technical principles applied. It will be appreciated by a person skilled in the art that the scope of protection covered by the present application is not limited to the embodiments with a specific combination of the features described above, but also covers other embodiments with any combination of the features described above or their equivalents without departing from the technical idea. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.
Claims (20)
1. A three-dimensional memory, comprising:
a stacked structure formed on a substrate, the stacked structure including a top select gate;
a plurality of storage channel structures penetrating the stacked structure and extending to the substrate; and
the top selection gate contact structure is positioned between two adjacent storage channel structures in the first direction, extends to the top selection gate electrode in a penetrating manner and is electrically connected with the top selection gate electrode;
wherein the first direction is an extending direction of the substrate.
2. The three-dimensional memory of claim 1, wherein: the laminated structure has a core region and a step region;
the plurality of top selection gate contact structures are positioned in the core area;
alternatively, a plurality of the top select gate contact structures are located in the core region and the step region.
3. The three-dimensional memory according to claim 1 or 2, further comprising:
a top select gate tangent line penetrating the top select gate and extending in the first direction to divide the top select gate into a plurality of regions insulated from each other;
a plurality of the top select gate contact structures and a plurality of the storage channel structures are located in each of the regions.
4. The three-dimensional memory of claim 3, wherein:
the stacked structure comprises gate layers and dielectric layers which are alternately stacked;
the top select gate tangent line passes through at least one of the gate layers to which the top select gate contact structure extends;
wherein the at least one of the gate layers constitutes the top select gate.
5. The three-dimensional memory of claim 3, wherein:
the stacked structure comprises a first stacked structure and a second stacked structure, wherein the first stacked structure and the second stacked structure respectively comprise gate layers and dielectric layers which are alternately stacked;
the memory channel structure comprises a first memory channel structure and a second memory channel structure respectively penetrating through the first laminated structure and the second laminated structure, and a first channel layer of the first memory channel structure is electrically communicated with a second channel layer of the second memory channel structure;
the top select gate tangent line passes through at least one of the gate layers of the second stacked structure, the top select gate contact structure extends to the at least one of the gate layers of the second stacked structure;
wherein the at least one of the gate layers of the second stack structure constitutes the top select gate.
6. The three-dimensional memory of claim 3, wherein:
the stacked structure comprises a first stacked structure including first gate layers and first dielectric layers which are alternately stacked, and a second stacked structure including second gate layers and second dielectric layers which are stacked
The memory channel structure comprises a first memory channel structure and a second memory channel structure respectively penetrating through the first laminated structure and the second laminated structure, and a first channel layer of the first memory channel structure is electrically communicated with a second channel layer of the second memory channel structure;
the top selection gate tangent line penetrates through the second laminated structure, and the top selection gate contact structure extends to the second gate layer;
wherein the second gate layer constitutes the top select gate.
7. The three-dimensional memory of claim 6, wherein:
the material of the first gate layer is different from the material of the second gate layer.
8. The three-dimensional memory of claim 7, wherein:
the first gate layer comprises a metal conductive material and the second gate layer comprises doped polysilicon.
9. The three-dimensional memory of claim 6, wherein a radial dimension of the second storage channel structure is smaller than a radial dimension of the first storage channel structure.
10. The three-dimensional memory of claim 3, wherein at least a portion of the top select gate tangent is wavy in the first direction.
11. The three-dimensional memory according to claim 1 or 2, further comprising:
and the interconnection structure is electrically connected with the top selection gate contact structure and is used for carrying out signal transmission with an external control circuit.
12. The three-dimensional memory of claim 1 or 2, further comprising a dummy channel structure extending through a portion of the stack structure and to the substrate at a location corresponding to the top select gate contact structure.
13. A method for preparing a three-dimensional memory comprises the following steps:
forming a stacked structure including a top select gate and a storage channel structure on a substrate; and
forming a top select gate contact structure between adjacent memory channel structures in a first direction, the top select gate contact structure extending to and in electrical contact with the top select gate;
wherein the first direction is an extending direction of the substrate.
14. The production method according to claim 13, wherein the laminated structure includes a first laminated structure and a second laminated structure;
wherein the step of forming the stack structure including the top select gate and the storage channel structure on a substrate comprises:
forming the first stacked structure including a first storage channel structure on the substrate, the first stacked structure including first dielectric layers and first gate layers alternately stacked; and
forming the second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto;
wherein the channel layer of the first storage channel structure is electrically connected to the channel layer of the second storage channel structure, the at least one second gate layer constituting the top select gate.
15. The production method according to claim 13, wherein the laminated structure includes a first laminated structure and a second laminated structure;
wherein the step of forming the stack structure including the top select gate and the storage channel structure on a substrate comprises:
forming a first stacked structure including a first storage channel structure on the substrate, the first stacked structure including alternately stacked first dielectric layers and gate sacrificial layers;
forming a second stacked structure including a second storage channel structure on the first stacked structure, the second stacked structure including at least one second gate layer and at least two second dielectric layers adjacent thereto; and
replacing a gate sacrificial layer in the first stacked structure with a first gate layer;
wherein the first dielectric layers and the first gate layers alternately stacked constitute the first stack structure, the channel layer of the first storage channel structure is electrically connected with the channel layer of the second storage channel structure, and the at least one second gate layer constitutes the top select gate.
16. The production method according to claim 14 or 15, further comprising:
forming a top select gate tangent line penetrating the top select gate, wherein the top select gate tangent line extends in the first direction and divides the top select gate into a plurality of regions insulated from each other, and a plurality of the top select gate contact structures and a plurality of the storage channel structures are located in each of the regions.
17. The three-dimensional memory of claim 14 or 15, wherein:
the material of the first gate layer is different from the material of the second gate layer.
18. The three-dimensional memory of claim 17, wherein:
the first gate layer comprises a metal conductive material and the second gate layer comprises doped polysilicon.
19. The method of manufacturing of claim 13, further comprising:
forming an interconnect structure in electrical contact with the top select gate contact structure for signal transmission with an external control circuit.
20. A storage system, comprising:
the three-dimensional memory of any one of claims 1-12; and
and the controller is electrically connected with the three-dimensional memory and is used for controlling the three-dimensional memory.
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| WO2024077595A1 (en) * | 2022-10-14 | 2024-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor, and memory system |
| WO2024077592A1 (en) * | 2022-10-14 | 2024-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor, and memory system |
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| WO2024077595A1 (en) * | 2022-10-14 | 2024-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor, and memory system |
| WO2024077592A1 (en) * | 2022-10-14 | 2024-04-18 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method therefor, and memory system |
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