KR101773044B1 - Nonvolatile memory device, memory module and system having the same, and method of fabricating the same - Google Patents

Abstract

A nonvolatile memory device improved in striation phenomenon and a method of manufacturing the same are provided. A channel layer extending from the substrate; a gate conductive layer surrounding the channel layer and having one end having a dog bone shape; a gate insulating layer positioned between the channel layer and the gate conductive layer; And a first insulating layer located above and below the gate conductive layer while being spaced apart from the gate conductive layer.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile memory device, a method of fabricating the same, and a memory module and system including the same.

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a vertical nonvolatile memory device having improved channel layer striation, a method of manufacturing the same, a memory module and a system .

Recently, in forming a nonvolatile memory device, methods for improving the degree of integration by stacking cell transistors included in each unit chip in the vertical direction have been studied. Particularly, in the case of a flash memory device, cell transistors can be vertically stacked to highly integrate the devices.

SUMMARY OF THE INVENTION The present invention provides a nonvolatile memory device having improved channel layer striation and a method of manufacturing the same.

A nonvolatile memory device according to an aspect of the present invention is provided. The nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer positioned between the channel layer and the gate conductive layer, The gate insulating layer may extend between the gate conductive layer and the first insulating layer. The gate insulating layer may extend between the gate conductive layer and the first insulating layer.

According to an example of the nonvolatile memory device, the nonvolatile memory device may further include a second insulation layer directly contacting the upper portion of the channel layer. In this case, the second insulating layer may be interposed between the first insulating layer and the channel layer.

According to another example of the nonvolatile memory device, the thickness of the first insulating layer may be greater than the thickness of the second insulating layer in a direction perpendicular to the substrate.

According to another example of the nonvolatile memory device, the second insulating layer may surround the channel layer.

According to another example of the nonvolatile memory device, the nonvolatile memory element includes a separating insulating layer that protrudes from the substrate, and a supporting member that is extended from the substrate and is located between the channel layer and the separating insulating layer. And an insulating layer for the insulating layer.

According to another example of the nonvolatile memory device, the gate insulating layer may be further formed between the first insulating layer and the channel layer.

According to another example of the non-volatile memory device, the non-volatile memory device may further include an air gap positioned between the first insulating layer and the channel layer.

According to another example of the nonvolatile memory device, the gate insulating layer may include a tunneling insulating layer, a charge storage layer, and a blocking insulating layer that are sequentially stacked on the sidewalls of the channel layer.

According to another example of the non-volatile memory device, the channel layer may be a pillar-type channel layer. Meanwhile, the channel layer may be a macaroni-type channel layer. In this case, the non-volatile memory device may further include an insulating layer filling the inside of the macrononi-type channel layer.

According to another example of the nonvolatile memory device, the channel layer may include a lower channel layer tapered in the direction of the substrate and an upper channel layer tapered in the direction of the lower channel layer. Further, the lower channel layer and the upper channel layer may be a single body continuously connected.

A nonvolatile memory device according to another aspect of the present invention is provided. The nonvolatile memory device includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer positioned between the channel layer and the gate conductive layer, A first insulating layer located above and below the gate conductive layer, a separating insulating layer extending from the substrate and connected to the plurality of first insulating layers, and a second insulating layer protruding from the substrate, And a supporting insulating layer disposed between the insulating layers.

According to an example of the nonvolatile memory device, the gate insulating layer may extend between the gate conductive layer and the first insulating layer.

According to another example of the nonvolatile memory device, the device further comprises a gate insulating layer formed between the gate insulating layer and the channel layer, and the gate insulating layer is extended between the gate conductive layer and the first insulating layer .

According to another example of the nonvolatile memory device, the separating insulating layer may be located between the channel layer and the supporting insulating layer.

According to another example of the nonvolatile memory device, the channel layers viewed in a plan view may be arranged in a zigzag manner. In this case, the supporting insulating layers viewed in a plan view may be arranged in a reverse-zigzag manner in a space between the channel layer and the separating insulating layer.

A memory module according to an aspect of the present invention is provided. Wherein the memory module comprises a non-volatile memory element, the non-volatile memory element comprising: a substrate; a channel layer protruding from the substrate; a gate conductive layer surrounding the channel layer; And a first insulating layer located above and below the gate conductive layer, the gate insulating layer being spaced apart from the channel layer, the gate insulating layer extending between the gate conductive layer and the first insulating layer .

A system according to an aspect of the present invention is provided. The system is a system that transmits data to the outside or receives data from the outside. The system includes a non-volatile memory device, a memory component configured to store the data, an input / output device configured to input or output the data, and a controller configured to control the memory component and the input / output device . The nonvolatile memory device also includes a substrate, a channel layer protruding from the substrate, a gate conductive layer surrounding the channel layer, a gate insulating layer positioned between the channel layer and the gate conductive layer, And a first insulating layer located above and below the gate conductive layer, the gate insulating layer extending between the gate conductive layer and the first insulating layer.

According to one example of the system, the system may be a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player such as a digital music player, a memory card, navigation, a portable multimedia player (PMP), a solid state disk (SSD), or household appliances.

A method of manufacturing a nonvolatile memory device according to an aspect of the present invention is provided. The method for fabricating a nonvolatile memory device includes: alternately laminating a plurality of sacrificial insulating layers and a plurality of first insulating layers on a substrate; etching the sacrificial insulating layers and the first insulating layers to form a plurality of channels Forming sacrificial spacers on the sidewalls of each of the channel holes, forming a channel layer in contact with the sacrificial spacers, etching the sacrificial insulating layers and the first insulating layers to form a plurality of sacrificial spacers Etching the sacrificial insulation layers and the sacrificial spacers such that the sidewalls of the channel layers are exposed. Forming a gate insulating layer on the sidewalls of the channel layer, and forming a gate conductive layer on the gate insulating layer.

According to an example of the method of manufacturing the nonvolatile memory device, the method of manufacturing the nonvolatile memory device may further include, between the step of forming the channel layer and the step of etching the upper part of the sacrificial spacers, Forming a dummy hole by etching the first insulating layers, and forming an insulating layer for supporting the dummy hole.

According to another example of the method for fabricating the nonvolatile memory device, the method for fabricating the nonvolatile memory device may further include forming a second insulating layer on the channel layer after forming the channel layer .

According to another example of the method of manufacturing the nonvolatile memory device, the step of forming the second insulating layer includes etching the upper portion of the sacrificial spacers so that the upper sidewall of the channel layer is exposed, And a second insulating layer in contact with the top sidewalls of the channel layer.

A nonvolatile memory device according to another aspect of the present invention is provided. The nonvolatile memory device includes a substrate, lower gate conductive layers stacked on the substrate, upper gate conductive layers stacked on the lower gate conductive layers, a channel layer passing through the lower and upper gate conductive layers, A gate insulating layer interposed between the lower and upper gate conductive layers and the channel layer, and a mask layer formed between the lower gate conductive layers and the upper gate conductive layers.

According to an example of the non-volatile memory device, the mask layer may include silicon (Si) or silicon germanium (SiGe).

According to another example of the non-volatile memory device, the non-volatile memory device may further include a stopping layer directly above the substrate. In this case, the stop layer may comprise aluminum oxide (Al2O3), tantalum nitride (TaN), or silicon carbide (SiC).

According to another example of the nonvolatile memory device, the channel layer may include a lower channel layer tapered in the direction of the substrate and an upper channel layer tapered in the direction of the lower channel layer. In this case, the lower channel layer and the upper channel layer may be a single body continuously connected.

A method of manufacturing a nonvolatile memory device according to another aspect of the present invention is provided. The method of fabricating the nonvolatile memory device includes: alternately laminating a plurality of lower sacrificial insulating layers and a plurality of lower insulating layers on a substrate; etching the lower sacrificial insulating layers and the lower insulating layers to form at least one Forming a lower channel hole, closing the lower channel hole, alternately laminating a plurality of upper sacrificial insulating layers and a plurality of upper insulating layers on the lower channel hole, Forming at least one lower upper channel hole by etching layers and the upper insulating layers, opening the lower channel hole, and etching the lower channel layer and the lower channel layer to fill the lower channel hole and the upper channel hole, respectively. And forming an upper channel layer at the same time.

According to an example of the method of fabricating the nonvolatile memory device, the step of closing the lower channel hole may include forming a closed insulating layer filling the lower channel hole.

According to another example of the method of manufacturing the nonvolatile memory device, the step of closing the lower channel hole may include forming a sacrificial spacer on the sidewall of the lower channel hole before forming the closed insulating layer filling the lower channel hole, And forming the second electrode layer. In this case, the step of opening the lower channel hole may include exposing the substrate by etching the insulating layer filled in the lower channel hole.

According to another example of the manufacturing method of the nonvolatile memory device, the step of closing the lower channel hole may include a step of selectively growing the lower channel hole using a selective growth process of a mask layer formed on an upper sidewall of the lower channel hole, And closing the lower channel hole.

According to another example of the method of manufacturing the nonvolatile memory device, an air gap may be formed between the mask layer and the substrate by closing the lower channel hole.

According to another embodiment of the nonvolatile memory device, the mask layer includes silicon (Si) or silicon germanium (SiGe), and the lower channel hole is formed by selective epitaxial growth of the mask layer ) Process. ≪ / RTI >

According to another example of the method of fabricating the non-volatile memory device, the step of closing the lower channel hole may further include oxidizing the mask layer.

According to another example of the method of manufacturing the nonvolatile memory device, the step of opening the lower channel hole may include exposing the substrate by etching the mask layer.

According to another example of the method of manufacturing the non-volatile memory device, the non-volatile memory device further includes a stopping layer directly on the substrate, and the stop layer is formed on the substrate during the selective epitaxial growth process. To prevent growth.

Since the channel layer is formed in the sacrificial layer, the non-volatile memory device and the method of fabricating the same according to the embodiments of the present invention can prevent the channel layer formed by the process using the double layer from being wrinkled.

The nonvolatile memory device and the method of fabricating the same according to embodiments of the present invention are not limited to a macaroni type but a pillar type channel layer is formed. Therefore, a couple between the control gate and the floating gate in the word line The coupling ratio can be increased, and thus the program / erase characteristic can be improved.

Further, in the nonvolatile memory device and the manufacturing method thereof according to the embodiments of the present invention, a high degree of integration of the memory device can be achieved by stacking a plurality of channel layers. Further, since the integrated channel layer is formed, the electrical characteristics between the memory cells can be improved.

1 is a plan view schematically illustrating a nonvolatile memory device according to some embodiments of the present invention.
2 is a cross-sectional view taken along the line A-A 'of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line B-B' of FIG.
4 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present invention.
FIGS. 5 to 14A and 14B are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to some embodiments of the present invention.
FIGS. 15 to 23 are cross-sectional views showing a method of manufacturing a non-volatile memory device according to another embodiment of the present invention.
FIGS. 23 to 29 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to another embodiment of the present invention.
30 to 47 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to embodiments of the present invention.
FIGS. 48 to 61 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.
62 to 73 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to still another embodiment of the present invention.
74 is an equivalent circuit diagram of a memory cell array according to an embodiment of a nonvolatile memory device according to the technical idea of the present invention.
75 is a cross-sectional view showing a nonvolatile memory device according to the technical idea of the present invention.
76 is a schematic diagram showing a card including a nonvolatile memory element according to embodiments of the present invention;
77 is a schematic diagram showing a system including a nonvolatile memory device according to embodiments of the present invention;

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the following embodiments may be modified in various other forms, The present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be more thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an," and "the" include plural forms unless the context clearly dictates otherwise. Also, " comprise " and / or " comprising " when used herein should be interpreted as specifying the presence of stated shapes, numbers, steps, operations, elements, elements, and / And does not preclude the presence or addition of one or more other features, integers, operations, elements, elements, and / or groups. As used herein, the term " and / or " includes any and all combinations of one or more of the listed items.

Although the terms first, second, etc. are used herein to describe various elements, regions and / or regions, it should be understood that these elements, components, regions, layers and / Do. These terms are not intended to be in any particular order, up or down, or top-down, and are used only to distinguish one member, region or region from another member, region or region. Thus, the first member, region or region described below may refer to a second member, region or region without departing from the teachings of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings schematically showing ideal embodiments of the present invention. In the figures, for example, variations in the shape shown may be expected, depending on manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions illustrated herein, including, for example, variations in shape resulting from manufacturing.

1 is a plan view schematically illustrating a nonvolatile memory device according to some embodiments of the present invention. 2 is a cross-sectional view taken along the line A-A 'of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line B-B' of FIG.

1 to 3, a non-volatile memory device includes a substrate 50, channel layers 110, supporting insulating layers 120, gate conductive layers 130, gate insulating layers 140, The first insulating layer 160, the second insulating layer 170, and the bit line conductive layer 180. The first insulating layer 160 may be formed of an insulating material.

Referring to FIG. 1, the channel layers 110 may be arranged in a zigzag manner. In addition, zigzagged channel layers 110 may surround the supporting insulating layer 120. More specifically, the channel layers 110 and the supporting insulating layers 120 may be disposed between the separating insulating layers 200, and the channel layers 110 between the separating insulating layers 200 It can be arranged in a zigzag manner. The supporting insulating layer 120 may be disposed in an empty space between the channel layer 110 and the separating insulating layer 200 arranged in a zigzag pattern. That is, each of the supporting insulating layers 120 may be surrounded by the separating insulating layer 200 and the channel layers 110, so that the insulating layers 120 for supporting between the insulating layers 200 for separation, Can be arranged in reverse-zigzag.

2 and 3, the substrate 50 may comprise a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI oxide semiconductor. For example, a Group IV semiconductor may comprise silicon, germanium or silicon-germanium. The substrate 50 may include a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, and / or a semiconductor-on-insulator .

The channel layer 110 may extend from the substrate 50 in a vertical direction. For example, the channel layers 110 may be formed of an epitaxial layer of polycrystalline or single crystal structure. In addition, the channel layers 110 may comprise a silicon material, or a silicon-germanium material. Although the channel layer 110 is shown as a pillar-type channel layer in the drawing, the present invention is not limited thereto. In other words, the channel layer 110 may be a macaroni-type channel layer. In this case, the nonvolatile memory device may further include a pillar insulating layer (not shown) filling the inside of the macaroni-type channel layer. The structure of the macron-type channel layer will be described later with reference to FIG.

The gate conductive layers 130 may be stacked on the side surfaces of the channel layer 110. More specifically, the first insulating layer 160 and the gate conductive layers 130 may be alternately stacked on the side of the channel layer 110, and may be a structure surrounding the channel. The gate conductive layers 130 may be formed of polysilicon, aluminum, ruthenium, tantalum nitride (TaN), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), hafnium nitride HfN) and tungsten silicide (WSi), or a combination thereof.

The first insulating layer 160 is spaced apart from the channel layer 110 and may be located above and below the gate conductive layer 130. More specifically, the first insulating layer 160 may be located between the gate conductive layers 130 and on the gate conductive layers 130. [ In addition, the thickness of the first insulating layer 160 at the uppermost one of the first insulating layers 160 may be greater than the thickness of the remaining first insulating layers. Further, the thickness of the first insulating layer 160, which is the lowest one of the first insulating layers 160, may be greater than the thickness of the remaining first insulating layers 160.

The second insulating layer 170 may be in direct contact with the top of the channel layer 110. More specifically, the second insulating layer 170 may be directly interposed between the first insulating layer 160 and the channel layer 110. For example, the second insulating layer 170 may be positioned between the first insulating layer 160 and the channel layer 110 of the first insulating layers 160. The second insulating layer 170 may be positioned between the gate insulating layer 140 and the bit line conductive layer 180. The first insulating layer 160 and the second insulating layer 170 may have substantially the same etch selectivity. The thickness of the first insulating layer 160 may be greater than the thickness of the second insulating layer 170. More specifically, in a direction perpendicular to the substrate 50, the thickness of the second insulating layer 170 may be smaller than the thickness of the first insulating layer 160. 1, the second insulating layer 170 may have a ring structure that surrounds the channel layer 110. In this case,

The gate insulating layers 140 may be positioned between the gate conductive layers 130 and the channel layer 110. More specifically, each of the gate insulating layers 140 may be formed to surround the gate conductive layer 130. Each of the gate insulating layers 140 may be located between the gate conductive layer 130 and the first insulating layer 160 and between the gate conductive layers 130 and the channel layer 110. [ In addition, the gate insulating layer 140 may be formed to surround the side surface of the channel layer 110.

The gate insulating layer 140 may include a plurality of gate insulating layers 142, 144, and 146 stacked on the side of the channel layer 110. For example, the gate insulating layer 140 may have a structure in which a tunneling insulating layer 142, a charge storage layer 144, and a blocking insulating layer 146 are sequentially stacked from the channel layer 110. The tunneling insulating layer 142, the charge storage layer 144, and the blocking insulating layer 146 constitute a storage medium.

The tunneling insulating layer 142, the charge storage layer 144 and the blocking insulating layer 146 are each formed of a silicon oxide layer (SiO ₂ ), a silicon oxynitride layer (SiON), a silicon nitride layer (Si ₃ N ₄ ) (Al ₂ O ₃ ), an aluminum nitride layer (AlN), a hafnium oxide layer (HfO ₂ ), a hafnium silicon oxide layer (HfSiO), a hafnium silicon oxynitride layer (HfSiON), a hafnium oxynitride layer (HfON) ), zirconium oxide (ZrO _2), tantalum oxide (Ta ₂ O _3), hafnium tantalum oxide (HfTa _x O _y), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), lanthanum hafnium oxide (LaHfO) and hafnium aluminum And an oxide layer (HfAlO), or a combination thereof. For example, the tunneling insulating layer 142 includes a silicon oxide layer, the charge storage layer 144 includes a silicon nitride layer, and the blocking insulating layer 146 may include a metal oxide layer.

In the direction perpendicular to the substrate 50, the air gaps 150 are formed between the gate conductive layers 130 and between the gate conductive layers 130 and 130, 170). These air gaps 150 can be formed by depositing a gate insulating layer 140 having poor step coverage at the time of manufacturing the non-volatile memory device. In a direction parallel to the substrate 50, air gaps 150 may be located between the first insulating layers 160 and the channel layer 110. A gate insulating layer 140 may be formed between the air gaps 150 and the channel layer 110 and / or between the air gaps 150 and the first insulating layer 160.

The separating insulating layer 200 is located between the channel layers 110 and may extend and extend in a direction perpendicular to the substrate 50. The separating insulating layer 200 may be connected to the first insulating layer 160. The bit line conductive layer 180 may be formed on the channel layer 110 and extend in a direction parallel to the substrate 50. The bit line conductive layer 180 may be in contact with the first insulating layer 160, the second insulating layer 170, and the isolation insulating layer 200.

The supporting insulating layer 120 is located between the channel layer 110 and the insulating layer 200 for separation and may extend and extend in a direction perpendicular to the substrate 50. The supporting insulating layer 120 may be connected to the first insulating layer 160. More specifically, only the first insulating layer 160 may be interposed between the supporting insulating layer 120 and the separating insulating layer 200. The bit line conductive layer 180 may be in contact with the first insulating layer 160, the second insulating layer 170, the insulating layer 200 for separation, and the insulating layer 120 for supporting. The supporting insulating layer 120 and the first insulating layer 160 may have substantially the same etch selectivity.

4 is a cross-sectional view schematically illustrating a nonvolatile memory device according to another embodiment of the present invention. The nonvolatile memory device according to this embodiment is a modification of the nonvolatile memory device of FIG. 2 described above. The following description will not be repeated.

Referring to FIG. 4, the gate insulating layer 140 may extend in a direction perpendicular to the substrate 50 between the second insulating layer 170 and the substrate 50. The gate insulating layer 140 may be formed not only between the gate conductor 130 and the channel layer 110 but also between the first insulating layers 160 and the channel layer 110. [ More specifically, the gate insulating layer 140 may be formed in a ring structure surrounding the channel layer 110. [

The non-volatile memory device may further include a gate isolation insulating layer 145 surrounding the gate conductive layer 130. The gate insulating layer 145 may be formed between the gate conductive layer 130 and the channel layer 110. The gate insulating layer 145 may extend between the gate conductive layer 130 and the first insulating layer 160.

The gate insulating layer 145 may include aluminum oxide (Al ₂ O ₃ ) or titanium nitride (TiN). Alternatively, the storage medium may be constituted by the gate insulating layer 140 and the gate insulating layer. In addition, an air gap 150 may be formed between the first insulating layers 160 and the gate insulating layer 140 by the gate insulating layer 145.

FIGS. 5 to 14A and 14B are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to some embodiments of the present invention. A manufacturing method of the non-volatile memory device according to these embodiments shows a manufacturing process for forming the non-volatile memory device shown in Fig. Therefore, the description overlapping with the description of FIG. 2 will be omitted.

Referring to FIG. 5, a plurality of sacrificial insulating layers 125 and a plurality of first insulating layers 160 are alternately stacked on a substrate 50. For example, the sacrificial insulating layers 125 may comprise silicon nitride, in which case the first insulating layers 160 may be silicon oxide or silicon so as to have etch selectivity with the sacrificial insulating layers 125 ≪ / RTI > In contrast, the sacrificial insulating layers 125 may comprise silicon germanium, in which case the first insulating layers 160 may comprise silicon oxide or silicon nitride. However, the present invention is not limited thereto, and the sacrificial insulating layers 125 may be formed of any material having an etch selectivity different from that of the first insulating layers 160.

Although not shown in FIG. 5, the thickness of the uppermost sacrificial insulation layer and the lowermost sacrificial insulation layer in the sacrificial insulation layers 125 may be greater than the thickness of the other sacrificial insulation layers 125. 74, the thickness of the uppermost and lowermost sacrificial insulation layers determines the thickness of the gates of the string selection transistor (SST in FIG. 74) and the ground selection transistor (GST in FIG. 74), respectively. Therefore, the uppermost and lowermost sacrificial insulating layers may be formed thicker than other sacrificial insulating layers so that sufficient current can be supplied to the memory cell string.

Thereafter, the sacrificial insulating layers 125 and the first insulating layers 160 are etched to form a plurality of channel holes 105. More specifically, the sacrificial insulating layers 125 and the first insulating layers 160 can be etched using an anisotropic etching process such as a reactive ion etching process. The anisotropic etching process may be performed excessively, and overetching may be performed, and as a result, the substrate 50 may also be partially etched. The channel holes 105 may be formed in a cylindrical shape having a diameter (X1) of 30 nm to 350 nm. In addition, although not shown in the drawing, the channel holes 105 may be formed in a tapered shape in the direction of the substrate.

Referring to FIG. 6, sacrificial spacers 127 are formed on the sidewalls of each of the channel holes 105. The sacrificial spacer 127 surrounds the sidewalls of the channel holes 105 and may be formed of a material having the same etch selectivity as the sacrificial insulating layer 125. In addition, the sacrificial spacer 127 may be formed to a thickness (X2) of 5 nm to 50 nm.

The sacrificial spacer 127 may be formed of the same material as the sacrificial insulating layer 125. For example, the sacrificial spacer 127 and the sacrificial insulating layer 125 may comprise silicon nitride, silicon oxide, silicon carbide, or silicon germanium.

Referring to FIG. 7, a channel layer 110 is formed that contacts sacrificial spacers 127. The channel layer may be formed in the form of a cylindrical or tapered conical column having a diameter (X3) of 20 nm to 150 nm. More specifically, for example, when the channel holes 105 are formed in a tapered shape, the channel holes 105 may be in the form of a conical column having a diameter (X1) of at least 30 nm to at most 350 nm. At this time, the sacrificial spacer 127 may have a thickness (X2) of at least 5 nm to a maximum of 50 nm, and thus the channel layer may be formed in the form of a conical column having a diameter (X3) of at least 20 nm to 150 nm .

The channel layer 110 is formed in a sacrificial spacer 127, which is a single film structure. Therefore, it is possible to prevent the wrinkle phenomenon of the channel layer 110, which may occur in the conventional process in which the channel layer 110 is formed from the double-layer structure.

31, the channel layer 110 is illustrated as a pillar-shaped channel layer, but the channel layer 110 may be a macaroni-type channel layer as described above. In this case, the channel layer 110 in contact with the sacrificial spacer 127 And then forming a pillar insulating layer (not shown) to fill the channel layer 110. [0064]

Referring to FIG. 8, an upper portion of the sacrificial spacer 127 is etched by a first depth to expose sidewalls of the uppermost first insulating layer 160 and the sidewalls of the channel layer 110. In a direction perpendicular to the substrate 50, the first depth may be less than the depth of the uppermost first insulating layer 160.

Referring to FIG. 9, a second insulating layer 170 is formed on the sacrificial spacer 127. More specifically, the second insulating layer 170 is formed to contact the sidewalls of the second insulating layer 170 and the first insulating layer 160 and the sidewalls of the channel layer 110, respectively. The second insulating layer 170 prevents the channel from being collapsed or lifted in a pull back process of etching the sacrificial insulating layer 125 and the sacrificial spacer 127. Accordingly, the second insulating layer 170 may be formed of a material having an etch selectivity with the sacrificial insulating layer 125 and the sacrificial spacer 127.

10, the second insulating layer 170, the sacrificial insulating layers 125, and the first insulating layers 125 and 125 are formed to perform a pullback process of etching the sacrificial insulating layer 125 and the sacrificial spacer 127, (Not shown) are etched to form a plurality of word line recesses 205. In this case, each of the word line recesses 205 is located between the channel layers 110.

11A and 11B, the sacrificial insulating layer 125 and the sacrificial spacer 127 are etched to expose the first insulating layer 160 and the channel layer 110 and the exposed first insulating layer 160, And a gate insulating layer 140 is formed on the channel layer 110.

For example, the first insulating layer 160 and the second insulating layer 170 are silicon oxide films, and the sacrificial insulating layer 125 and the sacrificial spacer 127 are formed on the first and second insulating layers 160 and 170, And a silicon nitride film having an etch selectivity. In this case, the sacrificial insulating layer 125 and the sacrificial spacer 127 made of a silicon nitride film are removed through a phosphoric acid strip process to expose the first insulating layer 160, the second insulating layer 170, and the channel layer 110 .

Then, a gate insulating layer 140 is formed on the exposed first insulating layer 160 and the channel layer 110. As described above, the gate insulating layer may include a tunneling insulating layer 142, a charge storage layer 144, and a blocking insulating layer 146. 11A, when the gate insulating layer 140 having a poor step coverage is deposited, the uppermost gate conductive layer 130 among the plurality of gate conductive layers 130 or the gate conductive layers 130, Air gaps 150 may be formed between the insulating layers 170. On the other hand, as shown in FIG. 11B, when the gate insulating layer 140 having good step coverage is deposited, the air gaps may not be formed. In this case, only the gate insulating layer 140 is interposed between the gate conductive layers 130.

Depending on the relationship between the thickness of the gate insulating layer 140 and the thickness of the sacrificial spacer 127, it can be determined whether or not an air gap is formed. Here, the thickness of the gate insulating layer 140 refers to the thickness of the gate insulating layer 140 deposited above and below the first insulating layer 160. The thickness of the sacrificial spacer 127 may also be defined as the thickness of the sacrificial spacer 127 in which the spacer is stacked on the sacrificial insulating layers 125 and the sidewalls of the first insulating layers 160.

An air gap 150 may be formed between the gate insulating layer 140 when the thickness of the sacrificial spacer 127 is about twice the thickness of the gate insulating layer 140 or less. On the other hand, if the thickness of the sacrificial spacer 127 is about twice the thickness of the gate insulating layer 140, the air gap 150 may not be formed between the gate insulating layers 140. That is, as the formation condition of the air gap 150, not only the deposition conditions of the gate insulating layer 140 such as step coverage but also the thicknesses of the sacrificial spacer 127 and the gate insulating layer 140 should be considered.

Referring to FIG. 12, a gate conductive layer 130 is formed on the gate insulating layer 140. The gate conductive layers 130 formed between the first insulating layers 160 each function as a word line. Referring to FIG. 13, a strip process is performed to remove the electrical connection between the gate conductive layers 130, thereby forming a separating insulating layer 200 filling the word line recess 205.

Referring to FIGS. 14A and 14B, a chemical mechanical polishing (CMP) process is performed to remove an upper portion of the isolation insulating layer 200 and expose the channel layer 110. The bit line conductive layer 180 is formed on the first insulating layer 160, the second insulating layer 170, the channel layer 110, and the insulating layer 200 for isolation. 14A shows a nonvolatile memory element in which air gaps 150 are formed and FIG. 14B shows a case where only air gap 150 is not formed and only a gate insulating layer is interposed between the gate conductive layers 130 Volatile memory device.

FIGS. 15 to 23 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to some embodiments of the present invention. The nonvolatile memory device manufacturing method according to these embodiments shows a manufacturing process for forming the nonvolatile memory device shown in FIG. In addition, the manufacturing method of the non-volatile memory device according to these embodiments may include the manufacturing process of the non-volatile memory device according to Figs. 5 to 14A and 14B. The following description will not be repeated.

Referring to FIG. 15, a plurality of sacrificial insulating layers 125 and a plurality of first insulating layers 160 are alternately stacked on a substrate 50, as described in FIGS. 5 to 7, Forming channel holes 105 and sacrificial spacers 127 and channel layer 110 filling channel holes 105. [

Referring to FIG. 16, the sacrificial insulating layers 125 and the first insulating layers 160 are etched to form dummy holes, and the supporting insulating layer 120 filling the dummy holes is formed. The supporting insulating layer 120 may be a material having an etch selectivity different from that of the sacrificial insulating layer 125 and the sacrificial spacer 127.

Referring to FIG. 17, as described in FIGS. 8 and 9, the sidewalls of the uppermost first insulating layer 160 and the sidewalls of the channel layer 110 of the first insulating layers 160 are exposed. A second insulating layer 170 is formed which is in contact with the sidewalls of the uppermost first insulating layer 160 and the sidewalls of the channel layer 110.

18, the second insulating layer 170, the sacrificial insulating layers 125, and the first insulating layers 125 are formed to perform a pullback process of etching the sacrificial insulating layer 125 and the sacrificial spacer 127. [ The word line recesses 205 are formed by etching the word lines 160. In this case, the word line recess 205 is located between the channel layer 110 and the supporting insulating layer 120.

Referring to FIG. 19, a pull back process is performed to etch the sacrificial insulating layer 125 and the sacrificial spacer 127. As described above, the supporting insulating layer 120 serves to prevent sinking of the first insulating layer 160 after the sacrificial insulating layer 125 is etched.

Referring to FIG. 20, a gate insulating layer 140 is formed on the exposed first insulating layer 160 and the channel layer 110, as described with reference to FIG. 11A. In this case, by depositing the gate insulating layer 140 having a poor step coverage, the uppermost gate conductive layer 130 and the uppermost gate conductive layer 130 among the plurality of gate conductive layers 130, 2 air gaps 150 may be formed between the insulating layers 170 as described above. Although not shown in the drawing, a structure in which an air gap is not formed as shown in FIG. 11B may be formed by depositing a gate insulating layer 140 having good step coverage.

Referring to FIGS. 21 and 22, a gate conductive layer 130 is formed on the gate insulating layer 140 and a separating insulating layer 130 filling the word line recess 205, as described in FIGS. 12 to 14A, (200). The channel layer 110 is exposed by removing the upper part of the separation insulating layer 200 and the second insulation layer 170 and then the first insulation layer 160, the second insulation layer 170, The bit line conductive layer 180 is formed on the insulating layer 110, the supporting insulating layer 120, and the insulating layer 200 for separation. Although not shown in the drawing, a structure in which an air gap is not formed as shown in FIG. 14B may be formed by depositing a gate insulating layer 140 having good step coverage.

FIGS. 23 to 29 are cross-sectional views illustrating a method of manufacturing a non-volatile memory device according to another embodiment of the present invention. The manufacturing method of the non-volatile memory device according to these embodiments shows a manufacturing process for forming the non-volatile memory device shown in Fig. The manufacturing method of the non-volatile memory device according to these embodiments may be a modification of the manufacturing process of the non-volatile memory device according to Figs. 5 to 14A and 14B. The following description will not be repeated.

Referring to FIG. 23, a plurality of sacrificial insulating layers 125 and a plurality of first insulating layers 160 are alternately stacked on a substrate 50, and a plurality of channel holes 105 are formed. Sacrificial spacers 127 and gate insulating layers 140 are then formed to fill each of the channel holes 105. More specifically, first, a sacrificial spacer 127 filling the channel hole 105 is formed, and a gate insulating layer 140 is formed in contact with the sacrificial spacer 127. Thereafter, a channel layer 110 filling the gate insulating layer 140 is formed.

24, a sacrificial spacer 127 and an upper portion of the gate insulating layer are formed to expose sidewalls of the uppermost first insulating layer 160 and the sidewalls of the channel layer 110 of the first insulating layers 160 And a second insulating layer 170 is formed in contact with the sidewalls of the uppermost first insulating layer 160 and the sidewalls of the channel layer 110.

25, a sacrificial insulating layer 125 and sacrificial spacers 127 are etched to form a second insulating layer 170, sacrificial insulating layers 125, and first insulating layers < RTI ID = 0.0 > The word line recesses 205 are formed by etching the word lines 160.

Referring to FIG. 26, a sacrificial insulating layer 125 and a sacrificial spacer 127 are etched to perform a full-back process. Although not shown in the drawing, the first insulating layer 160 can be supported by the supporting insulating layer by forming the supporting insulating layer 120 (see FIG. 3) between the word line recess and the channel layer 110 Therefore, it is possible to prevent the first insulating layer 160 from sinking.

27, a gate insulating layer 145 is formed on the exposed first insulating layer 160 and the channel layer 110 and a gate conductive layer 130 is formed on the gate insulating layer 145 . In this case, the uppermost gate insulating layer 145 among the gate insulating layers 145 or the gate insulating layers 145 may be deposited by depositing a gate insulating layer 145 having a poor step coverage, The air gap 150 may be formed between the first insulating layer 170 and the second insulating layer 170. Although not shown in the drawing, the gate insulation layer 145 having a good step coverage can be deposited to form the gate insulation layer 145 between the gate insulation layers 145 or the gate insulation insulation layer 145 145 and the second insulating layer 170 may be formed without forming an air gap.

28 and 29, a separating insulating layer 200 filling the word line recess 205 is formed and a part of the upper portion of the separating insulating layer 200 and the second insulating layer 170 is removed The channel layer 110 is exposed and then the bit line conductive layer 180 is formed on the first insulating layer 160, the second insulating layer 170, the channel layer 110, and the separating insulating layer 200 .

30 to 47 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to embodiments of the present invention. The manufacturing method of the non-volatile memory device according to these embodiments is a modification of the manufacturing process of the non-volatile memory device according to Figs. 5 to 14A and 14B. The following description will not be repeated.

Referring to FIG. 30, a lower mold stack 190a for forming a lower channel layer (not shown) is formed. The lower mold stack 190a may include a lower sacrificial insulating layer 125a and a lower insulating layer 160a. The lower sacrificial insulating layer 125a and the lower insulating layer 160a may be alternately and repeatedly laminated. The lower sacrificial insulating layer 125a and the lower insulating layer 160a may be materials having an etch selectivity ratio with each other as described above.

Referring to FIG. 31, lower channel holes 105a penetrating the lower mold stack 190a are formed. The lower channel holes 105a may be two-dimensionally arranged to expose the substrate 50. [ The lower channel holes 105a may be formed in a tapered shape in the direction of the substrate 50. That is, the lower channel holes 105a may be formed to have a narrower width at the lower portion than at the upper portion thereof.

In the drawing, the lower channel holes 105a are formed in the form of a rectangular column, but it is obvious that they may be formed in the form of a cylinder or a conical column as shown in FIG. Also, in the drawing, the lower channel holes 105a are arranged in an oblique shape, but the present invention is not limited thereto and may be arranged in a zigzag shape as shown in Fig.

A mask pattern (not shown) defining the position of the lower channel holes 105a of the lower mold stack 190a is formed to form the lower channel holes 105a, A step of etching the stack 190a may be performed.

Referring to FIG. 32, a lower sacrificial spacer 127a surrounding the side wall of the lower channel holes 105a is formed. The lower sacrificial spacer 127a is the same material as the lower sacrificial insulating layer 125a and may include silicon oxide, silicon nitride, silicon carbide, silicon, and silicon germanium.

The same material as the lower sacrificial insulating layer 125a may be deposited to form the lower sacrificial spacer 127a and an etchback process for the material may be performed. In this case, the lower sacrificial spacers 127a may be formed only on the sidewalls of the lower sacrificial insulating layer 125a and the lower insulating layer 160a, so that the upper surface of the substrate 50 may be exposed.

Referring to FIG. 33, a closed insulating layer 129 filling the lower channel holes 105a is formed. The closed insulating layers 129 may be a material having an etch selectivity with the lower sacrificial spacers 127a. Alternatively, the closed insulating layers 129 may be formed of the same material as the lower insulating layer 160a and may include, for example, silicon oxide, silicon nitride, or silicon germanium.

For example, to form a closed insulating layer 129 comprising silicon oxide, a deposition process of silicon oxide may be performed. Chemical mechanical polishing (CMP) or etchback of the silicon oxide may then be performed to expose the top surface of the lower mold stack 190a.

Referring to FIG. 34, an upper mold stack 190b for forming an upper channel layer (not shown) is formed. The upper mold stack 190b may include an upper sacrificial insulating layer 125b and an upper insulating layer 160b. The upper sacrificial insulating layer 125b and the upper insulating layer 160b may be alternately and repeatedly laminated. The upper sacrificial insulating layer 125b and the upper insulating layer 160b may be materials having an etch selectivity ratio with each other as described above.

A buffer layer 195 may then be formed on the top mold stack 190b. The buffer layer 195 may be formed to a thickness of about 50 nm to 100 nm. In addition, the buffer layer 195 may be formed of a material having an etch selectivity with the upper insulating layer 160b. The buffer layer 195 may be formed of the same material as the upper sacrificial insulating layer 125b.

The buffer layer 195 can prevent the upper mold stack 190b from being damaged during the process of etching the closed insulating layer 129. [ For example, when the closed insulating layer 129 is formed of the same material as the upper insulating layer 160b, for example, silicon oxide, the upper portion of the upper mold stack 190b during the process of etching the closed insulating layer 129 The insulating layer 160b may be etched. When the buffer layer 195 having the etch selectivity ratio is formed on the upper insulating layer 160b on the upper insulating layer 160b, the buffer layer 195 functions as an etch mask while etching the closed insulating layer 129 The upper insulating layer 160b can be prevented from being damaged.

Referring to FIG. 35, upper channel holes 105b penetrating the upper mold stack 190b are formed. The upper channel holes 105b may be arranged two-dimensionally and formed to expose the closed insulating layer 129. [ The upper channel holes 105b may be arranged to overlap with the lower channel holes 105a. In addition, the upper channel holes 105b may be formed in a tapered shape in the direction of the lower channel holes 105a.

A mask pattern (not shown) defining the position of the upper channel holes 105b of the upper mold stack 190b is formed to form the upper channel holes 105b and the buffer layer 195 and the upper mold stack 190b may be performed.

Referring to FIG. 36, upper sacrificial spacers 127b are formed to surround the side walls of the upper channel holes 105b. The upper sacrificial spacer 127b is the same material as the upper sacrificial insulating layer 125b and may include silicon oxide, silicon nitride, silicon carbide, silicon, and silicon germanium. The upper sacrificial spacer 127b may be formed only on the side walls of the upper sacrificial insulating layer 125b and the upper insulating layer 160b so that the upper surface of the closed insulating layer 129 is exposed .

Referring to FIG. 37, the closed insulating layer 129 is removed to expose the upper surface of the substrate 50. That is, the lower channel hole 105a is opened again. The upper sacrificial spacer 127b and the lower sacrificial spacer 127a prevent the upper and lower sacrificial insulating layers 125a and upper and lower insulating layers 160a and 160b from being damaged during the process of opening the lower channel hole 105a. . Therefore, even if the closed insulating layer 129 is removed, the lower sacrificial spacer 127a has an etch selectivity with the closed insulating layer 129, and thus remains without being removed.

Referring to FIG. 38, a channel layer 110 filling the lower channel hole 105a and the upper channel hole 105b is formed. More specifically, the lower channel layer 110a and the upper channel layer 110b filling the lower channel hole 105a and the upper channel hole 105b, respectively, may be formed at the same time. Accordingly, the lower channel layer 110a and the upper channel layer 110b may be formed as a single body continuously connected to each other.

In order to form the channel layer 110, the lower channel hole 105a and the upper channel hole 105b are filled with a semiconductor material containing silicon. Thus, the channel layer 110 may comprise a polycrystalline or monocrystalline silicon epitaxial layer. Thereafter, a chemical mechanical polishing or etch-back process may be performed until the top surface of the buffer layer 195 is exposed for separation between the channel layers 110.

Referring to FIG. 39A, a buffer layer 195, an upper mold stack 190b, and a lower mold stack 190a are etched to form dummy holes, and a supporting insulating layer 120 filling the dummy holes is formed. The supporting insulating layer 120 may be a material having an etch selectivity different from that of the sacrificial insulating layer 125 and the sacrificial spacer 127. Each of the supporting insulating layers 120 may be disposed between the channel layers 110. Further, the supporting insulating layers 120 viewed from the top view can be arranged in a zigzag manner.

As described above, the supporting insulating layer 120 serves to prevent sinking of the lower and upper insulating layers 160a and 160b during the pullback process in which the sacrificial insulating layer 125 is etched. 39A, the supporting insulating layer 120 is formed in the shape of a quadrangular prism, but the present invention is not limited thereto.

For example, as shown in FIG. 39B, the supporting insulating layers 120 may be formed in the form of L-shaped pillars, respectively. 39C, the supporting insulating layer 120 may be formed such that the L-shaped pillars are connected to each other. As a result, the supporting insulating layer 120 may have any shape, for example, to prevent the lower and upper insulating layers 160a and 160b from sinking.

Referring to FIG. 40, first, the buffer layer 195 is removed to expose the upper surface of the upper mold stack 190b. A chemical mechanical polishing or phosphoric acid stripping process may be performed to remove the buffer layer 195. As described above, the buffer layer 195 and the top sacrificial spacers 127b may be formed of the same material, for example silicon nitride, in which case a portion of the top sacrificial spacers 127b may be removed during the phosphoric acid strip process . More specifically, as shown in FIG. 8, an upper portion of the upper sacrificial spacer 127b contacting the buffer layer during the phosphoric acid strip process may be removed. In this case, not only the upper surface of the channel layer 110 but also the upper sidewall of the channel layer 110 may be exposed by the phosphoric acid strip process.

41, a second insulating layer 170 is formed on the upper mold stack 190b. The second insulating layer 170 may be formed of a material having an etch selectivity with the sacrificial insulating layer 125 and the sacrificial spacer 127. The second insulating layer 170 serves to prevent the channel from falling or lifting in a pull back process so that the second insulating layer 170 contacts the upper surface of the channel layer 110 And may be formed to be in contact with the surface. 9, the second insulating layer 170 may be formed to contact the sidewalls of the upper insulating layer 160b and the sidewalls of the channel layer 110. In addition, as shown in FIG.

42, a second insulating layer 170, an upper mold stack 190b, and a lower mold stack 190a are formed to perform a pullback process for etching the sacrificial insulating layer 125 and the sacrificial spacer 127 Thereby forming a word line recess 205. [ In this case, the word line recess 205 may be located between the channel layer 110 and the supporting insulating layer 120.

Referring to FIG. 43, the sacrificial insulating layer 125 and the sacrificial spacer 127 are etched to expose the first insulating layer 160 and the channel layer 110. When the sacrificial insulating layer 125 and the sacrificial spacer 127 are silicon nitride films, the sacrificial insulating layer 125 and the sacrificial spacers 127 can be removed through the phosphoric acid strip process. When the sacrificial insulating layer 125 and the sacrificial spacer 127 are silicon germanium, the sacrificial insulating layer 125 and the sacrificial insulating layer 125 are formed using SC-1 (standard clean-1) which is a mixture of ammonia, hydrogen peroxide, The sacrificial spacer 127 can be removed.

Referring to FIG. 44, a gate insulating layer 140 and a gate conductive layer 130 are formed on the exposed first insulating layer 160 and the channel layer 110. As described above, the gate insulating layer 140 may include a tunneling insulating layer, a charge storage layer, and a blocking insulating layer (142, 144, 146 in FIG. 2). 11A) or an air gap may not be formed between the gate insulating layer 140 and the channel layer 110 in accordance with the step coverage of the gate insulating layer 140 as described above (See FIG. 11B).

Thereafter, an impurity region 55 is formed on the upper surface of the substrate 50 by implanting the impurity into the substrate 50 through the word line recess 205. The impurity region 55 may be formed along the extending direction of the word line recess 205. The impurity region 55 can be electrically connected to the common source line (CSL in FIG. 75). The impurity region 55 is formed on the common source line (the impurity region 55 has the same conductivity as the conductivity of the substrate 50 or vice versa) If the conductivity is opposite to the conductivity, the impurity region 55 and the substrate 50 can form a PN junction.

45 and 46, a separating insulating layer 200 filling the word line recess 205 is formed and a chemical mechanical polishing process is performed to form a separating insulating layer 200 and a second insulating layer 170 ).

Referring to FIG. 47, a bit line conductive layer 180 is formed on the first insulating layer 160, the channel layer 110, and the isolation insulating layer 200. The bit line conductive layer 180 may be formed to extend in a direction perpendicular to the direction in which the separating insulating layer 200 extends.

48 to 61 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to embodiments of the present invention. The manufacturing method of the non-volatile memory device according to these embodiments is a modification of the manufacturing process of the non-volatile memory device according to Figs. 30 to 47. Fig. The following description will not be repeated.

Referring to FIG. 48, a stop layer 210, a lower mold stack 190a, and a mask layer 220 are sequentially formed on a substrate 50. The lower mold stack 190a may include the lower sacrificial insulating layer 125a and the lower insulating layer 160a and the lower sacrificial insulating layer 125a and the lower insulating layer 160a may include a material having an etch selectivity ratio Is as described above. Alternatively, a lid layer 230 may be further formed on the mask layer 220 to improve the uniformity of the selective growth process.

Referring to FIG. 49, lower channel holes 105a penetrating the cover layer 230, the mask layer 220, and the lower mold stack 190a are formed. The lower channel holes 105a may be two-dimensionally arranged to expose the stop layer 210. The stop layer 210 may serve as an etch stop layer during the etching process for forming the lower channel hole 105a. The stopper layer 210 may be formed of a material having an etch selectivity with the lower sacrificial insulating layer 125a and the lower insulating layer 160a constituting the lower mold stack 190a.

For example, the lower sacrificial insulating layer 125a may be formed of silicon nitride, and the lower insulating layer 160a may be formed of silicon oxide. In this case, stopping layer 210 may comprise materials such as aluminum oxide (Al2O3), tantalum nitride (TaN), and silicon carbide (SiC) with silicon nitride and silicon oxide and etch selectivity.

Referring to FIG. 50, in order to close the lower channel hole 105a, a selective growth process of the mask layer 220 is performed. More specifically, the process of selectively growing only the mask layer 220 is performed, so that the lower channel hole 105a is closed by the mask layer 220. [ Thus, an air gap 155 may be formed between the mask layer 220 and the substrate 50.

The mask layer 220 may comprise silicon (Si) or silicon germanium (SiGe) in a single crystal or polycrystalline structure. In this case, the lower channel hole 105a may be closed using a selective epitaxial growth process of the mask layer 220. [ The stop layer 210 can prevent the substrate 50, including the semiconductor material, from being grown together while the mask layer 220 is being grown. Therefore, the stopping layer 210 can also serve as a growth stop layer in a selective growth process for closing the lower channel hole 105a.

In the drawing, a cover layer 230 is formed on the mask layer 220, and the selective growth process is performed only on the sidewalls of the mask layer 220. However, the present invention is not limited thereto, and a selective growth process can be performed even when the cover layer 230 is not provided on the mask layer 220. In this case, the selective growth is performed on the upper surface and the side wall of the mask layer 220, so that the lower channel hole 105a can be closed.

Alternatively, a process of heating and thermally expanding the mask layer 220 may be performed so that the mask layer 220 can close the lower channel hole 105a. That is, when the mask layer 220 is heated, the exposed side wall of the mask layer 220 expands, and the lower channel hole 105a can be closed. Further, the thermal expansion process can be performed simultaneously with the selective growth process, and the lower channel hole 105a can be quickly closed by the mask layer 220. [

Referring to FIG. 51, the cover layer 230 is removed to expose the mask layer 220. For example, the cover layer 230 may comprise silicon oxide, and the cover layer 230 may be removed by a wet or dry etch process of the silicon oxide. Thereafter, an optional oxidation process of the exposed mask layer 220 may be performed. For example, if the mask layer 220 comprises silicon, a wet or dry oxidation process of the mask layer 220 may be performed, and thus the mask layer 220 may comprise silicon oxide.

Referring to FIG. 52, an upper mold stack 190b is formed on the mask layer 220. FIG. The upper mold stack 190b may include an upper sacrificial insulating layer 125b and an upper insulating layer 160b and the upper sacrificial insulating layer 125b and the upper insulating layer 160b may include a material having an etch selectivity ratio Is as described above.

Referring to FIG. 53, upper channel holes 105b penetrating the upper mold stack 190b are formed. The upper channel holes 105b may be arranged to be two-dimensionally formed to expose the mask layer 220. The upper channel holes 105b may be arranged to overlap with the lower channel holes 105a.

Referring to FIG. 54, the mask layer 220 is removed to expose the upper surface of the stopper layer 210. That is, the lower channel hole 105a is opened again. Even if the mask layer 220 is removed, the stop layer 210 has an etch selectivity with the mask layer 220, and thus remains without being removed. Thus, the stopping layer 210 serves to prevent the substrate 50 from being damaged during the process of opening the lower channel hole 105a.

55 and 56, the stopping layer 210 is removed to expose the upper surface of the substrate 50, and a channel layer 110 filling the lower channel hole 105a and the upper channel hole 105b is formed . The lower channel layer 110a and the upper channel layer 110b filling the lower channel hole 105a and the upper channel hole 105b may be formed at the same time so that the lower channel layer 110a and the upper channel layer 110b It can be formed as a single body continuously connected as described above.

57, an upper mold stack 190b, a mask layer 220, and a lower mold stack 190a (not shown) are formed to perform a pullback process to etch the lower sacrificial insulating layer 125a and the upper sacrificial insulating layer 125b. To form a word line recess 205. The word line recess 205 is formed by etching. Optionally, stopping layer 210 may be etched further.

58 and 59, the lower sacrificial insulating layer 125a and the upper sacrificial insulating layer 125b are etched to expose the sidewalls of the channel layer 110, An insulating layer 140 and a gate conductive layer 130 are formed.

60 and 61, a separating insulating layer 200 filling the word line recess 205 is formed and a first insulating layer 160, a channel layer 110, and a separating insulating layer 200 are formed. The bit line conductive layer 180 is formed. As described above, the bit line conductive layer 180 may be formed to extend in a direction perpendicular to the direction in which the separating insulating layer 200 extends.

62 to 73 are perspective views illustrating a method of manufacturing a nonvolatile memory device according to embodiments of the present invention. The manufacturing method of the non-volatile memory device according to these embodiments is a modification of the manufacturing process of the non-volatile memory device according to Figs. The following description will not be repeated.

62, a stop layer 210, a lower mold stack 190a, a mask layer 220, and a cover layer 230 are formed in this order on a substrate 50. The lower mold stack 190a may include a lower gate conductive layer 130a and a lower insulating layer 160a. The lower gate conductive layer 130a may be formed of an epitaxial layer of polycrystal or monocrystal structure. Further, the lower gate conductive layer 130a may include a silicon material, or a silicon-germanium material. The mask layer 220 may comprise silicon (Si) or silicon germanium (SiGe) in a single crystal or polycrystalline structure. Further, the mask layer 220 may be formed of the same material as the lower gate conductive layer 130a.

Referring to FIG. 63, lower channel holes 105a are formed through the cover layer 230, the mask layer 220, and the lower mold stack 190a. The lower channel holes 105a may be arranged two-dimensionally to expose the stop layer 210 as described above.

Referring to FIG. 64, a lower sacrificial spacer 127a is formed to surround the side wall of the lower channel holes 105a. The lower sacrificial spacer 127a may be formed to be in direct contact with the lower gate conductive layer 130a. More specifically, during the selective growth process of the mask layer 220, the lower sacrificial spacers 127a serve to prevent the lower gate conductive layer 130a from growing.

In order to form the lower sacrificial spacer 127a, a material having an etch selectivity with the lower insulating layer 160a and the lower gate conductive layer 130a may be deposited, and an etch-back process for the material may be performed. In this case, the lower sacrificial spacers 127a may be formed only on the sidewalls of the lower gate conductive layer 130a and the lower insulating layer 160a, and thus the sidewalls of the mask layer 220 may be exposed.

65, in order to close the lower channel hole 105a, a selective growth process of the mask layer 220 is performed. The lower channel hole 105a is closed by the selective growth process of the mask layer 220 and thus the air gap 155 can be formed between the mask layer 220 and the substrate 50 as described above.

Referring to FIG. 66, the cover layer 230 is removed to expose the mask layer 220. Alternatively, the oxidation process of the exposed mask layer 220 may be performed, as described above.

Referring to FIG. 67, an upper mold stack 190b including a top gate conductive layer 130b and an upper insulating layer 160b is formed on a mask layer 220. Referring to FIG. 68, upper channel holes 105b penetrating the upper mold stack 190b are formed. The upper channel holes 105b may be arranged to be two-dimensionally formed to expose the mask layer 220. The upper channel holes 105b may be arranged to overlap with the lower channel holes 105a.

Referring to FIG. 69, the mask layer 220 is removed to expose the upper surface of the stopper layer 210. That is, the lower channel hole 105a is opened again. Even when the mask layer 220 is removed, the stop layer 210 and the lower sacrificial spacers 127a have etch selectivity with respect to the mask layer 220, so that they remain unremoved.

70 and 71, the lower sacrificial spacer 127a is removed to expose the sidewalls of the lower gate conductive layer 130a and the sidewalls of the lower insulating layer 160a. Thereafter, the stopper layer 210 is removed, Thereby exposing the upper surface of the substrate 50.

Referring to FIG. 72, a gate insulating layer 140 is deposited along the sidewalls of the channel hole 105. The gate insulating layer 140 may be a stacked structure of a tunneling insulating layer 142 (FIG. 2), a charge storage layer 144 (FIG. 2), and a blocking insulating layer 146 (FIG. 2).

Referring to FIG. 73, a channel layer 110 filling the lower channel hole 105a and the upper channel hole 105b is formed. The lower channel layer 110a and the upper channel layer 110b filling the lower channel hole 105a and the upper channel hole 105b may be formed at the same time so that the lower channel layer 110a and the upper channel layer 110b As described above, can be formed integrally with each other in succession.

The mask layer 220 may be formed of a conductive material such as polysilicon. The mask layer 220 may function as a gate conductive layer when the oxidation process of the mask layer 220 referred to in FIG. 65 is not performed. The mask layer 220 can function to close the lower channel hole 105a for the upper mold stack 190b and simultaneously operate as a memory cell after the formation of the gate insulating layer 140 and the channel layer 110 You may.

74 is an equivalent circuit diagram of a memory cell array according to an embodiment of a nonvolatile memory device according to the technical idea of the present invention.

Referring to FIG. 74, the memory cell array 10 may include a plurality of memory cell strings 11. The plurality of memory cell strings 11 may each have a vertical structure extending perpendicularly to the extending direction of the main surface of the substrate (not shown). The memory cell block 13 can be constituted by a plurality of memory cell strings 11. [

The plurality of memory cell strings 11 may each include a plurality of memory cells MC1, MC2, ..., MCn-1, MCn, a string selection transistor SST, and a ground selection transistor GST . The ground selection transistor GST, the plurality of memory cells MC1, MC2, ..., MCn-1, MCn, and the string selection transistor SST are vertically arranged in series in each memory cell string 11 . Here, the plurality of memory cells MC1, MC2, ..., MCn-1, MCn can store data. The plurality of word lines WL1, WL2, ..., WLn-1, WLn are coupled to the respective memory cells MC1, MC2, ..., MCn-1, MCn, ..., MCn-1, MCn). The number of the plurality of memory cells MC1, MC2, ..., MCn-1, MCn can be appropriately selected in accordance with the capacity of the nonvolatile memory element.

On one side of each memory cell string 11 arranged in the first to m-th columns of the memory cell block 13, for example, on the drain side of the string select transistor SST, (BL1, BL2, ..., BLm-1, BLm) may be connected. A common source line CSL may be connected to the other side of each memory cell string 11, for example, the source of the ground selection transistor GST.

WLn (WL1, WL2, ..., WLn) are connected to gates of memory cells arranged on the same layer among a plurality of memory cells MC1, MC2, ..., MCn-1, MCn of the plurality of cell string units -1, and WLn may be commonly connected. The data is programmed, read or erased in the plurality of memory cells MC1, MC2, ..., MCn-1, MCn in accordance with driving of the word lines WL1, WL2, ..., WLn- .

In each memory cell string 11, the string selection transistor SST is connected to the bit lines BL1, BL2, ..., BLm-1, BLm and the memory cells MC1, MC2, ..., MCn- ). ≪ / RTI > Each of the string selection transistors SST in the memory cell block 13 is connected to a plurality of bit lines BL1, BL2, ..., BLm-1, BLm and a plurality MCn-1, and MCn of the memory cells MC1, MC2, ..., MCn-1, and MCn.

The ground selection transistor GST may be arranged between the plurality of memory cells MC1, MC2, ..., MCn-1, MCn and the common source line CSL. Each of the ground selection transistors GST in the memory cell block 13 is connected to the plurality of memory cells MC1, MC2, ..., MCn-1, MCn by a ground selection line GSL, And the common source line CSL can be controlled.

75 is a cross-sectional view showing a nonvolatile memory device according to the technical idea of the present invention. In Fig. 75, the same reference numerals as those in Fig. 2 denote the same components, and thus detailed description of the overlapping components will be omitted.

Referring to FIG. 75, the channel layer 110 'may be formed in the form of a macaroni, as described above with reference to FIG. In this case, the nonvolatile memory device may further include a pillar insulating layer 111 filling the channel layer 110 '. The channel layer may include a lower channel layer and an upper channel layer. In particular, the lower channel layer may include a bottom portion, a side wall portion, and a ring-shaped cover portion. As described above, the lower channel layer and the upper channel layer may be connected to each other continuously.

5, the uppermost gate conductive layer 130a and the lowermost gate conductive layer 130c may be thicker than the other gate conductive layer 130b. The uppermost gate conductive layer 130a functions as a string selection transistor (SST in FIG. 74). Also, the lowermost gate conductive layer 130b functions as a ground selection transistor (GST in FIG. 74).

One end of the gate conductive layer 130 may have a dogbone shape. More specifically, the gate conductive layer 130, which extends in a direction parallel to the substrate 50, can extend partially at a direction perpendicular to the substrate 50 at the end thereof, May have the same shape as a dog bone or triangular flask.

The air gap 150 may be formed between the gate conductive layers 130 as described above, which may improve the problem of inter-gate coupling. The air gap 150 may also have a profile that depends on the shape of the end of the gate conductive layer 130. That is, when the gate conductive layer 130 has a dog bone shape, the air gap 150 may have a rounded profile according to the dog bone shape.

The thickness of the air gap 150 in the direction parallel to the substrate 50 may be a difference between the thickness of the sacrificial spacer (127 in FIG. 6) and the thickness of the gate insulating layer 140 multiplied by 2. Therefore, as described in FIGS. 11A and 11B, whether or not the formation of the air gap 150 can be determined depending on whether the thickness of the sacrificial spacer 127 is about two times or more of the thickness of the gate insulating layer 140 .

The size of the air gap 150 is proportional to the thickness of the first insulating layer 160 and can be made smaller as the thickness of the gate insulating layer 140 is larger. Particularly, in the direction perpendicular to the substrate 50, the size of the air gap 150a at the uppermost one of the air gaps 150 can be reduced as the thickness of the second insulating layer 170 is increased.

In addition, the size of the air gap 150c at the lowermost position in the direction perpendicular to the substrate 50 may be proportional to the degree of overetching by the anisotropic etching process for forming the channel hole (105 in FIG. 5). That is, the greater the degree of overlap between the substrate 50 and the channel layer 110, the greater the lower air gap 150c can be formed.

77 is a schematic diagram showing a memory card 1000 including a nonvolatile memory device according to embodiments of the present invention.

77, controller 1010 and memory module 1020 may be arranged to exchange electrical signals. For example, when the controller 1010 issues a command, the memory module 1020 can transmit data. Memory module 1020 may include a vertical non-volatile memory device according to any of the embodiments of the present invention. Vertically-structured non-volatile memory devices in accordance with various embodiments of the present invention may be arranged in a "NAND" and "NOR" architecture memory array (not shown) corresponding to the appropriate logic gate design have. A memory array arranged in a plurality of rows and columns can constitute one or more memory array banks (not shown). Memory module 1020 may include such a memory array (not shown) or a memory array bank (not shown). In addition, the memory card 1000 may include a conventional row decoder (not shown), a column decoder (not shown), I / O buffers (not shown), and / And a control register (not shown). The memory card 1000 may include various kinds of cards such as a memory stick card, a smart media card (SM), a secure digital (SD) card, a mini-secure digital card a mini secure digital card (mini SD), or a multi media card (MMC).

78 is a schematic diagram showing a system 1100 including a non-volatile memory device according to embodiments of the present invention.

Referring to Figure 78, the system 1100 may include a controller 1110, an input / output device 1120, a memory component 1130, and an interface 1140. The system 1100 may be a mobile system or a system that transmits or receives information. The mobile system may be a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, a digital music player, or a memory card . The controller 1110 may execute a program and control the system 1100. [ More specifically, controller 1110 may be configured to control input / output device 1120, memory component 1130, and interface 1140. The controller 1110 may be, for example, a microprocessor, a digital signal processor, a microcontroller, or the like. The input / output device 1120 may be used to input or output data of the system 1100. The system 1100 may be connected to an external device, such as a personal computer or network, using the input / output device 1120 to exchange data with an external device. The input / output device 1120 may be, for example, a keypad, a keyboard, or a display. The memory component 1130 may store code and / or data for operation of the controller 1110 and / or store processed data at the controller 1110. [ Memory component 1130 may include a non-volatile memory according to any of the embodiments of the present invention. The interface 1140 may be a data transmission path between the system 1100 and another external device. The controller 1110, the input / output device 1120, the memory component 1130, and the interface 1140 can communicate with each other via the bus 1150. For example, the system 1100 may be a mobile phone, an MP3 player, navigation, a portable multimedia player (PMP), a solid state disk (SSD) appliances.

It is to be understood that the shape of each portion of the accompanying drawings is illustrative for a clear understanding of the present invention. It should be noted that the present invention can be modified into various shapes other than the shapes shown. Like numbers refer to like elements throughout the drawings.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Will be clear to those who have knowledge of.

50; A substrate 105; Channel hole
105a; A lower channel hole 105b; Upper channel hole
110; Channel layer 110a; The lower channel layer
110b; An upper channel layer 120; Insulating layer
125; A sacrificial insulating layer 125a; Lower sacrificial insulating layer
125b; Upper sacrificial insulation layer 127; Sacrificial spacer
127a; Lower sacrificial spacers 127b; Upper sacrificial spacer
129; A closing insulating layer 130; Gate conductive layer
130a; A bottom gate conductive layer 130b; The upper gate conductive layer
140; A gate insulating layer 145; Gate separation insulating layer
150; Air gap 155; Air gap
160; A first insulating layer 160a; The lower insulating layer
160b; Upper insulating layer 170; The second insulating layer
180; A bit line conductive layer 190a; Lower mold stack
190b; An upper mold stack 195; Buffer layer
200; A separation insulating layer 205; Wordline recess
210; Stop layer 220; Mask layer

Claims (15)

Forming a channel hole through a plurality of sacrificial insulating layers and a plurality of first insulating layers formed on the substrate;
Forming a sacrificial spacer on a sidewall of the channel hole;
Forming a channel layer in contact with the sacrificial spacer;
Etching an upper portion of the sacrificial spacer such that an upper sidewall of the channel layer is exposed;
Forming a second insulating layer in contact with an upper surface of the channel layer and an upper sidewall of the channel layer;
Etching the sacrificial insulation layers and the sacrificial spacers such that side walls of the channel layer are exposed;
And forming a gate conductive layer on the sidewalls of the channel layer. delete delete The method according to claim 1,
Further comprising forming a gate insulating layer on the sacrificial spacer between the step of forming the sacrificial spacer and the step of forming the channel layer. 5. The method of claim 4,
Further comprising forming a gate separation insulating layer on the channel layer between etching the sacrificial insulation layers and the sacrificial spacers and forming the gate conductive layer. ≪ / RTI > delete The method according to claim 1,
Wherein forming the channel hole and forming the sacrificial spacer comprise:
Alternately stacking a plurality of lower sacrificial insulating layers and a plurality of lower insulating layers on a substrate;
Etching the lower sacrificial insulating layers and the lower insulating layers to form lower channel holes;
Forming a lower sacrificial spacer on a sidewall of the lower channel hole;
Forming a closed insulating layer filling the lower channel hole;
Alternately stacking a plurality of upper sacrificial insulating layers and a plurality of upper insulating layers on the closed insulating layer;
Etching the upper sacrificial insulating layers and the upper insulating layers to form upper channel holes; And
And forming an upper sacrificial spacer on a sidewall of the upper channel hole. Alternately stacking a plurality of sacrificial insulating layers and a plurality of first insulating layers on a substrate;
Etching the sacrificial insulating layers and the first insulating layers to form channel holes;
Forming a sacrificial spacer on a sidewall of the channel hole;
Forming a channel layer in contact with the sacrificial spacer;
Etching an upper portion of the sacrificial spacer such that an upper sidewall of the channel layer is exposed;
Forming a second insulating layer in contact with an upper surface of the channel layer and an upper sidewall of the channel layer;
Etching the sacrificial insulating layers, and the first insulating layers to form word line recesses;
Etching the sacrificial insulation layers and the sacrificial spacers such that side walls of the channel layer are exposed;
Forming a gate insulating layer on the sidewalls of the channel layer; And
And forming a gate conductive layer on the gate insulating layer. 9. The method of claim 8,
Between forming the channel layer and etching the upper portion of the sacrificial spacers,
Etching the sacrificial insulating layers and the first insulating layers to form dummy holes;
And forming a supporting insulating layer filling the dummy holes. ≪ Desc / Clms Page number 20 > 9. The method of claim 8,
Wherein the channel layers are arranged in a zigzag manner. delete delete Board;
A channel layer protruding from the substrate;
A gate conductive layer surrounding the channel layer and having one end having a dog bone shape;
A gate insulating layer positioned between the channel layer and the gate conductive layer; And
And a first insulating layer located above and below the gate conductive layer, the first insulating layer being spaced apart from the channel layer. delete delete

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