KR102432793B1 - Semiconductor device - Google Patents

Abstract

A semiconductor device according to an embodiment of the present invention includes a first pad pattern extending in a first direction, and a second direction intersecting the first direction from the first pad pattern and extending in the first pad pattern. first conductive patterns including first line patterns that become wider as they get closer and stacked apart from each other; and first interlayer insulating layers disposed between the adjacent first conductive patterns.

Description

semiconductor device {SEMICONDUCTOR DEVICE}

Embodiments of the present invention relate to a semiconductor device, and more particularly, to a semiconductor device including a pad pattern and line patterns extending from the pad pattern.

The semiconductor device may include conductive patterns. Each of the conductive patterns may include a pad pattern for receiving a signal from the outside, and line patterns extending from the pad pattern and connected to the memory cells. The pad pattern may be connected to the contact plug to receive a signal from the outside.

SUMMARY An embodiment of the present invention provides a semiconductor device capable of improving the operating speed of memory cells connected to line patterns extending from a pad pattern.

A semiconductor device according to an embodiment of the present invention includes a first pad pattern extending in a first direction, and a second direction intersecting the first direction from the first pad pattern and extending in the first pad pattern. first conductive patterns including first line patterns that become wider as they get closer and stacked apart from each other; and first interlayer insulating layers disposed between the adjacent first conductive patterns.

A semiconductor device according to an embodiment of the present invention includes: a first pad pattern extending in a first direction; and first line patterns extending from the first pad pattern in a second direction intersecting the first direction and having a wider width as the first pad pattern approaches.

According to an embodiment of the present invention, the resistance of the pad pattern and the line pattern connecting portion can be reduced by forming the width of the line pattern extending from the pad pattern to be wider as it approaches the pad pattern. Accordingly, according to an exemplary embodiment of the present invention, the operation speed of memory cells connected to the line pattern can be improved by smoothly transmitting the signal applied to the pad pattern in the line pattern.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention.
2A and 2B are perspective views illustrating various structures of a memory cell array according to an embodiment of the present invention.
3 is a plan view illustrating a conductive pattern according to an embodiment of the present invention.
4A to 4C are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments.
5 and 6 are plan views for explaining various arrangements of channel pillars penetrating the line pattern.
7 is a view for explaining a laminated structure of a pad pattern.
8A to 8D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.
9 is a block diagram illustrating a memory system according to an embodiment of the present invention.
10 is a block diagram illustrating a computing system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the scope of the present invention is not limited to the embodiments described below. Only the present embodiment is provided to complete the disclosure of the present invention and to fully inform those of ordinary skill in the scope of the invention, and the scope of the present invention should be understood by the claims of the present application.

1 is a block diagram of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1 , a semiconductor device according to an exemplary embodiment may include a memory cell array 10 and a peripheral circuit 40 .

The memory cell array 10 may include memory blocks BLK0 to BLKn. Each of the memory blocks BLK0 to BLKn may include memory cells. Each of the memory cells may store one or more bits. Memory cells may be connected in units of memory strings through a channel layer. A memory string may be coupled to bit lines, and memory cells may be coupled to word lines.

The peripheral circuit 40 may include row decoders 20A and 20B and a page buffer 30 . The row decoders 20A and 20B may include a first row decoder 20A and a second row decoder 20B facing each other with the memory cell array 10 interposed therebetween.

The row decoders 20A and 20B may be electrically connected to the memory cell array 10 through pad patterns connected to word lines. The row decoders 20A and 20B may be configured to select a memory block and a word line connected to the selected memory block according to the address information.

The page buffer 30 may be electrically connected to the memory cell array 10 through bit lines. The page buffer 30 may be configured to selectively precharge bit lines or sense threshold voltages of memory cells using potentials of the bit lines.

2A and 2B are perspective views illustrating various structures of a memory cell array according to an embodiment of the present invention. More specifically, FIGS. 2A and 2B are diagrams illustrating a memory cell array having a three-dimensional structure. For convenience of description, the multilayer film and the insulating film including the memory film are not shown in FIGS. 2A and 2B .

Referring to FIG. 2A , each of the memory blocks of the memory cell array may include a straight-type cell string SCST. The straight-type cell string SCST may include a channel column CH extending in one direction, and line patterns LP that are spaced apart from each other to surround the channel column CH.

The channel column CH may be electrically connected between the source layer SL and the bit line BL. The channel pillar CH is formed inside the hole passing through the line patterns LP. The channel column CH may be formed in a tubular shape surrounding the core insulating film disposed in the central region of the hole, or may be formed in a buried type that completely fills the central region of the hole. A multilayer film including a memory film may be formed between the channel pillar CH and the line patterns LP. The multilayer film may be formed along the shape of the outer wall of the channel column CH, or may be formed along the shape of the outer wall of each of the line patterns LP. When the multilayer film is formed along the outer wall shape of each of the line patterns LP, the multilayer film may be separated by the first and second slits SI1 and SI2 .

The bit line BL is electrically connected to the upper end of the channel column CH, and may extend toward the page buffer 30 described above with reference to FIG. 1 . The source layer SL may be directly connected to the lower end of the channel pillar CH. The source layer SL may be a part of the semiconductor substrate into which impurities are implanted, or may be a doped silicon layer formed on the semiconductor substrate.

The line patterns LP may be separated by the first slit SI1 . The line patterns LP may include a lower select line LSL, word lines WL, and an upper select line USL sequentially stacked along the channel column CH. The lower select line LSL may be disposed between the word lines WL and the source layer SL. The number of the lower select lines LSL stacked between the word lines WL and the source layer SL may be one or two or more layers. The upper select line USL may be disposed between the word lines WL and the bit line BL. The number of stacked upper select lines USL stacked between the word lines WL and the bit line BL may be one or two or more layers. Any one of the lower select line LSL and the upper select line LSL and USL may be divided into units smaller than the word lines WL. For example, each of the word lines WL may be formed to surround the channel pillars CH in two or more columns, and the upper select line USL may be formed to surround the channel pillars CH in one column. In this case, the upper select line USL may be separated by not only the first slit SI1 but also the second slit SI2 to be narrower than the word lines WL. The line patterns LP may extend toward the first row decoder 20A or the second row decoder 20B described above with reference to FIG. 1 . One end of each of the line patterns LP may be connected to the pad pattern. Each of the line patterns LP may be electrically connected to the first row decoder 20A or the second row decoder 30B via a pad pattern connected thereto.

According to the above structure, the memory cells are formed at the intersection of the channel column CH and the word lines WL, and the lower select transistor is formed at the intersection of the channel column CH and the lower select line LSL. , the upper select transistor is formed at the intersection of the channel column CH and the upper select line USL. The lower select transistor, the memory cells, and the upper select transistor arranged in a line along one channel column CH are connected in series through the channel column CH to form a straight-type cell string SCST. The word lines WL transmit a signal to the gates of the memory cells, the lower select line LSL transmits a signal to the gate of the lower select transistor, and the upper select line USL transmits a signal to the gate of the upper select transistor can be transmitted.

Referring to FIG. 2B , each of the memory blocks of the memory cell array may include a U-type cell string UCST. The U-type cell string UCST is disposed below the U-type channel column CH, the line patterns LP_S and LP_D that are spaced apart to surround the channel column CH, and the line patterns LP_S and LP_D. and may include a pipe gate PG surrounding the channel column CH.

The channel column CH may include a pipe channel film P_CH buried in the pipe gate PG, a source side channel column S_CH and a drain side channel column D_CH extending from the pipe channel film P_CH. can The channel column CH may be formed in a tubular shape as described above with reference to FIG. 2A or may be formed in a buried type. The multilayer film including the memory film may be formed along the shape of the outer wall of the channel pillar CH or may be formed along the shape of the outer wall of each of the line patterns LP_S and LP_D. When the multilayer film is formed along the outer wall shape of each of the line patterns LP_S and LP_D, the multilayer film may be separated by the slit SI.

The channel column CH may be electrically connected between the common source line CSL and the bit line BL. The bit line BL and the common source line CSL are disposed on different layers and are spaced apart from each other. For example, the common source line CSL may be disposed under the bit line BL. The bit line BL is electrically connected to the upper end of the drain side channel column D_CH and may extend toward the page buffer 30 described above with reference to FIG. 1 . A contact plug may be formed between the bit line BL and the drain side channel column D_CH. The common source line CSL may be electrically connected to an upper end of the source side channel column S_CH. A contact plug may be formed between the common source line CSL and the source side channel column S_CH.

The pipe gate PG may be disposed under the bit line BL, the common source line CSL, and the line patterns LP_S and LP_D and may be formed to surround the pipe channel layer P_CH.

The line patterns LP_S and LP_D may include source side line patterns LP_S and drain side line patterns LP_D separated by a slit SI. The source side line patterns LP_S and the drain side line patterns LP_D may be disposed under the bit line BL and the common source line CSL.

The source side line patterns LP_S may include the source side word lines WL_S and the source select line SSL sequentially stacked along the source side channel column S_CH. The source side word lines WL_S may be disposed between the common source line CSL and the pipe gate PG. The source select line SSL may be disposed between the common source line CSL and the source side word lines WL_S. The number of stacks of the source select line SSL disposed between the common source line CSL and the source side word lines WL_S may be one or two or more layers.

The drain side line patterns LP_D may include drain side word lines WL_D and a drain select line DSL sequentially stacked along the drain side channel pillar D_CH. The drain side word lines WL_D may be disposed between the bit line BL and the pipe gate PG. The drain select line DSL may be disposed between the bit line BL and the drain side word lines WL_D. The number of stacks of the drain select line DSL disposed between the bit line BL and the drain side word lines WL_D may be one or two or more layers.

The line patterns LP_S and LP_D may extend toward the first row decoder 20A or the second row decoder 20B described above with reference to FIG. 1 . For example, the source side line patterns LP_S may extend toward the first row decoder 20A, and the drain side line patterns LP_D may extend toward the second row decoder 20B. One end of each of the line patterns LP_S and LP_D may be connected to the pad pattern. Each of the line patterns LP_S and LP_D may be electrically connected to the first row decoder 20A or the second row decoder 30B via a pad pattern connected thereto.

According to the above structure, the source-side memory cells are formed at intersections of the source-side channel column S_CH and the source-side word lines WL_S, and the drain-side memory cells are the drain-side channel column D_CH and the drain-side word. It is formed at the intersection of the lines WL_D. The source select transistor is formed at the intersection of the source side channel pillar S_CH and the source select line SSL, and the drain select transistor is formed at the intersection of the drain side channel pillar D_CH and the drain select line DSL. The pipe transistor is formed at the intersection of the pipe channel layer P_CH and the pipe gate PG. The source select transistor, the source side memory cells, the pipe transistor, the drain side memory cells, and the drain select transistor arranged along one channel column CH are connected in series through the channel column CH to form a U-type cell string ( UCST). The source side word lines WL_S transmit signals to the gates of the source side memory cells, the drain side word lines WL_D transmit signals to the gates of the drain side memory cells, and the source select line SSL. may transmit a signal to the gate of the source select transistor, the drain select line DSL may transmit a signal to the gate of the drain select transistor, and the pipe gate PG may transmit a signal to the gate of the pipe transistor.

The channel column CH may be formed in various shapes, such as a W-shape, in addition to the structure described above with reference to FIGS. 2A and 2B .

As described above with reference to FIGS. 2A and 2B , the line pattern LP, LP_S, or LP_D surrounding the channel column CH extends toward the row decoder 20A or 20B shown in FIG. 1 and passes through the pad pattern to the row pattern. It may be electrically connected to the decoder 20A or 20B. In the following drawings, the conductive pattern of each layer including the pad pattern and the line pattern will be described in more detail.

3 is a plan view illustrating a conductive pattern according to an embodiment of the present invention. FIG. 3 illustrates conductive patterns disposed on one plane extending along first and second directions I and II.

Referring to FIG. 3 , a semiconductor device according to an exemplary embodiment may include a first conductive pattern CA. The first conductive pattern CA may include a first pad pattern 110A extending along the first direction I and first line patterns 115A extending from the first pad pattern 110A. The first line patterns 115A may extend in a second direction (II) crossing the first direction (I).

A contact plug (not shown) may contact the first pad pattern 110A. The contact plug is a conductive structure for electrically connecting the first pad pattern 110A to the row decoder, and may extend in a third direction perpendicular to the first direction (I) and the second direction (II). The first line patterns 115A may receive a signal from the row decoder via the first pad pattern 110A. Each of the first line patterns 115A may include a first end connected to the first pad pattern 110A adjacent to the first pad pattern 110A and a second end facing the first end. The first width WA1 of the first end may be the same as the second width WA2 of the second end. That is, each of the first line patterns 115A may extend along the second direction II with a constant width. Each of the first line patterns 115A may be penetrated by the first through structure TH_A including the first channel pillar.

The semiconductor device according to an embodiment of the present invention may further include a second conductive pattern CB disposed on the same layer as the first conductive pattern CA. The second conductive pattern CB may include a second pad pattern 110B extending along the first direction I and second line patterns 115B extending from the second pad pattern 110B. The second pad pattern 110B may face the first pad pattern 110A with the first line patterns 115A interposed therebetween.

The second line patterns 115B may extend in a second direction (II) crossing the first direction (I). The second line patterns 115B may be alternately disposed with the first line patterns 115A in a space between the first pad pattern 110A and the second pad pattern 110B.

A contact plug (not shown) may contact the second pad pattern 110B. The contact plug is a conductive structure for electrically connecting the second pad pattern 110B to the row decoder, and may extend in a third direction perpendicular to the first direction (I) and the second direction (II). The second line patterns 115B may receive a signal from the row decoder via the second pad pattern 110B. Each of the second line patterns 115B may include a first end connected to the second pad pattern 110B adjacent to the second pad pattern 110B and a second end facing the first end. The first width WB1 of the first end may be the same as the second width WB2 of the second end. That is, each of the second line patterns 115B may extend along the second direction II with a constant width. Each of the second line patterns 115B may be penetrated by the second through structure TH_B including the second channel pillar.

The first line patterns 115A and the second line patterns 115B described above may be the line patterns LP described above with reference to FIG. 2A . In this case, each of the first through structure TH_A and the second through structure TH_B may include the channel column CH of the straight type described above with reference to FIG. 2A .

Alternatively, the first line patterns 115A may be the source side line pattern LP_S described above with reference to FIG. 2B , and the second line patterns 115B may be the drain side line pattern LP_D described with reference to FIG. 2B . In this case, the first through structure TH_A may include the source side channel pillar S_CH described above with reference to FIG. 2B , and the second through structure TH_B may include the drain side channel pillar D_CH described with reference to FIG. 2B . can

The first pad pattern 110A may be disposed adjacent to the first row decoder 20A described above with reference to FIG. 1 and may be electrically connected to the first row decoder 20A. The second pad pattern 110B may be disposed adjacent to the second row decoder 20B described above with reference to FIG. 1 and may be electrically connected to the second row decoder 20B.

According to the above-described embodiment, a signal may be simultaneously applied to the plurality of first line patterns 115A via one first pad pattern 110A, and via one second pad pattern 110B. A signal may be simultaneously applied to the plurality of second line patterns 115B. Each of the first and second line patterns 115A and 115B may be formed to have a uniform width in the second direction (II). In this case, the resistance of the first end of each of the first line patterns 115A adjacent to the first pad pattern 110A and the first end of each of the second line patterns 115B adjacent to the second pad pattern 110B this can be higher As a result, the operation speed of the memory cells connected to the first line patterns 115A and the memory cells connected to the second line patterns 115B may be slowed by the RC delay. For example, the program speed of the memory cells connected to the first and second line patterns 115A and 115B by RC delay due to an increase in resistance of the first end of each of the first and second line patterns 115A and 115B. can be slow

In the following embodiments, a structure of a conductive pattern capable of increasing the operation speed of memory cells by improving RC delay will be described.

4A to 4C are plan views and cross-sectional views illustrating semiconductor devices according to example embodiments. More specifically, FIG. 4A illustrates conductive patterns of a semiconductor device disposed on one plane extending along the first and second directions I and II. 4B and 4C are cross-sectional views of the semiconductor device taken along line "X-X'" shown in FIG. 4A.

Referring to FIG. 4A , a semiconductor device according to an exemplary embodiment may include a first conductive pattern CP_A. The first conductive pattern CP_A may include a first pad pattern 120A extending along the first direction I and first line patterns 125A extending from the first pad pattern 120A. The first line patterns 125A may extend in a second direction (II) crossing the first direction (I).

A contact plug (not shown) may contact the first pad pattern 120A. The contact plug is a conductive structure for electrically connecting the first pad pattern 120A to the row decoder, and may extend in a third direction perpendicular to the first direction (I) and the second direction (II). The first line patterns 125A may receive a signal from the row decoder via the first pad pattern 120A. Each of the first line patterns 125A may include a first end connected to the first pad pattern 120A adjacent to the first pad pattern 120A and a second end facing the first end. Each of the first line patterns 125A may become wider as it approaches the first pad pattern 120A. Accordingly, the first width WA11 of the first end may be wider than the second width WA21 of the second end. Each of the first line patterns 125A may be penetrated by the first through structure TH_A including the first channel pillar. In other words, each of the first line patterns 125A may surround the first through structure TH_A. Each of the first line patterns 125A may surround the plurality of first through structures TH_A arranged in one row along the second direction II, which is an extension direction thereof.

The semiconductor device according to an embodiment of the present invention may further include a second conductive pattern CP_B disposed on the same layer as the first conductive pattern CP_A. The second conductive pattern CP_B may include a second pad pattern 120B extending along the first direction I and second line patterns 125B extending from the second pad pattern 120B. The second pad pattern 120B may face the first pad pattern 120A with the first line patterns 125A interposed therebetween.

The second line patterns 125B may extend along a second direction II crossing the first direction I. The second line patterns 125B may be alternately disposed with the first line patterns 125A in a space between the first pad pattern 120A and the second pad pattern 120B.

A contact plug (not shown) may contact the second pad pattern 120B. The contact plug is a conductive structure for electrically connecting the second pad pattern 120B to the row decoder and may extend in a third direction perpendicular to the first direction (I) and the second direction (II). The second line patterns 125B may receive a signal from the row decoder via the second pad pattern 120B. Each of the second line patterns 125B may include a first end connected to the second pad pattern 120B adjacent to the second pad pattern 120B and a second end facing the first end. Each of the second line patterns 125B may become wider as it approaches the second pad pattern 120B. Accordingly, the first width WB11 of the first end may be wider than the second width WB21 of the second end. Each of the second line patterns 125B may be penetrated by the second through structure TH_B including the second channel pillar. In other words, each of the second line patterns 125B may surround the second through structure TH_B. Each of the second line patterns 125B may surround the plurality of first through structures TH_B arranged in one row along the second direction II, which is an extension direction thereof.

In the above, the width WA11 of the first end of each of the first line patterns 125A adjacent to the first pad pattern 120A is the width WA11 of each of the second line patterns 125B adjacent to the first pad pattern 120A. It may be formed wider than the width WB21 of the second end. In addition, the width WA21 of the second end of each of the first line patterns 125A adjacent to the second pad pattern 120B is the second width WA21 of each of the second line patterns 125B adjacent to the second pad pattern 120B. It may be formed to be narrower than the width WB11 of one end.

The first pad pattern 120A may be disposed adjacent to the first row decoder 20A described above with reference to FIG. 1 and may be electrically connected to the first row decoder 20A. The second pad pattern 120B may be disposed adjacent to the second row decoder 20B described above with reference to FIG. 1 and may be electrically connected to the second row decoder 20B.

According to the above-described embodiment, each of the first line patterns 125A extends along the second direction II, and the width increases as it approaches the first pad pattern 120A. Each of the second line patterns 125B extends along the second direction II, and increases in width as it approaches the second pad pattern 120B. Accordingly, at the first end of each of the first line patterns 125A adjacent to the first pad pattern 120A and at the first end of each of the second line patterns 125B adjacent to the second pad pattern 120B The resistance may be lower than in the embodiment shown in FIG. 3 . As a result, the RC delay may be improved by reducing the resistance of the first end of each of the first and second line patterns 125A and 125B, and the memory cell connected to the first and second line patterns 125A and 125B. can increase their operating speed.

In the above, the first conductive pattern CP_A and the second conductive pattern CP_B are separated through the slit 181 .

4B and 4C , the first conductive pattern CP_A illustrated in FIG. 4A is spaced apart and stacked along a third direction perpendicular to the first and second directions. The first conductive pattern CP_A may be alternately stacked with the first interlayer insulating layer ILD_A in the third direction. The first interlayer insulating layer ILD_A is disposed between adjacent first conductive patterns CP_A to insulate between the first conductive patterns CP_A disposed on different layers.

The second conductive patterns CP_B shown in FIG. 4A are spaced apart and stacked along the third direction. The second conductive pattern CP_B may be alternately stacked with the second interlayer insulating layer ILD_B in the third direction. The second interlayer insulating layer ILD_B is disposed between adjacent second conductive patterns CP_B to insulate between the second conductive patterns CP_B disposed on different layers.

Each of the first line patterns 125A of the first conductive pattern CP_A may surround the straight-type first through structure TH_A, and each of the second line patterns 125B of the second conductive pattern CP_B. Silver may surround the straight-type second through structure TH_B. The first through structure TH_A and the second through structure TH_B extend in the third direction.

The first through structure TH_A is disposed inside the first hole 171A penetrating through each of the first line patterns 125A and the first interlayer insulating layer ILD_A, and the second through structure TH_B has the second line It may be disposed inside the second hole 171B passing through each of the patterns 125B and the second interlayer insulating layer ILD_B.

The first through structure TH_A may include a first multilayer layer 173A, a first channel pillar 175A, a first core insulating layer 177A, and a first capping conductive layer 179A. The first multilayer film 173A may include a memory film. The first multilayer film 173A may further include a charge blocking film surrounding the outer wall of the memory film. The first multilayer film 173A may further include a tunnel insulating film surrounding the first channel column 175A and disposed between the memory film and the first channel column 175A. The first multilayer film 173A is formed on the sidewall of the first hole 171A. The memory layer may be formed of a silicon nitride layer capable of charge trapping. The charge blocking layer may include a silicon oxide layer. The tunnel insulating layer may include a silicon oxide layer. The first channel column 175A may be formed in a tubular shape along the sidewall shape of the first hole 171A. The first channel pillar 175A is formed on the first multilayer film 173A. The first channel column 175A is used as a channel film and may be formed of a semiconductor film such as a silicon film. When the first channel pillar 175A is formed in a tubular shape, a central region of the first channel pillar 175A may be filled with a stacked structure of the first core insulating layer 177A and the first capping conductive layer 179A. The first core insulating layer 177A may be formed to have a height lower than that of the first hole 171A, and the first capping conductive layer 179A may be disposed on the first core insulating layer 177A. The first capping conductive layer 179A may be formed of doped polysilicon. When the first channel pillar 175A is formed in a buried shape that completely fills the central region of the first hole 171A, the first core insulating layer 177A and the first capping conductive layer 179A may be omitted.

The second through structure TH_B may have the same structure as the first through structure TH_B. In detail, the second through structure TH_B may include a second multilayer film 173B, a second channel pillar 175B, a second core insulating film 177B, and a second capping conductive film 179B. The second multilayer film 173B may include a memory film. The second multilayer film 173B may further include a charge blocking film surrounding the outer wall of the memory film. The second multilayer film 173B may further include a tunnel insulating film surrounding the second channel column 175B and disposed between the memory film and the second channel column 175B. The second multilayer film 173B is formed on the sidewall of the second hole 171B. The second channel pillar 175B may be formed in a tubular shape along the sidewall shape of the second hole 171B. The second channel pillar 175B is formed on the second multilayer film 173B. The second channel column 175B is used as a channel film and may be formed of a semiconductor film such as a silicon film. When the second channel pillar 175B is formed in a tubular shape, a central region of the second channel pillar 175B may be filled with a stacked structure of the second core insulating layer 177B and the second capping conductive layer 179B. The second core insulating layer 177B may be formed to have a height lower than that of the second hole 171B, and the second capping conductive layer 179B may be disposed on the second core insulating layer 177B. The second capping conductive layer 179B may be formed of doped polysilicon. When the second channel pillar 175B is formed in a buried shape that completely fills the central region of the second hole 171B, the second core insulating layer 177B and the second capping conductive layer 179B may be omitted.

The first width WA of the stacked structure of the first line pattern 125A surrounding the first through structure TH_A and the second width WB of the stacked structure of the second line pattern 125B surrounding the second through structure TH_B ) may be changed according to the separation distance from the first pad pattern 120A or the second pad pattern 120B illustrated in FIG. 4A . The stacked structure of the first line pattern 125A and the stacked structure of the second line pattern 125B may be separated by the slit 181 and the slit insulating layer 185 filling the inside of the slit 181 . The slit 181 and the slit insulating layer 185 may be disposed between the first interlayer insulating layer ILD_A and the second interlayer insulating layer ILD_B.

The structure shown in FIG. 4B may be applied to the straight-type cell string shown in FIG. 2A. More specifically, referring to FIG. 4B , the stacked structure of the first line pattern 125A and the stacked structure of the second line pattern 125B may be the line patterns LP illustrated in FIG. 2A . The first channel pillar 175A penetrating through the stacked structure of the first line pattern 125A and the second channel pillar 175B passing through the stacked structure of the second line pattern 125B are of the straight type shown in FIG. 2A . It may be a channel column (CH). In this case, the first and second channel pillars 175A and 175B are common to the source layer SL disposed under the stacked structure of the first line pattern 125A and the stacked structure of the second line pattern 125B. can be connected

The structure shown in FIG. 4C may be applied to the U-type cell string shown in FIG. 2B . More specifically, referring to FIG. 4C , the stacked structure of the first line pattern 125A is the source side line patterns LP_S illustrated in FIG. 2B , and the stacked structure of the second line pattern 125B is illustrated in FIG. 2B . drain side line patterns LP_D. The first channel pillar 175A passing through the stacked structure of the first line pattern 125A is the source side channel pillar S_CH shown in FIG. 2B , and the second channel pillar 175A passing through the stacked structure of the second line pattern 125B is The channel pillar 175B may be the drain side channel pillar D_CH shown in FIG. 2B . In this case, the semiconductor device passes through the pipe gate PG and the pipe gate PG disposed under the stacked structure of the first line pattern 125A and the stacked structure of the second line pattern 125B to penetrate the first and second structures. A pipe through structure TH_P connecting at least one pair of the through structures TH_A and TH_B may be further included.

The pipe gate PG may be formed in a stacked structure of the first and second pipe gates PG1 and PG2 . The pipe gate PG may be penetrated by the pipe hole 171P.

The pipe hole 171P connects vertical portions extending from the first hole 171A and the second hole 171B passing through the second pipe gate PG2, and connecting the vertical portions to form the first pipe gate PG1. It may include a penetrating horizontal portion. A pipe through structure TH_P is disposed in the pipe hole 171P.

The pipe through structure TH_P may include a third multilayer film 173P, a pipe channel film 175P, and a third core insulating film 177P. The third multilayer film 173P connects the first and second multilayer films 173A and 173B and is formed on the surface of the pipe hole 171P. The first to third multilayer films 173A, 173B, and 173P may be an integrated liner film. The pipe channel layer 175P connects at least a pair of the first and second channel pillars 175A and 175B, and is formed on the third multilayer layer 173P. The pipe channel layer 175P and the first and second channel pillars 175A and 175B connected thereto may be an integrated liner layer. The third core insulating layer 177P connects the first and second core insulating layers 177A and 177B and may fill a central region of the pipe channel layer 175P. The first to third core insulating layers 177A, 177B, and 177P may be formed in an integrated pattern.

5 and 6 are plan views for explaining various arrangements of channel pillars penetrating the line pattern.

5 and 6 , a semiconductor device according to an embodiment of the present invention includes a first conductive pattern CP_A′ or CP_A″ and a second conductive pattern CP_B′ or CP_B″ as described above with reference to FIG. 4A . may include The first conductive pattern CP_A′ or CP_A″ and the second conductive pattern CP_B′ or CP_B″ may be separated by a slit 181 ′ or 181″ as described above with reference to FIG. 4A .

The first conductive pattern CP_A′ or CP_A″ is the same as described above with reference to FIG. 4A , the first pad pattern 120A′ or 120A″ and a first line pattern extending from the first pad pattern 120A′ or 120A″. 125A' or 125A". The second conductive pattern CP_B′ or CP_B″ is the same as described above with reference to FIG. 4A , the second line pattern extending from the second pad pattern 120B′ or 120B″ and the first pad pattern 120B′ or 120B″. 125B′ or 125B″. In order to improve the RC delay to increase the operation speed of memory cells connected to the first line patterns 125A′ or 125A″ and the second line patterns 125B′ or 125B″, the first line patterns 125A′ Alternatively, the width of the first pad pattern 120A' or 120A" may be increased as the width of the 125A" is increased, and the width of the second line patterns 125B' or 125B" may be increased as the width of the second pad pattern 120B' or 120A" is increased. 120B") can be widened.

Each of the first line patterns 125A′ or 125A″ may be penetrated by the first through structures TH_A′ or TH_A″, and each of the second line patterns 125B′ or 125B″ may pass through the second through structures TH_A′ or TH_A″. structures TH_B′ or TH_B″.

5 , each of the first line patterns 125A' surrounds the first through structures TH_A' in two rows, and each of the second line patterns 125B' has a second through structure in two rows. It is possible to wrap the TH_B'. Alternatively, as shown in FIG. 6 , each of the first line patterns 125A″ surrounds the first through structures TH_A″ of two or more rows (eg, four rows), and the second line patterns ( Each of 125B″) may surround the second through structures TH_B″ in two or more rows (eg, four rows).

Each of the first through structures TH_A′ or TH_A″ illustrated in FIGS. 5 and 6 may include a first channel column as described above with reference to FIGS. 4B and 4C , and the second through structures TH_B′ Alternatively, each of TH_B") may include a second channel column as described above with reference to FIGS. 4B and 4C. The first through structures TH_A′ or TH_A″ and the second through structures TH_B′ or TH_B″ may be arranged in a zigzag shape to improve integration.

7 is a view for explaining a laminated structure of a pad pattern. The stacked structure of the pad pattern illustrated in FIG. 7 may be a stacked structure of the first pad pattern or the stacked structure of the second pad pattern.

Referring to FIG. 7 , pad patterns 120_1 to 120_4 according to embodiments of the present invention may be stacked to form a step structure. Each of the pad patterns 120_1 to 120_4 may be connected to a line pattern 115_1 to 115_4 disposed on the same layer to transmit a signal from the row decoder to the line patterns 115_1 to 115_4. have.

The pad patterns 120_1 to 120_4 extend along the first direction I, and the line patterns 115_1 to 115_4 extend along the second direction II. The pad patterns 120_1 to 120_4 are spaced apart and stacked along the third direction III perpendicular to the first and second directions I and II, and form a step structure. Contact plugs CT_1 to CT_4 extending along the third direction III may contact the pad patterns 120_1 to 120_4 stacked in a step structure. The pad patterns 120_1 to 120_4 may be electrically connected to the row decoder via the contact plugs CT_1 to CT_4 .

8A to 8D are cross-sectional views illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the present invention.

Referring to FIG. 8A , a stacked structure in which first material layers 201 and second material layers 203 are alternately stacked is formed. Although not shown in the drawings, the stacked structure may be formed on the source layer or on the pipe gate penetrated by the pipe hole filled with the sacrificial material.

The second material layers 203 define regions in which conductive patterns are to be disposed, and the first material layers 201 define regions in which interlayer insulating layers are disposed. The second material layers 203 are formed of a material different from that of the first material layers 201 .

For example, the first material layers 201 may be formed of an insulating material for an interlayer insulating layer, and the second material layers 203 may be formed of a conductive material for a conductive pattern.

Alternatively, the first material layers 201 may be formed of an insulating material for an interlayer insulating layer, and the second material layers 203 may be formed of a sacrificial insulating material having an etch selectivity with respect to the first material layers 201 . have. In this case, the first material layers 201 may be formed of a silicon oxide layer, and the second material layers 203 may be formed of a silicon nitride layer. When both the first and second material layers 201 and 203 are formed of an insulating material, the difficulty of etching processes for forming the holes 211 and the slit may be reduced.

Alternatively, the second material layers 203 are formed of a conductive material for a conductive pattern, and the first material layers 201 are formed of a sacrificial conductive material having an etch selectivity with respect to the second material layers 203 . can be In this case, the first material layers 201 may be formed of an undoped silicon layer, and the second material layers 203 may be formed of a doped silicon layer.

Subsequently, the first material layers 201 and the second material layers 203 are etched to form holes 211 passing therethrough. The holes 211 may expose a source layer (not shown) or a sacrificial object (not shown) inside the pipe hole. When the sacrificial object inside the pipe hole is exposed, the sacrificial object may be removed through the holes 211 to open the pipe hole.

Subsequently, although not shown in the drawings, the first material layers 201 and the second material layers 203 may be etched in a step structure in order to define the pad patterns as a step structure.

Thereafter, a multilayer film 213 including a memory film may be formed on sidewalls of the holes 211 . The multilayer film 213 may be formed in a stacked structure of a charge blocking film, a memory film, and a tunnel insulating film. Each of the charge blocking layer, the memory layer, and the tunnel insulating layer may be a liner layer that conforms to the shape of the sidewalls of the holes 211 . After the multilayer film 213 is formed, a channel film 215 may be formed. The channel layer 215 is formed of a semiconductor material such as silicon. The channel film 215 may be formed in a buried type that completely fills the inside of the holes 211 , or may be formed in a tubular shape on the surface of the multilayer film 213 without completely filling the inside of the holes 211 . When the channel film 215 is formed in a tubular shape, a central region of the tubular channel film 215 may be filled with the core insulating film 217 .

When the pipe hole is opened, the multilayer film 213 , the channel film 215 , and the core insulating film 217 may extend to the inside of the pipe hole. The multilayer film 213 , the channel film 215 , and the core insulating film 217 may be planarized.

Referring to FIG. 8B , a portion of the core insulating layer 217 may be etched to lower the height of the core insulating layer 217 . Thereafter, the region from which the core insulating layer 217 is removed may be filled with a capping conductive layer 219 . The capping conductive layer 219 may contact the tubular channel layer 215 . The capping conductive layer 219 may be formed of a doped polysilicon layer.

Referring to FIG. 8C , the first and second material layers 201 and 203 are formed through the first and second material layers 201 and 203 to form a first stacked body ST_A and a second stacked body ST_B. ) to form a slit 221 to separate. The slit 221 may be formed in the same layout as that of the slits shown in FIGS. 4A, 5 and 6 .

When the first material layers 201 are formed of an insulating material for an interlayer insulating layer and the second material layers 203 are formed of a conductive material for a conductive pattern, the second material layers 203 of the first stacked body ST_A ) may be used as the first conductive pattern described above with reference to FIGS. 4A, 5 and 6 , and the second material layers 203 of the second stack body ST_B are described with reference to FIGS. 4A , 5 and 6 . It may be used as a second conductive pattern. In addition, each of the first material layers 201 may be separated into a first interlayer insulating layer and a second interlayer insulating layer by a slit 221 .

Referring to FIG. 8D , when the first material layers 201 are formed of an insulating material for an interlayer insulating layer and the second material layers 203 are formed of a sacrificial insulating material, the second material layers are formed through the slit 221 . (203) can be removed. Subsequently, the region from which the second material layers 203 are removed may be filled with a conductive material to form first and second conductive patterns CP_A and CP_B. The first conductive patterns CP_A are disposed in a region from which the second material layers 203 of the first stacked body ST_A have been removed, and the second conductive patterns CP_B are formed on the second stacked body ST_B. The second material layers 203 are disposed in the removed region. Each of the first material layers 201 may be separated into a first interlayer insulating layer ILD_A and a second interlayer insulating layer ILD_B by a slit 221 .

Although not shown in the drawings, when the first material layers 201 are formed of a sacrificial conductive material and the second material layers 203 are formed of a conductive pattern conductive material, the first material is passed through the slit 221 . The films 201 may be removed. Subsequently, the region from which the first material layers 201 are removed may be filled with an insulating material to form first and second interlayer insulating layers. The first interlayer insulating layers are disposed in a region from which the first material layers 201 of the first stack body ST_A are removed, and the second interlayer insulating layers are the first material layers 201 of the second stack body ST_B. It is placed in the removed area. Each of the second material layers 203 may be separated into first conductive patterns and second conductive patterns by a slit 221 . Specifically, the second material layers 203 of the first stacked body ST_A may be used as the first conductive patterns described above with reference to FIGS. 4A, 5 and 6 , and the second material layers 203 of the second stacked body ST_B The material layers 203 may be used as the second conductive pattern described above with reference to FIGS. 4A, 5 and 6 .

After that, the slit 221 is filled with a slit insulating film 223 .

9 is a block diagram illustrating a memory system according to an embodiment of the present invention.

Referring to FIG. 9 , a memory system 1100 according to an embodiment of the present invention includes a memory device 1120 and a memory controller 1110 .

The memory device 1120 may include a pad pattern extending in a first direction, and line patterns extending from the pad pattern in a second direction intersecting the first direction and having a wider width as the pad pattern approaches the pad pattern. . Also, the memory device 1120 may be a multi-chip package including a plurality of flash memory chips.

The memory controller 1110 is configured to control the memory device 1120 , and may include an SRAM 1111 , a CPU 1112 , a host interface 1113 , an ECC 1114 , and a memory interface 1115 . The SRAM 1111 is used as an operation memory of the CPU 1112 , the CPU 1112 performs various control operations for data exchange of the memory controller 1110 , and the host interface 1113 is connected to the memory system 1100 . The host's data exchange protocol is provided. In addition, the ECC 1114 detects and corrects errors included in data read from the memory device 1120 , and the memory interface 1115 interfaces with the memory device 1120 . In addition, the memory controller 1110 may further include a ROM for storing code data for interfacing with the host.

As described above, the memory system 1100 having the configuration may be a memory card or a solid state disk (SSD) in which the memory device 1120 and the controller 1110 are combined. For example, when the memory system 1100 is an SSD, the memory controller 1110 is external (eg, through one of various interface protocols such as USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI, IDE, etc.) For example, it can communicate with the host).

10 is a block diagram illustrating a computing system according to an embodiment of the present invention.

Referring to FIG. 10 , a computing system 1200 according to an embodiment of the present invention includes a CPU 1220 , a RAM 1230 , a user interface 1240 , a modem 1250 , and a memory electrically connected to a system bus 1260 . system 1210 . In addition, when the computing system 1200 is a mobile device, a battery for supplying an operating voltage to the computing system 1200 may be further included, and an application chipset, a camera image processor (CIS), a mobile DRAM, and the like may be further included. .

As described with reference to FIG. 9 , the memory system 1210 may include a memory device 1212 and a memory controller 1211 .

Although the technical idea of the present invention has been specifically recorded according to the above preferred embodiments, it should be noted that the above-described embodiments are for explanation and not for limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical spirit of the present invention.

CP_A, CP_A', CP_A": first conductive pattern
CP_B, CP_B', CP_B": second conductive pattern
120A, 120A', 120A": first pad pattern 125A, 125A', 125A": first line pattern
120B, 120B', 120B": second pad pattern 125B, 125B', 125B": second line pattern
ILD_A: first interlayer insulating film ILD_B: second interlayer insulating film
175A: first channel column 175B: second channel column
SL: source film PG: pipe gate
P_CH, 175P: pipe channel membrane

Claims (17)

A first pad pattern extending in a first direction, and a first line pattern extending from the first pad pattern in a second direction crossing the first direction and having a wider width as it approaches the first pad pattern first conductive patterns including and stacked spaced apart from each other; and
A semiconductor device comprising: first interlayer insulating layers disposed between adjacent first conductive patterns. ◈Claim 2 was abandoned when paying the registration fee.◈ The method of claim 1,
The semiconductor device further comprising: first channel pillars penetrating the first line patterns and the first interlayer insulating layers. ◈Claim 3 was abandoned when paying the registration fee.◈ 3. The method of claim 2,
Each of the first line patterns surrounds the first channel pillars in one or more rows. ◈Claim 4 was abandoned when paying the registration fee.◈ 3. The method of claim 2,
The first channel pillars are disposed in a zigzag shape. ◈Claim 5 was abandoned when paying the registration fee.◈ The method of claim 1,
The first pad patterns are stacked to form a step structure. ◈Claim 6 was abandoned when paying the registration fee.◈ The method of claim 1,
a second pad pattern facing the first pad pattern with the first line patterns interposed therebetween and extending in the first direction, and the second pad pattern extending from the second pad pattern in the second direction second conductive patterns having second line patterns alternately disposed with the first line patterns and disposed on the same layer as the first conductive patterns; and
The semiconductor device further comprising: second interlayer insulating layers disposed between the adjacent second conductive patterns. ◈Claim 7 was abandoned when paying the registration fee.◈ 7. The method of claim 6,
The semiconductor device further comprising second channel pillars penetrating the second line patterns and the second interlayer insulating layers. ◈Claim 8 was abandoned when paying the registration fee.◈ 8. The method of claim 7,
Each of the second line patterns surrounds the second channel pillars in one or more rows. ◈Claim 9 was abandoned at the time of payment of the registration fee.◈ 8. The method of claim 7,
The second channel pillars are disposed in a zigzag shape. ◈Claim 10 was abandoned when paying the registration fee.◈ 7. The method of claim 6,
An end of each of the first line patterns adjacent to the first pad pattern is formed to have a wider width than an end of each of the second line patterns adjacent to the first pad pattern. ◈Claim 11 was abandoned when paying the registration fee.◈ 7. The method of claim 6,
An end of each of the first line patterns adjacent to the second pad pattern is formed to have a narrower width than an end of each of the second line patterns adjacent to the second pad pattern. ◈Claim 12 was abandoned when paying the registration fee.◈ 7. The method of claim 6,
first channel pillars passing through the first line patterns and the first interlayer insulating layers; and
The semiconductor device further comprising second channel pillars penetrating the second line patterns and the second interlayer insulating layers. ◈Claim 13 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
The semiconductor device further comprising a source layer disposed under the first and second conductive patterns and commonly connected to the first channel pillars and the second channel pillars. ◈Claim 14 was abandoned when paying the registration fee.◈ 13. The method of claim 12,
a pipe gate disposed under the first and second conductive patterns; and
and a pipe channel layer buried in the pipe gate to connect at least one pair of the first channel pillars and the second channel pillars. ◈Claim 15 was abandoned when paying the registration fee.◈ 7. The method of claim 6,
The second pad patterns are stacked to form a step structure. a first pad pattern extending in a first direction; and
and first line patterns extending from the first pad pattern in a second direction intersecting the first direction, the width of which becomes wider as it approaches the first pad pattern,
The first pad pattern and the first line patterns constitute a conductive pattern connected to a memory cell array. ◈Claim 17 was abandoned when paying the registration fee.◈ 17. The method of claim 16,
a second pad pattern facing the first pad pattern with the first line patterns interposed therebetween and extending in the first direction; and
The semiconductor device further includes second line patterns extending from the second pad pattern in the second direction, the width of which increases as the second pad pattern approaches, and the second line patterns are alternately arranged with the first line patterns. .

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