P960071 24879twf.doc/p 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種記憶體結構及其陣列，且特別是 有關於一種非揮發記憶體結構及其陣列。 【先前技術】 非揮發性記憶體中的可電抹除可程式唯讀記憶體 (electrically erasable programmable read only memory » EEPROM)具有可進行多次資料之存入、讀取、抹除等動 作’且存入之資料在斷電後也不會消失之優點，所以已成 為個人電腦和電子設備所廣泛採用的一種記憶體元件。 典型的可電抹除且可程式唯讀記憶體是以摻雜的多晶 石夕製作浮置閘極(floating gate)與控制閘極(c〇mr〇1 gate)。當 記憶體進行程式化(program)時，注入浮置閘極的電子會均 勻分布於整個多晶矽浮置閘極層之中。 此外，目前習知的還有一種可電抹除且可程式唯讀記 憶體是採用電翻人層取代彡㈣浮置雜，此電荷陷入 層的材質例如是氮化矽。這種氮化矽電荷陷入層上下通常 各有一層氧化矽，而形成一種包含氧化矽/氮化矽/氧化矽 (〇N〇)複合介電層在内的堆疊式(stacked)閘極結構。 、^在上述習知的記憶體之通道區四周的基底上，具有用 以=離摻雜區或相鄰兩條字元線的氧化雜離、 方或相鄰兩條字元線之間的基底上。然而乂 、。己憶體在電性的表現上具有讀取電流低、互導 tmnscondUctance，GM)較差程式化速度慢及資料保存時 1342068 P960071 24879twf.doc/p 間短等缺點。 此外位;純上扣氧化 = =，ethod)等複雜的製造二在= 降低產〇口的生產效率及良率。 【發明内容】 有鑑於此，本發明的目的就是在提供一種非揮發記憶 體結構，可有效地降低製程的複雜度。 心 本發_另-目的是提供—種非揮發記憶體陣列，農 有較佳的電性表現。 〃 田本發明提出-種非揮發記憶體結構，包括基底、多個 堆豐圖案及？個應力圖案。堆疊圖案配置於基底上，各個 堆疊圖案由下社包括電荷儲存結構及酿，其中電荷儲 存結構至少包括電⑽存層。應力_分別 個堆疊圖案之間的基底上。 依照本發明的-實施例所述，在上述之 結構中，更包括多轉㈣，其分觀置於各個堆疊圖1 兩側的基底中。 〃 依照本發明的一實施例所述，在上述之非揮發記憶體 結構中，當摻雜區為NS摻料，應力圖案的材料包括拉 伸應力（tensile stress)材料。 依照本發明的一實施例所述，在上述之非揮發記憶體 結構中，當摻雜區為P型摻雜時，應力圖案的材料包括壓 縮應力（compressive stress)材料。 依照本發明的一實施例所述，在上述之非揮發記憶體 P960071 24879twf.doc/p 結構中，電韻存層的材料包括彳錄乡晶錢氮化石夕。 依照本發明的-實施例所述，在上述之非揮發記憶體 結構中’應力圖案的材料包括氮化石夕。 依照本發明的一實施例所述，在上述之非揮發記憶體 結構中，應力圖案的寬度等於相鄰兩個堆疊圖案^間^距 離。 本發明提出一種非揮發記憶體陣列，包括基底、多個 隔離圖案、多個摻雜區、多條字元線以及多個堆疊圖案。 隔離圖案彼此平行配置於基底上且沿著第一方向延伸，且 隔離圖案的讨料為一應力材料。摻雜區分別配置於隔離圖 案下方的基底中1'字元線彼此平行配置於隔離圖案上且沿 著第二方向延伸，而第一方向與第二方向相交。堆疊圖案 分別配置字元線下方的相鄰兩個隔離圖案之間的基底上，' 且在第〆方雨上的相鄰兩個堆疊圖案之間具有開口。各個 堆疊圖索由下而上包括電荷儲存結構及閘極，其中電荷儲 存結構炱少包括一電荷儲存層。 依照本發明的一實施例所述，在上述之非揮發記憶體 陣列中，電荷儲存層的材料包括摻雜多晶矽或氮化矽。 依照本發明的一實施例所述，在上述之非揮發記憶體 陣列中，應力材料包括氮化矽° 依照本發明的一實施例所述，在上述之非揮發記憶體 陣列中，當摻雜區為N型摻雜時，應力材料包括拉伸應力 材料。 依照本發明的一實施例所述，在上述之非揮發記憶體 1342068 P960071 24879twf.doc/p 陣列中，當摻雜區為P型摻雜時，應力材料包括壓縮應力 材料。 依照本發明的—實施例所述，在上述之非揮發記憶體 陣列中，更包括介電層，其配置於基底上並填滿開口。 依照本發明的一實施例所述，在上述之非揮發 陣列中：介電層的材料包括應力材料。 ㈣ 依知、本發明的—實施例所述，在上述之非揮發 =之的寬度等於在第二方向上的相鄰；堆 個提出另—種非揮發記憶體陣列’包括基底、多 =案;個摻雜區、多條字元線、多個堆疊圖案以 ,,a隔離圖案彼此平行配置於基底上且沿著第 -方向隔離圖案上且沿著第二方向延伸，而第 相鄰兩個相交。堆疊圖案分別配置字元線下方的 兩個堆疊圖荦二=基底乞，且在第-方向上的相鄰 電荷儲存堆疊圖案由下而上包括 儲存層。二荷儲存結構至少包括一電荷 料為應力材料於基底上並填糾σ，且介電層的材 體陣3本實施例所述，在上述之非揮發記憶 依照本“的：二：材料包括摻雜多晶矽或氮化矽。 體陣列中，應力材。=述’在上述之非揮發記憶 1342068 P960071 24879twf.doc/p 依照本發明的另一實施例所述， 體陣列中，當摻雜區為N型摻雜時， 力材料。 依照本發明的另一實施例所述， 體陣列中，當摻雜區為p型摻雜時， 力材料。P960071 24879twf.doc/p IX. Description of the Invention: [Technical Field] The present invention relates to a memory structure and an array thereof, and more particularly to a non-volatile memory structure and an array thereof. [Prior Art] The electrically erasable programmable read only memory (EEPROM) in non-volatile memory has the functions of storing, reading, erasing, etc., multiple times. The stored data does not disappear after power failure, so it has become a memory component widely used in personal computers and electronic devices. A typical electrically erasable and programmable read-only memory is a floating gate and a control gate (c〇mr〇1 gate) with doped polycrystalline silicon. When the memory is programmed, the electrons injected into the floating gate are evenly distributed throughout the polysilicon floating gate layer. In addition, there is also an electrically erasable and programmable read-only memory that replaces the 彡(4) floating impurity with an electric turnover layer, and the material of the charge trapping layer is, for example, tantalum nitride. The tantalum nitride charge trapping layer usually has a layer of tantalum oxide on top of each other to form a stacked gate structure including a tantalum oxide/tantalum nitride/yttria (〇N〇) composite dielectric layer. And on the substrate around the channel region of the above-mentioned conventional memory, having an oxidized impurity, a square or an adjacent two word line between the doped region or the adjacent two word lines. On the substrate. However, 乂,. In the electrical performance, the memory has low short reading current, mutual conductance tmnscondUctance, GM), slow programming speed and short time between data saving 1342068 P960071 24879twf.doc/p. In addition to the position; purely deductive oxidation = =, ethod) and other complex manufacturing two = reduce the production efficiency and yield of the sputum. SUMMARY OF THE INVENTION In view of the above, it is an object of the present invention to provide a non-volatile memory structure that can effectively reduce the complexity of the process. The heart of this hair _ another - the purpose is to provide a non-volatile memory array, the agricultural has better electrical performance. 〃 Tian The present invention proposes a non-volatile memory structure, including a substrate, a plurality of stacking patterns, and Stress patterns. The stacked pattern is disposed on the substrate, and each of the stacked patterns comprises a charge storage structure and a brewing, wherein the charge storage structure comprises at least an electric (10) storage layer. The stress _ is on the substrate between the stacked patterns. According to the embodiment of the present invention, in the above structure, a plurality of revolutions (four) are further included, which are placed in the substrates on both sides of each of the stacked layers. In accordance with an embodiment of the present invention, in the non-volatile memory structure described above, when the doped region is NS doped, the material of the stress pattern includes a tensile stress material. According to an embodiment of the invention, in the non-volatile memory structure described above, when the doped region is P-type doped, the material of the stress pattern comprises a compressive stress material. According to an embodiment of the present invention, in the above non-volatile memory P960071 24879 twf.doc/p structure, the material of the electromagnet storage layer includes the 晶 乡 乡 晶 晶 晶 晶 晶 晶In accordance with the embodiment of the present invention, the material of the 'stress pattern' in the non-volatile memory structure described above includes nitrite. According to an embodiment of the invention, in the non-volatile memory structure described above, the width of the stress pattern is equal to the distance between two adjacent stacked patterns. The present invention provides a non-volatile memory array comprising a substrate, a plurality of isolation patterns, a plurality of doped regions, a plurality of word lines, and a plurality of stacked patterns. The isolation patterns are disposed on the substrate in parallel with each other and extend along the first direction, and the spacer pattern is a stress material. The doped regions are respectively disposed in the substrate below the isolation pattern, and the 1' word lines are arranged parallel to each other on the isolation pattern and extend in the second direction, and the first direction intersects the second direction. The stacked pattern is respectively disposed on the substrate between adjacent two isolation patterns below the word line, and has an opening between adjacent two stacked patterns on the third side of the rain. Each of the stacked patterns includes a charge storage structure and a gate from bottom to top, wherein the charge storage structure comprises a charge storage layer. According to an embodiment of the invention, in the non-volatile memory array described above, the material of the charge storage layer comprises doped polysilicon or tantalum nitride. According to an embodiment of the present invention, in the non-volatile memory array, the stress material comprises tantalum nitride. According to an embodiment of the invention, in the non-volatile memory array, when doping When the region is N-doped, the stress material includes a tensile stress material. According to an embodiment of the invention, in the non-volatile memory 1342068 P960071 24879 twf.doc/p array, when the doped region is P-doped, the stress material comprises a compressive stress material. In accordance with an embodiment of the present invention, in the non-volatile memory array described above, a dielectric layer is further disposed on the substrate and filled with openings. According to an embodiment of the invention, in the non-volatile array described above, the material of the dielectric layer comprises a stress material. (4) According to the knowledge, in the embodiment of the present invention, the width of the above non-volatile = equal to the adjacent in the second direction; the stack of the other non-volatile memory array 'including the substrate, more = case a doped region, a plurality of word lines, a plurality of stacked patterns, and a isolation patterns are disposed on the substrate in parallel with each other and along the first-direction isolation pattern and along the second direction, and the adjacent two Intersect. The stacked patterns respectively configure two stacked patterns below the word line 乞 = substrate 乞, and adjacent charge storage stacked patterns in the first direction include a storage layer from bottom to top. The second charge storage structure comprises at least one charge material on the substrate and filled with σ, and the dielectric layer 3 of the dielectric layer is described in the embodiment, and the non-volatile memory in the above is in accordance with the "2: material: Doped polysilicon or tantalum nitride. In the bulk array, stress material. = described in the above non-volatile memory 1342068 P960071 24879twf.doc / p in accordance with another embodiment of the present invention, in the body array, when doped regions When N-doped, the force material. According to another embodiment of the present invention, in the bulk array, when the doped region is p-type doped, the force material.
基於上述，在本發明所提出的非揮發記憶體及其陣列 中，由於在相鄰兩個堆疊圖案之_基底上配置有應力圖 案，而此應力_會施加應力於基底上，會使得非揮發性 記憶體及其_在電㈣表現上具有讀取電流高、互ί較 佳、程式化速度快及資料保存時間長等優點。 此外，藉由本發明所提出的非揮發記憶體及其陣列可 有效地降低製程的複雜度，進而提升產品的生產效率。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易〖董，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 V。Based on the above, in the non-volatile memory and the array thereof proposed by the present invention, since the stress pattern is disposed on the substrate of the adjacent two stacked patterns, the stress _ exerts stress on the substrate, which makes the non-volatile Sexual memory and its _ have the advantages of high read current, good mutual ac, high stylization speed and long data storage time. In addition, the non-volatile memory and the array thereof proposed by the invention can effectively reduce the complexity of the process, thereby improving the production efficiency of the product. The above and other objects, features, and advantages of the present invention will become more apparent. V.
在上述之非揮發記憶 應力材料包括拉伸應 在上述之非揮發記憶 應力材料包括壓縮應 【實施方式】 圖1所繪示為本發明第一實施例到第三實施例之非揮 發§己憶體陣列的上視圖。圖2所繪示為本發明第一實施例 及第二實施例沿圖1中Α-Α，剖面線之非揮發記憶體結構的 剖面圖。圖3所繪示為本發明第一實施例及第三實施例沿 圖1中Β-Β’剖面線之非揮發記憶體結構的剖面圖。圖J中 的非揮發記憶體陣列包括基底1〇〇、隔離圖案1〇2、摻雜區 104、字元線106、堆疊圖案ι〇8以及介電層u〇。圖2中 9 P960071 24879twf.doc/p 的非揮發記憶體結構包括基底100、隔離圖案102、推雜區 104、字元線106、堆疊圖案108以及介電層11〇。圖3中 的非揮發記憶體結構包括基底100、字元線1〇6、維疊圖案 108以及介電層no。 請同時參照圖1至圖3,在第一實施例中，隔離圖案 102彼此平行配置於基底100上且沿著第—方向延伸第 方向例如是X-Y座標平面上的Y方向。隔離圖案102 ^材料為應力材料’如具有應力的氮化矽材料，而使得隔 離圖案102成為具有應力的應力圖案。另外，當摻雜區1〇3 為N型摻雜時，應力材料例如是具有拉申應力的拉伸應力 材料；當摻雜區104為P型摻雜時，應力材料例如是具有 壓縮應力的壓縮應力材料。 〃 此外，隔離圖案102的寬度Wi等於在第二方向上的 ，鄰兩個堆疊圖案⑽之間的距離⑴，其中第二方向例如 =X'座標平面上的X方向。除此之外，關於隔離圖案 2的阿度，於此技術領域具有通常知識者可依照製程 件及需求進行調整。 八 摻雜區104分別配置於隔離圖案102下方的基底1〇〇 。摻雜區104依照記憶體類型的不同需求可為Ν 或是Ρ型摻雜。 夕雜 一 兀綠106彼此平行配置於隔離圖案1〇2上且沿著第 3向延伸，而第—方向與第二方向相交。字元線106的 材枓例如是摻雜多晶矽。 堆豐圖案108分別配置字元線1〇6下方的相鄰兩個隔 1342068 P960071 24879twf.doc/p 離圖案102之間的基底100上，且在第一方向上的相鄰·兩 個堆疊圖案108之間具有開口 112。堆疊圖案舰由下而 上包括電荷儲存結構114及閘極116。閘極116在第二方 向上藉由字元線106互相電性連接，閘極116的材料例如 是摻雜多晶矽。 電荷儲存結構114由下而上包括底介電層118、電荷 儲存層120及頂介電層122。電荷儲存層12〇可用以儲存 電荷，其材料可以是摻雜多晶矽等導體材料或是氮化矽等 電荷陷入材料。底介電層118與頂介電層122可用以阻擋 電荷從電荷儲存層120中流失，其材料例如是氧化矽。 介電層110配置於基底1〇〇上並填滿開口 112，且介 電層110的材料為應力材料，如具有應力的氮化矽材料， 而使得介電層110成為具有應力的應力圖案。另外，當摻 雜區104為N型摻雜時，應力材料例如是具有拉申應力的 拉伸應力材料；當摻雜區1〇4為P型摻雜時，應力材料例 如是具有壓縮應力的壓縮應力材料。此外，位於開口 112 中的介電層110位於第一方向上的相鄰兩個堆疊圖案1〇8 之間的基底100上，且位於開口 112中的介電層11〇的寬 度W2等於在第一方向上的相鄰兩個堆疊圖案1〇8之間的 距離D2。 在上述第一實施例中，於相鄰兩個堆疊圖案1〇8之間 的基底100上配置有應力圖案（隔離圖案丨〇2及位於開口 112中的介電層110)，由於應力圖案可對基底100施加應 力’會使得非揮發性記憶體及其陣列在電性的表現上具有 1342068 P960071 24879twf.doc/p 讀取電流高、互導較佳、程式化速度快及資料保存時間 等優點。 < 此外’第-實施例中以位於摻雜區刚上的隔離圖案 102取代習知技術中位於摻雜區上的氧切隔離圖案，可 以有效地簡化製程’進而提升產品的生產效率。 雖然在第一實施例中是以隔離圖案1〇2與介電層ιι〇 的材料均為應力材料為例進行說明，然而只要隔離圖案 K)2與介電層U0兩者的其中之—的材料為應力材料，在 電性的表現即可獲得明顯地改善。以下，以第二實施例及 第三實施例繼續進行說明。 請同時參照圖1及圖2 ’在第二實施例中，隔離圖案 102的材料為應力材料’使得隔離圖案1〇2成為且有應力 的應力圖案，而介電層110的材料為氧化矽等一般介^材 料。另外，第二實施例之非揮發性記憶體結構中的其他構 件的材料、配置方式及功效與第—實施例中所揭露的内容 大致相同，故於此不再贅述。 由於隔離圖案102分別配置於第二方向上的相鄰兩個 堆疊圖案108之間的基底1〇〇Λ，因此隔離圖案1〇2可對 基底卿施加應力，進而提升非揮發性記憶體的電性效能。 此外，第二實施例+以位則參雜區104上的隔離圖案 102取代習知技術中位於摻雜區上的氧化碎隔離圖案，可 以有效地降低製程複雜度，進而提升產品的生產效率。 凊同時參照圖Ϊ及圖3’在第三實施例中，介電層u〇 的材料為應力材料’使得介電層UG成為具有應力的應力 12 1342068 P960071 24879twf.doc/p 圖案，而隔離圖案102的材料為氧化矽等一般介電材料。 另外，第二實施例之非揮發性記憶體結構中的其他構件的 材料、配置方式及功效與第—實施例中所揭露的内容大致 相同，故於此不再贅述。 由於位於開口 112中的介電層n〇位於第—方向上的 相鄰兩個堆疊圖案108之間的基底100上，因此位於開口 112中的介電層11〇可對基底1〇〇施加應力，進而提升非 揮發性記憶體的電性效能。 綜上所述，上述實施例至少具有下列優點： 1.本發明所提出的非揮發記憶體結構及其陣列可有效 地簡化製程，進而提升產品的生產效率。 2·本發明所提出的非揮發記憶體結構及其陣列具有較 佳的電性表現。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1所繪示為本發明第一實施例到第三實施例之非 發記憶體陣列的上視圖。 ' 圖2所繪示為本發明第一實施例及第二實施例沿圖】 中A-A’剖面線之非揮發記憶體結構的剖面圖。 圖3所繪示為本發明第一實施例及第三實施例沿圖工 中B-B’剖面線之非揮發記憶體結構的剖面圖。 13 1342068 P960071 24879twf.doc/p 【主要元件符號說明】 100 :基底 102 :隔離圖案 104 :摻雜區 106 :字元線 108 :堆疊結構 110 :介電層 112 :開口 114 :電荷儲存結構 116 :閘極 118 :底介電層 120 :電荷儲存層 122 :頂介電層 Dl、D2 :距離 Wl、W2 :寬度The non-volatile memory stress material mentioned above includes stretching, and the non-volatile memory stress material mentioned above includes compression. [Embodiment] FIG. 1 is a non-volatile § recall of the first embodiment to the third embodiment of the present invention. The top view of the volume array. 2 is a cross-sectional view showing the structure of the non-volatile memory of the cross-sectional line of the first embodiment and the second embodiment of the present invention taken along the line 图-Α of FIG. Fig. 3 is a cross-sectional view showing the structure of the non-volatile memory of the first embodiment and the third embodiment of the present invention taken along the line Β-Β' of Fig. 1. The non-volatile memory array of Figure J includes a substrate 1 , an isolation pattern 1 〇 2, a doped region 104, a word line 106, a stacked pattern ι 8 and a dielectric layer u 。. The non-volatile memory structure of 9 P960071 24879 twf.doc/p in Fig. 2 includes a substrate 100, an isolation pattern 102, a dummy region 104, a word line 106, a stacked pattern 108, and a dielectric layer 11A. The non-volatile memory structure of Figure 3 includes a substrate 100, a word line 〇6, a reticle pattern 108, and a dielectric layer no. Referring to Figs. 1 to 3 together, in the first embodiment, the isolation patterns 102 are disposed on the substrate 100 in parallel with each other and extend in the first direction along the first direction, for example, the Y direction on the X-Y coordinate plane. The isolation pattern 102^ material is a stress material such as a tantalum nitride material having stress, so that the isolation pattern 102 becomes a stress pattern having stress. In addition, when the doping region 1〇3 is N-type doped, the stress material is, for example, a tensile stress material having a tensile stress; when the doping region 104 is P-doped, the stress material is, for example, a compressive stress. Compressed stress material. Further, the width Wi of the isolation pattern 102 is equal to the distance (1) between the adjacent two stacked patterns (10) in the second direction, wherein the second direction is, for example, the X direction on the coordinate plane of the X'. In addition to this, the degree of the isolation pattern 2, which is generally known to those skilled in the art, can be adjusted according to the process and the requirements. The eight doped regions 104 are respectively disposed on the substrate 1 下方 under the isolation pattern 102. The doped region 104 may be doped with Ν or Ρ depending on the type of memory. The 106 一 兀 green 106 is disposed parallel to each other on the isolation pattern 1 〇 2 and extends along the third direction, and the first direction intersects the second direction. The material of the word line 106 is, for example, doped polysilicon. The stacking pattern 108 is respectively disposed on the substrate 100 between the adjacent two spacers 1342068 P960071 24879 twf.doc/p under the word line 1〇6, and adjacent to the two stacked patterns in the first direction. There is an opening 112 between 108. The stacked pattern ship includes a charge storage structure 114 and a gate 116 from the bottom. The gates 116 are electrically connected to each other in the second direction by word lines 106. The material of the gates 116 is, for example, doped polysilicon. The charge storage structure 114 includes a bottom dielectric layer 118, a charge storage layer 120, and a top dielectric layer 122 from bottom to top. The charge storage layer 12 can be used to store charges, and the material thereof can be a conductor material such as doped polysilicon or a charge trapping material such as tantalum nitride. The bottom dielectric layer 118 and the top dielectric layer 122 can be used to block the loss of charge from the charge storage layer 120, such as yttrium oxide. The dielectric layer 110 is disposed on the substrate 1 and fills the opening 112, and the material of the dielectric layer 110 is a stress material such as a barium nitride material having stress, so that the dielectric layer 110 becomes a stress pattern with stress. In addition, when the doping region 104 is N-type doped, the stress material is, for example, a tensile stress material having a tensile stress; when the doping region 1〇4 is P-doped, the stress material is, for example, a compressive stress. Compressed stress material. In addition, the dielectric layer 110 located in the opening 112 is located on the substrate 100 between the adjacent two stacked patterns 1〇8 in the first direction, and the width W2 of the dielectric layer 11〇 located in the opening 112 is equal to The distance D2 between adjacent two stacked patterns 1〇8 in one direction. In the first embodiment described above, a stress pattern (the isolation pattern 丨〇 2 and the dielectric layer 110 located in the opening 112) is disposed on the substrate 100 between the adjacent two stacked patterns 1 , 8 due to the stress pattern. Applying stress to the substrate 100 will make the non-volatile memory and its array have an electrical performance of 1342068 P960071 24879twf.doc/p high read current, better mutual conduction, fast programming speed and data retention time. . < Further, in the first embodiment, the isolation pattern 102 located on the doped region is substituted for the oxygen-cut isolation pattern on the doped region in the prior art, which can effectively simplify the process and thereby improve the production efficiency of the product. Although in the first embodiment, the materials of the isolation pattern 1〇2 and the dielectric layer ιι are both stress materials, as long as the isolation pattern K) 2 and the dielectric layer U0 are both The material is a stress material, and the electrical performance can be significantly improved. Hereinafter, the description will be continued with the second embodiment and the third embodiment. Referring to FIG. 1 and FIG. 2 simultaneously, in the second embodiment, the material of the isolation pattern 102 is a stress material such that the isolation pattern 1〇2 becomes a stress pattern with stress, and the material of the dielectric layer 110 is yttrium oxide or the like. General materials. In addition, the materials, arrangement, and functions of the other components in the non-volatile memory structure of the second embodiment are substantially the same as those disclosed in the first embodiment, and thus will not be described again. Since the isolation patterns 102 are respectively disposed on the substrate 1 之间 between the adjacent two stacked patterns 108 in the second direction, the isolation patterns 1 〇 2 can stress the substrate, thereby improving the power of the non-volatile memory. Sexual effectiveness. In addition, the second embodiment + replaces the oxidized fine isolation pattern on the doped region in the prior art by the isolation pattern 102 on the dummy region 104, which can effectively reduce the process complexity and thereby improve the production efficiency of the product. Referring to both FIG. 3 and FIG. 3', in the third embodiment, the material of the dielectric layer u is a stress material' such that the dielectric layer UG becomes a stressed stress 12 1342068 P960071 24879 twf.doc/p pattern, and the isolation pattern The material of 102 is a general dielectric material such as yttrium oxide. In addition, the materials, arrangement, and functions of the other components in the non-volatile memory structure of the second embodiment are substantially the same as those disclosed in the first embodiment, and thus will not be described again. Since the dielectric layer n〇 located in the opening 112 is located on the substrate 100 between the adjacent two stacked patterns 108 in the first direction, the dielectric layer 11 located in the opening 112 can stress the substrate 1〇〇 , thereby improving the electrical performance of non-volatile memory. In summary, the above embodiments have at least the following advantages: 1. The non-volatile memory structure and array thereof proposed by the present invention can effectively simplify the process and thereby improve the production efficiency of the product. 2. The non-volatile memory structures and arrays thereof proposed by the present invention have better electrical performance. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top plan view showing a non-volatile memory array according to first to third embodiments of the present invention. Figure 2 is a cross-sectional view showing the structure of the non-volatile memory of the A-A' hatching in the first embodiment and the second embodiment of the present invention. Fig. 3 is a cross-sectional view showing the structure of a non-volatile memory of the B-B' section line of the first embodiment and the third embodiment of the present invention. 13 1342068 P960071 24879twf.doc/p [Description of main component symbols] 100: substrate 102: isolation pattern 104: doped region 106: word line 108: stacked structure 110: dielectric layer 112: opening 114: charge storage structure 116: Gate 118: bottom dielectric layer 120: charge storage layer 122: top dielectric layer Dl, D2: distance Wl, W2: width