TW200910570A - Multi-chip package with window BGA type - Google Patents

Multi-chip package with window BGA type Download PDF

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Publication number
TW200910570A
TW200910570A TW096132146A TW96132146A TW200910570A TW 200910570 A TW200910570 A TW 200910570A TW 096132146 A TW096132146 A TW 096132146A TW 96132146 A TW96132146 A TW 96132146A TW 200910570 A TW200910570 A TW 200910570A
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Taiwan
Prior art keywords
substrate
wafer
wire
package structure
grid array
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TW096132146A
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Chinese (zh)
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TWI336937B (en
Inventor
Chih-Wei Wu
Hung-Hsin Hsu
Chien-Chi Chan
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Powertech Technology Inc
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Priority to TW096132146A priority Critical patent/TWI336937B/en
Publication of TW200910570A publication Critical patent/TW200910570A/en
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Publication of TWI336937B publication Critical patent/TWI336937B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Wire Bonding (AREA)

Abstract

Disclosed is a multi-chip package with window BGA type, primarily comprising a substrate, a first chip on the substrate, a second chip, an encapsulant and a plurality of solder balls. Therein, the second chip and the solder balls are disposed on a lower surface of the substrate so as to reduce package thickness and achieve the balances of inner stresses and mold flow. In an preferred embodiment, an insulating backside adhesive is formed on backside of the second chip to cover one ends of a plurality of bonding wires electrically connecting the first chip and a plurality of wire-bonded fingers of the substrate so that the bonding fingers are partially encapsulated in advance. Preferably, the wire-bonded fingers and ball pads are located on the lower surface of the substrate to reduce wiring layer(s) and PTH's of the substrate so that the substrate becomes thinner and cost-down.

Description

200910570 九、發明說明：200910570 IX. Invention Description:

型球格陣列（wind 封裝構造，特別係有關 ows ball grid array, WBGA) 之多晶片封裝構造。 【先前技術]A multi-chip package construction of a ball grid array (wind package construction, especially for ows ball grid array, WBGA). [prior art]

窗口型球格陣列（window 導體封裝構造為近年來半導體晶片封裝產品之主流。以 v、有® 口之電路基板承載晶片’並以複數個金屬銲線 穿過窗口以電性連接電路基板與晶片。電路基板之下表 面設置有複數個銲球’藉由該些銲球提供充分數量之輸Window type ball grid array (window conductor package structure is the mainstream of semiconductor chip package products in recent years. The circuit board carries the wafer with v, has a + port and passes through the window with a plurality of metal bonding wires to electrically connect the circuit substrate and the wafer a plurality of solder balls are disposed on the lower surface of the circuit substrate to provide a sufficient amount of losses by the solder balls

性基板且被封膠之晶片得與外界裝置如印刷電路板 (printed circuit board, PCB)構成電性連接關係，以符合 高密度表面接合的需求。然而’半導體封裝構造的高度 會隨著晶片堆疊數量的增加而增加，利用加厚的封裝膠 體以包覆晶片與銲線，而使整體封裝件尺寸難以進一步 細小。然而€封裝膠·體越厚’則與基板兩者熱膨脹係數 的不匹配會產生更嚴重的產品翹曲’並有模流不平衡的 填膠不實的問題’降低了多晶片封裝構造的產品良率與 可靠度。 lw 弟—晶片120、 及複數個銲球丨6 0。 如第1圖所示，一種習知的窗口型球格陣列之多晶 片封裝構造100主要包含一基板110、一第—曰 一第'一晶片130、一封膠體150以 200910570 該基板係110具有一上表面1丨丨、一下表面 窗口之一打線槽孔113，該基板丨10係更具 表面1 1 2之複數個第一打線接指1 1 4以及 1 1 6，以及位於該上表面丨丨丨之複數個第 1 1 4。該第一晶片1 2 〇之第一主動面i 2 i係 板11 0之該上表面111並形成有複數個第一 可利用複數個打線形成之第一銲線丨4 1通 孔1 1 3電性連接該第一晶片1 2 〇之第一銲塾 板1 1 0之該些第一打線接指丨丨4。該第二晶 對背堆疊於該第一晶片1 2 0，藉由一黏晶層 第二晶片1 3 0之第二背面1 3 2與該第一晶片 背面122。該第二晶片no之第二主動面1 數個第二銲墊1 3 3 ’可利用複數個打線形成 M2連接該些第二銲墊133至位於該基板1 1 1 1之第二打線接指1 1 5，故第一晶片1 2 0 皆設於該基板1 1 〇之同一上表面1 1丨。複类 係可設置於該基板1 1 〇之該下表面丨i 2 1 1 6，以供接合至一外部印刷電路板。該封 形成於該基板110之該上表面111與該打續 用以包覆該些晶片1 2 0、1 3 0與該些銲線p 如第1圖所示，以該基板丨丨〇為一水平 封膠體150在該基板11〇之該上表面m 1 1 2的分配量差異非常大，特別是晶片堆疊 該封膠體150在當該基板110之該上表面1 1 1 2及作為 有位於該下 複數個球墊 二打線接指 貼設於該基 -銲墊123， 過該打線槽 ‘ 123與該基 片1 3 0係背 1 7 〇黏貼該 120之第一 3 1形成有複 之第二銲線 1 〇之上表面 與第二晶片 c個銲球1 6 0 之該些球墊 膠體1 5 0係 I槽孔1 1 3， "、142 ° 基準線，該 與該下表面 數量過多， 11的上層厚 6 200910570The substrate and the encapsulated wafer are electrically connected to an external device such as a printed circuit board (PCB) to meet the requirements of high-density surface bonding. However, the height of the semiconductor package structure increases as the number of wafer stacks increases, and the thick package encapsulant is used to coat the wafer and the bonding wires, making the overall package size difficult to further fine. However, the thicker the encapsulating gel is, the mismatch between the thermal expansion coefficients of the substrate and the substrate will result in more severe product warpage and the problem of misfilling of the mold imbalance. 'Reduced product of multi-chip package construction Yield and reliability. Lw brother - wafer 120, and a plurality of solder balls 丨 60. As shown in FIG. 1 , a conventional multi-chip package structure 100 for a window type ball grid array mainly includes a substrate 110 , a first wafer 130 , and a gel 150 for 200910570 . An upper surface 1 丨丨, one of the lower surface windows, the slot 133, the substrate 丨 10 is a plurality of first splicing fingers 1 1 4 and 1 1 6 having a surface 1 1 2 and located on the upper surface 丨The number of the first one is 1 1 4 . The first active surface i 2 i of the first wafer 1 2 is the upper surface 111 of the board 110 and is formed with a plurality of first first bonding wires 丨 4 1 through holes 1 1 3 formed by a plurality of wires The first wire bonding wires 4 electrically connected to the first soldering plate 110 of the first wafer 1 2 . The second pair of crystals are stacked on the first wafer 120, and the second back surface 133 of the second wafer 1300 is bonded to the first wafer back surface 122 by a die bond layer. The second active pad 1 of the second wafer no, the plurality of second pads 1 3 3 ′ can be connected to the second bonding pads 133 by using a plurality of bonding wires 135 to the second bonding fingers located on the substrate 1 1 1 1 1 1 5 , so the first wafer 1 2 0 is disposed on the same upper surface 1 1 该 of the substrate 1 1 . The compound type may be disposed on the lower surface 丨i 2 1 1 6 of the substrate 1 1 以 for bonding to an external printed circuit board. The sealing surface is formed on the upper surface 111 of the substrate 110 and the coating is used to cover the wafers 120 and 130, and the bonding wires p are as shown in FIG. The difference in the distribution amount of the upper surface m 1 1 2 of the horizontal sealing body 150 on the substrate 11 is very large, in particular, the wafer stacking the sealing body 150 is on the upper surface of the substrate 110 and is located as The lower plurality of ball pads and two-wire fingers are attached to the base-pad 123, and the first wire 3 is formed by the wire-slot '123 and the substrate 1 300 back 1 7 〇. The second bonding wire 1 〇 the upper surface and the second wafer c solder balls 160 of the ball mats 150 0 I slot 1 1 3, ", 142 ° reference line, the lower surface Excessive quantity, 11 upper layer thickness 6 200910570

度需要越大，於製程中之溫度變化如基板烘烤 (baking)、封膠體固化（curing)、後續熱循環（thermal cycle)作業等環境下，該基板110之上表面111與下表 面112會產生不同之熱應力（thermal stress) ’使該窗口 型球格陣列之多晶片封裝構造1 〇〇的翹曲現象越嚴 重。整體封裳厚度亦會增加。此外’在模封灌膠時，該 封膠體150依該基板分隔的上下層厚度不同，導致上下 模流不平衡’易有填膠不充實產生氣泡的問題。再就封 裝成本而論’習知窗口型球格陣列之多晶片封裝構造 100所使用的電路基板110需在上表面111與下表面H2 雙面各a又置~線路層，方能形成供内部電性連接之打線 接指115與ιΜ，另設有電性導通孔（pTH或稱wy，以 電性互連上下線路層’這將增加電路基板的線路佈局複 雜度與基板製作成本。 【發明内容】 本毛月之主要目的係在於提供一種窗口型球格陣列 之多晶片封裝構造’改變第二晶片在窗口型球格陣列基 板的配置位置，降低封裝厚度並達到内應力與模流之平 衡，以避免封裝構造之翹曲及封膠體内積存氣泡^ 本毛月之人目的係在於提供一種窗口型球格陣列 之多晶片封裝構造，利用第二晶片之背面形成有二絕緣 性晶背黏著層，利用其對基板下表面之壓覆區域，能預 先局部密封通過窗口之鲜線，加強銲線接合強度並防止 沖線與壓觸晶片。 7 200910570 本發明之另一目的係在於提供一種窗口型球格陣列 之多晶片封裝構造，利用第二晶片的配置與電性連接方 式，能使基板之打線接指與球墊能形成於基板之同一下 表面，減少基板上層的線路層與導通孔，以降低基板製 作成本與厚度。 本發明的目的及解決其技術問題是採用以下技術方 案來實現的。依據本發明，一種窗口型球格陣列之多晶 片封裝構造主要包含一基板、一第一晶片、一第二晶片、 複數個第一銲線、一封膠體以及複數個銲球。該基板係具 有一上表面、一下表面及一打線槽孔，該基板係更具有 位於該下表面之複數個第一打線接指以及複數個球 塾。該第一晶片係具有一第一主動面與一第一背面。該 第一主動面係貼設於該基板之該上表面。該些第一銲線 係通過該打線槽孔並電性連接該第一晶片與該基板之 該些第一打線接指。該第二晶片係具有一第二主動面與 (一第二背面，該第二晶片係設置於該基板之該下表面。 該封膠體係形成於該基板之該上表面與該下表面。該些 銲球係設置於該些球墊。 在前述的多晶片封裝構造中，該第二晶片之該第二 背面係可形成有一絕緣性晶背黏著層，其係壓覆於該些 第一打線接指以及該些第一銲線之一端，而不覆蓋該些 球塑1。 在前述的多晶片封裝構造中，該基板係可更具有位 於該下表面之複數個第二打線接指，並另包含有複數個 8 200910570 第二銲線’其係電性連接該第二晶片與該基板之該些第 二打線接指。 在前述的多晶片封裴構造中，該封膠體係可密封該 第一晶片與該第二晶片。 在别述的多晶片封裝構造中，該封膠體係可具有一 頂面與一底面，該封膠體由該頂面至該第一晶片之厚度 概約相同於由該底面至該第二晶片之厚度。 f 在則述的多晶片封裝構造中，該封膠體係具有一頂面 與一底面，該封膠體由該底面至該基板之該下表面之高度係 可大於該些銲球之球徑。 在刖述的多晶片封裝構造中，該些銲球係可排列在 該基板之該下表面之周邊。 在前述的多晶片封裝構造中，該打線槽孔係可具有 兩端不被該第一晶片與該第二晶片所覆蓋之長度，以使 該封膠體填入該打線槽孔。 l 在刖述的多晶片封裝構造中，該打線槽孔之長度係 可貫穿S玄基板’以使該基板分離為兩個次基板。 【實施方式】 依據本發明之一具體實施例，具體揭示一種窗口型 球格陣列之多晶片封裝構造如下。 請參閱第2圖所示，一種窗口型球格陣列之多晶片 封裝構造200主要包含一基板210、一第一晶片22〇、 第 0片230、複數個第一鲜線241' 一封勝I# 250 以及複數個鲜球26〇。該基板21。係具有一上表二::° 9 200910570 一下表面2 1 2及一打線槽孔2 1 3，其中該打線槽孔 係貫穿該基板210之上表面211與下表面212，以 窗口型球格陣列封裝的窗口。該基板2丨〇係更具有 該下表面2 1 2之複數個第一打線接指2 1 4以及複數 墊2 1 6。較佳地，該基板2 1 〇係可為一單層線路基 甚至是電路薄膜，以省略在該基板21〇之上表面2 上層線路層以及貫穿該基板21〇之導通孔（Via，或 為鑛通孔（PTH))。即是有效降低該基板21〇之製造 與厚度’並可適用於窗口型球格陣列之多晶片封 後詳述）。 3玄第一晶片220係具有一第一主動面221與一 背面222。於第一主動面221之一中央區域設有複 第一辉塾223。該第一主動面221係朝向該基板： 並以—黏晶層270之黏貼而貼設於該基板2丨〇之該 面2 1 1 ’並使該些第一銲墊2 2 3顯露於該打線槽孔 °亥&第一銲線2 4 1係能通過該打線槽孔2 1 3並電性 該第日日片220之第一銲墊223與該基板210之該 打線接指2 1 4。該基板2 1 0係可更具有位於該ητ 2 1 2之複數個第二打線接指2丨5，以供打線電性連 第一晶片23 〇。因此’在一較佳實施例中，該基相 之内。Ρ電性接點（即第一打線接指2 1 4與第二打鎳 2 1 5 )以及對外電性接點（即球墊2 1 6)皆位於該基板 之5玄下表面212 ’該基板210可選用一種低成本具 面線路層之電路基板，可省去電性佈局之複雜度與 » 213 作為 位於 個球 板， 11之 可稱 成本 Μ容 % 一 數個 :ιο， 上表 2 13° 連接 些第 表面 接該 ：210 接指 210 有單 製程 10 200910570 困擾，提高訊號處理南速化，並降低基板之製作成本。 該第二晶片23〇係具有一第二主動面231與一第二 背面232,於第二主動面231設有複數個第二銲墊233。 該第二晶片2 3 0係設置於該基板2 1 0之該下表面2 1 2。 較佳地，該第二晶片2 3 0之該第二背面2 3 2係可形成有 一絕緣性晶背黏著層2 8 〇 ’其係壓覆於該些第一打線接 指2 1 4以及該些第一銲線24 1之一端’而不覆蓋該些球 墊2 1 6。通常該絕緣性晶背黏著層2 8 0係具有B階或半 固化特性，在加熱到一適當溫度能產生黏著力與黏稠 度，以密封該些第一銲線2 4 1之基板接合端並可調整降 低該些第一銲線2 4 1之弧高’以防止該第二晶片2 3 0之 該第二背面2 3 2被該些第一銲線2 4 1壓觸造成電性短路 之缺陷。因此，該些第一銲線2 4 1在第一打線接指2 1 4 的接合端被該絕緣性晶背黏著層2 8 0達成局部密封，以 加強第一銲線24 1接合強度並防止沖線。此外，該絕緣 性晶背黏著層280係為電絕緣性並可為雙面黏性膠帶 或液態環氧粘膠’以避免不當的電性短路。 在本實施例中’該多晶片封裝構造200可另包含有 複數個第二銲線242，其係電性連接該第二晶片23 〇之 第二銲墊233與該基板2 1 0之該些第二打線接指2 1 5。 此外’可利用轉移成型模封或是印刷等方法將該封 膠體250形成於該基板210之該上表面211、該下表面 2 1 2及該打線槽孔2 1 3，並可密封該第一晶片220、該 第二晶片2 3 0、該些第一銲線2 4 1與該些第二銲線2 4 2， 200910570 以提供適當的封裝保護以防止電性短路與塵埃污染。在本 實施例中’該基板2 1 0之該打線槽孔2 1 3係可具有兩端 不被該第一晶片220與該第二晶片230所覆蓋之長度， 以使該封膠體2 5 0填入該打線槽孔2 1 3。在不同實施例 中’該打線槽孔2 1 3之長度係可貫穿該基板2 1 0，以使 該基板2 1 0分離為兩個次基板。 此外，該封膠體250係可具有一頂面25 1與一底面 252’分別在該基板210之上表面211之上方與下表面 2 12之下方。較佳地，再如第2圖所示，該封膠體2 5 〇 由該頂面251至該第一晶片220之厚度T1概約相同於 由該底面252至該第二晶片230之厚度T2，使得該封 膠體250之上下層模流南度為相同，能改善模流不均勻 及熱應力不平衡而造成基板翹曲之問題，進而提高半導 體封裝產品的良率與可靠度。 該些銲球260係設置於該些球墊 基板210之該下表面212之周邊，可藉由該些銲球 表面接合至一外部印刷電路板。較佳地，該封膠體25〇 由該底面252至該基板21()之該下表面212之高度係可大於 該些録球260之球徑，藉以在儲放運送時能 貼固定該封膠體⑽之頂面251與底面252，避免該^ 球260被_球。在後段的表面接合時，則可在 電路板之連接塾（圖未緣出）上預先印刷上預銲材、錫膏或助 在干劑，經回銲而能與該些銲球26〇焊接。 因此’本發明之窗口型球格陣列之多晶片封裝構造 12 200910570 200能有效整合第二晶片23 0，不會增加封裝厚度、不 會造成模流不平衡與應力翹曲，甚至更有模流平衡與減 少產品翹曲的增益功效。 以上所述，僅是本發明的較佳實施例而已，並非對 本發明作任何形式上的限制，本發明技術方案範圍當依 所附申請專利範圍為準。任何熟悉本專業的技術人員可 利用上述揭示的技術内容作出些許更動或修飾為等同 變化的等效實施例，但凡是未脫離本發明技術方案的内 容，依據本發明的技術實質對以上實施例所作的任何簡 單修改、等同變化與修飾，均仍屬於本發明技術方案的 範圍内。 【圖式簡單說明】 第1圖：一種習知多晶片堆疊封裝構造之截面示意圖。 第2圖：依據本發明之一具體實施例，一種窗口型球格 陣列之多晶片封裝構造之截面示意圖。 【主要元件符號說明】 T1 厚度 T2 厚度 100 多晶片封裝構造 110 基板 111 上表面 112 下表面 113 打線槽孔 114 第一打線接指 115 第二打線接指 116 球墊 120 第一晶片 121 第一主動面 122 第一背面 123 第一銲墊 130 第·~~晶片 131 第二主動面 132 第二背面 13 200910570 133 第二銲墊 141 第一銲線 142 第二銲線 150 封膠體 160 焊球 170 黏晶層 200 多晶片封裝構造 210 基板 211 上表面 212 下表面 213 打線槽孔 214 第一打線接指 215 第二打線接指 216 球塾 220 第一晶片 221 第一主動面 222 第一背 面 223 第一銲墊 230 弟二晶片 231 第二主動面 232 第二背 面 233 第二銲墊 241 第一銲線 242 第二銲線 250 封膠體 25 1 頂面 252 底面 260 鲜球 270 黏晶層 280 絕緣性晶 背黏著層 14The greater the degree of need, the upper surface 111 and the lower surface 112 of the substrate 110 will be in the environment such as substrate baking, sealing curing, and subsequent thermal cycle operation. Producing different thermal stresses' makes the warpage of the multi-chip package structure of the window-type ball grid array more severe. The overall thickness of the cover will also increase. In addition, when the glue is encapsulated, the thickness of the upper and lower layers of the sealant 150 separated by the substrate is different, resulting in an imbalance of the upper and lower mold flows, which is a problem that the filler is not filled and bubbles are generated. Further, in terms of package cost, the circuit substrate 110 used in the multi-chip package structure 100 of the conventional window type ball grid array needs to be formed on the upper surface 111 and the lower surface H2 on both sides to form a circuit layer. The electrical connection of the wire connection fingers 115 and ι, and the electrical conduction hole (pTH or wy, to electrically interconnect the upper and lower circuit layers) will increase the circuit layout complexity of the circuit substrate and the substrate fabrication cost. Contents The main purpose of this month is to provide a multi-chip package structure of a window type grid array. 'Change the position of the second wafer in the window type grid array substrate, reduce the package thickness and achieve the balance between internal stress and mold flow. In order to avoid the warpage of the package structure and the accumulation of air bubbles in the sealant body. The purpose of this person is to provide a multi-chip package structure of a window type grid array, and a second insulating crystal back adhesion is formed on the back surface of the second wafer. The layer, by using the pressed region of the lower surface of the substrate, can partially seal the fresh line through the window in advance, strengthen the bonding strength of the bonding wire and prevent the punching and pressing of the wafer. 7 200910570 Another object of the present invention is to provide a multi-chip package structure of a window type ball grid array. The arrangement and electrical connection of the second wafer enable the wire bonding fingers of the substrate and the ball pad to be formed on the same substrate. The surface reduces the wiring layer and the via hole of the upper layer of the substrate to reduce the substrate fabrication cost and thickness. The object of the present invention and the technical problem thereof are achieved by the following technical solutions. According to the present invention, a window type ball grid array is used. The chip package structure mainly comprises a substrate, a first wafer, a second wafer, a plurality of first bonding wires, a gel and a plurality of solder balls. The substrate has an upper surface, a lower surface and a wire slot. The substrate has a plurality of first wire bonding fingers and a plurality of balls on the lower surface. The first wafer has a first active surface and a first back surface. The first active surface is attached to the substrate. The first surface of the substrate passes through the wire slot and is electrically connected to the first wire and the first wire bonding fingers of the substrate. Having a second active surface and (a second back surface, the second wafer is disposed on the lower surface of the substrate. The encapsulation system is formed on the upper surface and the lower surface of the substrate. The solder ball systems are disposed In the above multi-chip package structure, the second back surface of the second wafer may be formed with an insulating crystal back adhesion layer, which is pressed against the first wire bonding fingers and the One end of the first bonding wire, without covering the spherical plastics 1. In the foregoing multi-chip package configuration, the substrate may further have a plurality of second bonding fingers on the lower surface, and further comprising a plurality of 8 200910570 The second bonding wire ' electrically connects the second wafer to the second bonding wires of the substrate. In the foregoing multi-chip sealing structure, the sealing system can seal the first wafer and the In a multi-chip package structure, the encapsulation system may have a top surface and a bottom surface, and the thickness of the encapsulant from the top surface to the first wafer is about the same as the bottom surface to the The thickness of the second wafer. In the multi-chip package construction described above, the encapsulation system has a top surface and a bottom surface, and the height of the encapsulant from the bottom surface to the lower surface of the substrate may be greater than the ball diameter of the solder balls. In the multi-wafer package construction described above, the solder balls may be arranged around the lower surface of the substrate. In the above multi-chip package structure, the wire slot may have a length at which both ends are not covered by the first wafer and the second wafer, so that the sealant fills the wire slot. In the multi-chip package structure described above, the length of the wire slot can penetrate through the S-base substrate to separate the substrate into two sub-substrates. [Embodiment] According to an embodiment of the present invention, a multi-chip package structure of a window type ball grid array is specifically disclosed as follows. Referring to FIG. 2, a multi-chip package structure 200 of a window type ball grid array mainly includes a substrate 210, a first wafer 22, a 0th sheet 230, and a plurality of first fresh lines 241'. # 250 and a number of fresh balls 26〇. The substrate 21. The system has a top table 2::° 9 200910570 a surface 2 1 2 and a wire slot 2 1 3, wherein the wire slot is penetrated through the upper surface 211 and the lower surface 212 of the substrate 210 to form a window array Encapsulated window. The substrate 2 further has a plurality of first wire bonding fingers 2 1 4 and a plurality of pads 2 16 of the lower surface 2 1 2 . Preferably, the substrate 2 1 can be a single-layer wiring base or even a circuit film to omit the upper wiring layer on the surface 2 of the substrate 21 and the via hole extending through the substrate 21 (Via, or Mine Through Hole (PTH)). That is, it is effective to reduce the manufacturing and thickness of the substrate 21 and can be applied to the multi-wafer sealing of the window type lattice array. The first first wafer 220 has a first active surface 221 and a back surface 222. A first first ridge 223 is disposed in a central region of the first active surface 221. The first active surface 221 is oriented toward the substrate: and is adhered to the surface 2 1 1 ′ of the substrate 2 by adhesion of the bonding layer 270, and the first pads 2 2 3 are exposed to the surface a wire slot hole ° & first wire 2 1 1 can pass through the wire slot 2 1 3 and electrically connect the first pad 223 of the first day wafer 220 with the wire bonding finger 2 1 of the substrate 210 4. The substrate 210 may further have a plurality of second bonding fingers 2丨5 located at the ητ 2 1 2 for electrically bonding the first wafer 23 打. Thus, in a preferred embodiment, the base phase is within. The electrical contact (ie, the first wire contact 2 1 4 and the second nickel 2 15) and the external electrical contact (ie, the ball pad 2 16) are located on the lower surface 212 of the substrate. The substrate 210 can be selected from a low-cost circuit board with a circuit board layer, which can save the complexity of the electrical layout and » 213 as a spherical board, and the cost of the 11 can be said to be a few: ιο, Table 2 above 13° Connect the surface to the surface: 210 The finger 210 has a single process 10 200910570 trouble, improve the signal processing speed, and reduce the manufacturing cost of the substrate. The second wafer 23 has a second active surface 231 and a second back surface 232. The second active surface 231 is provided with a plurality of second pads 233. The second wafer 203 is disposed on the lower surface 2 1 2 of the substrate 2 10 . Preferably, the second back surface 2 2 2 of the second wafer 203 is formed with an insulating crystal back adhesive layer 28 〇 'which is pressed against the first wire bonding fingers 2 1 4 and the One of the first bonding wires 24 1 ' does not cover the ball pads 2 16 . Generally, the insulating crystal back adhesive layer has a B-stage or semi-curing property, and can be adhesively and viscous when heated to a suitable temperature to seal the substrate bonding ends of the first bonding wires 241. The arc height ' of the first bonding wires 241 may be adjusted to prevent the second back surface 223 of the second wafer 203 from being electrically contacted by the first bonding wires 24 1 to cause an electrical short circuit. defect. Therefore, the first bonding wires 241 are partially sealed by the insulating crystal back adhesive layer 280 at the joint end of the first wire bonding fingers 2 1 4 to strengthen the bonding strength of the first bonding wire 24 1 and prevent Line up. In addition, the insulative crystalline back adhesive layer 280 is electrically insulating and can be a double-sided adhesive tape or liquid epoxy adhesive' to avoid undue electrical shorting. In the present embodiment, the multi-chip package structure 200 may further include a plurality of second bonding wires 242 electrically connected to the second pads 233 of the second wafer 23 and the substrate 2 1 0 The second line is connected to 2 1 5 . In addition, the encapsulant 250 can be formed on the upper surface 211 of the substrate 210, the lower surface 2 1 2 and the wire slot 2 1 3 by means of transfer molding or printing, and the first can be sealed. The wafer 220, the second wafer 203, the first bonding wires 241 and the second bonding wires 224, 200910570 provide appropriate package protection to prevent electrical short circuits and dust contamination. In the present embodiment, the wire slot 2 1 3 of the substrate 2 10 may have a length that is not covered by the first wafer 220 and the second wafer 230, so that the seal body 2 50 Fill in the wire slot 2 1 3 . In various embodiments, the length of the wire slot 2 1 3 may extend through the substrate 210 to separate the substrate 210 into two secondary substrates. In addition, the encapsulant 250 can have a top surface 25 1 and a bottom surface 252 ′ above the upper surface 211 of the substrate 210 and below the lower surface 2 12 . Preferably, as shown in FIG. 2, the thickness T1 of the encapsulant 25 from the top surface 251 to the first wafer 220 is about the same as the thickness T2 from the bottom surface 252 to the second wafer 230. The lower mold flow of the sealant 250 is the same, which can improve the unevenness of the mold flow and the thermal stress imbalance, thereby causing the problem of warpage of the substrate, thereby improving the yield and reliability of the semiconductor package product. The solder balls 260 are disposed on the periphery of the lower surface 212 of the ball pad substrate 210, and are bonded to an external printed circuit board by the surface of the solder balls. Preferably, the height of the sealing body 25 from the bottom surface 252 to the lower surface 212 of the substrate 21 can be greater than the spherical diameter of the recording balls 260, so that the sealing body can be attached and fixed during storage and transportation. (10) The top surface 251 and the bottom surface 252 prevent the ball 260 from being _ ball. When the surface of the rear stage is joined, the pre-welding material, the solder paste or the dry-drying agent may be pre-printed on the connection port of the circuit board, and the solder ball 26 can be soldered by reflowing. . Therefore, the multi-chip package structure 12 200910570 200 of the window type ball grid array of the present invention can effectively integrate the second wafer 230, without increasing the package thickness, causing mold flow imbalance and stress warping, and even more mold flow. Balance and reduce the gain of product warpage. The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. The scope of the present invention is defined by the scope of the appended claims. Any person skilled in the art can make some modifications or modifications to the equivalent embodiments by using the technical content disclosed above, but the content of the technical solution of the present invention is made according to the technical essence of the present invention without departing from the technical solution of the present invention. Any simple modifications, equivalent changes and modifications are still within the scope of the technical solutions of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing a conventional multi-wafer stacked package structure. Figure 2 is a cross-sectional view showing a multi-chip package structure of a window type ball grid array in accordance with an embodiment of the present invention. [Main component symbol description] T1 Thickness T2 Thickness 100 Multi-chip package structure 110 Substrate 111 Upper surface 112 Lower surface 113 Wire slot 114 First wire connection finger 115 Second wire connection finger 116 Ball pad 120 First wafer 121 First initiative Surface 122 first back surface 123 first pad 130 first ~~ wafer 131 second active surface 132 second back surface 13 200910570 133 second bonding pad 141 first bonding wire 142 second bonding wire 150 sealing body 160 solder ball 170 sticky Crystal layer 200 multi-chip package structure 210 substrate 211 upper surface 212 lower surface 213 wire slot 214 first wire bonding finger 215 second wire bonding finger 216 ball 220 first wafer 221 first active surface 222 first back surface 223 first Pad 230 second wafer 231 second active surface 232 second back surface 233 second solder pad 241 first bonding wire 242 second bonding wire 250 sealing body 25 1 top surface 252 bottom surface 260 fresh ball 270 adhesive layer 280 insulating crystal Back adhesive layer 14

Claims (1)

200910570 十、申請專利範圍： 1、一種窗口型球格陣列之多晶片封襞構造，包含： 一基板，其係具有一上表面、一下表面及一打線槽孔， «亥基板係更具有位於該下表面之複數個第一打線接指 以及複數個球墊； 第一晶片，其係具有一第一主動面與一第一背面該 第主動面係貼設於該基板之該上表面； 複數個第一銲線，其係通過該打線槽孔並電性連接該第 一晶片與該基板之該些第一打線接指； 一第二晶片，其係具有一第二主動面與一第二背面，該 第二晶片係設置於該基板之該下表面； 一封膠體’其係形成於該基板之該上表面與該下表面； 以及 複數個銲球，其係設置於該些球墊。 2如申请專利範圍第1項所述之窗口型球格陣列之多晶 片封裝構造，#中該第二晶片之該第二背面係形成有 一絕緣性晶背黏著層，其係壓覆於該些第一打線接指 以及該些第一銲線之一端’而不覆蓋該些球墊。 3、如申請專利範圍第2項所述之窗口型球格陣列之多晶 片封裝構造，其中該基板係更具有位於該下表面之複 數個第二打線接指，益另包含有複數個第二銲線，其 係電性連接該第二晶片與該基板之該此-指。 二弟一打線接 4、如申請專利範圍第】項所述 丄琢袼陣列之多晶 15 200910570 片封裝構造，其 二晶片。 5、 如申請專利範圍】 片封裝構造，其， 該封膠體由該頂€ 該底面至該第二盖 6、 如申請專利範圍| 片封裝構造，其1 該封膠體由該底茂 該些銲球之球徑。 7、 如申請專利範圍第 片封裝構造，其中 面之周邊。 8、 如申請專利範圍第 片封裝構造，其中 晶片與該第二晶片 該打線槽孔。 9、 如申請專利範圍第 片封裝構造，其中 以使該基板分離為 中該封膠體係密封該第與該第 1 4㈣^ “型球格陣列之多晶 卜該封膠體係具有-頂面與-底面， '至該第一晶片之厚度概约相同於由 1片之厚度。 ’ 4項所述之窗口型球格陣列之多晶 ’該封膠體係具有一頂面與一底面， z至該基板之該下表面之高度係大於 1項所述之固口型球格陣列之多晶 該些銲球係排列在該基板之該下表 1項所述之窗口型球格陣列之多晶 6亥打線槽孔係具有兩端不被該第一 所覆蓋之長度’以使該封膠體填入 8項所述之窗口型球格陣列之多晶 該打線槽孔之長度係貫穿該基板， 兩個次基板。 16200910570 X. Patent application scope: 1. A multi-chip sealing structure of a window type ball grid array, comprising: a substrate having an upper surface, a lower surface and a wire slot, the «Hi-substrate system is further located a plurality of first wire bonding fingers and a plurality of ball pads on the lower surface; the first wafer has a first active surface and a first back surface; the first active surface is attached to the upper surface of the substrate; a first bonding wire passing through the wire slot and electrically connecting the first wire and the first wire bonding fingers of the substrate; a second wafer having a second active surface and a second back surface The second wafer is disposed on the lower surface of the substrate; a gel is formed on the upper surface and the lower surface of the substrate; and a plurality of solder balls are disposed on the ball pads. 2, in the multi-chip package structure of the window type ball grid array according to claim 1, wherein the second back surface of the second wafer is formed with an insulating crystal back adhesive layer, which is pressed against the The first wire bonding finger and one of the first wire bonding wires ' do not cover the ball pads. 3. The multi-chip package structure of the window type ball grid array according to claim 2, wherein the substrate system further has a plurality of second wire bonding fingers on the lower surface, and the plurality of second wire bonding fingers are further included a bonding wire electrically connecting the second wafer and the substrate to the substrate. The second brother is connected with a wire. 4. As described in the scope of the patent application, the polycrystalline layer of the 丄琢袼 array is 15 200910570. 5, as claimed in the patent scope] a package structure, the sealant from the top of the bottom surface to the second cover 6, such as the patent scope | sheet package structure, the sealant is sealed by the primer The ball diameter of the ball. 7. If the patent application scope is the first package structure, the periphery of the surface. 8. The package structure of claim 1, wherein the wafer and the second wafer have the wire slot. 9. The patented range of the first package structure, wherein the substrate is separated into a sealant system to seal the first and the fourth (four) ^ "type ball grid array of polycrystalline silicon, the sealant system has a top surface and - the bottom surface, 'to the thickness of the first wafer is approximately the same as the thickness of one sheet. 'The polycrystalline crystal of the window type grid array of the item 4' has a top surface and a bottom surface, z to The height of the lower surface of the substrate is greater than that of the solid-state ball grid array of the above-mentioned one. The solder balls are arranged on the substrate, and the polycrystalline crystal of the window type grid array according to the item 1 of the following table 6 打 线 系 系 具有 具有 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Two sub-substrates. 16
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