TW200848730A - Test apparatus for chip strength - Google Patents

Test apparatus for chip strength Download PDF

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Publication number
TW200848730A
TW200848730A TW96120511A TW96120511A TW200848730A TW 200848730 A TW200848730 A TW 200848730A TW 96120511 A TW96120511 A TW 96120511A TW 96120511 A TW96120511 A TW 96120511A TW 200848730 A TW200848730 A TW 200848730A
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Taiwan
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wafer
platform
tested
coating
testing device
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TW96120511A
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Chinese (zh)
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TWI334028B (en
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Wei-Hua Lu
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Univ Nat Pingtung Sci & Tech
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Publication of TWI334028B publication Critical patent/TWI334028B/en

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Investigating Strength Of Materials By Application Of Mechanical Stress (AREA)

Abstract

A test apparatus for chip strength comprises a testing device, a first glue filled device and a second glue filled device. The testing device has a first surface and a second surface for two chips to adhere to; and the first and second glue filled devices are respectively mounted on the two chips adhered on the first and second surfaces of the testing device by glue. After the chips are securely mounted between the three devices, the testing device is pulled to detect the strength of the two chips.

Description

200848730 九、發明說明: 【發明所屬之技術領娀】 本發明係關於一種晶片層間強度測試裝置,特別是 關於一種可以精確地測量晶片層間強度之測試裝置。 【先前技術】 隨著晶片製程微小化,積體電路技術進步一日千里 ,晶片應用的層面也越來越廣,因此,將晶片葬 塑膠材料進行封裝,是半導體元件製程中的^步驟= 在於晶片封裝製程中,材料本身以及各材料之間的界面需 要進行許多熱處理的步驟,雖然,熱處理過程並非直接針 〜對,片本身,也因為如此,才需要進行晶片層間強度之精 量測,熱處理過程中,㈣晶片各層間的結構強^過: ,將會間接導致晶㈣裝於電路錢,發生紐不良 :中諸多熱處理程序’例如黏晶、迴焊及封膠 裝必然具備之步驟’由於各材料之模數或熱膨脹 % 極:能導致材料與材料、材料與膠材之間產生應 力之問喊〔特別是在晶片之介電層或保護層 此,古、 良率降低及封裝可靠度不佳等結果。因 ,^必要對晶片相強度進行射地檢測。 弟1圖為習用之晶片強度測試 開第200520127號「耔#士 1 r畢民國公 專利所述。請參考第 _向黏著力檢測方法」發明 是在檢測平台;之單圖’習用之晶片層間強度測試裝置 PK10324 2007/6/7 7之單侧上固置一待測物8,該待測物$且 —h —— /、 200848730 =日日片81及灌膠成型成品82,且該灌膠成型成品幻 ,黏附於該晶片81之—表面,且利用—檢測棒9向該灌 膠成型成品82施加-剪向外力。藉此,在該晶片81層間 ,或者晶片與灌膠成型成品82之間的界面被破壞的瞬間 ’即:測得該晶片81層間’或者與灌膠成^成品幻之 的一剪向應力的大小。 曰200848730 IX. Description of the Invention: The present invention relates to a wafer interlaminar strength testing device, and more particularly to a testing device capable of accurately measuring the interlaminar strength between wafers. [Prior Art] With the miniaturization of the wafer process, the advancement of integrated circuit technology has become more and more extensive, and the level of wafer application has become wider and wider. Therefore, packaging the wafer to bury the plastic material is a step in the manufacturing process of the semiconductor device. In the process, the material itself and the interface between the materials need to be subjected to a number of heat treatment steps. Although the heat treatment process is not a direct pin-to-pair, the film itself, because of this, it is necessary to perform the precision measurement of the inter-layer strength of the wafer during the heat treatment. (4) The structure between the layers of the wafer is strong: it will indirectly cause the crystal (4) to be installed in the circuit, and the defects occur: many heat treatment procedures, such as the steps of the adhesive crystal, reflow and sealant, are necessary. Modulus or thermal expansion % pole: can cause stress between material and material, material and glue (especially in the dielectric layer or protective layer of the wafer, ancient, low yield and poor package reliability) Wait for the result. Therefore, it is necessary to perform the ground detection of the wafer phase intensity. Brother 1 is the conventional wafer strength test. No. 200520127, “耔#士1r毕民国公专利. Please refer to the _adhesive force detection method”. The invention is in the inspection platform; A test object 8 is fixed on one side of the strength testing device PK10324 2007/6/7 7, and the object to be tested is $ and -h —— /, 200848730 = day piece 81 and glue forming finished product 82, and the filling The glue molding is finished, adhered to the surface of the wafer 81, and the shearing force is applied to the potting molded product 82 by the detecting rod 9. Thereby, the moment between the layers of the wafer 81, or the interface between the wafer and the potting molded product 82 is destroyed, that is, the inter-layer stress of the wafer 81 is measured or the shear stress of the glue is formed. size.曰

然而’由於該檢測棒9所施加之剪向外力僅係施加 1檢測平台7之-側’且該檢測棒9不易與該檢測平台 =全平行,造成其所施加之剪向外力不易無晶片^ 完f平行或完全正面接觸該灌膠成型成品82,使—部分 之剪向外力成為該晶片81與灌膠成型成品82之間的黏^ g之正向分力,_可能造成轉成型成品8 _ 之料與非剪切形變’進—步導致該制裝量^ 得到之剪向黏著力失真。 厅里測 另—習用之晶片強度測試裝置,如中華民國公 428263號「測試Lead_〇n_Chip(L〇c)晶片與導線架之^ 裝結合強叙方法」發明專觸述。其係湘—夹具: 加作用力於黏附於-導線座之一晶片的一側,持續增加 遠作用力直龍晶片被破壞,或其與導線座分離』 得知受測之封裝結構的結合強度。 :般而言’上述習用具有許多缺點,例如測 之封衣、、、σ s強度或勇向黏著力不精確、於檢測過程中產生 垂直方向分力、甚至造成檢測平台彎曲變形等等缺勢 於上述原因,本發明實施例揭示之晶片層間強度測試裝^ 200848730 片層間或者晶片與基板之間 ’將可針對晶片封裝廠中, 強度進行精確量測。 【發明内容】 本發明之目的就是在提供一種晶片層間強度測試裝 、β1二由位於1固檢測平台上方及下方之二個液態膠材塗 3Π確棚妓記雜剌w赵層間結構 、 ”相晶#絲毁損,财紀賴待測晶片 之強度符合規格。 日月 檢到=明提出一種晶片層間強度測試裝置’其包含一 才欢測千台、一第一塗測平台及_ 台具有互相平行之—第一表 千口。該檢測平 曰片葬ώ一政从* 表面及—弟二表面,以供二待測 1 '才颇,·該第-塗測平台鄰近該檢測平a之 4-表面,並以膠材黏著於該 =汗口之 第二塗測平台鄰近於該檢測 :測曰曰片上;該 著於該第二表面之待测晶片上。c,並以膠材黏 於》亥一待測曰曰片之後,拉動該檢剛平么, :口 u疋 其中之-產生層間結構毁損後“曰^亥―待測晶片 晶片其中之-層間之強度,紀錄該二待測 並未毁損,則紀錄該待測晶片之%二純别’該待測晶片 上述晶片層間強度_裝X #合,格。 試裝置依液態或固態膠材熱固化條’將晶片層間強度測 或固態膠材黏合固定於該第一待、、貝,、進行口化,且待液態 之後,將該檢測平台拉動該第—、3片及忒弟—待測晶片 片,藉此對待測晶片層間施予晶片及該第二待測晶 _3242_/7 __ 又損之外力,以便測量並 I -- 200848730 紀錄该二待測晶片其中之層間之強度。 依本發明之較佳實施例所述之晶片層間強度測試裝 置’上述晶片毁損外力係一相對於檢測平台及液態或固態 膠材塗測平台之平面之剪向切力。 依本發明之較佳實施例所述之晶片層間強度測試裝 ^ 置,上述膠材塗測平台具有一塗膠平面。 【實施方式】 為讓本發明之上述及其他目的、特徵、優點能更明 顯易懂’下文特舉本發明之較佳實施例,並配合所附圖式 ,作詳細說明如下: 第2圖為本發明實施例之晶片層間強度測試裝置之 y側視圖。請參考第2圖,本實施例之晶片層間強度測試裝 置包括一檢測平台1、一第一塗測平台2及一第二塗測平 台3。該檢測平台1具有一第一表面η及一第二表面12 ,且該第一表面11與該第二表面12相互平行,以便供二 待測晶片4分別貼附於該第一表面11及第二表面12上; 該第一塗測平台2及第二塗測平台3分別接近該檢測平台 1之第一表面11及第二表面12,且該二塗測平台2、3各 具有一表面平行於該第一及第二表面11、12,以便該二 塗測平台2、3貼附設置於该二表面11、12之待測晶片4 。其中,該二待測晶片4係可選擇為半導體材料,例如為 同一種晶片〔chip〕。此外,各該待測晶片4與該檢測平 台1、第一塗測平台2及第二塗測平台3互相接觸的表面 之間均佈設一膠材5,該膠材較佳係選擇為一液態或固態 PK10324 2007/6/7 —8 — 200848730 膠材,其更佳係選擇為一熱固性膠材。 斤第3、圖為第2圖實施例之晶片層間強度測試示意圖 弟图為第2圖實施例之塗測平台2之立體圖。請參照 第3及4圖所示,當利用本發明實施例之晶片層 測試裝置進行測試時,首先將呈液態之該膠材5塗佈於該 檢測:台1之第-表面11及第二表面12,以及該第〆塗 測平口 2及第二塗測平台3朝向該檢測平台 當,隨後,將該第一塗測平台2、待測晶片= 平口1、:待測晶片4及第二塗測平台3等依次疊合。 〜將_合強度顺裝置依該雜5之_However, 'the outer force of the shear applied by the detecting rod 9 is only applied to the side of the detecting platform 7' and the detecting rod 9 is not easily parallel with the detecting platform = the outward force of the shearing force applied thereto is not easy to be wafer-free ^ Finishing the parallel or complete frontal contact with the glue-molded finished product 82, so that the shearing outward force of the portion becomes the positive component of the adhesion between the wafer 81 and the glue-molded finished product 82, which may result in a finished product. 8 _ material and non-shear deformation 'in step-by-step results in the amount of shear to obtain the shear force distortion. In the hall, another test, the wafer strength test device, is described in the Republic of China, No. 428263, "Testing Lead_〇n_Chip (L〇c) Wafers and Lead Frames." It is a fixture-clamp: the force is applied to the side of one of the wafers of the wire holder, and the far-acting force of the straight dragon wafer is continuously damaged, or it is separated from the wire holder. The bonding strength of the package structure to be tested is known. . In general, the above-mentioned practices have many disadvantages, such as measuring the seal, the σ s strength or the inaccurate adhesion, the vertical component in the detection process, and even the bending deformation of the detection platform. For the above reasons, the inter-wafer strength test of the wafer disclosed in the embodiment of the present invention can be accurately measured for the strength of the wafer package factory. SUMMARY OF THE INVENTION The object of the present invention is to provide a wafer interlaminar strength test package, and the two liquid glues on the top and bottom of the 1st solid detection platform are coated with three liquids, and the inter-layer structure and the phase are The crystal# wire is damaged, and the strength of the wafer to be tested conforms to the specifications. The monthly inspection = clearly proposed a wafer inter-layer strength testing device, which includes a thousand units, a first coating platform and a Parallel - the first table of thousands of mouths. The test flats are buried from the surface of the * and the surface of the two brothers, for the second to be tested 1 'cause, · the first - coating platform adjacent to the test level a 4-surface, and the second coating platform adhered to the sweat joint by the glue material is adjacent to the detection: on the test piece; on the wafer to be tested on the second surface, c, and adhered to the glue material After the test of the 曰曰 一 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , If it is not damaged, record the % of the wafer to be tested. Said interlaminar strength between the wafer _ X # engagement means, grid. The test device is based on a liquid or solid glue heat-curing strip' to bond the inter-layer strength test or the solid glue to the first to-be, the shell, and the mouth, and after the liquid is to be liquid, the test platform pulls the first- , 3 pieces and the younger brother - the wafer to be tested, whereby the wafer to be tested between the wafer layers and the second crystal to be measured _3242_/7 __ is also damaged, so as to measure and I - 200848730 record the second to be tested The strength of the layers in the wafer. The wafer interlaminar strength test apparatus according to the preferred embodiment of the present invention is characterized in that the wafer damage external force is a shearing shear force with respect to the plane of the inspection platform and the liquid or solid glue coating platform. According to the wafer inter-layer strength test apparatus of the preferred embodiment of the present invention, the glue coating platform has a glue coating plane. The above and other objects, features, and advantages of the present invention will become more <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; A side view of the wafer interlayer strength testing device of the embodiment of the present invention. Referring to FIG. 2, the inter-wafer strength testing device of the embodiment includes a detecting platform 1, a first coating platform 2 and a second coating platform 3. The detecting platform 1 has a first surface η and a second surface 12, and the first surface 11 and the second surface 12 are parallel to each other, so that the two wafers to be tested 4 are respectively attached to the first surface 11 and The first coating platform 2 and the second coating platform 3 are respectively adjacent to the first surface 11 and the second surface 12 of the detecting platform 1, and the two coating platforms 2, 3 each have a surface parallel The first and second surfaces 11, 12 are disposed so that the two coating platforms 2, 3 are attached to the wafer 4 to be tested disposed on the two surfaces 11, 12. The two wafers to be tested 4 can be selected as a semiconductor material, for example, the same chip. In addition, a glue material 5 is disposed between each of the test wafers 4 and the surface of the detection platform 1, the first coating platform 2, and the second coating platform 3, and the glue is preferably selected as a liquid. Or solid state PK10324 2007/6/7 — 8 — 200848730 glue, the better choice is a thermosetting glue. Fig. 3 is a schematic view showing the inter-layer strength test of the wafer in the embodiment of Fig. 2. The figure is a perspective view of the coating platform 2 of the embodiment of Fig. 2. Referring to FIGS. 3 and 4, when testing by the wafer layer testing apparatus of the embodiment of the present invention, the liquid material 5 is first applied to the inspection: the first surface 11 and the second of the table 1. The surface 12, and the second coating flat 2 and the second coating platform 3 face the detecting platform, and then, the first coating platform 2, the wafer to be tested = flat 1, the wafer 4 to be tested, and the second The coating platform 3 and the like are sequentially stacked. ~ Will _ combined strength device according to the hybrid 5 _

3膠固最後,待該膠材5黏合固定於待測晶 同奸;^11平°1係對塗覆於該制晶片4上之膠材5 同_予-日日片相之毀損外力,且測量並 :ΓΓ斤需施予之外力大小。-般而言,晶= 護層、济^ 曰八中對日日片4整體封裝效果影響最大者 面保護層及介t層。 $料,亥表 &gt;此外,施加於該檢測平自i之一外力方向6,盘 反。由二Ϊ 外力方向6係互為平行且相 台2及第:涂、、^厚度較薄’並不致於影響該第—塗測平 备 〜解台3之間的平行設置義,故可#此避 ::檢::程:產生與該二種外力方向6、6,ί= :至k成该檢測平台1彎曲變形等缺點。 PK10324 2007/6/7 於°亥弟一塗測平台2可至少另設一固定孔21,以便 200848730 將該第-塗測平台2蚊於—測試機台上,另外,於該第 二塗測平台3同時可至少另設一固定孔3卜 將;3 Glue finally, until the glue 5 is adhered and fixed to the crystal to be measured; ^11 flat °1 is applied to the wafer 4 coated on the wafer 4 with the external force of the Japanese-Japanese film, And measure and: the amount of force required to apply. In general, the crystal layer, the protective layer, and the top layer of the Japanese film 4 have the greatest influence on the overall protective layer and the t layer. $ material, hai table &gt; In addition, applied to the detection flat from the direction of one of the external forces of i, the disk is reversed. From the direction of the external force, the 6 series are parallel to each other, and the phase 2 and the first: the coating, and the thickness of the film are not thin, which does not affect the parallel setting between the first coating and the measuring platform. This avoidance:: Check:: Cheng: produces the disadvantages of the two external force directions 6, 6, ί = : to k into the bending deformation of the detection platform 1 . PK10324 2007/6/7 At least one fixed hole 21 can be set in the Haidiyi coating platform 2 for the 200848730 to apply the first coating platform 2 to the test machine. In addition, the second coating is used. The platform 3 can be provided with at least one fixing hole 3 at the same time;

一㈣平台2及第二塗測平台3固定於—測試機台上了例 如一拉力試驗機〔未緣示〕。藉此,在該檢測平台工對谬 材j施予毁損外力時,可更強化穩定性,使該塗測平台^ f第,塗辭台3與檢測平台i之表硫_持穩定^平 二增加毁損外力之測量精準度。誠,該檢測平台!亦 可°又置固定孔13以供一拉力裝置〔未綠示〕穿設其中 進而提供該檢測平台1穩定之毀損外力。將所測得之毁 損外力除以該膠材5在該待測晶片4之塗佈面積,即可得 到,待測晶片4之剪向毁損外力。—般而言,相對於該: 測晶片4之表面積,該膠材5之塗佈面積較佳係相等於該 待測晶片4之表面積,藉以更進一步增加剪向機械強度之 測試精準度。 ,在本領域具有通常知識者應知,各廠商對於該檢測 平台1及第一、第二塗測平台2、3之設計方法均不相同 ,而且該膠材5可依各種半導體製程所需而選擇,其固化 ,件也因此不同,所以本發明之應用不應以此為限。舉例 來說’該第一塗測平台2也可以不設置該固定孔21,該 第一塗測平台3也可以不設置該固定孔31,而直接以一 體成i的方式與_穩定之結構〔如該測試機台之底盤〕結 a i曰加%疋性。同樣地,該檢測平台1亦可不設置該固 ^孔13,而直接與該拉力裝置結合。當然,該拉力裝置 可連接至一記錄器〔未繪示,如個人電腦與分析軟體〕, PK10324 2007/6/7 10 — 200848730 以便紀錄歷次試驗所需之鍍損外力。 換句f說,本發明之精神在於:只要是二塗測平台2 仏3^^地平❿又置在—檢測平台1之對稱兩侧,使該 檢測平台1能夠對二待測晶片4同時施予相同大小之毁損 外^藉此將二待測晶片4的各層間或各層界面間所產生 二相2之正向分力減到最小,以便更為精確地量測獲 付毀相外力。 由於本發明之檢測平台!、第一塗測平台2及第二塗 測平台3均僅利用數個簡易之平面構成,並直接於該平面 上以人工方式或機械方式塗抹該谬材5,此The first (four) platform 2 and the second coating platform 3 are fixed on the test machine, for example, a tensile testing machine (not shown). Therefore, when the detecting platform worker applies the damage external force to the coffin j, the stability can be further enhanced, so that the coating platform ^f, the coating table 3 and the detection platform i are stable and stable. Increase the measurement accuracy of the damage external force. Sincerely, the detection platform! Alternatively, the fixing hole 13 may be provided for a tensioning device (not shown) to provide a stable external force of the detecting platform 1. By dividing the measured external force of the damage by the coated area of the glue 5 on the wafer 4 to be tested, it is obtained that the shearing force of the wafer 4 to be tested is damaged. In general, with respect to the surface area of the test wafer 4, the coated area of the adhesive material 5 is preferably equal to the surface area of the wafer 4 to be tested, thereby further increasing the test accuracy of the shearing mechanical strength. It should be known to those skilled in the art that the design methods of the testing platform 1 and the first and second coating platforms 2 and 3 are different, and the adhesive 5 can be used according to various semiconductor processes. The choice, the curing, and the parts are therefore different, so the application of the invention should not be limited thereto. For example, the first coating platform 2 may not be provided with the fixing hole 21, and the first coating platform 3 may not be provided with the fixing hole 31, but directly integrated into the i-shaped and _ stable structure. For example, the chassis of the test machine is more than 疋. Similarly, the detecting platform 1 may not be provided with the fixing hole 13 but directly combined with the tensioning device. Of course, the tension device can be connected to a recorder (not shown, such as a personal computer and analysis software), PK10324 2007/6/7 10 - 200848730 in order to record the plating damage required for previous tests. In other words, the spirit of the present invention is that the detection platform 1 can simultaneously apply the two wafers to be tested 4 as long as the two coating platforms 2 仏 3 ^ ^ are placed on the symmetrical sides of the detection platform 1 . The same amount of damage is applied to minimize the positive component of the two phases 2 generated between the layers of the two wafers to be tested 4 or between the layers to more accurately measure the external force that is destroyed. Thanks to the detection platform of the invention! The first coating platform 2 and the second coating platform 3 are each formed by using only a plurality of simple planes, and the coffin 5 is manually or mechanically applied directly to the plane.

:Π:Γ僅十分簡易且快速,同時更具有精= 效果’另外’因結構精簡,進行測量所需之膠材$較少, :!=:量所需之成本。因此,對於晶片封裝及晶圓 生產製造成品並進行晶片之相關檢測’ ㈣門L j需要滿足其需求,並可針對晶片4的各層 =間:或曰曰片4的各層本身之強度,或該膠材5熱固化 後契铺測晶4之間的膠合強度進行精確量剛。 綜上所述,相較於習用之晶片強度測試|置,因為 ’造成測量得到之封裝結合強度或剪 ° 實施_為使用檢測平台用以固置 -待測4,待測晶片其—固置於檢測平台—方 置於檢測平台另—方;以及使用二膠材塗測平台,宜一位 於才双測平台一方,另一位於檢測平台另-方,用以將液能 或固態膠材塗覆於待測晶片上。因此,待液態或固態膠ί ΡΚ10324 2007/6/7 200848730 黏合固定於待測晶片之後,檢測平台能對二待測晶片之層 間結構,施予一相同大小之破壞力,且能夠將毁損外力造 成之正向分力減至最小,以便測量並紀錄該二待測晶月其 中之層間之強度,倘若晶月層間結構良好,當該膠材毀 知丽,該待測晶片並未毀損,則紀錄該待測晶片之強度符 合規格。 雖然本發明已利用上述較佳實施例揭示,然其並非 用以限定本發明,任何熟習此技藝者,在不脫離本發明之 矛範圍之内,當可作各種更動與修改,因此本發明之 保護範圍當視後社申請專利範_界定者為準。:Π:Γ is only very simple and fast, and at the same time has a fine = effect 'other' because of the structure is reduced, the amount of glue required for measurement is less, :! =: the cost required. Therefore, for wafer packaging and wafer production, the finished product is processed and the related inspection of the wafer is performed. (4) The gate L j needs to meet its requirements, and can be directed to the strength of each layer of the wafer 4 = between: or the layers of the wafer 4 itself, or After the heat curing of the rubber material 5, the bonding strength between the crystals 4 is accurately measured. In summary, compared to the conventional wafer strength test | set, because 'the resulting package bonding strength or shear ° implementation _ for the use of the detection platform for fixing - to be tested 4, the wafer to be tested - it is fixed In the inspection platform—the square is placed on the inspection platform, and the second rubber coating platform is used. One is located on the side of the dual-test platform, and the other is located on the other side of the inspection platform to coat the liquid or solid glue. Overlay on the wafer to be tested. Therefore, after the liquid or solid glue 10524 2007/6/7 200848730 is bonded and fixed to the wafer to be tested, the detecting platform can apply a same magnitude of destructive force to the interlayer structure of the two wafers to be tested, and can cause damage to the external force. The positive component force is minimized to measure and record the strength between the layers of the two crystal cells to be measured. If the interlayer structure of the crystal is good, when the glue is damaged, the wafer to be tested is not damaged, then the record is recorded. The strength of the wafer to be tested conforms to specifications. Although the present invention has been disclosed in the above-described preferred embodiments, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spear of the present invention. The scope of protection shall be subject to the definition of the patent application patent.

PK10324 2007/6/7 12 — 200848730 【圖式簡單說明】 第1圖:習用晶片強度測試裝置之侧視圖。 第2圖:本發明較佳實施例之晶片層間強度測試裝 置之侧視圖。 第3圖:本發明較佳實施例之晶片層間強度測試裝 置之使用示意圖。 第4圖:本發明較佳實施例之晶片層間強度測試裝 置之第一塗測平台之立體圖。 【主要元件符號說明】PK10324 2007/6/7 12 — 200848730 [Simple description of the diagram] Figure 1: Side view of the conventional wafer strength test device. Figure 2 is a side elevational view of a wafer interlaminar strength test apparatus in accordance with a preferred embodiment of the present invention. Figure 3 is a schematic illustration of the use of a wafer interlaminar strength test apparatus in accordance with a preferred embodiment of the present invention. Figure 4 is a perspective view of a first coating platform of a wafer interlayer strength testing apparatus in accordance with a preferred embodiment of the present invention. [Main component symbol description]

1 檢測平台 11 第一表面 12 第二表面 13 固定孔 2 第一塗測平台 21 固定孔 3 第二塗測平台 31 固定孔 4 待測晶片 5 膠材 6 外力方向 6, 外力方向 7 檢測平台 8 待測物 81 晶片 82 灌膠成型成品 9 檢測棒 PK10324 2007/6/7 131 Detection platform 11 First surface 12 Second surface 13 Fixing hole 2 First coating platform 21 Fixing hole 3 Second coating platform 31 Fixing hole 4 Chip to be tested 5 Adhesive material 6 External force direction 6, External force direction 7 Detection platform 8 Test object 81 wafer 82 glue molding finished product 9 detection rod PK10324 2007/6/7 13

Claims (1)

200848730 十、申請專利範圍·· 1、一種晶片層間強度測試裝置,包含·· -檢測平台,其具有互相平行之表面及—第二 表面,以供二待測晶片藉由一膠材黏附; ~ 第塗身/平台,其係鄰近該檢測平台之第一表面 並以膠材黏I於該第一表面之待測晶片上;及 一第二塗測平台,其係鄰近於該檢測平台之第二表 ,並以膠材黏著於該第二表面之待測晶片上; 其中’待該膠材黏合固定於該二待測晶片之後, =檢測平台’當該二待測晶片其中之一產生層間結構 ,毀知後,測量並紀錄該二待測晶片其中之一層門之 g?纟’當該膠材毀損前,該待測晶片並未毁損^ 該待測晶片之強度符合規格。 ’、 2 依申請專職圍第丨項所述之晶片層間強度測試 ’其中該膠材係選自一液態膠材。 依申請專利範圍第2項所述之晶片層間強度測試 ,其中該膠材之黏合固定方法係將該膠材依其妖固化 條件進行固化。 ^ 4、 依申請專利範圍第1項所述之晶片相強 ,其中紐損外力係―相對於該檢測平台及魏^ 材塗測平台之平面之剪向切力。 心私 5、 依申/專利範㈣1項所述之晶片層間強度測試裝置 、中該第-塗測平台及第二塗測平台之至 有一平面,以供該膠材進行塗覆。 〃、 PK10324 2007/6/7 —_ _ 200848730 6、 依申請專利範圍第1項所述之晶片層間強度測試裝置 ,其中該第一塗測平台及第二塗測平台之至少一個具 有一固定孔。 7、 依申請專利範圍第1項所述之晶片層間強度測試裝置 : ,其中該檢測平台具有一固定孔。 , 8、依申請專利範圍第1項所述之晶片層間強度測試裝置 ’其中該膠材之塗佈面積係相等於該待測晶片之面積 〇 ί 9、依申請專利範圍第1項所述之晶片層間強度測試裝置 ,其中當該二待測晶片其中之一,其產生層間結構毁 損係於表面保護層與介電層。 ΡΚ10324 2007/6/7 15 —200848730 X. Patent Application Range·1. A wafer interlaminar strength testing device, comprising: a detection platform having mutually parallel surfaces and a second surface for attaching two substrates to be tested by a glue; a first coating body/platform adjacent to the first surface of the detection platform and adhered to the wafer to be tested on the first surface by a glue material; and a second coating platform adjacent to the inspection platform a second meter, and adhered to the wafer to be tested on the second surface with a glue; wherein 'after the adhesive is adhered to the two wafers to be tested, the detection platform' generates an interlayer when one of the two wafers to be tested After the structure is destroyed, the one of the two layers of the wafer to be tested is measured and recorded. The wafer to be tested is not damaged before the adhesive is damaged. ^ The strength of the wafer to be tested conforms to the specifications. ', 2 According to the application of the full-time 丨 丨 之 之 晶片 晶片 晶片 晶片 晶片 ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ ’ According to the inter-layer strength test of the wafer according to Item 2 of the application patent, the adhesive fixing method of the adhesive is to cure the adhesive according to the curing condition of the bristles. ^ 4, according to the patent scope of the first paragraph of the wafer phase strength, wherein the external force is the shearing force relative to the plane of the detection platform and the surface of the coating platform. 5. The wafer inter-layer strength testing device, the first-coating platform and the second coating platform described in the above-mentioned application/patenting section (4) have a flat surface for coating the rubber material. The wafer inter-layer strength testing device according to claim 1, wherein at least one of the first coating platform and the second coating platform has a fixing hole. . 7. The wafer interlayer strength testing device according to claim 1, wherein the detecting platform has a fixing hole. 8. The wafer interlayer strength testing device according to item 1 of the patent application scope, wherein the coating area of the glue material is equal to the area of the wafer to be tested 〇ί 9, according to the first item of the patent application scope. A wafer interlayer strength testing device, wherein one of the two wafers to be tested, which causes interlayer structure damage, is attached to the surface protective layer and the dielectric layer. ΡΚ10324 2007/6/7 15 —
TW96120511A 2007-06-07 2007-06-07 Test apparatus for chip strength TWI334028B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387414B (en) * 2009-06-01 2013-02-21 Univ Yuan Ze High speed ball shear machine
CN109374439A (en) * 2018-10-23 2019-02-22 北京航天时代光电科技有限公司 A kind of Y waveguide integrated optical device chip shear test tooling and cutting method
CN111208018A (en) * 2020-01-10 2020-05-29 长江存储科技有限责任公司 Detection method and detection device for semiconductor structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI387414B (en) * 2009-06-01 2013-02-21 Univ Yuan Ze High speed ball shear machine
CN109374439A (en) * 2018-10-23 2019-02-22 北京航天时代光电科技有限公司 A kind of Y waveguide integrated optical device chip shear test tooling and cutting method
CN109374439B (en) * 2018-10-23 2021-04-13 北京航天时代光电科技有限公司 Y waveguide integrated optical device chip shearing test tool and shearing method
CN111208018A (en) * 2020-01-10 2020-05-29 长江存储科技有限责任公司 Detection method and detection device for semiconductor structure

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