200843605 " 九、發明說明： *【發明所屬之技術領域】 本發明是有關不包含具有藉由引洞（via)連接而導通 •連接之穿孔（through hole)的核（core)基板之半導體用多層 .電路基板，且有關藉由將導體電路層與絕緣層交互地單面 積層之增建（build up)方法所製作的多層電路基板及半導 【先前技術】 近年在半導體領域，自高密度安農技術之進步以來就 有由以往之面安㈣向區域性安裝之傾向，而持續開發並 增加BGA (Ball Grid A卿；球閘陣列封裝）或csp卿p200843605 " IX. Description of the invention: * [Technical field to which the invention pertains] The present invention relates to a semiconductor for a core substrate that does not include a through hole that is connected and connected by a via connection. Multilayer circuit substrate, and multilayer circuit substrate and semi-conductor fabricated by a build-up method of a single-area layer in which a conductor circuit layer and an insulating layer are alternated. [Prior Art] In recent years, in the field of semiconductors, since high density Since the advancement of Annong technology, there has been a tendency to install from the past (4) to the regional, and continue to develop and increase BGA (Ball Grid A; ball gate array package) or csp clear p
Scale Package;晶片尺寸封震）等新的封裝。又資訊傳達之 =速化也正進行中。因此，中介層（interpQser)用硬質（r_ 土板係變付比以前更受到注目，而對高耐熱、低熱膨服、 低誘電基板（low dielectric substme)之要求也變高。 再者，隨著電子機器的高機能化等之要求，而邁向電 冬件的*密度聚集化，更邁向高密度安裝化等，在此所 對應高密度安㈣半導體用多層電路基板等係比以 1邁向小型化及高錢化。此半導體用多層電路基板等 之對應商密度化手段係多採用增建多層電路基板。 又：取代以在一直使用之增建多層電路基板(第 半導❹多層電路基板之更薄魏、高速信號化， f鐵有不^具有藉由引洞接連而導通接連之穿孔的核基 板之由在單面上將導體電路層與絕緣層交互地增建而成之 319876 5 200843605 —多層電路基板（第2圖），其中，在多層電路基板之一邊的 -面上形成内墊（inner pad)，在另一邊之面上形成外墊（〇ut pad)(例如，參照專利文獻1 :日本特開2〇〇〇一 323613號 •公報）。 ^ θ然而，由於是在單面上積層，故在以往使用之絕緣層 疋會隨著絕緣層之薄型化而降低彈性模數，又由於絕緣層 之線膨脹係數為與導體電路之線膨脹係數不同，所以在多 φ層電路基板之製造步驟中，多層電路基板有大幅反鍾之問 題。 :了抑制夕層電路基板之反_，而檢討將2片金屬 =對向組合製成一體化的複合金屬板，在此複合金屬板 =2互地積層導體電路層與絕緣層，最後剝開黏在 、：“反，错由蝕刻金屬板而可得到多層 二=專利文獻 2,2。。3,92一^ 僅如此則仍不能達到充分的改善。 【發明内容】 本發明是在由單面積層而成之多層電路基板中，繁 中’二多路基板’且在進行安裝半導體元件之‘ 在、仃女裝半導體元件後的信 反翹少之多層電路基板及半導體裝°置/〜， 53^目的’記載”述⑴至_本發明 1 J種多層電路基板，苴# i * 與絕緣層所形成，為不包含且稷數組之導體電萬 之穿孔的核基板之單面積連接而導通驾 層之夕層電路基板，其特徵為 319876 200843605 前述絕緣層的玻璃移轉溫度為l7(rc以上，在破璃移轉溫 度以下之線膨脹係數為35 ppm以下，彈性模數為5Gpa以 上。 [2] 如[1]所述之多層電路基板，其中，前述絕緣層中 至少有一層為含有纖維基材者。 、 [3] 如[2]所述之多層電路基板，其中，前述含有纖维 基材之絕緣層係至少具有第！樹脂詹、第2樹脂層、及纖 維基材，且在第1樹脂層與第2樹脂層之間介設有纖維基 材。 土 [4] 如[3]所述之多層電路基板，其中，前述第i樹脂 層之厚度m與第2樹脂層之厚度B2之比值（B2/bi)為滿 足 0<B2/B1$ 1 者。 [5] 如[2]所述之多層電路基板，其中，前述絕緣層之 纖維基材厚度為10至35以m。 [6] 、如[2]所述之多層電路基板，其中，前述纖維基材 為玻璃纖維布（Glass Cloth)。 ⑺如⑴所述之多層電路基板，其中，前述絕緣層為 由3有氰酸酯樹脂之樹脂組成物所構成者。 [8]種半‘體裝置’其特徵是使用上述⑴所述 層電路基板。 【實施方式】 本發明知半導體用多層電路基板，多層電路基板係例 如可=在如BGA之半導體元件搭载基板上。 弟1圖係表示以往之代表性的增建多層電路基板的 319876 7 200843605 圖。第2圖係表示在本發明相關的由複數組的導體電路層 -與絕緣層所形成，且不包含具有藉由引洞（yia)連接而導通 連接之穿孔的核基板之單面積層的多層電路基板的概略結 .構圖，其中，在多層電路基板之一邊的面上形成内塾，在 *另一邊之面上形成外墊。 在本發明之多層電路基板中所使用的絕緣層之玻璃 移轉溫度是以170t；以上為宜。更佳為以上。若小於 _上述範圍，在製造步驟加熱後回到室溫時之反翹會變大。 控制多層電路基板之反翹的因素，可列舉玻璃移轉溫度以 I的線膨脹係數。若線膨脹係數為35 ppm以上，則與通 常在電路巾所使用軸之線膨脹係數（17 i i8 ppm/t) 相比係變大2倍以上，而為反趣變大之原因。又，本發明 之多層電路基板之彈性模數是以在5GPa以上為佳。:發 明之多層電路基板與.以往之多層電路基板相比，由於沒有 核層，故為了保持形狀而以彈性模數為5 以上者為宜。 本發明使用之絕緣層，以含有玻璃纖維基材或有機纖 維基材作為纖維基材者為宜，例如，可列舉如作為玻璃纖 維基材的玻璃織布、玻璃不織布等玻璃纖維布（⑽μ㈤⑻ =作為有機纖維基材的有機織布、有機不織布等。在多層 電路基板中含有纖維基材的絕緣層係至少要有一層為宜。 因此：使用如此纖維基材的絕緣層，因為構成纖：基材的 纖維：不t發生彎曲’所以彈性模數等機械特性為優異。 3有七述纖維基材的絕緣層，較佳為至少具有第工樹 曰第2树月曰層、及纖維基材，且在第丨樹脂層與第2 8 319876 200843605 樹脂層之間介設有纖維基材者。 * …又，若依本發明之較佳的態樣，可列舉如上述絕緣層 的第1樹脂層厚度B1與第2樹脂層厚度B2之比值（B2; • B1)滿胃足0<B2/Blgl者。亦即，纖維基材係相對於絕緣 層的厚度方向為不均勻分布。因内層的電路圖型而使需要 之樹脂量有所不同時，樹脂可能有擠出之情形，或有掩埋 電路=樹脂不足之情形。本發明之絕緣層即使是在此情 • ^藉由適度调整第1樹脂層與第2樹脂層之厚度，而變 化纖維基材之厚度方向之位置，可充分掩埋電路，又可防 止不必要之樹脂擠出。 此比值（Β2/Β1)以在〇.5以下為宜，尤其以在〇2至 〇·4更佳，此比值（Β2/Β1)在上述範圍内時，特別可降低 纖維基材之起伏，依此而使絕緣層的平坦性可更加提升。 本發明使m㈣，為了降低絕緣層之線膨服係New packages such as Scale Package; And the information is conveyed = speeding is also in progress. Therefore, the inter-layer (interpQser) is hard (r_ soil-based conversion is more noticeable than before, and the requirements for high heat resistance, low heat expansion, and low dielectric substme are also higher. In the high-performance of electronic equipment, the density of the electric components is increasing, and the high-density mounting is required. The high-density (4) semiconductor multilayer circuit board is equivalent to one. In order to miniaturize and increase the cost, the multi-layer circuit board and the like have been used to increase the number of multi-layer circuit substrates. In addition, the multi-layer circuit substrate (the semi-conductive multilayer circuit) has been replaced by the conventionally used multi-layer circuit substrate. The substrate is thinner, high-speed signalized, and f-iron has a core substrate having a via which is connected by a via hole to be connected to each other, and the conductor circuit layer and the insulating layer are alternately added on one side, 319876 5 200843605 - Multilayer circuit substrate (Fig. 2), wherein an inner pad is formed on one side of one side of the multilayer circuit substrate, and an outer pad is formed on the other side (for example, reference) Patent 1: JP-A-2-231613 • Bulletin. ^ θ However, since the layer is laminated on one side, the insulating layer used in the past will decrease the modulus of elasticity as the thickness of the insulating layer is reduced. Moreover, since the linear expansion coefficient of the insulating layer is different from the linear expansion coefficient of the conductor circuit, the multilayer circuit substrate has a large problem in the manufacturing steps of the multi-φ layer circuit substrate. And review the two pieces of metal = opposite combination into an integrated composite metal plate, where the composite metal plate = 2 mutually laminated conductor circuit layer and insulation layer, and finally peeled off,: "reverse, wrong by etching A metal plate can be used to obtain a plurality of layers 2 = Patent Document 2, 2. 3, 92 - ^ This is not enough to achieve sufficient improvement. [Invention] The present invention is in a multilayer circuit substrate formed of a single-area layer. In the case of the "two-way multi-path substrate", the multi-layer circuit board and the semiconductor device are mounted on the semiconductor device, and the semiconductor device is mounted on the semiconductor device. _Inventive 1 J multi-layer The circuit board, which is formed of an insulating layer, is a single-layer circuit substrate that is connected to a single-core substrate of a core substrate that does not include a plurality of perforated conductors, and is characterized by a 319876 200843605 insulating layer. The glass transition temperature is l7 (rc or more, the linear expansion coefficient below the glass transition temperature is 35 ppm or less, and the elastic modulus is 5 GPa or more. [2] The multilayer circuit substrate according to [1], wherein The multilayer circuit board according to the above [2], wherein the insulating layer containing the fiber base material has at least a resin, a second resin. A layer and a fibrous base material, and a fibrous base material is interposed between the first resin layer and the second resin layer. [4] The multilayer circuit board according to [3], wherein a ratio (B2/bi) of a thickness m of the i-th resin layer to a thickness B2 of the second resin layer is 0/B2/B1$1 . [5] The multilayer circuit substrate according to [2], wherein the insulating layer has a fiber base material having a thickness of 10 to 35 m. [6] The multilayer circuit substrate according to [2], wherein the fiber base material is a glass cloth (Glass Cloth). (7) The multilayer circuit board according to the above aspect, wherein the insulating layer is composed of a resin composition of three cyanate resin. [8] A half-body device is characterized in that the layer circuit substrate described in the above (1) is used. [Embodiment] The present invention relates to a multilayer circuit board for a semiconductor, and the multilayer circuit board can be, for example, a semiconductor element mounting substrate such as a BGA. The figure 1 shows a representative representative of a conventional multilayer circuit board 319876 7 200843605. Fig. 2 is a view showing a multilayered single-layer layer of a core substrate formed of a plurality of arrays of conductor circuits--insulating layers and having no vias connected by yia connection according to the present invention. A schematic diagram of a circuit board in which an inner crucible is formed on one side of a multilayer circuit board and an outer mat is formed on the other side of the *. The glass transition temperature of the insulating layer used in the multilayer circuit substrate of the present invention is preferably 170 t; More preferably. If it is less than the above range, the backlash will become large when it is returned to room temperature after heating in the manufacturing step. The factor for controlling the backlash of the multilayer circuit substrate is exemplified by the coefficient of linear expansion of the glass transition temperature by I. If the coefficient of linear expansion is 35 ppm or more, it is twice as large as the linear expansion coefficient (17 i i8 ppm/t) of the shaft used in the circuit towel, which is a cause of aggravation. Further, the multilayer circuit substrate of the present invention preferably has an elastic modulus of 5 GPa or more. In the multilayer circuit board of the invention, since there is no core layer as compared with the conventional multilayer circuit board, it is preferable to have a modulus of elasticity of 5 or more in order to maintain the shape. The insulating layer used in the present invention is preferably a glass fiber substrate or an organic fiber substrate as a fiber substrate. For example, a glass fiber cloth such as a glass fiber substrate or a glass nonwoven fabric ((10) μ(5)(8) = An organic woven fabric, an organic nonwoven fabric, or the like as an organic fiber base material. It is preferable to have at least one insulating layer containing a fibrous base material in a multilayer circuit substrate. Therefore, an insulating layer of such a fibrous base material is used because it constitutes a fiber base. The fiber of the material: no bending occurs, so the mechanical properties such as the elastic modulus are excellent. 3 There are seven insulating layers of the fibrous substrate, preferably at least the second tree of the second tree, and the fibrous substrate. And a fibrous substrate is interposed between the second resin layer and the resin layer of the 2 8 319 876 200843605. Further, according to a preferred aspect of the present invention, the first resin such as the above insulating layer may be mentioned. The ratio of the layer thickness B1 to the thickness B2 of the second resin layer (B2; • B1) is full of stomach 00&B; B2/Blgl, that is, the fiber substrate is unevenly distributed with respect to the thickness direction of the insulating layer. Circuit pattern When the amount of resin required is different, the resin may be extruded or there may be a case where the buried circuit = resin is insufficient. Even if the insulating layer of the present invention is in this case, the first resin layer and the second layer are appropriately adjusted. The thickness of the resin layer, and changing the position of the thickness direction of the fiber substrate, can fully bury the circuit and prevent unnecessary resin extrusion. The ratio (Β2/Β1) is preferably less than 55, especially in More preferably, 〇2 to 〇·4, when the ratio (Β2/Β1) is within the above range, the undulation of the fibrous base material can be particularly lowered, whereby the flatness of the insulating layer can be further improved. The present invention makes m (four) for Reduce the line expansion of the insulation layer
^以使用亂酸酯樹脂為宜。說酸醋樹脂可使用例如由齒 ㈣與賴反應而成者、或將此以加熱等方法而預聚 二=寺雔具體而言’可列舉如軸青漆型(―)氰酸 甲二ΓA型氰酸醋樹脂、雙齡E型氰酸酯樹脂、四 甲基雙^魏酸_脂等㈣㈣酸等。 酯樹腊之中，若使用崎漆型氰酸酯樹 二=交聯密度而可更加提高耐熱性的同時， :=p:tr薄型物作為乃附有㈣之預浸體—） 布時，也可賦予附有㈣之預浸體之 硬化物優兴之剛性（彈性模數），尤其可提高在加熱時之别 319876 9 200843605 - 性（彈性模數)。 因此’將此附有銅箔之預浸體應用在已安裝半導體零 件之封裝基板上時，可提高其連接信賴性。 又’藉由使用酚醛清漆型氰酸酯樹脂，可提高硬化物 j難燃性。判定其原因是酚醛清漆型氰酸酯樹脂在結構上 苯％所佔比率偏高，因而容易碳化之故。 上述盼齡清漆型氰酸酯樹脂，例如以使用下述一般式 • (1)所示者為宜。^ It is preferred to use a chaotic acid ester resin. It is said that the acid vinegar resin can be used, for example, by reacting the teeth (four) with the lanthanum, or by preheating the method by heating or the like. Specifically, it can be exemplified as a shaft blue lacquer type (-) cyanuric acid Type cyanic acid vinegar resin, double age E type cyanate resin, tetramethyl bis-weilic acid _ lipid, etc. (4) (tetra) acid. In the ester tree wax, when the lacquer-type cyanate tree 2 = cross-linking density is used, the heat resistance can be further improved, and the :=p:tr thin material is attached to the (4) prepreg-) cloth. It is also possible to impart rigidity (elastic modulus) to the hardened material of the prepreg (4), and in particular to increase the temperature (3198.1 9 200843605) (characteristic modulus of elasticity) when heated. Therefore, when the prepreg with the copper foil is applied to the package substrate on which the semiconductor component is mounted, the connection reliability can be improved. Further, by using a novolac type cyanate resin, the flame retardancy of the cured product j can be improved. The reason for this was judged to be that the novolac type cyanate resin had a high proportion of benzene in the structure, and thus it was easy to be carbonized. The above-mentioned aging-type varnish-type cyanate resin is preferably used, for example, by using the following general formula (1).
上述一般式（1)所示之酚醛清漆型氰酸酯樹脂之重複 w元η例如可使用j至丨〇者，而以2至7者為特別適宜 使用。 一藉此，使酚醛清漆型氰酸酯樹脂之處理性、或硬化物 之又％猪度良好者，可作為此等特性的平衡優異者。 上述η數太小時，變得易結晶化，對於泛用溶劑之溶 解性變小且處理性變差。另—方面，上述續太大時，硬 化物之交聯密度過剩而變高，產生耐水性下降或硬化物變 脆寺現象。 旦就上述氰酸酯樹脂之分子量而言，例如重量平均分子 里（Mw)可使用5〇〇至4,5⑼者，特別可適用議至3,刪 者。 ’ 319876 10 200843605 藉此’使製作附有載體（carrier)之預浸體時的處理 1*生或衣作夕層電路基板時的成形性、層間剝離強度等良 好者，可作為此等特性之平衡優異者。 ^上述Mw太小時，製作附有載體之預浸體時會產生黏 著（減)性，會使處理性降低。另—方面，上述Mw太大時， 則反應變快，在製作多層電路基板時有成形不良或層間剝 離強度下降之情形。 上述i酸酷樹脂較佳為可使用Mw在上述範圍内者之 中的-種，亦可併用Mw為不同之2種以上者。 層析法又二氛酸，樹㈣ 本發明所使用之絕緣層中，構成 =構=2樹脂層之_組成物可為"之= 二=1'同樹脂組成物作為第r樹脂層與第2樹脂 "I 可^更使用之樹月旨種類或使用量，亦可㈣# 無機充填材等添加劑之種類或使用量 ： :=成物作為第1樹脂層與第2樹脂層 應所要求之性能爽号呌斟昨昆 ^ 丁 又传可因 耒计树月日層，有可使樹脂選擇之卢声㈣ '點。例如’面對内層電路之樹脂層可考，到：：、文 而做成柔軟的組成，相反側之面:到掩埋性 成：均勾地粗磁化的組成等，在絕緣；的而做 之機能。 w卸了賦予不同 在本發明所使用之絕緣層中， 無特別限定者，但以比第2樹赌層之厚度度 319876 200843605 • 1樹脂層所掩埋之電路層只要為可掩埋者即可。例如 ♦ •經掩埋之電路層之厚度為Τ，第1樹脂層之厚度^ t時當 (T/t)是以 0.3S(T/t)S1.5 為宜，更佳為 〇5$汀/=)2 • 1，一般而言，為了充分掩埋電路，以將面對内層電路之 *脂層的厚度變厚為宜。 & 本發明使用之纖維基材，在上述纖維基材之中，也以 玻璃纖維布為宜，玻璃纖維布之厚度舉例如可使用1 〇 、 ⑩180/zm者。又，基重（每lm2之玻璃纖維布重量）可使用例 如12至209g/m2者。尤其以使用玻璃纖維布之厚度為忉 至35/zm，基重為12s25g/m2之薄的破璃纖維布^佳。 在本發明中，尤其以線膨脹係數（CTE: c〇efficient〇f Thermal Expansion)在6 ppm以下之玻璃纖維布為更佳又 以3 · 5 ppm以下之玻璃纖維布為特佳。藉由使用具有如上 述之線膨脹係數的玻璃纖維布，則·可有效地抑制由本發明 使用之絕緣層所構成的多層電路基板以及使用該多層電路 •基板之半導體封裝的反翹。 再者，本發明使用之玻璃纖維布是以揚氐率在62至 lOOGPa為宜，較佳為65至92GPa，更佳為89至92(}pa。 當玻璃纖維布之揚氐率在上述之範圍時，由於例如可有效 地抑制半導體安裝時因回流（reflow)熱而造成之電路基板 的變形，故可提高電子零件之連接信賴性。 又，本發明使用之玻璃纖維布，以在1MHz的介電常 數為3.8至7.0為宜，較佳為4.7至7·0,更佳為5.4至6 8。 玻璃纖維布之介電常數在上述範圍時，可降低絕緣層之介 12 319876 200843605 電常：古可適用在使用高速信號之半導體封裝中。 纖唯布、二上34之線膨脹係數、楊氐率及介電常數之破璃 本發明使用之破璃纖維布之厚度，以10至 宜，較佳為10至20 為 限定一 使用之破璃纖維布片數並不 重晶，可重疊複數片薄玻璃纖維布來使用。同時， 重^:稷數以_料來使料 述範圍就可以。 口子度/、要滿足上 方法將本Γ?所使用之樹脂組成物含浸在纖維基材中的 ’亚…、特龍制，刊舉有··將樹* 劑中調製成樹脂租成物、、主、、先*、，+ 謂錢至J冷 潰纏…二： 丽述樹脂組成物清漆中浸 .' 法，將該樹脂組成物清漆以各種塗布機塗 布到纖維基材之塗布方法；藉由喷霧而之吹附之方法ς 附有支持基材之樹脂層予以積層之方法等。此等之中，以 將纖維基材浸潰在樹脂組成物清漆中的方法為佳，藉此， 可，高樹脂組成物對於纖維基材之含浸性。又’將‘維基 材浸潰在樹脂組成物清漆巾時，可使料常之含浸塗布ς 備。 ϋ 尤其是當纖維基材之厚度在〇.〇45mm以下時，以從纖 維基材之兩面積層薄膜狀之樹脂層的方法為宜。藉此，可 自由自在地調節樹脂組成物對纖維基材之含浸量，可提高 絕緣層的成形性。X，藉由分別改變從兩面積層之樹脂: 之厚度，而可在纖維基材之表面内面自由變更樹脂層之厚 度。又，當積層薄膜狀之樹脂層時，以使用真空的積層裝 319876 13 200843605 置等較佳。 具體而言，製造含有纖維基材之絕緣層的方法，可 舉如以下之方法。 第12圖表示製造樹脂層2之步驟的—個例子之步驟 圖在此，針對預先製造載體材料5a、％，將此載體材料 a 5b積層在纖維基材卩上之後，剝離載體薄膜之方法， 具體說明之。 預先製造由將第-樹脂組成物塗布在載體薄膜上而 —之载i材料5a ’與由將第二樹脂組成物塗布在別的載體 ::上：成之載體材料5b。此時，藉由先變更第一樹脂組 之4度與帛二賴組成物之厚度，料將在纖維基材 ^面内面上所形成之樹脂厚度予以自由變更。其次，使 用真空積層裝置6，在減壓下 纖維基材之兩面重疊載 姑人 檟層輥61接合。如此，藉由在減壓下 即使在纖維基材U之内部或在載體材料5a、％之 纖維基材η接合之部位存在有非充填部份，也可 將此作為減壓空洞或實質的直处 铁路π从 貝貝耵具工空洞。因此，可減少在最 直介：之"曰層2中所產生之空洞。此係由於減壓空洞或 洞：用後述之加熱處理而消除。作為在如此之減麗 下使纖維基材11盥载俨鉍袓< ^ 如^ ”戟版材科5a、讣接合之其他裝置，例 如可使用真空箱裝置等。 埶其二f’在纖維基材11與载體材料5a、5b接合後，用 …、風乾燥裝置62 ’以在载體材料 ^ ^ 戰舨材枓上塗布之樹脂的熔融溫度 之溫度進行加熱處理。藉此，在前述減屢下於接合步 319876 14 200843605 •驟中所產生之減壓空洞等幾乎可穸令姑、^ .古土 ^ 手戍十了凡王被扁除。加熱處理之 ，、他方法’例如可使用紅外線加熱裝置、加 板狀之熱盤加麗裝置等來實施。 …、輥衣置、平 • 將载體材料5a、5b積層在纖維基材u ， •載體薄膜。藉由此方法，可在输维其好"之後剝離 料，而獲得内藏有纖維基材u之絕緣層。#持树月曰材 物、主基材浸潰在樹脂域物清料，樹脂组成 漆中所使用之溶劑，雖然期望其對則旨組成物中之: 月曰成分顯示有良好溶解性，但在 A 旦/ 亦可使用弱溶劑。•干有W解、机衫’之乾圍内 剑鴻不有良好洛解性之溶劑，可列皋如· 丙_、甲基乙基，、甲基異丁基鲷、環已，、四氫料： 一甲基甲醯胺、二甲基乙軸、二甲基亞硬、乙二醇、溶 纖劑（cellosolve)系、卡必醇（carbit〇1)系等。 彳 前述樹脂組成物请漆之固形成分，並無特別限定 以…〇重量％為宜，尤其以50至65重量％為佳。藉 此’可更加提高樹脂組成物清漆對於纖維基材的含浸性。 藉由在前述纖維基材中含浸前述樹脂組成物，並在預定之 溫度，例如在80至20(TC等使其乾燥，而可得到絕緣層。 其次，針對本發明之多層電路基板之製造方法的一個 例子使用實施例之第3圖至n圖說明，但不一定侷限於 此0 實施例 [實施例1] 首先，將預浸體5(住友電木（股）製EI— 6785Gs，厚度 319876 15 200843605 ，0·2 mm)使用2張250x250mm正方形之可剝離（Peelable)型 ， 之附有載體銅箔之銅羯（古河電氣工業（股）製：9//m銅箔， 品名F—DP附有銅載體之極薄電解銅箔、載體銅箔70# • m)以使附有載體銅箔之銅箔中的載體銅箔4相接於預浸體 • 5之方式挾住，加壓（3MPa)加熱（180°C)放置1小時而獲得 支持基材（第3圖）。 支持基材之表面經軟性蝕刻處理後，使乾膜抗蝕劑（東 ⑩京應化工業（股）製：AR — 320，膜厚20//m)對支持基材的 兩面進行輥積層，使用預定之圖案形成用遮罩來曝光、顯 像，形成在導體電路之形成中所需要的抗電鍍層。其次， 使支持基材作為電解電鍍用之導線，藉由電解電鍍金而形 成0.1//m之電鍍金層7，在其上藉由電解電鍍鎳而形成3 //m之電鍍鎳層8，再於其上藉由電解電鍍銅而形成14// m之電鍍銅層9，而得到導體電路層60。其次，將乾膜抗 蝕劑剝離（第4圖）。 • 其次，在導體電路層60之表面上藉由粗糙化液 (Atotech Japan(股）製：Bond film)浸潰處理 90 秒鐘。其 次，將藉由本發明之内有玻璃纖維布之絕緣層a (住友電木 (股）製：APL — 3651玻璃纖維布種玻璃不織布（曰本 Vilene(股）製；EPC4015玻璃纖維布厚度12/zm)絕緣層厚 度40/zm、以PET薄膜作為支持薄膜）裁斷成240x240mm 之正方形，對導體電路層60之兩面進行真空加壓（名機製 作所（股）製MVLP— 500/600-ILA)，在第1次為溫度80 °C、壓力0.5MPa，第2次為溫度100°C、壓力l.OMPa之 16 319876 200843605 ， 條件下形成，在150°C加熱30分鐘之後，剝離PET薄膜， ^ 作成絕緣層10 (第5圖）。The repeating w element η of the novolak type cyanate resin represented by the above general formula (1) can be, for example, j to be used, and 2 to 7 is particularly preferably used. As a result, it is possible to make the novolac type cyanate resin rational or the cured product having a good pig's degree, and it is excellent in the balance of these characteristics. When the number of η is too small, it becomes easy to crystallize, and the solubility in a general-purpose solvent is small and the handleability is deteriorated. On the other hand, when the above is too large, the crosslinking density of the hard material becomes excessive and becomes high, resulting in a decrease in water resistance or a phenomenon in which the hardened material becomes brittle. In the case of the molecular weight of the above cyanate resin, for example, a weight average molecular weight (Mw) may be used in the range of 5 Å to 4, 5 (9), and it is particularly applicable to 3, whichever is the case. '319876 10 200843605 This is a good condition for forming a prepreg with a carrier, and when it is excellent in formability and interlayer peel strength when processing a 1* raw or a printed circuit board substrate, it can be used as such characteristics. The balance is excellent. ^ When the above Mw is too small, adhesion (decrease) occurs when the prepreg with the carrier is produced, and the handleability is lowered. On the other hand, when the Mw is too large, the reaction becomes fast, and when the multilayer circuit board is produced, there is a case where the molding is poor or the peeling strength between the layers is lowered. The above-mentioned i-acid-cooling resin is preferably one which can be used in the above range of Mw, and two or more kinds of Mw may be used in combination. The chromatographic method is also a secondary acid, and the tree (4) In the insulating layer used in the present invention, the composition of the structure = 2 resin layer may be "the = 2 = 1' with the resin composition as the r-th resin layer and The second resin "I can be used in addition to the type or amount of use of the tree, or (4)# Types or amounts of additives such as inorganic fillers: := The product is used as the first resin layer and the second resin layer. The required performance is cool. 呌斟 昆 ^ 丁 丁 丁 又 又 又 又 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 丁 昆 昆 昆 昆For example, 'the resin layer facing the inner layer circuit can be tested, to::, the text is made into a soft composition, the opposite side of the surface: to the buried into: the composition of the coarse magnetization, etc., in the insulation; function. w Unloading the difference The insulating layer used in the present invention is not particularly limited, but the circuit layer buried with the resin layer of the thickness of the second tree layer 319876 200843605 • 1 may be buried. For example, if the thickness of the buried circuit layer is Τ, the thickness of the first resin layer is (T/t) is preferably 0.3S(T/t)S1.5, more preferably 〇5$ /=) 2 • 1. In general, in order to sufficiently bury the circuit, it is preferable to thicken the thickness of the * grease layer facing the inner layer circuit. & The fibrous base material used in the present invention is preferably a glass fiber cloth among the above fibrous base materials, and the thickness of the glass fiber cloth can be, for example, 1 〇 or 10180/zm. Further, the basis weight (weight of the glass fiber cloth per lm2) can be, for example, 12 to 209 g/m2. In particular, it is preferable to use a glass fiber cloth having a thickness of 忉 to 35/zm and a basis weight of 12s25g/m2. In the present invention, in particular, a glass fiber cloth having a coefficient of linear expansion (CTE: c〇efficient〇f Thermal Expansion) of 6 ppm or less is more preferable, and a glass fiber cloth of 3 · 5 ppm or less is particularly preferable. By using the glass fiber cloth having the linear expansion coefficient as described above, it is possible to effectively suppress the multilayer circuit substrate composed of the insulating layer used in the present invention and the reverse warpage of the semiconductor package using the multilayer circuit substrate. Furthermore, the glass fiber cloth used in the present invention preferably has a sputum ratio of 62 to 100 GPa, preferably 65 to 92 GPa, more preferably 89 to 92 (} pa. When the glass fiber cloth is raised in the above-mentioned manner In the range, for example, deformation of the circuit board due to reflow heat during semiconductor mounting can be effectively suppressed, and connection reliability of the electronic component can be improved. Further, the glass fiber cloth used in the present invention is at 1 MHz. The dielectric constant is preferably 3.8 to 7.0, preferably 4.7 to 7.5, and more preferably 5.4 to 6.8. When the dielectric constant of the glass fiber cloth is in the above range, the dielectric layer can be reduced by 12 319876 200843605 : Ancient can be applied to semiconductor packages using high-speed signals. Fiber-optic cloth, two-line expansion coefficient, Yang 氐 rate and dielectric constant of the glass used in the invention, the thickness of the glass fiber cloth, to 10 Preferably, the ratio of 10 to 20 is to limit the number of pieces of the glass fiber to be used, and it is not to be recrystallized, and a plurality of thin glass fiber cloths may be overlapped for use. Meanwhile, the weight is determined by the number of turns. Yes. The degree of mouth /, to meet the above method will be used? The resin composition is impregnated into the fiber substrate by 'Asia..., Tron, and the product is prepared by dissolving the resin into a resin rent, and the main, first *, and + Wrap 2: The method of coating the varnish of the resin composition varnish. The method of applying the varnish of the resin composition to the fiber substrate by various coaters; the method of blowing by spraying ς with a supporting base A method of laminating the resin layer of the material, etc. Among these, a method of impregnating the fiber base material in the resin composition varnish is preferable, whereby the impregnation property of the high resin composition with respect to the fiber base material can be obtained. When the 'dimensional' substrate is immersed in the resin composition varnish towel, the material can be impregnated and coated. ϋ Especially when the thickness of the fiber substrate is less than 45 mm, from both sides of the fiber substrate. A method of laminating a film-like resin layer is preferable, whereby the impregnation amount of the resin composition to the fiber base material can be freely adjusted, and the formability of the insulating layer can be improved. X, by changing the resin from the two-area layer separately: Thickness, but free on the inner surface of the fiber substrate Further, when a film-like resin layer is laminated, it is preferably used in a laminate 319876 13 200843605 using a vacuum. Specifically, a method of producing an insulating layer containing a fiber substrate can be exemplified below. Fig. 12 shows a step of an example of the step of producing the resin layer 2. Here, after the carrier material a 5b is laminated on the fiber substrate by pre-manufacturing the carrier material 5a, %, the carrier film is peeled off. The method is specifically described. The pre-manufactured carrier material 5a' which is coated with the first resin composition on the carrier film and the second resin composition coated on another carrier: 5b. At this time, the thickness of the resin formed on the inner surface of the fiber substrate is freely changed by first changing the thickness of the first resin group of 4 degrees and the thickness of the bismuth composition. Next, using the vacuum laminating apparatus 6, the enamel layer roll 61 is joined by laminating the both sides of the fiber base material under reduced pressure. Thus, by using a non-filling portion even under the reduced pressure in the fiber substrate U or at the portion where the carrier material 5a, the fiber substrate η is joined, it can be used as a vacuum hole or a substantial straight line. At the railway π, there is a hollow from Beibei. Therefore, it is possible to reduce the void generated in the most direct layer of "曰2. This is due to the decompression cavity or hole: it is eliminated by heat treatment described later. As another means for causing the fibrous base material 11 to be entangled in such a reduced thickness, a vacuum box device or the like can be used, for example, a vacuum box device or the like can be used. After the base material 11 is joined to the carrier materials 5a and 5b, the air drying device 62' is heat-treated at a temperature of the melting temperature of the resin coated on the carrier material 。 舨 。. Subtraction in the joint step 319876 14 200843605 • The decompression cavity generated in the sudden can almost make the aunt, ^. Ancient soil ^ handcuffs ten Fan Wang was flattened. Heat treatment, his method 'for example It is carried out by using an infrared heating device, a plate-shaped hot plate, a glazing device, etc. ..., roller coating, flating, and laminating the carrier materials 5a, 5b on the fiber substrate u, the carrier film. After the material is removed, the material is peeled off, and an insulating layer containing the fiber substrate u is obtained. #持树月曰物物, the main substrate is impregnated in the resin domain material clearing material, and the resin composition paint is used. The solvent, although it is expected to be in the composition of the composition: Solubility, but in the A / can also use weak solvents. · Dry W solution, the Sweater's dry inside the sword does not have a good solution solvent, such as · · · _, methyl ethyl ,, methyl isobutyl hydrazine, cyclohexene, tetrahydrogen: monomethylformamide, dimethyl acetonitrile, dimethyl hard, ethylene glycol, cellosolve, card Alcohol (carbit〇1), etc. 彳 The resin composition of the above-mentioned resin composition is not particularly limited to 〇% by weight, particularly preferably 50 to 65% by weight, thereby further improving the resin composition. The impregnation property of the varnish to the fibrous base material is obtained by impregnating the above-mentioned resin composition with the above-mentioned resin composition and drying it at a predetermined temperature, for example, 80 to 20 (TC or the like). An example of a method of manufacturing a multilayer circuit substrate of the present invention is described using Figs. 3 to n of the embodiment, but is not necessarily limited to this embodiment. [Example 1] First, the prepreg 5 (Sumitomo Bakelite) (share) EI-6785Gs, thickness 319876 15 200843605, 0·2 mm) using two 250x250mm squares Peelable type, copper crucible with carrier copper foil (made by Furukawa Electric Co., Ltd.: 9//m copper foil, product name F-DP, very thin electrolytic copper foil with copper carrier, carrier copper foil 70 # • m) Hold the carrier copper foil 4 in the copper foil with the carrier copper foil in contact with the prepreg • 5, and pressurize (3 MPa) for heating for 1 hour to obtain support. Substrate (Fig. 3). After the surface of the supporting substrate is soft-etched, the dry film resist (made by Dong 10 Jingying Chemical Co., Ltd.: AR-320, film thickness 20/m) is supported. The both sides of the substrate are laminated by a roll, and a predetermined pattern is used to form a mask for exposure and development to form an anti-plating layer required for formation of a conductor circuit. Next, the supporting substrate is used as a wire for electrolytic plating, and an electroplated gold layer 7 of 0.1/m is formed by electrolytic plating of gold, and an electroplated nickel layer 8 of 3 //m is formed thereon by electrolytic plating of nickel. Further, an electroplated copper layer 9 of 14/m was formed by electrolytic plating of copper to obtain a conductor circuit layer 60. Next, the dry film resist is peeled off (Fig. 4). • Next, it was immersed on the surface of the conductor circuit layer 60 by a roughening liquid (Atotech Japan: Bond film) for 90 seconds. Next, the insulating layer a of the glass fiber cloth of the present invention (made by Sumitomo Bakelite): APL-3651 glass fiber cloth type glass non-woven fabric (made by Viene Vilene); EPC4015 glass fiber cloth thickness 12/ Zm) The thickness of the insulating layer is 40/zm, and the PET film is used as the supporting film. The film is cut into a square of 240×240 mm, and the both sides of the conductor circuit layer 60 are vacuum-pressed (MVLP-500-IL-made by the famous machine manufacturer). In the first time, the temperature was 80 ° C, the pressure was 0.5 MPa, the second time was 100 ° C, the pressure was 1.0 MPa, 16 319876 200843605, and it was formed. After heating at 150 ° C for 30 minutes, the PET film was peeled off. The insulating layer 10 is formed (Fig. 5).
接著，使用C02雷射加工機（日立Via機械（股）製：LG • 一2G212)以加工條件為第1步驟：脈衝寬度6/z sec、投射 • 數1發，第2步驟：脈衝寬度2 // sec、投射數1發來形成 引導孔（via hole)，為了洗淨、活化絕緣層10之表面，在 主成分為單乙基丁基醇之溶液（羅門哈斯（Rohm and Haas) ▲ 電子材料（股）製，MLB調節劑）中以液溫80°C浸潰5分鐘， 接著，在氧化性粗糙化液的過锰酸_作為主成分的溶液（羅 門哈斯電子材料（股）製，MLB促進劑）中以液溫80°C浸潰 10分鐘，接著為了洗淨猛殘渣，以硫酸溶液（羅門哈斯電 子材料（股）製，MLB中和劑）在液溫40°c浸潰5分鐘，再 進行水洗及溫水洗淨（第6圖）。 接著，使用無電解電鍍銅液（Atotech(股）製Print Gantt MSK-DK系列）在兩面形成厚度1.0/zm之無電解電 ⑩鍍銅層，以積層機將感光性乾膜（東京應化工業（股）製 AR-320)在無電解電鍍層上於兩面形成，並曝光、顯像， 而形成财電鐘抗韻劑（plating resist)，對财電鍍抗餘劑之非 形成部藉由電解電鍍銅而於兩面形成厚度14/zm之電解電 鍍銅層。 之後，剝離耐電鍍抗蝕劑，並將露出之無電解電鍍銅 層以軟性蝕刻液（荏原電產（股）製SAC)除去，將由無電解 電鍍銅層與電解電鍍銅層所構成之導體電路層12形成在 兩面上，用200°C熱處理60分鐘（第7圖）。 17 319876 200843605 • 重復上述步驟，將絕緣層10與導體電路層12積層單 % 面6層（弟8圖）。 其a ’剝開支持基材之載體銅箔4與銅箔3之間，可 •得到附轴^多層電路基板（第9圖）。 、 接著’在導體電路層12經剝開之面上張貼遮罩膠帶 (東包（版）‘.Elep masking N-380)，以使液不會渗 之方式將附有鋼H之多層電路基板浸潰在触刻液（氯化 亞鐵40。Be)中，^丄 _ ⑩ 卜 ； 除去銅箔3(第10圖）。此時，經蝕刻出 銅v白3 t包鑛金層7係具有作為抗餘刻劑之機能，不會溶 解導體電路。 然後剝離遮罩膠帶13,在出現電鍍金層7之部份上貼 附遮罩膠帶。 ▼之後’在導體電路層12之表面上藉由粗糙化 /夜（Atotech Japan(股）製：Bond film)浸潰處理9〇秒鐘，使 導體電路層12之表面被粗糙化，對多層電路基板沒被遮罩 之面以網版印刷機（難0 group(股）製，force2525 )印刷阻 制造（股）製，psr-4000 aus703)，以使導 春焊層14(太陽油';^用預定之遮罩進行曝光、顯像 '硬化， 體電路露出之方^ s〇lder Resist Layer)厚度以成為12 導體電路上之陴评0 //m之方式形成。焊層14露出之導體電路12上，形成由 其次，在從降 m與再於其上之無電解電鍍金層〇·；[ 無龟解電鐘鎳廣 产；[5，之後剝離遮罩膠帶，藉由銑刀 μ m所構成的電據0片之單面積層多層電路基板（4〇mm (r〇mer)加工機 γ 11圖 18 319876 X 40mm基板）（第 200843605 ^ 同時，第ίο圖之下面變成半導體晶片搭載部，上面 ， 變成BGA球搭載部。 [實施例2] • 將實施例1之絕緣層a改為使用絕緣層b(住友電木（股） • 製APL— 3601，厚度40//m，以PET作為支持薄膜），可 得到單面積層多層電路基板。製作方法基本上是與實施例 1相同地進行。 0 以下記述與實施例1相異處。 對支持基材貼附絕緣層b之條件是用真空加壓機（名 機製作所（股）製MVLP-500/600-IIA)以第1次：溫度80 °C、壓力〇.5MPa，第2次：溫度100°C、壓力l.OMPa之 條件下，在兩面形成絕緣層b ，剝開PET薄膜後，在170 °C加熱45分鐘製作絕緣層10。 ，其次，使用UV-YAG雷射加工機（三菱電機（股）製： ML605LDX)，以先端輸出94//J、射出數30發之加工條件 ⑩在絕緣層10形成引導孔。 用以將雷射開口後之絕緣層10的表面洗淨、活性化 之條件：在主成分為單乙基丁基醇之溶液（羅門哈斯（Rohm and Haas)電子材料（股）製，MLB調節劑）中以液溫80°C浸 潰10分鐘，接著，在氧化性粗糙化液的過錳酸鉀作為主成 分的溶液（羅門哈斯電子材料（股）製，MLB促進劑）中以液 溫80°C浸潰20分鐘，接著為了洗淨錳殘渣，以硫酸溶液（羅 門哈斯電子材料（股）製，MLB中和劑）在液溫40°C浸潰5 分鐘，再進行水洗及溫水洗淨。 19 319876 200843605 • 除了上述之外，其餘與實施例1同樣進行，而可得25 ， 片之單面積層多層電路基板（40mm X 40mm基板）。 [實施例3] 1. 樹脂組成物清漆之調整 ， 將作為熱硬化性樹脂之酴盤清漆型氰酸酯樹脂（LonzaNext, using the C02 laser processing machine (Hitachi Via Machinery Co., Ltd.: LG • 2G212), the processing conditions are the first step: pulse width 6/z sec, projection • number 1 round, second step: pulse width 2 // sec, the number of projections is 1 to form a via hole. In order to clean and activate the surface of the insulating layer 10, the main component is a solution of monoethyl butyl alcohol (Rohm and Haas ▲ In the electronic material (stock) system, the MLB regulator) was immersed at a liquid temperature of 80 ° C for 5 minutes, and then, in the oxidizing roughening liquid, permanganic acid _ as a main component solution (Rohm and Haas electronic materials (shares) , MLB accelerator) was immersed at a liquid temperature of 80 ° C for 10 minutes, followed by a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB Neutralizer) at a liquid temperature of 40 ° C for washing the residue. Dip for 5 minutes, then wash with water and wash with warm water (Fig. 6). Next, an electroless plating copper solution (Atotech Co., Ltd. Print Gantt MSK-DK series) was used to form an electroless 10 copper plating layer having a thickness of 1.0/zm on both sides, and a photosensitive dry film was laminated by a laminator (Tokyo Chemical Industry Co., Ltd.) (Stock) AR-320) is formed on both sides of the electroless plating layer, and exposed and developed to form a plating resist, which is electrolyzed by the non-formation part of the anti-residue agent. Electroplated copper was used to form an electrolytically plated copper layer having a thickness of 14/zm on both sides. Thereafter, the plating resist is peeled off, and the exposed electroless copper plating layer is removed by a soft etching liquid (SAC manufactured by Ebara Electric Co., Ltd.), and a conductor circuit composed of an electroless copper plating layer and an electrolytic plating copper layer is formed. Layer 12 was formed on both sides and heat treated at 200 ° C for 60 minutes (Fig. 7). 17 319876 200843605 • Repeat the above steps to laminate the insulating layer 10 and the conductor circuit layer 12 with a single layer of 6 layers (Fig. 8). This a' peels off between the carrier copper foil 4 of the support substrate and the copper foil 3, and a multilayer circuit board (Fig. 9) can be obtained. Then, 'make a mask tape (Dongban (Version)'. Elep masking N-380) on the peeled surface of the conductor circuit layer 12 so that the liquid H does not penetrate the multilayer circuit substrate with the steel H Dip in the etchant (ferric chloride 40. Be), ^ 丄 _ 10 卜; remove the copper foil 3 (Fig. 10). At this time, the copper v white 3 t gold ore layer 7 is etched to function as an anti-residual agent, and the conductor circuit is not dissolved. Then, the mask tape 13 is peeled off, and a mask tape is attached to the portion where the gold plating layer 7 appears. After that, 'the surface of the conductor circuit layer 12 is immersed by roughening/night (Atotech Japan: Bond film) for 9 sec seconds, and the surface of the conductor circuit layer 12 is roughened to the multilayer circuit. The substrate is not covered by a screen printing machine (difficult to 0 group (share), force2525) printing resistance manufacturing (stock) system, psr-4000 aus703), so that the spring solder layer 14 (solar oil '; The exposure is performed with a predetermined mask, and the image is 'hardened, and the thickness of the body circuit is formed. The thickness is formed to be 0/m on the 12-conductor circuit. The solder layer 14 is exposed on the conductor circuit 12, and the gold layer is formed by the electroless plating of the lowering m and then on it; [no cracking electric clock nickel production; [5, after peeling the mask tape A single-area multilayer circuit board composed of a milling cutter μ m (4 mm (r〇mer) machine γ 11 Fig. 18 319876 X 40 mm substrate) (No. 200843605 ^ Meanwhile, at the same time, The lower surface becomes a semiconductor wafer mounting portion, and the upper surface thereof becomes a BGA ball mounting portion. [Embodiment 2] • The insulating layer a of the first embodiment is replaced with an insulating layer b (Sumitomo Bakelite) APL-3601, thickness 40//m, using PET as a supporting film), a single-layer multilayer circuit board can be obtained. The manufacturing method is basically the same as in the first embodiment. 0 The following description differs from the first embodiment. The condition of the insulating layer b is the first time using a vacuum press machine (MVLP-500/600-IIA manufactured by Nihon Seisakusho Co., Ltd.): temperature 80 °C, pressure 〇5 MPa, second time: temperature 100 ° C. Under the condition of pressure l.OMPa, the insulating layer b is formed on both sides, and after peeling off the PET film, it is heated at 170 ° C for 45 minutes. The insulating layer 10 was produced. Next, a UV-YAG laser processing machine (Mitsubishi Electric Co., Ltd.: ML605LDX) was used to form a guide hole in the insulating layer 10 with a processing condition 10 of a front end output of 94//J and an emission number of 30. The condition for washing and activating the surface of the insulating layer 10 after the laser opening is: a solution in which the main component is monoethyl butyl alcohol (Rohm and Haas electronic material (stock), MLB conditioner) was immersed at a liquid temperature of 80 ° C for 10 minutes, and then, in a solution of potassium permanganate having a oxidizing roughening solution as a main component (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB accelerator) Immersed at a liquid temperature of 80 ° C for 20 minutes, and then washed with a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB Neutralizer) at a liquid temperature of 40 ° C for 5 minutes, and then carried out. Washing with water and warm water. 19 319876 200843605 • Except for the above, the same procedure as in Example 1 was carried out, and a single-layer multilayer circuit board (40 mm X 40 mm substrate) of 25 sheets was obtained. [Example 3] 1 Adjustment of resin composition varnish, which will serve as a thermosetting resin Varnish type cyanate resin (Lonza
Japan(股）製，Prime set PT_30，重量平均分子量約2,600)15 重量份、作為環氧樹脂之聯苯二亞曱基型環氧樹脂（曰本化 _ 藥（股）製，NC- 3000Ρ，環氧當量275)8重量份、作為酚樹 脂之聯苯二亞曱基型酚樹脂（明和化成（股）製， MEH-7851-S，羥基當量203)7重量份及作為偶合劑之環氧 矽烷型偶合劑（曰本UNIKA(股）製，Α-187)，於常溫下溶解 至相對於後述之無機充填材1〇〇重量份為0.3重量份之曱 基乙基酮中，並添加作為無機充填材之球狀熔融二氧化矽 SFP-10X(電氣化學工業（股）製，平均粒徑0.3//m)20重量 份及球狀熔融二氧化石夕SO-32R(Admatechs(股）製，平均粒 ⑩徑1.5/zm)50重量份，用高速攪拌機攪拌10分鐘，調製樹 脂組成物清漆。 2. 載體材料之製造 載體薄膜是使用聚對苯二曱酸乙二酯（三菱化學聚酯 公司製，SFB-38，厚度38// m、寬480 // m)，將上述樹脂 組成物清漆用逗點塗布機裝置（comma Coater)塗布，在170 °(：之乾燥裝置乾燥3分鐘，形成厚度20//m、寬410/zm 之樹脂層並使其位於載體薄膜之寬度方向的中心，而得載 體材料1(最終形成第1樹脂層）。 20 319876 200843605 7 ^以同樣之方法調整塗布之樹脂組成物清漆之量， 形成厚度8vm、寬360//111之樹脂層並使其位於載體薄膜 之寬度方向的中心，而得載體材料2(最終形成第2樹脂 • 層）。 4 3 ·絕緣層a之製造 纖維基材是使用E玻璃織布（交聯型#1〇15、寬36〇 =:、厚度Wm、基重17g/m2)’如第12圖所示藉由真 ⑩工積層裝覃及熱風乾燥裝置而製造預浸體。 具體而言’在玻璃織布之兩面上，將前述载體材料i 舁載體材肖2以㈣玻璃織布之寬度方向之中心的方式八 =重疊’並*75〇Τ〇ΓΓ之減壓條件下使用啊積層㈣^ 合0 在此，在玻璃織布之寬度方向尺寸的内側領域中，將 $體材料1與㈣材料2.之樹脂層在纖維布之兩側各別接 合，同時’在玻璃織布之寬度方向尺寸的外側領域中，將 载體材料1與載體材料2之樹脂層互相接合。 、、，其次，將上述經接合者，藉由在設定成12〇它之橫搬 迗型之熱風乾燥裝置内通過2分鐘，而於沒有加壓作用下 進行加熱處理，得到厚度為35#m(第i樹脂層：^以瓜， 纖維基材：15#m，第2樹脂層：4/zm)之絕緣層d。 將實施例1之絕緣層a改用絕緣層d，可得25片之單 面積層多層電路基板（40mm x40mm基板）。製作方法是除 了使第1樹脂層配置成面對導體電路層6之外，基本上是 與實施例1同樣地進行。 319876 21 200843605 -[比較例1 ] 、 比較例係將實施例1之絕緣層a改用絕緣層C (味之素 (股）製ABF-GX13,厚度40/zm、PET薄膜作為支持薄膜）， . 可得單面積層多層電路基板。製作方法，基本上是與實施 • 例1同樣地進行。 以下記述與實施例1不同之處。 對支持基材貼附絕緣層c之條件是用真空加壓機（名 _ 機製作所（股）製MVLP-500/600- ΠΑ)以第1次：溫度105 °C、壓力〇.6MPa，第2次：溫度105°C、壓力0.5MPa之 條件下，在兩面形成絕緣層c ，剝開PET薄膜後，在180 °C加熱30分鐘製作絕緣層10。 其次，使用UV-YAG雷射加工機（三菱電機（般)製： ML605LDX)，以先端輸出70 // J、射出數30發之加工條件 在絕緣層10形成引導孔。 用以將雷射開口後之絕緣層10表面洗淨、活性化之 ⑩條件是：在主成分為單乙基丁基醇之溶液（羅門哈斯電子材 料（股）製，MLB調節劑）中以液溫80°C浸潰5分鐘，接著， 在氧化性粗糙化液的過錳酸鉀作為主成分的溶液（羅門哈 斯電子材料（股）製，MLB促進劑）中以液溫80°C浸潰20分 鐘，接著為了洗淨錳殘渣，以硫酸溶液（羅門哈斯電子材料 (股）製，MLB中和劑）在液溫40°C浸潰5分鐘，再進行水 洗及溫水洗淨。 除了上述之外，其餘與實施例1同樣地進行，可得25 片之單面積層多層電路基板（40mm X 40mm基板）。 22 319876 200843605 以下表示評估項目與評估方法。 評估方法是如下所述。 [玻璃移轉溫度及彈性模數] 1吏用$ C積層機’積層2片絕緣層，將在2〇〇。〇硬化 J牷後所％之物切成試驗片（寬5mmx長度刈mmx厚度 80 μ m)。 在測定中，使用動態黏彈性測定襞置（精工儀器公司Japan (stock) system, Prime set PT_30, weight average molecular weight of about 2,600) 15 parts by weight, biphenyl dithylene-based epoxy resin as epoxy resin (曰本化_药(股), NC-3000Ρ, Epoxy equivalent of 275) 8 parts by weight, benzoic fluorene-based phenol resin as phenol resin (manufactured by Megumi Chemical Co., Ltd., MEH-7851-S, hydroxyl equivalent 203), 7 parts by weight, and epoxy as a coupling agent a decane-type coupling agent (manufactured by UNIKA Co., Ltd., Α-187), which is dissolved at room temperature to 0.3 parts by weight based on 1 part by weight of the inorganic filler described later, and added as a decyl ethyl ketone. Spherical molten cerium oxide SFP-10X (manufactured by Electrochemical Industry Co., Ltd., average particle diameter 0.3//m) 20 parts by weight and spherical molten sulphur dioxide Xi-SO-32R (Admatechs) 50 parts by weight of an average particle diameter of 10/zm), and the mixture was stirred for 10 minutes with a high speed mixer to prepare a resin composition varnish. 2. Preparation of carrier material The carrier film was varnished with polyethylene terephthalate (manufactured by Mitsubishi Chemical Polyester Co., Ltd., SFB-38, thickness 38//m, width 480 // m). Coating with a comma coater (comma Coater), drying at 170 ° (: drying device for 3 minutes, forming a resin layer having a thickness of 20 / / m and a width of 410 / zm and placing it in the center of the width direction of the carrier film, The carrier material 1 was obtained (final formation of the first resin layer). 20 319876 200843605 7 ^ The amount of the coated resin composition varnish was adjusted in the same manner to form a resin layer having a thickness of 8 vm and a width of 360//111 and placed in the carrier. The center of the film in the width direction is obtained as the carrier material 2 (finally forming the second resin layer). 4 3 · The insulating layer a is made of E glass woven fabric (crosslinked type #1〇15, width 36) 〇=:, thickness Wm, basis weight 17g/m2)' As shown in Fig. 12, a prepreg is manufactured by a true 10 layer laminate and a hot air drying device. Specifically, 'on both sides of the glass woven fabric, The carrier material i 舁 carrier material xiao 2 is at the center of the width direction of the (four) glass woven fabric Formula VIII = overlap 'and * 75 〇Τ〇ΓΓ under reduced pressure conditions use layer (4) ^ 0 Here, in the inner side of the width direction of the glass woven fabric, $ body material 1 and (4) material 2. The resin layer is bonded to each other on both sides of the fiber cloth, and the resin layer of the carrier material 1 and the carrier material 2 are joined to each other in the outer region of the width direction of the glass woven fabric. Secondly, the above The jointer was subjected to heat treatment without pressure under a hot air drying device set to 12 〇, and was subjected to heat treatment to obtain a thickness of 35 #m (i-th resin layer: ^ The insulating layer d of the melon, the fiber substrate: 15#m, the second resin layer: 4/zm). The insulating layer a of the embodiment 1 is changed to the insulating layer d, and 25 single-layer multilayer circuit boards can be obtained. (40 mm x 40 mm substrate). The production method was basically the same as in Example 1 except that the first resin layer was placed so as to face the conductor circuit layer 6. 319876 21 200843605 - [Comparative Example 1], Comparative Example The insulating layer a of the first embodiment was changed to the insulating layer C (ABF-GX13 made of Ajinomoto (feel), thickness 4 0/zm, PET film as a support film), a single-layer multilayer circuit board can be obtained. The production method is basically the same as in the first embodiment. The difference from the first embodiment is described below. The condition for attaching the insulating layer c is the first time using a vacuum press machine (MVLP-500/600-ΠΑ made by _Machine Co., Ltd.): temperature 105 °C, pressure 〇.6 MPa, second time: temperature Under the conditions of 105 ° C and a pressure of 0.5 MPa, an insulating layer c was formed on both surfaces, and the PET film was peeled off, and then heated at 180 ° C for 30 minutes to form an insulating layer 10. Next, a UV-YAG laser processing machine (Mitsubishi Electric Co., Ltd.: ML605LDX) was used to form a guide hole in the insulating layer 10 under the processing conditions of a front end output of 70 // J and an emission number of 30. The condition for washing and activating the surface of the insulating layer 10 after the laser opening is as follows: in a solution in which the main component is monoethyl butyl alcohol (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB regulator) The solution was immersed at a liquid temperature of 80 ° C for 5 minutes, and then at a liquid temperature of 80 ° in a solution of oxidizing roughening solution of potassium permanganate as a main component (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB accelerator). C was immersed for 20 minutes, and then, in order to wash the manganese residue, it was immersed in a sulfuric acid solution (manufactured by Rohm and Haas Electronic Materials Co., Ltd., MLB neutralizer) at a liquid temperature of 40 ° C for 5 minutes, and then washed with water and warm water. net. Except for the above, the same procedure as in Example 1 was carried out, and 25 single-layer multilayer circuit boards (40 mm X 40 mm substrates) were obtained. 22 319876 200843605 The evaluation project and assessment method are indicated below. The evaluation method is as follows. [Glass transfer temperature and modulus of elasticity] 1 吏Use the $C laminator to build two layers of insulation, which will be 2 〇〇. After the hardening, the % of the material was cut into test pieces (width 5 mm x length 刈 mm x thickness 80 μ m). In the measurement, dynamic viscoelasticity measurement is used (Seiko Instruments)
來判定玻璃移轉溫度（Tg)，又藉由測定求得25。〇、25〇t 之彈性模數。 昇溫，——邊給予 ’從tan (5之峰值 [線膨脹係數] 使用常壓積層機，積層2片絕緣層，在2〇〇。〇硬化2 小時後獲得樹脂硬化物。自所得之樹脂硬化物採取4mmx 20mm之評估用試料，使用TMA裝置（ΤΑ儀器公司製），以 _ 10 C/分鐘昇溫後測定。α 1是玻璃移轉溫度以下之線膨 脹係數，α 2是玻璃移轉溫度以上之線膨脹係數。 [抗拉彈性模數] 使用常壓積層機，積層2片絕緣層，在200°C硬化2 小時後獲得樹脂硬化物。將所得之樹脂硬化物以抗拉模式 (tensile mode)在負重滿刻度20 kgf、速度5mm/min條件 下進行測定。 [隨溫度變化之基板反翹量] 所得之多層電路基板之反翹量係使用溫度可變雷射 23 319876 200843605 - 三次元測定機（曰立Technologies and Services公司製，型 、 式LS220-MT100 MT50)測定在高度方向之變位，變位差之 最大值當作反翹量。測定溫度是在一 55t：、25t：、150T：、 ,260°C等4點進行。在全部測定溫度中之反翹量在200 μ m * 以下者為◎、400 // m以下者為〇、600 /z m以下者為△， 800 // m以下者為X。 絕緣層之物性值及此等之評估結果係在表1表示。 [表1] 實施例1 實施例2 實施例3 比較例1 絕緣層 a b d c 玻璃移轉溫度 CC) 200 180 200 165 抗拉彈性模數 25t：(GPa) 12 13 12 5 250°C(GPa) 6.2 0.8 6.8 0 線膨脹係數 a l(ppm) 29 28 29 29 a 2 (ppm) 72 73 71 63 基板反翹量 溫度變化時 之反麵 ◎ 〇 ◎ Δ 由評估之結果可知，實施例1、2及3之溫度變化時 之反翹變動小，但比較例1推測是因絕緣層之彈性模數 低，又絕緣層與導體電路層之線膨脹係數差大，故溫度變 化時之反_變動也大。 (產業上之可利用性) 依本發明，因絕緣層與導體電路層之線澎脹係數差為 少，所以層間產生之内部應力變小，多層電路基板之反翹 變小。又，使用前述多層電路基板之半導體裝置係在半導 24 319876 200843605 w 11骏/驟、仏賴性試驗中，變成反翹少之半導體裴 m:具有在產業上之可利用性。 【圖式簡單說明】 》5 2::表:以往之代表性的增建多層電路基板圖。 ^圖。θ係表示本發明相關的多層電路基板之概略結構 美材f ?仏表不用以說明本發明之多層電路基板的支持 基材之一個例子的截面圖。 文得 持表不用以說明本發明之多層電路基板的在支 持㈣t成導體電路層之一個例子的截面圖。 持基:上說明本發明之多層電路基板的在支 緣層上藉St; 明本發明之多層電路基板的在絕 :田射而形成開口部之一個例子之截面圖。 緣層的二:以說:本發明之多層電路基板的在絕 圖。^於兩面形成導體電路層之—個例子的截面 二8 !:ΐ:用以說明本發明之多層電路基板的在單 第肢電路層與絕緣層之-個例子的截面圖。 持基材的以說明本發明之多層電路基板的將支 路結, 與銅落剝離’並形成附有銅落之多声電 路基板之-個例子的截面圖。 夕層免 電路ί體1本發明之多層電路基板的在 曰上貼附遮罩膠帶之一個例子的截面圖。 319876 25 200843605 第π圖係表示用以說明本發明之多層電路基板的形 成有阻焊層（S〇ider Resist)及鏡覆層之多層電路基板之一 個例子的截面圖。 土 ㈤第12圖係表示製造本發明絕緣層之裝置的概略結構 【主要元件符號說明】 核層 1 la lb 1 c 2 4 5 _ 5a、5b 6 7 9 10 11 12 13 增建層 絕緣層 内塾 外墊（BGA墊) 樹月旨層 附有載體銅落之銅箔中的銅箔 附有载體㈣之銅n中的载體銅箱 預浸體 栽體材料 真空積層裝置 電鍍金層 電鑛鎳層 銅層 絕緣層 纖維基材 導體電路層 遮罩膠帶 319876 26 200843605 14 阻焊層 15 電鍍層 20 阻焊層 60 導體電路層 61 積層輥 62 熱風乾燥裝置 110 增建基板The glass transition temperature (Tg) was determined and 25 was determined by measurement.弹性, 25〇t elastic modulus. Heating, - while giving 'from tan (5 peak [linear expansion coefficient] using an atmospheric laminator, laminating 2 layers of insulation, at 2 〇〇. After hardening for 2 hours, the resin is cured. The resulting resin is hardened. A 4 mm x 20 mm evaluation sample was taken and measured by a TMA apparatus (manufactured by Nippon Instruments Co., Ltd.) at a temperature of _ 10 C/min. α 1 is a linear expansion coefficient below the glass transition temperature, and α 2 is a glass transition temperature or higher. Linear expansion coefficient. [Tensile elastic modulus] Using an atmospheric laminator, two layers of insulating layers were laminated, and a cured resin was obtained after hardening at 200 ° C for 2 hours. The obtained cured resin was in a tensile mode. The measurement is carried out under the condition of a load weight of full scale of 20 kgf and a speed of 5 mm/min. [Substrate anti-warpage amount with temperature change] The obtained anti-warpage amount of the multilayer circuit substrate is a temperature-variable laser using 23 319876 200843605 - three-dimensional measurement The machine (type LS220-MT100 MT50, manufactured by the company of Technology and Services) measures the displacement in the height direction, and the maximum value of the displacement difference is taken as the amount of anti-warpage. The measured temperature is at 55t:, 25t:, 150T. :, ,260 °C is performed at 4 o'clock. The amount of anti-warpage in all measurement temperatures is 200 μ m * or less, ◎, 400 // m or less, 600, 600 /zm or less, △, 800 // m or less. X. The physical property values of the insulating layer and the evaluation results of these are shown in Table 1. [Table 1] Example 1 Example 2 Example 3 Comparative Example 1 Insulation layer abdc Glass transfer temperature CC) 200 180 200 165 Tensile Elastic modulus 25t: (GPa) 12 13 12 5 250 ° C (GPa) 6.2 0.8 6.8 0 Linear expansion coefficient a (ppm) 29 28 29 29 a 2 (ppm) 72 73 71 63 When the substrate anti-warpage temperature changes Negative surface ◎ 〇 ◎ Δ As a result of the evaluation, it is understood that the change in the warpage of the temperatures of Examples 1, 2, and 3 is small, but Comparative Example 1 is presumed to be because the elastic modulus of the insulating layer is low, and the insulating layer and the conductor circuit are Since the difference in linear expansion coefficient of the layer is large, the inverse _ variation at the time of temperature change is also large. (Industrial Applicability) According to the present invention, since the difference in the coefficient of linear expansion between the insulating layer and the conductor circuit layer is small, the internal stress generated between the layers is small, and the back warpage of the multilayer circuit substrate is small. Further, the semiconductor device using the above-mentioned multilayer circuit substrate is a semi-conductive semiconductor 裴 m which has an industrially usable property in the semi-conducting test. [Simple description of the diagram] 》5 2:: Table: A representative representative of the multilayer circuit board. ^ Figure. θ is a schematic view showing a schematic configuration of a multilayer circuit substrate according to the present invention. The material is not used to explain a cross-sectional view of an example of a supporting substrate of the multilayer circuit substrate of the present invention. The cross-sectional view of an example of supporting a (four)-t conductor circuit layer of the multilayer circuit substrate of the present invention is not required. Base: The multilayer circuit board of the present invention is described as a cross-sectional view of an example of forming an opening portion of the multilayer circuit board of the present invention. The second layer of the edge layer is said to be the absolute image of the multilayer circuit substrate of the present invention. ^ Cross section of an example of forming a conductor circuit layer on both sides. Fig. 8 is a cross-sectional view showing an example of a single-limb circuit layer and an insulating layer of the multilayer circuit substrate of the present invention. A cross-sectional view of an example of a substrate in which a multilayer circuit substrate of the present invention is bonded to a copper drop and a multi-sound circuit board with a copper drop is formed. The circuit layer of the multilayer circuit board of the present invention is a cross-sectional view of an example in which a mask tape is attached to the enamel. 319876 25 200843605 Fig. π is a cross-sectional view showing an example of a multilayer circuit substrate on which a solder resist layer and a mirror layer are formed to explain the multilayer circuit substrate of the present invention. Fig. 12 is a schematic view showing the structure of the apparatus for manufacturing the insulating layer of the present invention. [Main element symbol description] Core layer 1 la lb 1 c 2 4 5 _ 5a, 5b 6 7 9 10 11 12 13 In the insulating layer of the build-up layer塾外垫(BGA垫) The tree layer of the moon is attached with a copper foil in the copper foil of the carrier. The carrier of the carrier (4) is used in the copper n. The carrier copper box prepreg carrier material vacuum lamination device electroplating gold layer electricity Mineral nickel layer copper layer insulation layer fiber base material conductor circuit layer mask tape 319876 26 200843605 14 solder resist layer 15 plating layer 20 solder resist layer 60 conductor circuit layer 61 laminating roll 62 hot air drying device 110 additional substrate