TW200841423A - Method for manufacturing collars of deep trench capacitors - Google Patents
Method for manufacturing collars of deep trench capacitors Download PDFInfo
- Publication number
- TW200841423A TW200841423A TW096113241A TW96113241A TW200841423A TW 200841423 A TW200841423 A TW 200841423A TW 096113241 A TW096113241 A TW 096113241A TW 96113241 A TW96113241 A TW 96113241A TW 200841423 A TW200841423 A TW 200841423A
- Authority
- TW
- Taiwan
- Prior art keywords
- deep trench
- hard mask
- capacitor
- manufacturing
- neck
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000003990 capacitor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 238000001039 wet etching Methods 0.000 claims abstract description 3
- 238000005530 etching Methods 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 2
- 239000004020 conductor Substances 0.000 claims description 2
- 239000002023 wood Substances 0.000 claims 2
- 238000002513 implantation Methods 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 claims 1
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 235000013405 beer Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003248 secreting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
- H10B12/0387—Making the trench
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Description
200841423 九、發明說明： 【發明所屬之技術領域】 部之方法 本發明係關於-種深溝渠電容頸部之製作方法，特別 是關於「種使㈣擇性祕取實質上保護深溝渠電容頸 【先前技術】 於動態隨機存取記憶體中，習知使用兩種不同形式的 2 ’其中—種稱為深溝渠電容。於形成深溝渠電容的步 驟中，會使用氟碳化物的钕刻劑挖出頸部，同時也”積一 ，勿來保護溝渠頂部的頸部。通常餘刻後的聚::合 ==㈣内，於是在頸部形成之後另需要增祕刻時間 ::除頸部殘餘物，但是這種作法卻會傷㈣ 來解決以 於是需要一種製作深溝渠電容頸部之方 上的問題。 【發明内容】 本發明提供-種深溝渠電容頸部之 遮覃;s西？人楚Aw a 乍方法。利用硬 渠電容頸部不受 曰a專向性蝕刻能實質上保護深溝 過蝕刻的傷害。本發明方法，包含·· 沬溝渠内具有位於底部 提供一基材，其具有深溝渠， 6 200841423 之溝渠電容； 形成内壁層以完全覆蓋深溝渠與基材； 於内壁層表面形成硬遮罩層； 對硬遮罩層進行一選擇性斜角離子佈植製程，使得位 於深溝渠壁上之硬遮罩層未受離子佈植； 進行選擇性濕触刻製程，以移除未受離子佈植之該硬 遮罩層；以及 進行非等向性乾蝕刻製程，以實質上去除位於深溝渠 底部之内壁層而暴露出部分之溝渠電容，並實質上保留深 溝渠電容頸部。 【實施方式】 本發明製作深溝渠電容頸部之方法，因為利用選擇性 蝕刻的特殊效果，能實質上保護深溝渠電容頸部不受過蝕 刻（over etch)的傷害。第la至第le圖繪示本發明製作深溝 渠電容頸部方法的一較佳實施例。首先，請參考第la圖， 首先提供基材100。基材100通常包含一半導體材料，例 如矽，其上依照習知方式已預先建立有墊氧化層110、氮 化矽層120與深溝渠130。深溝渠130内具有位於底部之 溝渠電容140，溝渠電容140中通常包含一導電材料，例 如多晶石夕。 然後例如使用化學氣相沉積法，形成一層完全覆蓋深 7 200841423 基材1〇。之内壁層15°。内壁層15。通常包含 材料’例如砍氧化物’其厚度大約為25。A。 請參考第lb圖，於内壁層15 硬遮罩層“ο通常包含多晶梦，較=硬遮罩層· 積法使其厚度大約為14GA。 ^使用化學氣相沉 居^後請參考第le圖’對位於内壁層15 層160進行—選擇性離 二 硬涉^ π值衣秩，以形成有摻質的 遮罩層161，但是位於深溝渠13() 則未受離子佈I若佈:之硬遮罩層160 之入射角為α〜1Q度。使用啤作為摻質時，較佳 罩2於受祕子佈植⑹與未受過離子佈植16G的硬遮 “於特殊蝕刻條件具有明顯的差異，於是如第ld圖所 碗罢進行—選擇性濕_製程，以移除未受離子佈植之硬 “、、層160。可以使用如濃度比例約為1/300的丽40ή/ 2〇飾刻劑以約15分鐘的時間來進行此選擇性濕蝕刻製 ^ ’較佳能完全移除未受過離子佈植的硬遮罩層16〇，但 實貝保留受過離子佈植的硬遮罩層161，例如硬遮罩層161 的厚度剩下大約105人，以作為下一步蝕刻時的硬遮罩。 然後如第le圖所示，使用硬遮罩層161作為硬遮罩， 8 200841423 進行-非等向性乾㈣製程，以實質上去除位於深溝渠底 部之内壁層150而暴露出部分之溝渠電容17〇。可以使用 姓刻性氣體如C4F6/0条進行此料向性㈣製程。由於 此餘刻製程係料向性，除了位於深溝渠底部之内壁層會 被钱刻而暴露出部分之溝渠電容170夕卜硬遮罩層161也 會被㈣:較佳還實質上完全移除硬遮罩層161，如此即 可省略後續移除硬遮罩層161的額外步驟。由於餘刻的緣 故，通常會在深溝渠13〇的開口附近留下肩形18〇。 由於硬遮罩層161的保護’於是能實質上保留深溝渠 電谷頸部免於蝕刻的傷害。當完成非等向性乾蝕刻製程 後，便可依照習知方式繼續完成深溝渠電容的製作。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾’統屬本發明之_蓋範圍。 【圖式簡單說明】 渠電容頸部方法的 第la至弟le圖緣示本發明製作深溝 一較佳實施例。 110墊氧化層 130深溝渠 【主要元件符號說明】 100基材 120氮化矽層 200841423 140、170溝渠電容 • 160、161硬遮罩層 150内壁層 180肩形
10
Claims (1)
- 200841423 十、申請專利範圍： 1. -種深溝渠電容頸部之製作方法，包含· 提供-基材，其具有—深溝渠，該深溝 一溝渠電容；木内具有位於底部之 對該硬遮罩錢行—獅性深溝渠壁上之該硬遮罩層未受離子佈植于佈植製程，使得位於該 進行-選擇性濕_製程， 層；以及 示未文離子佈植之該硬遮罩 進行-非等向性乾蝕刻製一 部之該内壁層而暴露出部分之 :貝上去除位於該深溝渠底 電容頸部。 /木電各，並實質上保留該深溝渠 2·如請求項1之深溝渠 導體基材。 電容頸部之製 作方法，其中該基材為一半 3.如請求項1之深溝渠電容 含多晶矽。 頊部之製作方法， 其中該溝渠電容包 項1之深溝渠電容轉之製作方法，其中該内壁層包含 200841423 5·如請求項1之縣m電轉部 含多晶石夕。 i乍方法，其中該硬遮罩層包 該選擇性斜角離子佈植製程。4方法’其中 BF2+進行 7.如請求項1之深溝渠電容頸 其中使用濃度比例 劑進行該選擇性濕蝕刻製程。 約為1/300的 離子佈植製程之人㈣大纟UQ〜法，其巾親擇性斜角 =請求们之麵f_㈣作方法， NH4〇H/H2〇 蝕刻 9.如請求項1之深溝渠電容 刻製程。 體如進行該非料H作方法，其纽祕刻性氣 性絲該非等向 12
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW096113241A TW200841423A (en) | 2007-04-14 | 2007-04-14 | Method for manufacturing collars of deep trench capacitors |
| US11/829,067 US20080254589A1 (en) | 2007-04-14 | 2007-07-26 | Method for manufacturing collars of deep trench capacitors |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW096113241A TW200841423A (en) | 2007-04-14 | 2007-04-14 | Method for manufacturing collars of deep trench capacitors |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| TW200841423A true TW200841423A (en) | 2008-10-16 |
Family
ID=39854091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW096113241A TW200841423A (en) | 2007-04-14 | 2007-04-14 | Method for manufacturing collars of deep trench capacitors |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20080254589A1 (zh) |
| TW (1) | TW200841423A (zh) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9881840B2 (en) * | 2011-06-09 | 2018-01-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of fabricating gate electrode using a treated hard mask |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6498061B2 (en) * | 2000-12-06 | 2002-12-24 | International Business Machines Corporation | Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation |
| TWI223385B (en) * | 2003-09-04 | 2004-11-01 | Nanya Technology Corp | Trench device structure with single side buried strap and method for fabricating the same |
| US6960503B2 (en) * | 2003-11-16 | 2005-11-01 | Nanya Technology Corp. | Method for fabricating a trench capacitor |
-
2007
- 2007-04-14 TW TW096113241A patent/TW200841423A/zh unknown
- 2007-07-26 US US11/829,067 patent/US20080254589A1/en not_active Abandoned
Also Published As
| Publication number | Publication date |
|---|---|
| US20080254589A1 (en) | 2008-10-16 |
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