200841022 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種對多級治具之等效電路補償之架構及其 方法，尤指一種架構可適用於複雜組合之治具，能量測具有不 同電氣特性及物理特性之待測物，並同時儲存多組不同待測物 之補償參數以供重覆使用。200841022 IX. INSTRUCTIONS: [Technical field of invention] The present invention relates to an architecture and method for equivalent circuit compensation of multi-stage jigs, and more particularly to a jig for a complex combination of structures, energy measurement The test object has different electrical characteristics and physical properties, and simultaneously stores compensation parameters of multiple sets of different test objects for repeated use.
【先前技術】 隨著近幾年電子相關產業不斷蓬勃發展，尤其以3c等消 費性產品成為熱Η消費主流，然而要組成這些產品需要大量電 子兀件’為確保產品品質就需要檢測其電子元件規袼是否標符 合標準，❺了檢測電容、電感及電阻等基本被動元件外，也量 測由這些元件組合或複合而成、或具有相近特性之各式電子零 組件，前者包含各式繞線元件、通訊及電源渡波器等，後者則 1開關、連接器、導線、金屬材料、介電材料、磁性材料及 半導體元件等。早期因治具本身的雜散電容、殘餘電阻、開關 之接點電阻、線與線相互干擾、外部雜訊及量測頻率不斷提昇 戶^致里㈣置之精_度產生很大的影響，其精確度之定義為 量測精確度加上治具之誤差，為確保量測裝置之精確度在規袼 内而而對里測裝置進行校正動作’並對治具進行補償動作以消 除該量测裝置與治具兩相之誤差。基於上述原因目前已發展 出各種補仏方法，包括第—種為偏移補償（offset eompensation ) 200841022 方法是利用治具之量測端開路時形成雜散電容並影響量測 值，此時只需將量測值減去雜散電容值就可得到補償後之量測 值，但此補償方法僅用於夾具類治具。 第二種為開路/短路補償（open/short compensation)方法 假設治具之雜散電容及殘餘電阻為一等效電路，當等效電路開 路時，由於量測端阻抗無限大而殘餘電阻相對變小，所以可測 得雜散電容。當等效電路短路時，由於量測端阻抗無限1、而雜 散電容相對變大，所以可測得殘餘電阻，此補償方法僅適用於 等效電路，屬於惟一對稱之簡單電路。 第三種為開路/短路/負載補償（open/short/load compensation)方法，由於上述第二種開路/短路補償無法補償 過於複雜或不對稱之等效電路，因此需要使用該第三種開路/ 短路/負載之補償方法，需分別進行開路、短路補償後在電性連 接一標準待測物利用測得之參數進行負載補償。 已知的先前技術僅能對一般治具進行單一組待測物之補 償，但如需要使用掃描治具、可擴充之治具或較複雜之其他治 具組合等時，因治具之路徑過於複雜，易造成複雜之等效電 路，所以將無法有效得到補償，且其記憶體容量有限，將無法 記錄多筆參數，故以先前技術為主之治具無法充分利用參數計 算補償值或重覆使用，使其在準確性及效率大為減低。 200841022 【發明内容】 為解決上述習知技術之問題，本發明之一主要目的係提供 一種對多級治具之等效電路補償之架構，可與掃描治具、可擴 充之治具或較複雜之各種治具組合，並量測標準待測物及待測 物之值以取得所需各補償參數，且經由運算後所得一補償值， 使該治具中每一量測路徑所形成之等效電路及雜散干擾皆得 以補償。 • 本發明之一次要目的係提供一種對多級治具之等效電路補 償之方法，其中各掃描治具、可擴充之治具或較複雜之治具組 合，依據不同待測物之電氣特性或物理特性的需要，同時進行 多組不同電氣特性或物理特性的補償，而無需如習知技術僅能 進行單一組待測物之量測，因此可提升量測時之效率及降低工 時。 本發明之另一目的係提供一種對多級治具之等效電路補償 ⑩ 之架構，用於儲存多組不同待測物之量測值或補償參數，並可 多次重覆使用或使用於不同的待測物但具有同一物理特性，且 因其記憶空間也較先前技術有擴充性，故可儲存較多資料，故 能方便使用者之量測操作。 為了獲得上述發明目的，本發明係提供一種對多級治具之 等效電路補償之架構，包含：一計算單元、至少一量測裝置、 一掃描治具、一標準待測物及一輸出單元，其中該量测裝置係 電性連接該掃描治具進而構成一等效電路以對一標準待測物 200841022 及一待測物進行量測並得各所需之補償參數。該計算單元進一 步包括一通訊介面、一操作介面、一記憶體單元及一邏輯運算 單元。該通訊介面係提供與量測裝置通訊之用。該操作介面係 提供使用者選擇是否進行補償或進行何種補償以輸入量測參 數及測試條件。該記憶體單元係存取該量測裝置所量測到之補 償參數，且可依據所設定之排程存取多組補償參數，以在下次 使用時可呼叫（Recall)為量測各元件之相同參數。該邏輯運 算單元係為一軟體程式，在得到各補償參數後即可計算出一補 償量測值。該多級治具之等效電路補償之架構進一步包括一輸 出單元用以顯示該邏輯運算單元所計算之補償量測值。 此外，可依據本發明之對多級治具之等效電路補償架構， 獲得一系列的對多級治具之等效電路補償方法。 【實施方式】 請參閱第一圖，為一種依據本發明之對多級治具之等效電 路補償之架構，其中包括一計算單元100、一量測裝置102、 一掃描治具104、一標準待測物106以及一輸出單元108。請 進一步參閱該第五圖，係顯示一種依據本發明之第一實施例之 該計算單元1〇〇可為一具有輸出/入、控制、算術邏輯及記憶功能之計 算器(如一個人電腦），其包括一通訊介面120、一操作介面140、 一記憶體單元160及一邏輯運算單元180。其中該操作介面140 可為一特定的人機介面程式，而該掃描治具104係採模組化設 200841022 計，具有可擴充之測試通道，且該量測襄置可為一電阻/電容/ 電感量測器（LCR Metei〇。 如第-及五圖所示，當量測裝置102電性連接至該通訊介 面i20以執行該操作介面140時，可經由該操作介们4〇輸入 量測參數及測試條件至量測裝置102，並傳送控制訊號至該邏 輯運算單元180以判斷使用何種補償公式，之後選擇進行何種 鲁補償方法。該記憶體單元160用以存取使用者自該操作介面 輸入至量測裝置102的量測參數及測試條件，先經由該量測裝 置102量測該標準待測物1〇6，再電性連接該掃描治具⑽， 並電性連接該標準待測物106及一待測物，以回傳各補償參數 至該邏輯運算單元18〇進行計算。該邏輯運算單元⑽係以一 軟體程式為主之補償程式且聯接該記憶體單元16〇。當該記憶 體單元160存取完各種所需之補償參數，包括標準值'開路值、 • ㈣值、標準量測值及實際量靠（待後詳述），即回傳這些補 償參數至該邏輯運算單元16〇_，並利用該補償程式即可計算 出其補償量測值並經由該輸出單元1〇8顯示。舉例而言，當該 邏輯運算單元180得到各補償參數後，即可利用如下負載補償 計异公式（1)，精確計算出一補償量測值（zdut): ⑴ ILdut^ 為冰(Ζο-Zsm)*( Zxrn^Zy) (Zsm-~Zsr)*(Zo-Zxm) 其中Zstd為一標準值，係透過該量測裝置直接量測一標準 200841022 符測物所得值；Zo為一開路值，係透過該量測裝置電性連接一 掃描治具以量測該標準待測物所得值；Zs為一短路值，係透過 該1測裝置電性連接一掃描治具所得值，將測試通道設成短路 或藉由一短路片；Zo——開路值，係透過該量測裝置電性連接一 掃描治具，將測試通道設成開路所得值；Zxm為一實際量測值， 係透過該量測裝置電性連接一掃插治具以量測一待測物。 • 另請進一步參閱第二、三圖，係依據本發明第一實施例在 鬲頻時與先前技術阻抗誤差率及補償誤差率之曲線圖，在高頻 時，掃瞄治具上的殘餘電阻、雜散電容及其他的雜訊干擾，會 明顯的造成在里測上的誤差’使用一量測裝置電性聯接一掃描 治具及一標準待測物，並取100KHz、2〇〇KHz、3〇〇KHZ、 400KHz、500KHz、600KHZ、700KHz、800KHz、900KHz 及 1MHz 等頻率點，以比較開路/短路補償及開路/短路/負載補償在高頻 _ 時的補償效果。接著’將計算(Zstd標準值-Zdm實際量测值)/Zstd標準 值之結果，即可得到阻抗量測的誤差，整理如下表一所示： ΙΟΟΚΗζ 200KHz 300KHz 400KHz SOOKHz 600KHz 700ΚΗζ 800ΚΗζ 9〇ΟΚΗζ ΙΜΗζ[Prior Art] With the continuous development of electronic related industries in recent years, consumer products such as 3c have become the mainstream of enthusiasm consumption. However, to form these products, a large number of electronic components are required. To ensure product quality, it is necessary to detect electronic components. Whether the standard conforms to the standard, and detects basic passive components such as capacitors, inductors, and resistors, and also measures various electronic components that are combined or composited by these components or have similar characteristics. The former includes various windings. Components, communication and power supply, etc., the latter are 1 switch, connector, wire, metal material, dielectric material, magnetic material and semiconductor components. In the early days, due to the stray capacitance of the fixture itself, the residual resistance, the contact resistance of the switch, the mutual interference of the line and the line, the external noise and the measurement frequency are constantly improving, the degree of the fineness of the household (4) has a great influence. The accuracy is defined as the measurement accuracy plus the error of the fixture, and the correcting action is performed on the measuring device to ensure the accuracy of the measuring device in the gauge, and the fixture is compensated to eliminate the amount. The error between the measuring device and the fixture. Based on the above reasons, various methods of supplementing have been developed, including the first type of offset compensation (offset eompensation). The method of 200841022 is to use the measuring end of the measuring tool to form a stray capacitance and affect the measured value. The compensated measured value can be obtained by subtracting the stray capacitance value from the measured value, but this compensation method is only used for the fixture type fixture. The second method is open/short compensation. It is assumed that the stray capacitance and residual resistance of the fixture are an equivalent circuit. When the equivalent circuit is open, the residual resistance is relatively large due to the infinite impedance of the measuring end. Small, so the stray capacitance can be measured. When the equivalent circuit is short-circuited, since the impedance of the measuring end is infinite and the stray capacitance is relatively large, the residual resistance can be measured. This compensation method is only applicable to the equivalent circuit and belongs to a simple symmetrical simple circuit. The third type is the open/short/load compensation method. Since the above second open/short compensation cannot compensate for an overly complicated or asymmetrical equivalent circuit, the third open circuit/ For the short-circuit/load compensation method, it is necessary to separately perform open-circuit and short-circuit compensation, and then electrically connect a standard test object with the measured parameters for load compensation. The known prior art can only compensate a single set of test objects for a general fixture, but if a scanning fixture, an expandable fixture or a more complicated combination of other fixtures is required, the path of the fixture is too Complex, easy to create complex equivalent circuits, so it will not be able to effectively compensate, and its memory capacity is limited, it will not be able to record multiple parameters, so the fixtures based on the prior art can not fully utilize the parameters to calculate the compensation value or repeat Use it to reduce accuracy and efficiency. 200841022 SUMMARY OF THE INVENTION In order to solve the above problems of the prior art, one of the main objects of the present invention is to provide an architecture for equivalent circuit compensation of a multi-level jig, which can be combined with a scanning jig, an expandable jig or a more complicated one. a combination of various fixtures, and measuring the values of the standard object to be tested and the object to be tested to obtain the required compensation parameters, and obtaining a compensation value through the operation, so that each measurement path in the fixture is formed Both the efficiency circuit and the spurious interference are compensated. • A primary object of the present invention is to provide a method for compensating for equivalent circuit of a multi-stage jig, wherein each scanning jig, an expandable jig or a more complex jig combination is based on electrical characteristics of different test objects. Or the need of physical characteristics, while compensating for multiple sets of different electrical characteristics or physical characteristics, without the need to perform measurement of a single group of test objects as in the prior art, thereby improving efficiency and reducing man-hours during measurement. Another object of the present invention is to provide an architecture for equivalent circuit compensation 10 of a multi-stage jig for storing measurement values or compensation parameters of a plurality of different test objects, and can be repeatedly used or used for multiple times. Different test objects have the same physical characteristics, and because the memory space is more expandable than the prior art, more data can be stored, so that the user can measure the operation. In order to achieve the above object, the present invention provides an architecture for equivalent circuit compensation of a multi-stage jig, comprising: a computing unit, at least one measuring device, a scanning jig, a standard object to be tested, and an output unit. The measuring device is electrically connected to the scanning fixture to form an equivalent circuit for measuring a standard object to be tested 200841022 and a sample to be tested and obtaining respective required compensation parameters. The computing unit further includes a communication interface, an operation interface, a memory unit, and a logic operation unit. The communication interface provides communication with the measurement device. The operator interface provides the user with the option of whether to compensate or what compensation to enter the measurement parameters and test conditions. The memory unit accesses the compensation parameter measured by the measuring device, and can access multiple sets of compensation parameters according to the set schedule, so that the next time the device is used, it can call (Recall) to measure each component. The same parameters. The logic operation unit is a software program, and after obtaining the compensation parameters, a compensation measurement value can be calculated. The architecture of the equivalent circuit compensation of the multi-level jig further includes an output unit for displaying the compensation measurement value calculated by the logic operation unit. In addition, according to the equivalent circuit compensation architecture of the multi-stage jig of the present invention, a series of equivalent circuit compensation methods for the multi-stage jig can be obtained. [Embodiment] Please refer to the first figure, which is an architecture for equivalent circuit compensation of a multi-stage jig according to the present invention, including a computing unit 100, a measuring device 102, a scanning jig 104, and a standard. The object to be tested 106 and an output unit 108. Please refer to the fifth figure, which shows that the computing unit 1 according to the first embodiment of the present invention can be a calculator (such as a personal computer) having output/input, control, arithmetic logic and memory functions. It includes a communication interface 120, an operation interface 140, a memory unit 160, and a logic operation unit 180. The operation interface 140 can be a specific human interface program, and the scanning fixture 104 is modularized with a 200841022 meter, and has a scalable test channel, and the measurement device can be a resistor/capacitor/ Inductance measuring device (LCR Metei). As shown in the first and fifth figures, when the equivalent measuring device 102 is electrically connected to the communication interface i20 to execute the operation interface 140, the input can be measured through the operation. The parameter and the test condition are sent to the measuring device 102, and the control signal is transmitted to the logic operation unit 180 to determine which compensation formula is used, and then the method of performing the compensation is performed. The memory unit 160 is used to access the user. The measurement interface is input to the measurement parameter and the test condition of the measurement device 102. The standard test object 102 is first measured by the measurement device 102, and then the scan fixture (10) is electrically connected, and the standard is electrically connected. The object to be tested 106 and an object to be tested are calculated by returning the compensation parameters to the logic operation unit 18. The logic operation unit (10) is a compensation program mainly based on a software program and is coupled to the memory unit 16A. When the note The body unit 160 accesses various required compensation parameters, including the standard value 'open circuit value, · (four) value, standard measurement value and actual quantity (to be detailed later), that is, returning the compensation parameters to the logic operation unit 16〇_, and using the compensation program, the compensation measurement value can be calculated and displayed through the output unit 1〇 8. For example, when the logic operation unit 180 obtains each compensation parameter, the following load compensation can be utilized. Calculate the difference formula (1) and accurately calculate a compensation measure (zdut): (1) ILdut^ is ice (Ζο-Zsm)*( Zxrn^Zy) (Zsm-~Zsr)*(Zo-Zxm) where Zstd is A standard value is obtained by directly measuring the value of a standard 200841022 measuring object through the measuring device; Zo is an open circuit value, and the measuring device is electrically connected to the scanning fixture to measure the standard test object. Value; Zs is a short-circuit value, which is electrically connected to the value obtained by scanning the fixture through the 1 measuring device, and the test channel is set to be short-circuited or by a short-circuit piece; Zo-opening value is transmitted through the measuring device Connect a scanning fixture and set the test channel to an open value; Zxm is one The actual measured value is electrically connected to the swept fixture through the measuring device to measure a test object. • Please refer to the second and third figures further, in accordance with the first embodiment of the present invention. The curve of the previous technical impedance error rate and the compensation error rate. At high frequencies, the residual resistance, stray capacitance and other noise interference on the scanning fixture will obviously cause the error in the measurement. The measuring device is electrically connected to a scanning fixture and a standard object to be tested, and takes frequency points of 100KHz, 2〇〇KHz, 3〇〇KHZ, 400KHz, 500KHz, 600KHZ, 700KHz, 800KHz, 900KHz and 1MHz to compare Open/short circuit compensation and open/short/load compensation compensation at high frequency _. Then, the result of the (Zstd standard value - Zdm actual measurement value) / Zstd standard value will be calculated, and the error of the impedance measurement can be obtained, as shown in the following Table 1: ΙΟΟΚΗζ 200KHz 300KHz 400KHz SOOKHz 600KHz 700ΚΗζ 800ΚΗζ 9〇ΟΚΗζ ΙΜΗζ
200841022 .(表一） 若將表一之誤差改為如第二圖所示，從第二圖中的開路/短 路補償誤差曲線200與開路/短路/負載補償誤差曲線202中可 明顯的發現，開路/短路/負載補償隨著頻率的改變仍然能將阻 抗量測誤差維持在正負0.1%之内，而以開路/短路補償後的阻 抗量測誤差則是呈現不穩定的現象，其誤差範圍介於4%〜-2% 之間。將以上表一之誤差取20LOG後正如第三圖所示，利於觀 察兩種補償間的差異。自第三圖中的開路/短路補償誤差曲線 300與開路/短路/負載補償誤差曲線302可明顯的發現，開路/ 短路補償誤差曲線300的準位都比開路/短路/負載補償誤差曲 線302來的高（代表其誤差也較大），其之間的差異約為20dB， 最大差異則有到40dB左右，因此可知道之間的補償效果的差 距在10倍〜10000倍左右。由此實驗可知在高頻時開路/短路/ 負載補償的穩定性及補償效果都比開路/短路補償好且開路/短 路/負載補償誤差也比開路/短路補償誤差好1〇倍以上。 此外，如第四圖所示，係顯示一種依據本發明之對多級治 具之等效電路補償之方法的步驟流程圖，其中利用一等效電路 補償之架構，該架構包括一計算單元、至少一量測裝置（如電 阻/電容/電感量測器（LCR Meter))、一掃描治具（Scanner)、一標 準待測物及一輸出單元（如LCD顯示器或LED顯示器等）互 為分別電性連接，且該計算單元具有如第五圖所示之各元件， 200841022 該方法包含以下步驟： 、，步驟/伽’將—量測裝置進行開路補償，以測得雜散電容， 並將測得之雜散電容值傳送到邏輯運算單元計瞀. 步驟s術，該量測裝置進行短路補償以測得殘餘電阻，並 將測得之殘餘電阻值傳送到邏輯運算單元計瞀· 步驟_，將該量測裝置進行負載補償，先電性連接-桿 準待測物所得值係—標準值（Zstd)，並將測得之標準值 (Zstd) ’經由通訊介面存取到記憶體單元； ^步驟_，該量測裝置電性連接一掃插治具並進行開路補 =所得值係-開路值（z。），將測得之開路值（z。），經由通訊 "面存取到記憶體單元； 步驟S4〇8,該掃㈣具進行短路㈣所得值係—短路值 )將測传之短路值（Zs)，、經由通訊介面傳送到記憶體 元； 、、步^ S410，該掃插治具電性連接該標準待測物，並進行量 測所得值係一標準量測值㈣，將測得之標準量測值(㈣， 經由通訊介面存取到記憶體單元； 步驟S4i2’該掃描治具電性連接一待測物，進行量測所得 值係一實際量測值 值（ZX)’將測得之實際量測值（Zx)，經由通 訊）丨面存取到記單元；以及 /驟S414’將存取在該記憶體單元中各補償參數（包括標準 * · 12 200841022 值、.開路值、短路值、標準量測值及實際量測值），傳送至邏輯 運算單元計算，得到—補償量測值（Zdut)並經由該輪出單元 顯示。 綜上所論，本發明係將掃描治具、掃瞎治具及以不對稱路 位之冶具產生之等效電路經由本發明加以補償，並提供可存取 多筆補償參數之記憶空間及呼叫功能，可提供用於之後多次重 覆使用之數據，以俾解決上述習知技術之問題。 雖然本發明已用較佳實施例揭露如上，然其並非用以限定 本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍 内’當可作錢之更動與修?文，因此本發明之保護範圍當視後 附之申請專利範圍所界定者為準。 13 200841022 【圖式簡單說明】 第1圖係本發明之對多級治具之等效電路補償之架構。 第2圖係依據本發明第一實施例之在高頻時阻抗誤差率之 曲線圖。 第3圖係依據本發明第一實施例之在高頻時補償誤差率之 曲線圖。 第4圖係本發明之對多級治具之等效電路補償之方法流程 • 圖。 第5圖係依據本發明第一實施例之計算單元之内部架構方 塊圖。 【主要元件符號說明】 100 計算單元 102 量測裝置 104 掃瞎治具 106 標準待測物 108 輸出單元 120 通訊介面 140 操作介面 160 記憶體單元 180 邏輯運算單元 200 - 300 開路/短路補償誤差曲線 202 - 302 開路/短路/負載補償誤差曲線200841022 . (Table 1) If the error of Table 1 is changed as shown in the second figure, it can be clearly found from the open/short compensation error curve 200 and the open/short/load compensation error curve 202 in the second figure, The open/short/load compensation can still maintain the impedance measurement error within plus or minus 0.1% with the change of frequency, and the impedance measurement error after open/short compensation is unstable, and the error range is Between 4% and -2%. Taking the error of Table 1 above as 20LOG, as shown in the third figure, is helpful to observe the difference between the two compensations. From the open/short compensation error curve 300 and the open/short/load compensation error curve 302 in the third figure, it can be clearly found that the level of the open/short compensation error curve 300 is higher than the open/short/load compensation error curve 302. The high (representing the error is also large), the difference between them is about 20dB, and the maximum difference is about 40dB, so it can be known that the difference between the compensation effects is about 10 times to 10000 times. From this experiment, it can be seen that the stability and compensation effect of open/short/load compensation at high frequency are better than open/short compensation and the open/short/load compensation error is more than 1〇 more than the open/short compensation error. In addition, as shown in the fourth figure, there is shown a flow chart of a method for the equivalent circuit compensation of a multi-stage jig according to the present invention, wherein an architecture of an equivalent circuit compensation is used, the architecture including a computing unit, At least one measuring device (such as a resistor/capacitor/inductance meter (LCR Meter)), a scanning fixture (Scanner), a standard object to be tested, and an output unit (such as an LCD display or an LED display) are mutually different Electrically connected, and the computing unit has the components as shown in the fifth figure, 200841022 The method comprises the following steps: , step / gamma - the measuring device is open circuit compensated to measure the stray capacitance, and The measured stray capacitance value is transmitted to the logic operation unit. In step s, the measuring device performs short-circuit compensation to measure the residual resistance, and transmits the measured residual resistance value to the logic operation unit. Step _ The measuring device is load-compensated, and the value obtained by electrically connecting the rod-measured object is the standard value (Zstd), and the measured standard value (Zstd) is accessed to the memory unit via the communication interface. ; ^ Step _, the measuring device is electrically connected to a sweeping fixture and performs an open circuit compensation = the obtained value system - the open circuit value (z.), and the measured open circuit value (z.) is accessed via the communication & face access to the memory The body unit; step S4〇8, the sweep (four) has a short circuit (four) value obtained - short circuit value) will pass the measured short circuit value (Zs), transmitted to the memory element via the communication interface; , , step ^ S410, the sweep The insertion test is electrically connected to the standard test object, and the measured value is a standard measurement value (4), and the measured standard measurement value ((4) is accessed to the memory unit via the communication interface; step S4i2' The scanning fixture is electrically connected to a test object, and the measured value is an actual measured value (ZX)', and the measured actual measured value (Zx) is accessed via the communication to the unit. And /Step S414' will access the compensation parameters (including the standard * · 12 200841022 value, open circuit value, short circuit value, standard measurement value and actual measurement value) in the memory unit to the logical operation unit The calculation obtains a compensation measurement value (Zdut) and displays it via the wheel-out unit. In summary, the present invention compensates for the scanning jig, the broom jig, and the equivalent circuit generated by the tool of the asymmetric road position, and provides a memory space and a call function for accessing multiple compensation parameters. Data for subsequent repeated use can be provided to solve the above-mentioned problems of the prior art. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 13 200841022 [Simple description of the drawings] Fig. 1 is a diagram showing the structure of the equivalent circuit compensation for the multi-stage jig of the present invention. Fig. 2 is a graph showing the impedance error rate at a high frequency according to the first embodiment of the present invention. Fig. 3 is a graph showing the compensation error rate at a high frequency according to the first embodiment of the present invention. Figure 4 is a flow chart of the method for compensating the equivalent circuit of the multi-stage jig of the present invention. Figure 5 is a block diagram showing the internal architecture of a computing unit in accordance with a first embodiment of the present invention. [Description of main component symbols] 100 Calculation unit 102 Measuring device 104 Broom jig 106 Standard DUT 108 Output unit 120 Communication interface 140 Operation interface 160 Memory unit 180 Logic operation unit 200 - 300 Open/short compensation error curve 202 - 302 open/short/load compensation error curve