TW200840444A - Via-adjusting method and system - Google Patents

Via-adjusting method and system Download PDF

Info

Publication number
TW200840444A
TW200840444A TW96109290A TW96109290A TW200840444A TW 200840444 A TW200840444 A TW 200840444A TW 96109290 A TW96109290 A TW 96109290A TW 96109290 A TW96109290 A TW 96109290A TW 200840444 A TW200840444 A TW 200840444A
Authority
TW
Taiwan
Prior art keywords
hole
pin
preset
attribute data
electronic component
Prior art date
Application number
TW96109290A
Other languages
Chinese (zh)
Other versions
TWI319298B (en
Inventor
Chun-Qing Mao
Bg Fan
Original Assignee
Inventec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inventec Corp filed Critical Inventec Corp
Priority to TW96109290A priority Critical patent/TWI319298B/en
Publication of TW200840444A publication Critical patent/TW200840444A/en
Application granted granted Critical
Publication of TWI319298B publication Critical patent/TWI319298B/en

Links

Abstract

A via-adjusting method and system applicable to a PCB wiring software are disclosed, wherein the PCB is deposited with at least an electronic component having a plurality of pins. The via-adjusting method and system include: acquiring location information on two adjacent pins of each electronic component on the PCB and the preset via property data thereof; calculating an interval value between the two adjacent pins according to the acquired location information; calculating an interval value between a pin and its corresponding preset via and determining if the calculated interval value is within the range of a predetermined value, and if not, assigning the via property data to the electronic component having the corresponding pin and depositing a via in the component area according to the relation between a predetermined interval range of the pin and the via property data; and if yes, reserving the preset via property data and depositing a via in the component area according to the preset via property data, thereby providing for a rapid and convenient adjustment of via property data for different components.

Description

200840444 九、發明說明: 【發明所屬之技術領域】 本發明係有關於一種通孔調整技術,更詳而言之,係 關於一種應用於一印刷電路板之佈線軟體中之通孔調整 方法及系統。 【先前技術】 。 目前印刷電路板上多數佈設有具有不同功能之電子 ,元件,例如球柵陣列式(BGA)、覆晶式(FlipChip)、晶片 •尺寸封裝(Chip Size package ; csp)與多晶片模組(mcm, Multi chip module)等之半導體封裝件,而且,印刷電路 板大多為多層板,各層板之間係透過通孔(via)電性連 接,且该通孔通常係設置於電子元件之複數接腳之間。 透過例如Allegro、protel等現有各類佈線軟體程式 設計印刷電路板時,對於同一印刷電路板,一般係設計同 一屬性資料(包括通孔直徑尺寸訊息)之通孔。但隨著技 -籲術的不斷發展,為使半導體封裝件更輕薄短小,生產具有 r縮小線路寬度與電性連接墊尺寸之細線距(Fine_pitch) 產品已成為業界持續努力之目標,而諸如球柵陣列式 (Ball Grid Array ; BGA)、覆晶式(Flip Chip)、晶片尺 寸封裝(Chip size package; csp)與多晶片模組(Muiti chip module ; MCM)等可縮小積體電路(Ic)面積且具有高 密度與多接腳化特性之電子元件遂日漸成為封裝市場上 的主流,如此,造成有的電子元件之接腳之間的間距愈來 愈小,在此電子元件元件區域只能選擇較小直徑尺寸之通 110202 6 200840444 孔’使得同-印刷電路板中佈設之各該電子元件所對 各接腳間距的大小不一,導致於各該電子元件 : 孔屬性資料亦不可处知π f ^ ΰ直 < 通 不了此相同,此時,則需依據不同電 所包含之接腳間距值設定不同之通孔屬性資料。 目4之做法係以手動方式逐個檢測印刷電路板上夂 該電子元件中各接腳之間距值,以於發現上述電子元件°接 ::距值過小(或過大)時,於該電子元件區域::= 錄尺寸之通孔更換為直徑尺寸較預設值更小、 三更大)之通孔,如此一來,將耗費大 :亍檢測與更換動作,而且’由於同一電 : 般:為Γ寸相同’且各該接㈣均勾分佈於‘ ::1: 該電子元件中其中二相鄰接腳之間距 值不適合於該二接腳間佈設具有預設直徑尺寸之通 t則表明該電子元件區域财預佈狀通孔屬 :行同樣的更換作業’因此,往往是找到待修改之電』 件,則需士重複執行通孔更換之相同作業,無疑增加了佈線 之工作時間,極大地影響佈線效率。 2=述:如何提出—種可解決f知技術之缺失 ^周整方法及系統,實為目前亟欲解決之技 【發明内容】 馨於上述習知技術之缺點,本發明之主要目的在於提 二周敕整方法m以節省不同電子元件之通孔 调正%間、人力及精力,進而提高佈線效率。 為達上述目的及其他目的,本發明提供-種通孔調整 110202 7 200840444 方法及系統。本發明之通孔調整方法係應用於一印刷電路 •板之佈線軟體中,其中,該印刷電路板係佈設有至少一呈 有複數接腳(pin)之電子^件,該通孔調整方法係包括 以下步驟:(1)預先設定不同接腳間距範圍及其對應之通 孔屬性貧料訊息;(2)於該印刷電路板選取所有電子元 件,以摘取該各電子元件中之其中二相鄰之接腳之位置訊 ‘息’並擷取該預設之通孔屬性資料;⑶依據所操取之二 •相鄰接胳P之位置訊息,計算該二相鄰接腳之間距值;⑷ '依據該擷取模組所擷取之二相鄰接腳之位置訊息、該預設 之通孔屬性資料、透過該第一計算模組所計算之二相鄰接 腳之間距值、以及預設之運算規則,計算該接腳至其對應 之預設通孔之間距值;(5)判斷所計算出之該間距值是否 在預没值範圍内,若否,則進至步驟(6),若是,進至步 驟(了);(6)自該預設之資料中搜尋出與所計算之二相鄰接 I7之間距值相對應的接腳間距範圍,並從中提取與該接腳 間距範圍對應之通孔屬性資料作為新的通孔屬性資料,將 對應該接腳之該電子元件之通孔屬性資料由預設之通孔 屬性資料調整為該新的通孔屬性資料,並令該佈線軟體依 據該新的通孔屬性資料於該電子元件區域佈設通孔;以及 (Ό保留對應該接腳之該電子元件之預設之通孔屬性資 料,並令§亥佈線軟體依據該預設之通孔屬性資料於該電子 元件區域佈設通孔。 . 此外’本發明之通孔調整系統係應用於一印刷電路板 之佈線軟體中,其中,該印刷電路板係佈設有至少一具有 110202 8 200840444 ‘衩數接腳(Pin)之電子元件,該通孔調整系統係包括: 用以提供預先設定不同接腳間距範圍及其對應之通孔屬 性貧料訊息之設定模組;用以於該印刷電路板選取所有電 子兀件,以擷取該各電子元件中之其中二相鄰之接腳之位 置汛息,並擷取該預設之通孔屬性資料之擷取模組;用以 依據該擷趣模組所擷取之二相鄰接腳之位置訊息,計算該 二相鄰接腳之間距值之第一計算模組;用以依據該擷取模 組所擷取之二相鄰接腳之位置訊息、該預設之通孔屬性資 料、透過該第一計算模組所計算之二相鄰接腳之間距值、 以及預設之運算規則,計算該接腳至其對應之預設通孔之 間,值之第二計算模組;以及用以判斷該第二計算模組所 2异出之該間距值是否在預設值範圍内,若否,則自該設 定核組所預設之資料中搜尋出與該第—計算模組所計算 之一相鄰接腳之間距值相對應的接腳間距範圍,並從中提 取㈣接腳間距範圍對應之通孔屬性資料作為新的通孔 _屬性資料,將對應該接腳之該電子元件之通孔屬性資料由 預設之通孔屬性資料調整為該新的通孔屬性資料,並令該 :線軟體依據該新的通孔屬性資料於該電子元件區域^ 設通孔,若是,則保留對應該接腳之該電子元件之預設之 L孔屬II資料’並令該佈線軟體依據該預設之通孔屬性資 料於。亥书子元件區域佈設通孔之處理模組。 /於本發明之通孔調整方法及系統中,該接腳之位置訊 息係包括該接腳之中心、點位置訊息以及半徑尺寸,相應 地’該二相鄰接腳之間距值的計算係依據所賴取之二相鄰 110202 9 200840444 •接腳之中心點位置訊息,計算該二相鄰接腳之間距值。 . 相較於習知技術,本發明之·調整方法及系統係於 擷取印刷電路板中之各電子元件中之其中二相鄰接腳之 位置訊息以及預設之通孔屬性資料後,計算該二相鄰接腳 之間距值,並依據上述所擷取以及所計算之 腳至其對應之預設通孔之間距值,以判斷所計:°出=該/間 距值是否在預設值範圍内,若否,則依據一 ^腳0 •距範圍與通孔屬性資料的對應關係,賦予對二 電子元件該通孔屬性資料,並令該佈線軟體依據該通孔屬 性資料於該電子元件區域佈設通孔,若是,則保留預設之 通孔屬性資料,並令該佈線軟體依據該預設之通孔屬性資 料於該電子元件區域佈設通孔。如此,即可依據印刷電路 板中所佈設之各電子元件包含之各接腳之間距大小,相應 调整各該電子元件區域所允許佈設之通孔之屬性資料,俾 節省不同電子元件之通孔調整時間、人力及精力,進而提 _高佈線效率。 【實施方式】 以下係藉由特定的具體實例說明本發明之實施方 式,熟悉此技藝之人士可由本說明書所揭示之内容輕易地 瞭解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實例加以施行或應用,本說明書中的各項細節亦可 基於不同觀點與應用,在不悖離本發明之精神下進行各種 修飾與變更。 请參閱第1圖,係顯示本發明之通孔調整方法之操作 Π0202 10 200840444 •=如圖所示’本發明之通孔調整方法係應用於 .:過貢料處理裝置執行之印刷電路板之佈線軟體,該資料 =裝置可例如為個人電腦、筆記型電腦、飼服器或工作 寻’而該钸線軟體則可例如為A U egr。、Pr〇te!等。於 衫施例=該印刷電路板係佈設有至少—具有複數接腳 陣兀件’更詳而言之,該電子元件係為球栅 !二 1 Gri“rray;叫覆晶式(FUpChip)、 :二:寸封裝(Chip size package;csp)或其他所具有 ^接=尺寸均相同且各該接腳分佈均勻之電子元件 寺,该通孔之屬性資料係為該通孔之直徑尺寸。以 第2圖詳細㈣本發明之通孔調整方法之具體操 如弟1圖所示,首先執行步驟S1 00,預先設定不同 接腳間距範圍及其對應/° 資料係鱼qa 、札屬r生貝科汛息,該通孔屬性 貝料係㈣接腳間距範圍對應。接著進行步驟⑽。 於步驟S110中’於該印刷電路板選取所有電 以顧取該各電子元件中之其中二相鄰之接腳之位置訊 心’亚擷取該預設之通孔屬性資料。更詳而言之,該接腳 之位置,息係包括該接腳之中心點位置訊息以及半徑尺 寸。接著進行步驟S120。 二 自^步驟S120中,依據所擷取之二相鄰接腳之位置气 距值。點位置訊息’計算該二相鄰接腳之間 接者進仃步驟S130。 110202 11 200840444 於步驟S130中,依據該擷取模組所擷取之二相鄰接 腳之位置訊息、該預設之通孔屬性資料、透過該第 模組所料之二相_敎間距值、以及預設之運算f f H該㈣至其對應之舰職之_值。具體而 言,係利用所擷取之二相鄰接腳之半徑尺寸(r)、該通孔 直徑尺寸⑷、以及所計算出之二相鄰接腳:間距 進行δ十异,以得出該接腳至其對應之通孔之間距值 ⑴’其中,該間距值⑴之計算方式係如等式⑴所示: (1)= ((L)-2x(r)-(d))/2 (1)。 接著進行步驟S140。 < =步驟S140巾,判斷所計算出之該間距值是否在預 设值範圍内,若否,則進至步驟S151,若是, 驟 S152 。 、 於步驟S151中,自該預設之資料中搜尋出與所計算 ^二相鄰接腳之間距值(L)相對應的接腳間距範圍,並從 二預π又之資料中提取與該接腳間距範圍對應之通孔屬性 資料作為新的通孔屬性資料,將對應該接腳之該電子元件 之通孔屬性育料由預設之通孔屬性資料調整為該新的通 孔屬性資料,得到如第2圖所示之通孔屬性資料設定介· 面,其中,電子兀件A及電子元件c之通孔屬性資料均為 依據預設之資料分別重新調整為對應之新的通孔直徑尺 寸並々A佈線軟體依據該新的通孔直徑尺寸於該對應之 電子元件A或C區域佈設通孔。 於步驟S152中,保留對應該接腳之該電子元件之預 110202 12 200840444 設之通孔屬性資料,如第2圖所示,此時,該電子元件b ’之通孔屬性資料並未更改,而是保留預設值,即為通孔之 預設直徑尺寸’並令該佈線軟體依據該預設之通孔直徑尺 寸於该電子元件β區域佈設通孔。 ^執行上述通孔調整方法,係透過如第3圖所示之通孔 調整系統1得以實現。請參閱第2圖,本發明之通孔調整 ,統1係應用於一印刷電路板之例如AUegr〇、卜的η .寺佈線軟體中’其中,其中,該印刷電路板係佈設有至少 一具有複數接腳(pin)之電子元件(於本實施例中,係 =單個電子元件為例進行說明,但不以此為限),更詳而 。之,忒電子70件係為球柵陣列式(Bali Grid ; Β⑷、覆晶式(Flip Chip)、晶片尺寸封裝(叫200840444 IX. Description of the Invention: [Technical Field] The present invention relates to a through hole adjustment technique, and more particularly to a through hole adjustment method and system for use in a wiring software for a printed circuit board . [Prior Art]. At present, most of the printed circuit boards are provided with electronic components with different functions, such as ball grid array (BGA), flip chip (FlipChip), chip size package (csp) and multi-chip module (mcm). a semiconductor package such as a multi-chip module, and the printed circuit board is mostly a multi-layer board, and each layer is electrically connected through a via, and the through-hole is usually disposed on a plurality of pins of the electronic component. between. When designing a printed circuit board through various existing wiring software programs such as Allegro, protel, etc., the same printed circuit board is generally designed with through holes for the same attribute data (including via diameter size information). However, with the continuous development of technology-claim, in order to make the semiconductor package lighter and thinner, the production of Fine-pitch products with r-reduced line width and electrical connection pad size has become the goal of the industry's continuous efforts, such as the ball. Grid array Array (BGA), Flip Chip, Chip size package (CSP) and Multi-chip module (MCM) can reduce the integrated circuit (Ic) Electronic components with high density and multi-pinning characteristics are becoming the mainstream in the packaging market. As a result, the spacing between the pins of some electronic components is becoming smaller and smaller. Selecting the smaller diameter size of the pass 110202 6 200840444 hole 'so that the spacing of the pins of the electronic components arranged in the same - printed circuit board is different, resulting in each of the electronic components: hole attribute information is not known π f ^ ΰ straight < can not pass this the same, in this case, you need to set different through hole attribute data according to the pin spacing value included in different electricity. The method of the fourth step is to manually detect the distance between the pins of the electronic component on the printed circuit board, so as to find that the electronic component is connected to the electronic component region when the distance value is too small (or too large). ::= The through hole of the recorded size is replaced with a through hole whose diameter is smaller than the preset value and three larger). As a result, it will cost a lot: 亍 detection and replacement action, and 'because the same electricity: like: The same size is used and each of the four (four) hooks are distributed in ':1: the distance between two adjacent pins in the electronic component is not suitable for the connection between the two pins with a preset diameter. The electronic component area is pre-wired through hole: the same replacement operation is performed. Therefore, it is often found that the electric part to be modified is the same operation, and the same operation of the through hole replacement is repeated, which undoubtedly increases the working time of the wiring. Ground affects wiring efficiency. 2=Describe: How to propose a kind of method and system that can solve the problem of knowing the technology, and it is the technology that is currently being solved. [Invention] The main purpose of the present invention is to mention the disadvantages of the above-mentioned prior art. Two weeks to adjust the method m to save the through hole adjustment of different electronic components, manpower and energy, thereby improving wiring efficiency. To achieve the above and other objects, the present invention provides a method and system for through hole adjustment 110202 7 200840444. The through hole adjusting method of the present invention is applied to a wiring circuit of a printed circuit board, wherein the printed circuit board is provided with at least one electronic component having a plurality of pins, and the through hole adjusting method is The method includes the following steps: (1) pre-setting a range of different pin pitches and corresponding via-hole attribute information; (2) selecting all electronic components on the printed circuit board to extract two of the electronic components The position of the adjacent pin is called 'interest' and the predetermined through hole attribute data is captured; (3) the distance between the two adjacent pins is calculated according to the position information of the second adjacent pin P; (4) 'based on the position information of the two adjacent pins captured by the capture module, the preset through hole attribute data, the distance between two adjacent pins calculated by the first calculation module, and The preset operation rule calculates the distance between the pin and the corresponding preset through hole; (5) determines whether the calculated pitch value is within the pre-no value range, and if not, proceeds to step (6) ), if yes, proceed to step (); (6) from the preset capital Searching for the pin spacing range corresponding to the calculated distance between the adjacent I7, and extracting the through hole attribute data corresponding to the pin spacing range as the new through hole attribute data, which will be connected The through hole attribute data of the electronic component of the foot is adjusted to the new through hole attribute data by the preset through hole attribute data, and the routing software arranges the through hole in the electronic component area according to the new through hole attribute data; And (retaining the through-hole property information of the predetermined electronic component corresponding to the pin, and causing the WI wiring software to arrange the through hole in the electronic component region according to the preset through-hole property data. The through hole adjustment system is applied to a wiring software of a printed circuit board, wherein the printed circuit board is provided with at least one electronic component having 110202 8 200840444 'pins, which is a through hole adjustment system. The method includes: a setting module for pre-setting a range of different pin pitches and corresponding via-hole attribute information; for selecting all electronic components on the printed circuit board, Taking the position of two adjacent ones of the electronic components, and extracting the preset through-hole property data capture module; and using the two phases captured by the fun module a first computing module for calculating a distance between the two adjacent pins, and a position information of the two adjacent pins captured by the capturing module, and the preset The hole attribute data, the distance between the two adjacent pins calculated by the first calculation module, and the preset operation rule, calculate the second calculation between the pin and the corresponding preset through hole. And determining whether the spacing value of the second computing module 2 is within a preset value range, and if not, searching for the first data from the preset data of the setting core group Calculate the range of pin spacing corresponding to the distance between adjacent pins calculated by the module, and extract the through hole attribute data corresponding to the range of the pin spacing (4) as the new through hole_attribute data, which will correspond to the pin. The through hole attribute data of the electronic component is adjusted by the preset through hole attribute data to a new through hole attribute data, and the line software body is provided with a through hole in the electronic component area according to the new through hole attribute data, and if so, the preset L hole genus corresponding to the electronic component corresponding to the pin is retained II data 'and let the wiring software according to the preset through hole attribute data. The processing module of the through hole is arranged in the area of the Haishu sub-component. In the through hole adjusting method and system of the present invention, the position information of the pin includes the center of the pin, the position information of the point, and the radius size, and accordingly, the calculation of the distance between the two adjacent pins is based on The second adjacent 110202 9 200840444 • the position of the center point of the pin, calculate the distance between the two adjacent pins. Compared with the prior art, the adjustment method and system of the present invention are calculated after capturing the position information of two adjacent pins of each electronic component in the printed circuit board and the preset through hole attribute data. The distance between the two adjacent pins is determined according to the distance between the extracted and the calculated foot to the corresponding preset through hole, and the value is determined: ° = whether the / spacing value is at a preset value In the range, if not, according to the corresponding relationship between the range of the distance and the through hole attribute data, the through hole attribute data of the two electronic components is given, and the wiring software is based on the through hole attribute data on the electronic component. The through hole is arranged in the area, and if yes, the preset through hole attribute data is retained, and the wiring software arranges the through hole in the electronic component area according to the preset through hole attribute data. In this way, according to the distance between the pins included in each electronic component disposed in the printed circuit board, the attribute information of the through holes allowed in each of the electronic component regions can be adjusted correspondingly, and the through hole adjustment of different electronic components can be saved. Time, manpower and energy, and then improve the efficiency of wiring. [Embodiment] The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied by other specific embodiments, and various modifications and changes may be made without departing from the spirit and scope of the invention. Please refer to FIG. 1 for the operation of the through hole adjusting method of the present invention. Π0202 10 200840444 •= As shown in the figure, the through hole adjusting method of the present invention is applied to: a printed circuit board executed by a tribute processing device. Wiring software, the data = device can be, for example, a personal computer, a notebook computer, a food server or a job searcher, and the cable software can be, for example, AU egr. , Pr〇te!, etc. In the case of the shirt = the printed circuit board is provided with at least - a plurality of pin arrays. In more detail, the electronic component is a ball grid! 2 1 Gri "rray; called FUpChip, : 2: Chip size package (csp) or other electronic component temples having the same size and uniform distribution of the pins. The attribute data of the through holes is the diameter of the through hole. 2 is a detailed description of the fourth embodiment of the through hole adjustment method of the present invention. First, step S1 00 is performed, and the range of different pin pitches and their corresponding values are preset in advance. The fish qa and the genus R. Asbestos, the through hole attribute bead system (four) pin spacing range corresponds. Then step (10) is performed. In step S110, 'select all the electricity on the printed circuit board to take care of two of the adjacent electronic components. The position of the foot is selected from the preset through hole attribute data. More specifically, the position of the pin includes the center point position information of the pin and the radius size. Then, step S120 is performed. Second self-step S120, according to the two adjacent The position of the foot is determined by the position of the foot. The position information of the two adjacent pins is calculated as step S130. 110202 11 200840444 In step S130, two adjacent pins are taken according to the capture module. The position information, the through-hole attribute data of the preset, the two-phase _敎 spacing value predicted by the first module, and the preset operation ff H (the fourth) to the corresponding shipboard _ value. Specifically, Using the radius dimension (r) of the two adjacent pins taken, the diameter dimension of the through hole (4), and the calculated two adjacent pins: the spacing is δ, to obtain the pin to Corresponding via hole spacing value (1)', wherein the pitch value (1) is calculated as shown in equation (1): (1) = ((L) - 2x(r) - (d)) / 2 (1). Next, proceed to step S140. <=Step S140, determine whether the calculated pitch value is within a preset value range, if not, proceed to step S151, and if yes, step S152. In step S151, from The default data is searched for the range of pin spacing corresponding to the distance (L) between the two adjacent pins, and the data from the two pre-π Extracting the through hole attribute data corresponding to the pitch range of the pin as the new through hole attribute data, and adjusting the through hole attribute breeding of the electronic component corresponding to the pin by the preset through hole attribute data to the new pass According to the hole attribute data, the through-hole attribute data setting interface shown in FIG. 2 is obtained, wherein the through-hole attribute data of the electronic component A and the electronic component c are respectively re-adjusted to corresponding new ones according to the preset data. The through hole diameter size and the 布线A wiring software are arranged in the corresponding electronic component A or C area according to the new through hole diameter size. In step S152, the electronic component corresponding to the pin is reserved 110202 12 200840444 Set the through hole attribute data, as shown in Fig. 2, at this time, the through hole attribute data of the electronic component b' is not changed, but the preset value is retained, that is, the preset diameter size of the through hole 'and The wiring software lays a through hole in the electronic component β region according to the preset through hole diameter size. The above-described through hole adjustment method is implemented by the through hole adjustment system 1 as shown in Fig. 3. Referring to FIG. 2, the through hole adjustment system of the present invention is applied to a printed circuit board, such as AUegr〇, 卜, 寺. Temple wiring software, wherein the printed circuit board is provided with at least one The electronic components of the plurality of pins (in the present embodiment, the single electronic component is described as an example, but not limited thereto), and more specifically. The 70 pieces of 忒Electronics are ball grid array type (Bali Grid; Β (4), flip chip (Flip Chip), wafer size package (called

Package; CSP)或其他所具有之接腳之尺寸均相同且夂該 接腳分佈均勻之晶片等;該通孔之屬性資料係為該通^ 直徑尺寸。 • >第3 ®所示’本發明之通孔調整系統1係包括設定 -模組Π、擷趣模組13、第一計算模組15、第二計算模組 Π、以及處理模組19’以下即對本發明之通 之上揭各物件進行詳細說明。 糸、、死1 心疋权組U係用以提供預先設定不同接腳間距範 /及其對應之通孔屬性資料訊A,亦即,該通孔屬性 係與遠接腳間距範圍--對應。 -該擷取模組13係用以於該印刷電路板選取所有電子 凡件’以擷取該各電子元件中之其中二相鄰之接腳之位置 110202 13 200840444 ^吼息,並擷取該預設之通孔屬性資料。其中,該接腳之位 置汛息係包括該接腳之中心點位置訊息以及半徑尺寸。 该第一計算模組15係用以依據該擷取模組13所擷取 之二相鄰接腳之位置訊息,計算該二相鄰接腳之間距值。 具體而s,係依據該擷取模組丨3所擷取之二相鄰接腳之 中心點位置訊息,計算該二相鄰接腳之間距值。 、忒第一计异模組17係用以依據該擷取模組η所擷取 •籲之二相鄰接腳之位置訊息及該預設之通孔屬性資料以及 該第一計算模組15所計算之二相鄰接腳之間距值,並依 據預"又之運异規則,計算該接腳至其對應之預設通孔之 間距值。更詳而言之,係利用所擷取之二相鄰接腳之半徑 尺寸(r)、忒通孔之預設直徑尺寸(d)、以及所計算出之 二相鄰接腳之間距值α)進行計算,以㈣該接腳至其對 應之通孔之間距值(1),其中,該間距值⑴之計算方式係 如等式(1)所示: ⑴:((L)一2x(r)一(d))/2 ⑴。 該處理模組19係用以判斷該第二計算模組17所計算 =该間距值⑴是否在預設值㈣内,若否,則自該設 疋核,11所預設之資料中搜尋出與該第—計算模組11 ^計算之二相鄰接腳之間距值(L)相對應的接腳間距範 a ^攸相⑦之貝料中提取與該接腳間距範圍對應之通 ^屬性資料作為新的通孔屬性資料,將對應該接腳之該電 新^之通孔屬性㈣由預設之通孔屬性資料調整為該 ,人孔屬性貢料’並令該佈線軟體依據該新的通孔屬性 110202 14 200840444 .資料於該電子元件區域佈設通孔,若是,則保留對應該接 .腳之該電子元件之預設之通孔屬性資料,並令該佈線軟體 依據該預設之通孔屬性資料於該電子元件區域佈設通孔。 綜上所述’本發明之通孔調整方法及系統係於擷取印 刷電路板中之各電子元件中之其中二相鄰接腳之位置訊 息及預設之通孔屬性資料後,計算該二相鄰接腳之間距 值,並依據上述所擷取及所計算之訊息計算該接腳至其對 _應之預設通孔之間距值,以判斷所計算出之該間距值^否 在預δ又值範圍内,若否,則依據一預設之接腳間距範圍與 通孔屬性資料的對應關係,賦予對應該接腳之該電子元^ 該通孔屬性資料,並令該佈線軟體依據該通孔屬性資料於 該電子元件區域佈設通孔,若是,則保留預設之通孔屬性 資料,並令該佈線軟體依據該預設之通孔屬性資料於該電 =70件區域佈設通孔。如此,即可依據印刷電路板中所佈 設之各電子元件包含之各接腳之間距值大小,相應調整各 •"亥电子元件區域所允許佈設之通孔之屬性資料,俾節省不 —同電子元件之通孔調整時間、人力及精力,進而提高佈線 效率。 上述實施例僅例示性說明本發明之原理及其功效,而 非用於限制本發明。任何熟習此項技藝之人士均可在不違 背本發明之精神及範疇下,對上述實施例進行修飾與改 變。因此,本發明之權利保護範圍,應如後述之申請專利 範圍所列。 【圖式簡單說明】 110202 15 200840444 第i圖係本發明之通孔調整方法之操作流程示意圖; ^ 第2圖係本發明之通孔調整方法所調整之電子元件 ^ 之通孔屬性資料設定介面示意圖;以及 第3圖係本發明之通孔調整系統之基本架構方塊示 意圖。 【主要元件符號說明】 1 通孔調整系統 11 設定模組 13 擷取模組 15 第一計算模組 17 第二計算模組 19 處理模組 S100〜S152 步驟 16 110202Package; CSP) or other wafers having the same size and uniform distribution of the pins; the property information of the through holes is the diameter of the through hole. • > 3® shows the through hole adjustment system 1 of the present invention comprising a set-module, a fun module 13, a first computing module 15, a second computing module, and a processing module 19 The following is a detailed description of each item on the basis of the present invention.糸, 死1 疋 疋 组 U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U U . The capture module 13 is configured to select all electronic components on the printed circuit board to capture the position of two adjacent ones of the electronic components 110202 13 200840444 ^ Preset through hole attribute data. The position information of the pin includes a center point position message of the pin and a radius size. The first computing module 15 is configured to calculate a distance between the two adjacent pins according to the position information of the two adjacent pins captured by the capturing module 13. Specifically, the distance between the two adjacent pins is calculated according to the central point position information of the two adjacent pins captured by the capture module 丨3. The first metering module 17 is configured to: according to the location information of the adjacent pins of the capturing module η and the through hole attribute data of the preset and the first computing module 15 Calculate the distance between two adjacent pins, and calculate the distance between the pin and its corresponding preset through hole according to the pre-and-synchronization rule. More specifically, the radius dimension (r) of the two adjacent pins taken, the preset diameter dimension (d) of the through hole, and the calculated distance between the adjacent pins of the adjacent pins are used. The calculation is performed by (4) the distance between the pin and its corresponding through hole (1), wherein the pitch value (1) is calculated as shown in equation (1): (1): ((L) - 2x ( r) a (d))/2 (1). The processing module 19 is configured to determine whether the second computing module 17 calculates whether the spacing value (1) is within a preset value (4), and if not, searches for the preset data from the setting core, 11 Extracting the pin attribute corresponding to the pin pitch range from the pin material corresponding to the distance between the adjacent pins (L) calculated by the first calculation module 11^ As the new through-hole attribute data, the data will be adjusted to the corresponding through-hole attribute data of the corresponding new hole attribute of the corresponding pin (4), and the wiring software is based on the new The through hole attribute 110202 14 200840444. The data is arranged in the electronic component area, if yes, the preset through hole attribute data of the electronic component corresponding to the foot is retained, and the wiring software is based on the preset The through hole attribute data is provided with a through hole in the electronic component area. In summary, the through hole adjustment method and system of the present invention calculates the position information of two adjacent pins in each electronic component in the printed circuit board and the preset through hole attribute data. The distance between the adjacent pins is calculated, and the distance between the pin and the preset through hole is calculated according to the above-mentioned captured and calculated information to determine whether the calculated pitch value is Within the range of δ value, if not, according to the correspondence between the preset pin spacing range and the through hole attribute data, the corresponding attribute of the electronic element corresponding to the pin is given, and the wiring software is based on The through hole attribute data is arranged in the electronic component area, if yes, the preset through hole attribute data is retained, and the wiring software arranges the through hole in the electric=70 area according to the preset through hole attribute data. . In this way, according to the distance between the pins included in each electronic component disposed in the printed circuit board, the attribute information of the through holes allowed in each of the "electronic components" can be adjusted accordingly, thereby saving the same The through hole of the electronic component adjusts the time, manpower and energy, thereby improving the wiring efficiency. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Modifications and alterations of the above-described embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the scope of the patent application to be described later. BRIEF DESCRIPTION OF THE DRAWINGS 110202 15 200840444 FIG. 1 is a schematic diagram showing the operation flow of the through hole adjusting method of the present invention; ^ FIG. 2 is a through hole attribute data setting interface of the electronic component adjusted by the through hole adjusting method of the present invention. Schematic diagram; and Fig. 3 is a block diagram showing the basic structure of the through hole adjustment system of the present invention. [Main component symbol description] 1 Through hole adjustment system 11 Setting module 13 Capture module 15 First calculation module 17 Second calculation module 19 Processing module S100~S152 Step 16 110202

Claims (1)

200840444 十、申請專利範圍: 被 ,丨· 一種通孔調整方法,係應用於透過資料處理裝置執行 之印刷電路板之佈線軟體中,其中,該印刷電路板係 佈5又有至少一具有複數接腳(pin)之電子元件,該 通孔调整方法係包括以下步驟: U )預先設定不同接腳間距範圍及其對應之通孔 • 屬性資料訊息; - 選取該印刷電路板之所有電子元件,以擷取 , 該各電子元件中之其中二相鄰之接腳之位置訊息,並 擷取該預設之通孔屬性資料; (3)依據所擷取之二相鄰接腳之位置訊息,計算 該二相鄰接腳之間距值; (4 )依據該擷取模組所擷取之二相鄰接腳之位置 成息、該預設之通孔屬性資料、透過該第一計算模組 所計算之二相鄰接腳之間距值、以及預設之運算規 _ 則,計算該接腳至其對應之預設通孔之間距值; u (5)判斷所計算出之該間距值是否在預設值範圍 内,若否,則進至步驟(6),若是,進至步驟(了); (6)自該預設之資料中搜尋出與所計算之二相鄰 接腳之間距值相對應的接腳間距範圍,並從該預設之 資料中提取與該接腳間距範圍對應之通孔屬性資料 作為新的通孔屬性資料,將對應該接腳之該電子元件 之通孔屬性資料由預設之通孔屬性資料調整為該新 的通孔屬性育料,並令該佈線軟體依據該新的通孔屬 110202 17 200840444 “ 性資料於該電子元件區域佈設通孔;以及 ^ (7)保留對應該接腳之該電子元件之預設之通孔 屬性育料,並令該佈線軟體依據該預設之通孔屬性資 料於該電子元件區域佈設通孔。 2·如申請專利範圍第丨項之通孔調整方法,其中,該接 腳之位置吼息係包括該接腳之中心點位置訊息以及 半徑尺寸。 _ 3·如申請專利範圍第2項之通孔調整方法,其中,該二 1 1 相鄰接腳之間距值的計算係依據所擷取之二相鄰接 腳之中心點位置訊息,計算該二相鄰接腳之間距值。 4·如申請專利範圍第1項之通孔調整方法,其中,該電 子元件係為球栅陣列式(Ban Grid Array ; BGA)、覆 晶式(Flip Chip)或晶片尺寸封裝(Chip size package ; CSP)之其中一者。 5· —種通孔調整系統,係應用於透過資料處理裝置執行 _ 之印刷電路板之佈線軟體中,其中,該印刷電路板係 佈β又有至少一具有複數接腳(p i η )之電子元件,該 通孔調整系統係包括: 設定模組’係用以提供預先·設定不同接腳間距範 圍及其對應之通孔屬性資料訊息; 擷取模組’係用以選取該印刷電路板之所有電子 元件’以擷取該各電子元件中之其中二相鄰之接腳之 位置訊息’並擷取該預設之通孔屬性資料; 第一計算模組,係用以依據該擷取模組所擷取之 18 110202 200840444 二相鄰接腳之位置訊息,計算該二相鄰接腳之間距 •值; 警 第二計算模組,係用以依據該擷取模組所擷取之 二相鄰接腳之位置訊息、該預設之通孔屬性資料、透 過忒第一計算模組所計算之二相鄰接腳之間距值、以 及預設之運算規則,計算該接腳至其對應之預設通孔 ,之間距值;以及 , ‘ 處理模組,係用以判斷透過該第二計算模組所計 1 算出之該間距值是否在預設值範圍内,若否,則自該 設定模組所預設之資料中搜尋出與該第一計算模組 所計算之二相鄰接腳之間距值相對應的接腳間距範 圍並從忒預没之資料中提取與該接腳間距範圍對應 之通孔屬性資料作為新的通孔屬性資料,將對應該接 腳之该電子元件之通孔屬性資料由預設之通孔屬性 ‘ 資料調整為該新的通孔屬性資料,若是,則保留對應 • 该接腳之該電子元件之預設之通孔屬性資料。 6·如申請專利範圍第5項之通孔調整系統,其中,該接 腳之位置訊息係包括該接腳之中心點位置訊息以及 半徑尺寸。 7·如申請專利範圍第6項之通孔調整系統,其中,該二 相鄰接腳之間距值的計算係依據該擷取模組所顧取 之二相鄰接腳之中心點位置訊息,言十算該二相鄰接腳 之間距值。 8·如申請專利範圍第5項之通孔調整系統,其中,該電 110202 19 200840444 子元件係為球柵陣列式(Ball Grid Arra/; 覆晶式(FI ip Chip)、及晶片尺寸封裝(Chip package ; CSP)之其中一者。 BGA)、 size200840444 X. Patent application scope: 丨· A through-hole adjustment method is applied to a wiring software of a printed circuit board executed by a data processing device, wherein at least one of the printed circuit board fabrics 5 has a plurality of connections The electronic component of the pin, the through hole adjustment method comprises the following steps: U) presetting the range of different pin pitches and corresponding through holes and attribute information messages; - selecting all the electronic components of the printed circuit board to Extracting the position information of two adjacent ones of the electronic components, and extracting the preset through hole attribute data; (3) calculating according to the position information of the two adjacent pins that are captured The distance between the two adjacent pins; (4) according to the position of the two adjacent pins captured by the capturing module, the predetermined through hole attribute data, and the first computing module Calculating the distance between the adjacent pins and the preset operation rule _, calculating the distance between the pin and the corresponding preset through hole; u (5) determining whether the calculated pitch value is Within the preset range, Otherwise, proceed to step (6), and if yes, proceed to step (); (6) search for the range of pin spacing corresponding to the calculated distance between the two adjacent pins from the preset data. And extracting the through hole attribute data corresponding to the pin pitch range from the preset data as the new through hole attribute data, and the through hole attribute data of the electronic component corresponding to the pin is preset through the through hole The attribute data is adjusted to the new through hole attribute breeding, and the wiring software is arranged according to the new through hole 110202 17 200840444 "sexual data in the electronic component area through the through hole; and ^ (7) retains the corresponding pin The predetermined through hole attribute of the electronic component is bred, and the wiring software arranges the through hole in the electronic component area according to the preset through hole attribute data. 2. The through hole adjustment according to the scope of the patent application The method, wherein the position of the pin includes a position information of a center point of the pin and a radius size. _ 3· A method for adjusting a through hole according to the second item of the patent application, wherein the two 1 1 adjacent Gauge value between feet The distance between the two adjacent pins is calculated according to the position information of the center points of the two adjacent pins that are captured. 4. The method for adjusting the through hole according to the first item of the patent application, wherein the electronic component is One of the Ball Grid Array (BGA), Flip Chip, or Chip Size Package (CSP). 5. A through-hole adjustment system for data processing The device performs the wiring software of the printed circuit board, wherein the printed circuit board fabric β has at least one electronic component having a plurality of pins (pi η ), and the through hole adjustment system comprises: a setting module For providing pre-sets of different pin pitch ranges and their corresponding through-hole property information messages; the capture module 'is used to select all electronic components of the printed circuit board' to capture two of the electronic components The position information of the adjacent pin 'and the predetermined through hole attribute data; the first calculation module is used to select the position of the 18 110202 200840444 two adjacent pins according to the capture module message Calculating the distance between the two adjacent pins; the second computing module is configured to: according to the position information of the two adjacent pins captured by the capturing module, the preset through hole attribute data, Calculating the distance between the pin and its corresponding preset through hole by the distance between the two adjacent pins calculated by the first computing module and the preset operation rule; and, 'the processing module, The method is configured to determine whether the pitch value calculated by the second computing module is within a preset value range, and if not, search for the first computing mode from the data preset by the setting module. The range of pin spacing corresponding to the distance between two adjacent pins calculated by the group and extracting the through hole attribute data corresponding to the range of the pin spacing from the data of the pre-existing data as the new through hole attribute data, The through hole attribute data of the electronic component that should be pinned is adjusted by the preset through hole attribute 'data to the new through hole attribute data, and if so, the corresponding through hole of the electronic component of the pin is reserved. Property data. 6. The through hole adjustment system of claim 5, wherein the position information of the pin includes a center point position information of the pin and a radius size. 7. The through hole adjustment system of claim 6, wherein the calculation of the distance between the two adjacent pins is based on the position information of the center points of the two adjacent pins that the capture module takes. The tenth counts the distance between the two adjacent pins. 8. The through hole adjustment system of claim 5, wherein the 110202 19 200840444 sub-component is a ball grid array type (Ball Grid Arra/; flip chip (FI ip Chip), and wafer size package ( Chip package; CSP) One of them. BGA), size 20 11020220 110202
TW96109290A 2007-03-19 2007-03-19 Via-adjusting method and system TWI319298B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW96109290A TWI319298B (en) 2007-03-19 2007-03-19 Via-adjusting method and system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW96109290A TWI319298B (en) 2007-03-19 2007-03-19 Via-adjusting method and system

Publications (2)

Publication Number Publication Date
TW200840444A true TW200840444A (en) 2008-10-01
TWI319298B TWI319298B (en) 2010-01-01

Family

ID=44821166

Family Applications (1)

Application Number Title Priority Date Filing Date
TW96109290A TWI319298B (en) 2007-03-19 2007-03-19 Via-adjusting method and system

Country Status (1)

Country Link
TW (1) TWI319298B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI724447B (en) * 2018-08-13 2021-04-11 日商日本麥克隆尼股份有限公司 Wiring board design support device, wiring board through hole placement method and wiring board through hole placement program

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI724447B (en) * 2018-08-13 2021-04-11 日商日本麥克隆尼股份有限公司 Wiring board design support device, wiring board through hole placement method and wiring board through hole placement program

Also Published As

Publication number Publication date
TWI319298B (en) 2010-01-01

Similar Documents

Publication Publication Date Title
Huang et al. Wafer level system integration of the fifth generation CoWoS®-S with high performance Si interposer at 2500 mm2
KR101154621B1 (en) Structures for improving current carrying capability of interconnects and methods of fabricating the same
Pal et al. Architecting waferscale processors-a GPU case study
Liu et al. Synergistic effect of electromigration and Joule heating on system level weak-link failure in 2.5 D integrated circuits
KR101367671B1 (en) Microelectronic package and method of manufacturing same
US9955567B2 (en) Crosstalk reduction between signal layers in a multilayered package by variable-width mesh plane structures
Chiang et al. InFO_oS (integrated fan-out on substrate) technology for advanced chiplet integration
TWI231165B (en) Method for fabricating electrical connection structure of circuit board
CN106531656B (en) A kind of detection method of the nano mattisolda package quality based on boundary scan testing
US8354298B2 (en) Semiconductor device and manufacturing method of a semiconductor device
CN1716266A (en) The number of plies estimating device of BGA component mounting substrate and method and program
TW200840444A (en) Via-adjusting method and system
CN108828382A (en) Multi-chip integration test method
TW201010529A (en) Circuit substrate having power/ground plane with grid holes
CN1783055A (en) Automatic designing method for ICT test conversion PCB
Lattard et al. ITAC: a complete 3D integration test platform
Vaisband et al. Network on interconnect fabric
CN203368919U (en) Printed circuit board (PCB) pad and ball grid array (BGA) packaging PCB
TW201222304A (en) Method for setting width of printed circuit board trace
TW200844778A (en) Method for designing printed circuit board
CN113947046A (en) Design method, design device and computer storage medium for integrated circuit
Bautista Tera-scale computing and interconnect challenges
CN101271482B (en) Through hole regulation method and system
Gualandris et al. Wafer level packaging fan out thermal management: Is smaller always hotter?
Pal Scale-Out Packageless Processing

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees