CN113947046A

CN113947046A - Design method, design device and computer storage medium for integrated circuit

Info

Publication number: CN113947046A
Application number: CN202111181480.2A
Authority: CN
Inventors: 王贻源; 薛迎飞; 王喜龙
Original assignee: ICLeague Technology Co Ltd
Current assignee: ICLeague Technology Co Ltd
Priority date: 2021-10-11
Filing date: 2021-10-11
Publication date: 2022-01-18

Abstract

The embodiment of the disclosure provides a design method, design equipment and computer storage medium of an integrated circuit, wherein the design method comprises the following steps: obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate; grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area; grabbing a target area within the at least one first area, the target area being free of the intermediate metal layer and being located at a central position of the first area; placing a thermally conductive via in the target area.

Description

Design method, design device and computer storage medium for integrated circuit

Technical Field

The present disclosure relates to the field of integrated circuit design, and in particular, to a method and apparatus for designing an integrated circuit, and a computer storage medium.

Background

Three-dimensional (3D) integrated circuits are a novel packaging form in which multiple layers of chips are sequentially stacked and electrically connected through conductive vias, which can effectively reduce the interconnection power consumption and interconnection delay between chips, and can better realize the miniaturization and diversification of devices.

However, the heat conduction efficiency in the 3D integrated circuit is not high, and the heat generated by the chip cannot be discharged in time, which seriously affects the normal operation of the chip.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method for fabricating the same to solve at least one of the problems of the related art.

The technical scheme of the disclosure is realized as follows:

the embodiment of the disclosure provides a design method of an integrated circuit, which includes:

obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate;

grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area;

grabbing a target area within the at least one first area, the target area being free of the intermediate metal layer and being located at a central position of the first area;

placing a thermally conductive via in the target area.

In the above solution, the shape of the first region includes a square; the shape of the target area includes a square.

In the scheme, the side length of the first region is between 22 and 30 micrometers; the target area has a side length of between 4.5 microns and 10 microns.

In the foregoing solution, after the placing of the thermal via in the target region, the method further includes: and checking the design rule of the heat conduction through hole and the electric conduction through hole.

In the foregoing solution, the layout further includes: a top metal layer, the target region including the top metal layer;

placing a thermally conductive via within the target area, comprising:

acquiring the network attribute of the top metal layer of the target area;

adding a heat conduction through hole with the same network property as the top metal layer in the target area, wherein the top surface of the heat conduction through hole is at least partially in contact with the top metal layer.

In the above scheme, the layout further includes at least one pad, and the pad is located on the lower surface of the substrate; after placing the thermally conductive vias within the target area, the method further comprises:

electrically connecting the thermally conductive vias to pads having the same network properties as the thermally conductive vias.

In the above scheme, the layout further includes a physical unit; after placing the thermally conductive vias within the target area, the method further comprises:

and removing the physical units overlapped with the heat conduction through holes in the layout, and adding the physical units again in other areas which are not overlapped with the heat conduction through holes.

In the above scheme, the method further comprises: checking the design rule of the layout added with the heat conduction through hole; and checking the consistency of the layout added with the heat conduction through hole and the circuit diagram corresponding to the layout.

The disclosed embodiment also provides a design apparatus for an integrated circuit, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, the processor implementing any of the above design methods when executing the computer program.

The embodiment of the disclosure also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements any one of the design methods described above.

The design method, the design device and the computer storage medium of the integrated circuit provided by the embodiment of the disclosure are provided, wherein the design method comprises the following steps: obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate; grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area; grabbing a target area within the at least one first area, the target area being free of the intermediate metal layer and being located at a central position of the first area; placing a thermally conductive via in the target area. The heat conduction through hole provides an additional heat dissipation channel for the integrated circuit, so that the overall heat conduction coefficient of the integrated circuit is improved, and the heat dissipation performance of the integrated circuit is improved. Furthermore, the placement of the thermally conductive vias in areas without the standard cells, the electrically conductive vias and the intermediate metal layer does not cause any adverse effects on the existing design of the integrated circuit to be designed.

The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the disclosure will be apparent from the description and drawings, and from the claims.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic diagram of an exemplary 3D integrated circuit;

fig. 2 is a flow chart of a method for designing an integrated circuit according to an embodiment of the disclosure;

fig. 3a, fig. 4a, fig. 5a, and fig. 6a are schematic layout diagrams of steps in a method for designing an integrated circuit according to an embodiment of the present disclosure; FIG. 3b, FIG. 4b, FIG. 5b, and FIG. 6b are schematic cross-sectional views taken along line A-A' in FIG. 3a, FIG. 4a, FIG. 5a, and FIG. 6a, respectively;

FIG. 7 is a schematic structural diagram of a design apparatus provided in an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a computer-readable storage medium provided in an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art, that the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features of the art have not been described in order to avoid obscuring the present disclosure; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.

In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure. And the discussion of a second element, component, region, layer or section does not necessarily imply that the first element, component, region, layer or section is necessarily present in the disclosure.

Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Fig. 1 is a schematic diagram of an exemplary 3D integrated circuit, wherein the 3D integrated circuit includes a package substrate 10, a base plate 12 on the package substrate 10, a first chip 14 on the base plate 12, and a second chip 16 on the first chip 14; the substrate 12 and the package substrate 10 are electrically connected by a first bump 11, the first chip 14 and the substrate 12 are electrically connected by a second bump 13, and the second chip 16 and the first chip 14 are bonded by a bonding layer 15.

The package substrate 10 has a thermal conductivity between 25-35W/m.k in a direction parallel to its surface and between 0.2-0.5W/m.k in a direction perpendicular to its surface; the substrate 12 has a thermal conductivity between 40-50W/m.k in a direction parallel to its surface and between 5-7W/m.k in a direction perpendicular to its surface; the thermal conductivity of the first bump 11 is between 380-420W/m.k; the thermal conductivity of the second bump 13 is between 380-420W/m.k; the thermal conductivity of the bonding layer 15 is between 100 and 120W/m.k.

The first chip 14 includes a substrate 141, a device layer 142 on a surface of the substrate 141, an interconnect layer 143 on the device layer 142, and a conductive via 144 penetrating the substrate 141 and the device layer 142. The conductive vias 144 raise the thermal conductivity of the substrate 141 and the device layer 142 from 0.18-0.21W/m.k to 3-5W/m.k, and the thermal conductivity of the interconnect layer 143 is between 100-120W/m.k.

The second chip 16 includes a substrate 161, a device layer 162 on a surface of the substrate 161, and an interconnect layer 163 on a surface of the device layer 162. Specifically, the interconnection layer 163 of the second chip 16 and the interconnection layer 143 of the first chip 14 are bonded through a bonding layer 15. The thermal conductivity of the substrate 161 and the device layer 162 is between 0.18-0.21W/m.k, and the thermal conductivity of the interconnect layer 163 is between 100-120W/m.k.

When the 3D integrated circuit shown in fig. 1 is operating normally, the first chip 14 and the second chip 16 generate a large amount of heat. Since the thermal conductivity of the substrate 141 and the device layer 142 of the first chip 14 and the thermal conductivity of the substrate 161 and the device layer 162 of the second chip 16 are small, the thermal resistance of the upward or downward heat dissipation channel of the 3D integrated circuit is large, and heat cannot be quickly discharged. This greatly affects the heat dissipation of the first chip 14 and the second chip 16 during normal operation, thereby affecting the performance of the first chip 14 and the second chip 16.

Based on this, the disclosed embodiment provides a method for designing an integrated circuit, referring to fig. 2 specifically, as shown in the figure, the method includes the following steps:

step 201, obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate;

step 202, grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area;

step 203, grabbing a target area in the at least one first area, wherein the target area does not contain the intermediate metal layer and is located at the central position of the first area;

and 204, placing a heat conduction through hole in the target area.

According to the design method of the integrated circuit, the heat conduction through hole is arranged in the target area, and an additional heat dissipation channel is provided for the integrated circuit, so that the overall heat conduction coefficient of the integrated circuit is improved, and the heat dissipation performance of the integrated circuit is improved. Furthermore, the placement of the thermally conductive vias in areas without the standard cells, the electrically conductive vias and the intermediate metal layer does not cause any adverse effects on the existing design of the integrated circuit to be designed.

Fig. 3a, fig. 4a, fig. 5a, and fig. 6a are schematic layout diagrams of steps in a method for designing an integrated circuit according to an embodiment of the present disclosure; fig. 3b, 4b, 5b and 6b are schematic cross-sectional structures taken along the line a-a' in fig. 3a, 4a, 5a and 6a, respectively. The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. In describing the embodiments of the present disclosure in detail, the drawings are not to be taken as being generally to scale, and are for illustrative purposes only and should not be taken as limiting the scope of the present disclosure.

First, please refer to fig. 3a and fig. 3 b; executing step 201, obtaining a layout of the integrated circuit to be designed, wherein the layout comprises: a substrate 30 and a plurality of standard cells 32 within the substrate 30, intermediate metal layers M1, M2, M3 over the substrate 30 for electrically connecting the plurality of standard cells 32, and conductive vias 31 through the substrate 30.

Here, the layout of the integrated circuit to be designed includes a layout of an integrated circuit for which back-end design has been completed; the integrated circuit to be designed comprises a 3D integrated circuit.

The substrate may be a semiconductor substrate and may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In a particular embodiment, the substrate is a silicon (Si) substrate.

The conductive via may be a through silicon via; in a specific embodiment, the conductive via may be a backside through-substrate via.

It should be noted that, in order to make the drawings more clear and concise, only one standard cell and one conductive via are shown in fig. 3a and 3b, but in an actual layout design, the number of the standard cell and the number of the conductive via may be multiple.

In an embodiment, the layout further includes: a top metal layer TM1, the top metal layer TM1 being located on the middle metal layers M1, M2, M3. In a more specific embodiment, the layout further includes a second top metal layer TM2 located between the top metal layer TM1 and the middle metal layers M1, M2, M3. In practical processes, the top metal layer TM1 and the sub-top metal layer TM2 have a thicker thickness than the middle metal layers M1, M2 and M3, and the material of the top metal layer TM1 and the sub-top metal layer TM2 includes aluminum.

More specifically, the layout further includes contact plugs V1, V2, V3, and V4 for connecting two adjacent layers of the middle metal layers M1, M2, M3, the top metal layer TM1 and the next top metal layer TM2, wherein the middle metal layers M1, M2, M3, the next top metal layer TM2, the top metal layer TM1, and the contact plugs V1, V2, V3, and V4 are alternately distributed in a direction perpendicular to the substrate 30, as shown in fig. 3 b.

In an actual process, the integrated circuit further includes a dielectric layer 35, and the dielectric layer 35 wraps the middle metal layers M1, M2, M3, the second top metal layer TM2, the top metal layer TM1, and the contact plugs V1, V2, V3, and V4.

It should be noted that the number of layers of the intermediate metal layer may be more or less. Specifically, the number of layers of the intermediate metal layer and the number of contact plugs are not limited to those shown in fig. 3b, and the number of layers of the intermediate metal layer and the number of contact plugs may be greater or smaller.

The conductive via 31 comprises a via (not identified) through the substrate 30 and a conductive material within the via (not identified); the conductive material includes, but is not limited to, aluminum; the conductive via 31 functions to conduct an electrical signal.

As shown in fig. 3b, the upper surface of the conductive via 31 is in contact with the middle metal layer M1, so that an electrical signal can be conducted to the standard cell 32 through the conductive via 31. It is understood that the conductive via 31 is not limited to be connected to the middle metal layer M1, but may be connected to other metal layers, such as the middle metal layer M2, the middle metal layer M3, the second top metal layer TM2, and the top metal layer TM 1.

In an embodiment, the layout further includes a physical unit 33, and the physical unit 33 is located in the substrate 30 or the dielectric layer 35.

Here, the physical unit includes a unit having only physical information without timing information or logic information, and a unit having power and ground pins without a signal pin, for example, a pad unit, a decoupling capacitor unit.

In an embodiment, the layout further includes at least one pad 34, and the pad 34 is located on the lower surface of the substrate 30. In a specific embodiment, the lower surface of the conductive via 31 is in contact connection with the pad 34.

Next, please refer to fig. 4a and fig. 4 b; step 202 is executed, at least one first region 36 is grabbed in the layout, and the standard cells 32 and the conductive through holes 31 are not contained in the first region 36.

The method comprises the steps of grabbing a first area without standard cells and conductive through holes in a layout of an integrated circuit to be designed, and then placing a heat conduction through hole in the center of the first area meeting specific conditions. In general, when designing through-substrate vias, such as the conductive and thermal vias in the embodiments of the present disclosure, a designer will reserve an area around the via where no standard cells or other vias are located, which is also referred to as an exclusion zone. It will be appreciated that the first region may accommodate at least a subsequently arranged thermally conductive via and an exclusion zone around the thermally conductive via. In other words, in a direction parallel to the substrate, a boundary of the subsequently arranged heat conductive through hole and a boundary of the first region have a space therebetween, and a width of the space is greater than or equal to a width of an exclusion zone of the subsequently arranged heat conductive through hole. In one embodiment, the first region is square in shape. In a specific embodiment, the first region has a side length in a range of 22 to 30 micrometers, for example 24 to 28 micrometers. But not limited thereto, the first region may also be of other shapes, such as circular. When the first region is circular in shape, the first region has a diameter of between 22 and 30 microns.

In the actual capturing process, a plurality of first regions can be captured in the layout at the same time or sequentially captured in the layout. In other words, the plurality of first regions may be captured at the same time or may be captured at different times. The plurality of first regions may not overlap each other, and there may be a case where two or more first regions partially overlap. When two or more first areas are partially overlapped, the relation between the central distance between the two partially overlapped first areas and a preset minimum distance is considered, wherein the preset minimum distance refers to the closest distance by which the two first areas can be close, and the specific value of the distance is equal to the sum of the width of a subsequently arranged heat conduction through hole and the width of a forbidden zone around the heat conduction through hole. If the distance between the centers of the two partially overlapped first areas is greater than or equal to the preset minimum distance, both the two partially overlapped first areas can be reserved; and if the two partially overlapped first areas are smaller than the preset minimum distance, deleting any one of the two partially overlapped first areas. Therefore, the heat conduction through holes which are arranged adjacently in the following process can not appear in the forbidden zone of the other side.

Next, refer to fig. 5a, 5 b; step 203 is performed, grabbing a target area 37 within the at least one first area 36, the target area being free of the intermediate metal layers M1, M2, M3, and the target area 37 being located at a central position of the first area 36.

In one embodiment, the shape of the target region 37 comprises a square. In a more specific embodiment, the target area 37 has a side length of between 4.5 microns and 10 microns. But not limited thereto, the shape of the target area may also be a circle having a diameter between 4.5 and 10 micrometers.

In one embodiment, the target region 37 does not contain the sub-top metal layer TM 2. In other words, the target region 37 is free of windings of the middle metal layers M1, M2, M3, the next highest metal layer TM 2.

Finally, refer to fig. 6a, 6 b; step 204 is performed to place a thermally conductive via 38 in the target area 37.

Specifically, the characteristic size of the thermal via 38 is the same as the characteristic size of the target region 37. Without limitation, the feature size of the thermal via 38 may be smaller than the feature size of the target area 37.

In one embodiment, the target region 37 includes a top metal layer TM1, and the thermal via 38 is disposed in the target region 37, including:

acquiring network attributes of the top metal layer TM1 of the target area 37;

adding a thermal via 38 having the same network properties as the top metal layer TM1 in the target area 37, wherein the top surface of the thermal via 38 is at least partially in contact with the top metal layer TM1, so that the thermal via can conduct electrical signals in addition to serving as a heat dissipation channel.

Here, the network property may refer to the type of electrical signal transmitted, such as VDD or ground. In an actual design process, if the target area includes a top metal layer, the network property of the top metal layer is determined, and then a heat conduction through hole with the same network property as the top metal layer is placed in the target area. It can be understood that the upper surface of the heat conducting through hole should be in full contact with the top metal layer as much as possible, so that a good heat dissipation effect and an electrical signal transmission effect can be obtained. In a specific embodiment, the upper surface of the thermally conductive via is completely covered by the top metal layer.

In one embodiment, after placing the thermally conductive vias 38 in the target area 37, the method further comprises:

the thermally conductive vias 38 are electrically connected to the pads 34 having the same network properties as the thermally conductive vias 38. As such, the thermally conductive vias 38 may transmit electrical signals from the pads 34 to the interior of the integrated circuit, or from the interior of the integrated circuit to the pads 34.

removing the physical unit 33 overlapping with the heat conducting through hole 38 in the layout, and adding the physical unit 33 again in other areas not overlapping with the heat conducting through hole 38.

In one embodiment, after placing the thermally conductive vias 38 in the target area, the method further comprises: checking the design rule of the layout added with the heat conduction through hole; and checking the consistency of the layout added with the heat conduction through hole and the circuit diagram corresponding to the layout.

Here, the Design Rule Check (DRC) is a Design Rule Check of each layer of physical patterns in the layout to which the heat conductive via is added, and it also includes a Check of an antenna effect to ensure normal chip flow of the integrated circuit; the consistency check of the Layout added with the heat conduction through holes and the corresponding circuit diagram refers to the check of a Layout comparison circuit (LVS), and mainly compares the Layout added with the heat conduction through holes with a circuit netlist to ensure that the Layout circuit of the integrated circuit after tape out is consistent with the actually required circuit. The DRC and LVS checks are typically performed using Electronic Design Automation (EDA) tools.

After checking of DRC and LVS, the layout with the heat conducting through holes can enter a tape-out link. It is noted that the heat dissipation performance of the integrated circuit obtained after tape-out is greatly improved. Taking the 3D integrated circuit in fig. 1 as an example, the chip occupancy of the standard cells of the non-physical cells in the first chip is 60%, the chip occupancy of the conductive vias is 5%, the chip occupancy of the region where the thermal conductive vias can be added is 20%, and the thermal conductive vias are disposed in the region where the thermal conductive vias can be added, so that the occupancy of the vias in the first chip is increased to 25%, and the thermal conductivity of the substrate and the device layer of the first chip is increased from 3-5W/m.k to 15-25W/m.k, so that the downward thermal resistance of the 3D integrated circuit is significantly reduced. It should be noted that the design method of the integrated circuit disclosed in the embodiment of the present disclosure is not only applicable to the 3D integrated circuit in fig. 1, but also applicable to any other integrated circuit with a requirement for enhancing heat dissipation.

It can be seen that the design method of the integrated circuit disclosed in the embodiments of the present disclosure can add the thermal via in the integrated circuit in the design link of the integrated circuit without affecting the existing design, thereby improving the thermal conductivity of the integrated circuit as a whole and improving the heat dissipation performance of the integrated circuit.

The embodiment of the present disclosure also provides a design apparatus for an integrated circuit, as shown in fig. 7, including: a memory 42, a processor 41, and a computer program 43 stored on the memory 42 and operable on the processor 41, wherein when the processor 41 executes the computer program 43, the design method of an integrated circuit provided by the above embodiments is implemented, for example: obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate; grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area; grabbing a target area within the at least one first area, the target area being free of the intermediate metal layer and being located at a central position of the first area; placing a thermally conductive via in the target area.

An embodiment of the present disclosure further provides a computer-readable storage medium, as shown in fig. 8, where a computer program 40 is stored on the computer-readable storage medium, and when executed by a processor, the computer program 40 implements a design method of an integrated circuit provided in the foregoing embodiments, such as: obtaining a layout of an integrated circuit to be designed, wherein the layout comprises: the device comprises a substrate, a plurality of standard units positioned in the substrate, a middle metal layer positioned above the substrate and used for electrically connecting the standard units, and a conductive through hole penetrating through the substrate; grabbing at least one first area in the layout, wherein the standard unit and the conductive through hole are not contained in the first area; grabbing a target area within the at least one first area, the target area being free of the intermediate metal layer and being located at a central position of the first area; placing a thermally conductive via in the target area.

It should be understood that the skilled in the art can change the above sequence of steps without departing from the scope of the disclosure, which is only an alternative embodiment of the disclosure, and is not intended to limit the scope of the disclosure, and any modification, equivalent replacement, and improvement made within the spirit and principle of the disclosure should be included in the scope of the disclosure.

Claims

1. A method of designing an integrated circuit, comprising:

placing a thermally conductive via in the target area.

2. The design method of claim 1, wherein the shape of the first region comprises a square; the shape of the target area includes a square.

3. The design method of claim 2, wherein the first region has a side length between 22 and 30 microns; the target area has a side length of between 4.5 microns and 10 microns.

4. The design method of claim 1, wherein after placing the thermally conductive via in the target area, the method further comprises: and checking the design rule of the heat conduction through hole and the electric conduction through hole.

5. The design method according to claim 1, wherein the layout further comprises: a top metal layer, the target region including the top metal layer;

placing a thermally conductive via within the target area, comprising:

acquiring the network attribute of the top metal layer of the target area;

6. The design method according to claim 5, wherein the layout further comprises at least one pad, the pad being located on a lower surface of the substrate; after placing the thermally conductive vias within the target area, the method further comprises:

7. The design method according to claim 1, wherein the layout further comprises physical units; after placing the thermally conductive vias within the target area, the method further comprises:

8. The design method of any one of claims 1-7, further comprising: checking the design rule of the layout added with the heat conduction through hole; and checking the consistency of the layout added with the heat conduction through hole and the circuit diagram corresponding to the layout.

9. A design apparatus for an integrated circuit, comprising: memory, processor and computer program stored on the memory and executable on the processor, the processor implementing the design method according to any one of claims 1 to 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a computer program which, when being executed by a processor, implements the design method according to any one of claims 1 to 8.