200839938 九、發明說明： 【發明所屬之技術領域3 發明領域 本發明一般係有關於一種半導體裝置，特別是有關於 5 一種具有防潮環之半導體裝置及其製造方法。 t先前技術】 發明背景 一般在半導體裝置之製造技術中，數個半導體於矽晶 除圓等半導體基板上形成行列狀，進一步，沿切割道將此半 10 導體基板切斷，藉此，可獲得分別形成有各半導體元件之 半導體晶片作為半導體裝置。 在此種半導體晶片中’由於在其切斷面’構成半導體 裝置之半導體層、絕緣層或金屬層等露出，故為抑制大氣 中之水份經由此切斷面侵入半導體裝置中，一般係於其周 15 邊部形成具有與半導體裝置中之多層配線構造相同之層構 造之防潮環。 • 【發明内容】 發明概要 發明揭示 20 第1圖係顯示形成於矽基板11上之本發明相關技術之 半導體元件一部份之平面圖，第2圖係顯示包含此半導體元 件之防潮環之部份截面圖。 參照第1圖，於矽基板11上以鏈線所示之切割道劃分成 元件區域11A、11B、11C、11D，各元件區域11A、11B、 5 200839938 lie、11D於防潮環12A、12B、12C、12D内側具有構成各 半導體元件之電路區域13。在圖所示之例中，於元件區域 11A形成電路區域13,同樣之電路區域亦形成於其他元件區 域11B〜11D中任一者。 5 又，在第1圖之結構中，於前述各元件區域11A〜11D， 在對應之防潮環12A〜12D之外側且以鏈線所示之切割道内 侧，為遮斷切割時之龜裂傳導，而形成保護溝部14A〜14D 中之任一個。 是故，在第1圖之平面圖中，藉沿前述鏈線所示之切割 10 道切斷矽基板11，各半導體裝置可以半導體晶片之形式分 離0 第2圖係顯示如此而得之半導體裝置10之截面圖。 參照第2圖，前述半導體元件10形成於形成有元件分離 區域15及電晶體15ΤΪ之矽基板15上，前述電晶體15IY為SiN 15 膜ΠΑ所覆蓋，於前述矽基板15上形成多層配線構造，此多 層配線構造係具有將覆蓋前述電晶體15TY及SiN膜17A，且 以各氧化矽膜構成之層間絕緣膜16A、16B、…、16G間交 互摻雜氮化矽膜17B、17C、…、17F之結構。 在圖中所示之例中，在前述層間絕緣膜16A中由W等構 20 成之通孔圖案16aR對應於前述防潮環12A，接觸前述石夕基 板15之表面而連續形成，又，在前述電路區域13，通孔栓 塞16a接觸覆蓋前述電晶體15IY之擴散區域15a、15b之矽化 物層15c、15d而形成於前述電路區域13。 在前述層間絕緣膜16B中，銅圖案16bR對應於前述防 6 200839938 潮環12A ’接觸前述通孔圖案16aR，以單層鑲嵌法連續形 成’又，在前述電路區域13，Cu配線圖案16b接觸前述W通 - 孔圖案16aR，也是以單層鑲嵌法形成。 v 再者，在前述層間絕緣膜16C中，Cu圖案16cR對應於 5 前述防潮環12A，接觸其下方之前述Cu圖案16bR，以單層 或雙層鑲嵌法連續形成，在前述電路區域13，具有通孔栓 塞之Cu配線圖案16c接觸前述Cu配線圖案16b，以單層或雙 層鑲嵌法形成。 _ 又，在前述層絕緣膜16D中，Cu圖案16dR對應於前述 10 防潮環12A，接觸其下方之前述C11圖型16cR，以單層或雙 層鑲嵌法連續形成，且於前述電路區域13，具有通孔栓塞 之Cu配線圖案16d接觸前述Cu配線圖案16c，也是以單層或 雙層鑲嵌法形成。 在前述層間絕緣膜16E中，Cu圖案16eR對應於前述防 15 潮環12A，接觸其下方之Cu圖案（圖中未示），以雙層鑲嵌法 連續形成，且，在前述電路區域Π，具有通孔栓塞之Cu配 • 線圖案16e接觸前述Cu配線圖案（圖中未示），以雙層鑲喪法 形成。 - 又，在前述層間絕緣膜16F中，Cu圖案16fR對應於前述 ^ 20防潮環12A，接觸其下方之前述Cu圖案16eR，以雙層鑲嵌 法連續形成’在前述電路區域13中，具有通孔栓塞之Cu配 線圖案16fR接觸其下方之對應之Cu配線圖型16e，也是以雙 層鑲嵌法形成。 在前述層間絕緣膜16G中，W圖案16gR對應於前述防 7 200839938 潮環12A，接觸其下方之前述Cu圖案16fR，以鑲嵌法連續 形成，在前述電路區域13中，W通道栓塞i6g接觸前述Cu 配線圖案16f，也是以鑲嵌法形成。 : 在此，應注意前述Cu配線圖案16b〜16f及Cu圖案 5 ：161^〜16汉為1^等之位障金屬膜所覆蓋，前述\¥通孔栓塞 % 16a、16名及〜圖案16aI^、16gR為TiN等阻絕膜所覆蓋。 再者，在前述層間絕緣膜16G上，對應於前述防潮環而 為Ti/TiN構造之密合膜所夹持之八丨圖案18A接觸前述w圖 _ 案16gR而形成’在鈾述通道检塞i6g上，具同樣構造之電極 10 塾18B接觸前述通道栓塞I6g而形成。 前述A1圖形18 A及電極墊丨8 B在前述層間絕緣腠16 上，為以高密度電漿CVD法沉積之氧化矽膜18所覆篸，進 一步於其上形成由SiN膜構成之純化膜19。在前述缺化勝19 及氧化石夕膜18中，形成使前述電極塾丨8B露出之開口鄯 15 19A。 在第2圖之結構中，如箭頭所示，在圖中左侧端鄯中， ® 進行晶片切割機之切割，為阻止此時之龜裂傳導，而於前 述防潮環外側形成先前第1圖所說明之保護溝部丨4 A。 - 另一方面，在第2圖之結構之半導體裝置中，由於_中 20左側端部曝露於大氣，故如第3圖所示，在層間感緣麟 16A〜16F中，水份侵入防潮環12A之外側之部份，此水份對 電路區域13之侵入為前述防潮環π所阻止，因此，有防潮 環12之負荷大，易腐蝕之問題。當防潮環12之一部份虞生 缺陷時，水份便在此部份傳導，而侵入半導體裝置内#。 8 200839938 在第3圖中，以虛線圍住且構成防潮環12AiCu圖案16(^產 生此種缺陷。 此種防潮環12之負％之問題在使用密度低之低介質常 數膜、亦即所謂之Low-K膜作為層間絕緣膜16A〜16F時特別 5 顯著。 第4圖係顯示減輕此種防潮環之負荷之本發明相關技 術之半導體裝置結構。惟，在第4圖中，先前說明之部份附 上同一參照標號，省略說明。 參照第4圖，在第4圖之結構中，前述保護溝部14A形成 10深至到達矽基板15之表面，進一步覆蓋其表面而連續形成 SiN鈍化膜19。 結果，前述層間絕緣膜16A〜16F及層間絕緣膜16G之各 端部連接為SiN鈍化膜所覆蓋，實質減輕對前述防潮環之負 荷，而可期待提高半導體裝置之信賴性。 15 然而，當要形成前述第4圖之構造時，需於由層間絕緣 膜16A〜16G構成之層疊體中形成深溝14A，特別是將光阻圖 案於光罩W案轉料，有圖案轉移精確度產生問題之情形。 又，前述SiN鈍化膜19為儲存有應力之膜，特別是前述 層間絕緣膜16A〜16F為低介質常數膜時，產生密合力降 20 低、易剝離之問題。 亦有考慮以藉高密度電漿CVD法形成之氧化石夕膜形成 此鈍化膜19，特別是若前述層間絕緣膜16A〜16F為有機： 低介質常數膜或含有許多有機基之低介質常數膜時，有= 膜時之氧氣侵餘前述層間絕緣膜之虞，而難以適用此方法。 9 200839938 又’在第4圖之結構中，當前述鈍化膜19由儲存有應用 之SiN膜構成時，切斷時之截斷在前述鈍化膜19傳遞，從防 潮環12A到達内侧，而有半導體裝置之信賴性降低之虞。 專利文獻1:日本專利公開公報2004_47575號 5 專利文獻2 :日本專利公開公報2004-134450號 專利文獻3:日本專利公開公報2〇〇4_79596號 專利文獻4:日本專利公開公報2〇〇3-273〇43號 專利文獻5 :日本專利公開公報2004-119468號 專利文獻6:日本專利公開公報2〇〇5-217411號 10 專利文獻7 :日本專利公開公報2005-260059號 專利文獻8:日本專利公開公報2004-296904號 專利文獻9:日本專利公開公報2〇〇6_114723號 根據一觀點，本發明提供一種半導體裝置，其包含有： 基板；形成於前述基板上，含有多層配線構造之層疊體； 15 於前述層疊體中，包圍形成有活性元件之元件區域並連續 延伸之防潮環；及在前述層疊體中，於前述防潮環外側沿 前述防潮環連續形成，以使前述基板表面露出之保護溝 部。前述層疊體係由具有較Si〇2膜低之介質常數的層間絕 緣膜之疊層構成，前述層疊體上面及前述保護溝部之侧壁 20 面與底面除了前述多層配線構造上之電極墊外，皆以保護 膜連續覆蓋，且於前述保護膜與前述保護溝部側壁面之間 形成以Si及C為主成份之界面膜。 根據另一觀點，本發明提供一種半導體裝置，其包含 有：基板；形成於前述基板上，含有多層配線構造之層疊 10 200839938 體；於前述層疊體中，包圍形成有活性元件之元件區域並 連續延伸之防潮環；及在前述層疊體中，於前述防潮環外 側沿前述防潮環連續形成，以使前述基板表面露出之=護 溝部。於前述層疊體表面第1及第2金屬光罩圖案分別沿前 5 述保護溝部之外緣及内緣延伸。 根據又乃一觀點 个弓X /3致供一種半導體裝置，具包 10 15 20 含有：基板；形成於前述基板上，含有多層配線構造之層 豐體；於則述層疊體中，包圍形成有活性元件之元件區域 並連、、，貝延伸之防潮環，及在前述層疊體中，於前述防潮環 ㈣沿前述_環連續形成，以使前述基板表面露出之保 蒦冓P $述層$體上面除了前述多層配線構造上之電極 墊外，其餘皆為保護膜所覆蓋，前述保護膜在前述保護溝 部内側，連續覆蓋從前述層疊體上面至前述溝部側壁中之 :=:= 部份’前述保護膜在從前述保護溝部之外緣 土面至外側之位置上被去除一部份。 根據本發明，在基板上具有構成 田 體的半導髒壯m Α Θ配線構造之層豐 之深保置中’藉於防潮環外側形成到達基板而形成 部份免二 =1可保護前述防潮環内側之半導體裝置主要 部之至少内辟丁之龜4。此時’藉以保護祺覆蓋此保護溝 半導體元件ί面，可阻止水份從此保護涛邹侧壁面侵入至 疊構=是配線構造以低介質常数層間絕緣膜之層 壁面露出之® π成保護膜知’有侵餘在前述保護溝部侧 層間絕緣膜端面之虞，而根辕本發明，藉以以 11 200839938 y « 5 Si及c為主成份之界面膜覆蓋此側壁面，可避免此保護膜形 成時之溝部侧壁面之侵蝕問題。 又，根據本發明，當於前述層疊體中形成前述保護溝 部時，藉以形成於前述層疊體表面之金屬圖案作為硬式光 罩，進行保護溝部形成，即使為到達矽基板表面之深溝部， 仍可穩定進行所期之保護溝部形成。 根據本發明，藉在前述保護溝部之外側壁面或保護溝 部之外側去除前述保護膜，即可以切割步驟切割前述半導 體裝置時，亦可抑制龜裂在儲存了變形之保護膜中傳導而 10 侵入至半導體裝置内部，而可提高半導體裝置之製造產率。 圖式簡單說明 第1圖係顯示本發明相關技術之半導體晶圓表面一部 份之平面圖。 第2圖係顯示本發明相關技術之半導體裝置一部份之 15 截面圖。 第3圖係顯示本發明另一相關技術之半導體裝置一部 份之截面圖。 第4圖係顯示本發明另一相關技術之半導體裝置一部 份之截面圖。 20 第5圖係顯示本發明第1實施形態之半導體裝置結構之 截面圖。 第6A圖係說明第5圖之半導體裝置的製程者(之一)。 第6B圖係說明第5圖之半導體裝置的製程者(之二）。 第6C圖係說明第5圖之半導體裝置的製程者(之三）。 12 200839938 第6D圖係說明第5圖之半導體裝置的製程者(之四）。 第6E圖係說明第5圖之半導體裝置的製程者(之五）。 第6F圖係說明第5圖之半導體裝置的製程者(之六）。 第7圖係顯示第5圖之半導體裝置之一變形例之截面 5 圖。 第8A圖係顯示本發明第2實施形態之半導體裝置之製 程者（之一）。 第8B圖係顯示本發明第2實施形態之半導體裝置之製 | 程者（之二）。 10 第8C圖係顯示本發明第2實施形態之半導體裝置之製 程者（之三)。 第9圖係顯示本發明第2實施形態之一變形例者。 第10圖係顯示本發明第2實施形態之另一變形例者。 第11圖係顯示本發明第3實施形態之半導體裝置之結 15 構者。 第12圖係顯示第11圖之半導體裝置之一變形例者。 Φ 第13圖係顯示第11圖之半導體裝置之一變形例者。 第14圖係顯示本發明第4實施形態之半導體裝置之結 構者。 20 第15圖係顯示第14圖之半導體裝置之一變形例者。 第16圖係顯示本發明第5實施形態之半導體裝置之結 構者。 L實施方式】 較佳實施例之詳細說明 13 200839938 1 5 第5圖係顯示本發明第1實施形態之半導體裝置2〇之結 構。 參照第5圖，前述半導體裝置20形成於形成有元件分離 區域251及電晶體25Tr之矽基板25上，前述電晶體251Y為SiN 膜27A所覆蓋，於前述矽基板25上覆蓋前述電晶體25Tr及 SiN膜27，而形成層間絕緣膜26Α、26Β、···、26G間交互摻 雜由SiN或Sic構成之蝕刻阻擋膜27B、27C、…、27F而層疊 之結構且具有多層配線構造的層疊體。 • 在圖中所示之例中，在前述層間絕緣膜26A中，由W等 10 構成之通孔圖案26aR對應於防潮環22A，接觸前述矽基板 25之表面而連續形成，在以前述防潮環22A包圍之電路區域 23中，通孔栓塞26a接觸覆蓋前述電晶體25Tr之擴散區域 25a、25b之石夕化物層25c、25d而形成。 再者，在前述層間絕緣膜26B中，由Cu圖案26bR對應 15 • 於前述防潮環22A，接觸前述通孔樣26aR，以單層鑲嵌法 連續形成，在前述電路區域23，Cu配線圖案26b接觸前述W 圖案26a，也是以單層鑲嵌法形成。 又，在前述層間絕緣膜26C中，由Cu圖案26cR對應於 防潮環22A，接觸其下方之前述Cu圖案26bR，以雙層鑲嵌 20 法連續形成，又，在前述電路區域23，具有通孔栓塞之Cu 配線圖案26c接觸前述Cu配線圖案26b，也是以單層或雙層 鑲嵌法形成。 又，在前述層間絕緣膜26D中，Cu圖案26dR對應於前 述防潮環22A，接觸其下方之前述Cu圖案26cR，以單層或 14 200839938 雙層鑲嵌法連續形成，在前述電路區域23，具有通孔栓塞 之Cu配線圖案26d接觸前述Cu配線圖案26c，也是以雙層鑲 . 嵌法形成。 _ 又，在前述層間絕緣膜26E中，Cu圖案26eR對應於前 5述防潮環22A，接觸其下方之前述^^圖案（圖中未示），以雙 # 層鑲嵌法連續形成，在前述電路區域23，具有通孔栓塞之 Cu配線圖案26e接觸前述Qi配線圖案（圖中未示），也是以雙 層鑲嵌法形成。 # 又，在前述層間絕緣膜26F中，Cu圖案26fR對應於前述 10防潮環22A，接觸其下方之前述Cu圖案26eR，以雙層鑲嵌 法連續形成，在前述電路區域23，具有通孔栓塞之Cu配線 圖案26f接觸前述Cu配線圖案26e，也是以雙層鑲嵌法形成。 又，在前述層間絕緣膜26G中，W圖案26gR對應於前 述防潮環22A，接觸其下方之前述Cll圖案26fR，以鑲嵌法 15 連續形成，在前述電路區域23，W通孔栓塞26g接觸前述Cu 配線圖案26f，也是以鑲嵌法形成。 _ 在此，應注意前述Cu配線圖案26b〜26f及Cu圖案 26brR〜26fR為Ta膜或Ta/TaN層疊膜等之位障金屬膜所覆 — 蓋，前述W通孔栓塞26a、26g及W圖案26aR、26gR為TiN等 20 阻絕膜所覆蓋。 又，在前述層間絕緣膜26G上，對應於前述防潮環而為 Ti/TiN構造之密合膜所夾持之Ai圖案28A接觸前述W圖案 26gR而形成，在前述通孔栓塞26g上，相同構造之電極墊 28B接觸别述通孔检塞26g而形成。在圖中所示之例中，前 15 200839938 述層間絕緣膜26G以氧化石夕膜形成。 又’前述A1圖案28A及電極墊28B為在前述層間絕緣膜 26G上以高密度電漿CVD法所沉積之氧化矽膜28所覆蓋，進 一步’在其上面，以電漿CVD法形成由SiN膜構成之鈍化膜 5 29。在前述鈍化膜29及氧化矽膜28中，形成使前述電極墊 28B露出之開口部29A。 前述層間絕緣膜26A〜26F可使用註冊商標Flare或SiLK 等名稱且在市面販售之烴系絕緣膜、有機或無機矽氧烷 膜、或者該等之多孔質膜。該等層間絕緣膜可以電漿Cvd 10法或塗佈法形成。前述層間絕緣膜26A〜26D形成200〜40〇nm 左右之膜厚’前述層間絕緣膜26E、26F形成400〜600nm左 右之膜厚。 此時，在本實施形態中，在前述層疊體中，於前述防 潮環22A之外側，到達前述矽基板25表面之保護溝部24八與 15之鈾之第1圖之保護溝部14A同樣地沿前述防潮環22A連續 形成，前述氧化砍膜28及鈍化膜29連續覆蓋此保護溝部24a 之内壁面、底面及外壁面。 又，前述保護溝部24A係藉對層疊有前述層間絕緣膜 26A〜26G之層疊體實施以光阻圖案為光罩之乾蝕至前述矽 2〇 基板25之表面露出為止而形成。 在本實施形態中’於前述氧化矽膜28與前述保護溝部 24A之内壁面、底面及外壁面間，以電漿cvd法形成 5〜200nm之膜厚之SiC界面膜281。 藉形成此界面膜281 ’於前述保護溝部24a内壁面、底 200839938 面及外壁面形成前述氧化石夕卿時，可抑制露出至前述内 壁面或外壁面之低介質常數層間絕緣膜26a〜26F之損傷。 此外，前述界面膜281之組成不限定Sic膜，即使為以 Si及C為主成份之SiCH膜或SiOC膜、Si〇CH膜等，只要在 5界面膜成膜時，可抑制前述低介質常數層間絕緣犋 26A〜26F之損傷者，便可使用。 當從SiC膜形成前述界面膜281時，提供四甲基石夕燒作 為原料，將此在350〜40(rc之基板溫度中，以激發電裝之電 漿CVD法而形成。 书 10 如此，根據本實施形態，於前述保護溝部24A之表面、 亦即内側侧壁面、底面及外側侧壁面以高密度電衆cvd法 形成前述氧化石夕膜28前，以界面膜281連續覆蓋前述保護溝 部24A之表面，藉此’可抑制形成前述氧化石夕膜辦之前述 保護溝部24A表面之氧基及離子之損傷。由於前述界面膜 15 281之形成係在氧少之條件下進行，故實質上未產生前述層 間絕緣膜26A〜26F之前述保護溝部24A之露出端面的損傷二 又，藉於SiN膜29之正下方形成此氧化_28，可抑制 易儲存應力之SiN之鈍化膜29之剝離。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device having a moisture barrier ring and a method of fabricating the same. BACKGROUND OF THE INVENTION Generally, in a semiconductor device manufacturing technique, a plurality of semiconductors are formed in a matrix on a semiconductor substrate such as a germanium crystal, and further, the semiconductor substrate is cut along a dicing street, thereby obtaining A semiconductor wafer in which each semiconductor element is formed is separately used as a semiconductor device. In such a semiconductor wafer, the semiconductor layer, the insulating layer, the metal layer, and the like which constitute the semiconductor device are exposed at the cut surface thereof, so that the moisture in the atmosphere is prevented from entering the semiconductor device through the cut surface, and is generally A moisture-proof ring having a layer structure identical to the multilayer wiring structure in the semiconductor device is formed at the side portion of the circumference 15 thereof. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a part of a semiconductor element of the related art of the present invention formed on a germanium substrate 11, and FIG. 2 is a view showing a portion of a moisture-proof ring including the semiconductor element. Sectional view. Referring to Fig. 1, the dicing lines indicated by the chain lines are divided into the element regions 11A, 11B, 11C, and 11D on the 矽 substrate 11, and the respective element regions 11A, 11B, 5 200839938 lie, 11D are in the moisture-proof rings 12A, 12B, 12C. Inside, 12D has a circuit region 13 constituting each semiconductor element. In the example shown in the figure, the circuit region 13 is formed in the element region 11A, and the same circuit region is also formed in any of the other device regions 11B to 11D. Further, in the configuration of Fig. 1, in the respective element regions 11A to 11D, on the outer side of the corresponding moisture-proof rings 12A to 12D and on the inner side of the dicing line indicated by the chain line, the crack conduction at the time of cutting is cut off. And any one of the protective groove portions 14A to 14D is formed. Therefore, in the plan view of Fig. 1, the semiconductor substrate can be separated in the form of a semiconductor wafer by cutting 10 turns along the above-mentioned chain lines. The second figure shows the semiconductor device 10 thus obtained. Sectional view. Referring to Fig. 2, the semiconductor element 10 is formed on a germanium substrate 15 on which the element isolation region 15 and the transistor 15 are formed, and the transistor 15IY is covered by a SiN 15 film, and a multilayer wiring structure is formed on the germanium substrate 15. The multilayer wiring structure has an interlayer insulating film 16A, 16B, ..., 16G which covers the transistor 15TY and the SiN film 17A and is formed of a respective yttria film, and is doped with a tantalum nitride film 17B, 17C, ..., 17F. The structure. In the example shown in the figure, the via pattern 16aR formed of the W structure 20 in the interlayer insulating film 16A is formed continuously corresponding to the moisture-proof ring 12A, and is in contact with the surface of the stone substrate 15, and further, in the foregoing In the circuit region 13, the via plug 16a is formed in the circuit region 13 by contacting the vaporization layers 15c, 15d covering the diffusion regions 15a, 15b of the transistor 15IY. In the above-mentioned interlayer insulating film 16B, the copper pattern 16bR corresponds to the aforementioned prevention 6 200839938, the moisture ring 12A' contacts the aforementioned via pattern 16aR, and is continuously formed by a single layer damascene method. Further, in the aforementioned circuit region 13, the Cu wiring pattern 16b contacts the aforementioned The W-pass pattern 16aR is also formed by a single layer damascene method. Further, in the interlayer insulating film 16C, the Cu pattern 16cR corresponds to the aforementioned moisture-proof ring 12A, and the Cu pattern 16bR which is in contact therebelow is continuously formed by a single layer or a double-layer damascene method, and has the above-described circuit region 13 The Cu wiring pattern 16c of the via plug contacts the Cu wiring pattern 16b, and is formed by a single layer or double layer damascene method. Further, in the above-mentioned layer insulating film 16D, the Cu pattern 16dR corresponds to the aforementioned 10 moisture-proof ring 12A, and the aforementioned C11 pattern 16cR which is in contact therebelow is continuously formed by a single layer or double layer damascene method, and in the above-mentioned circuit region 13, The Cu wiring pattern 16d having the via plugs is in contact with the Cu wiring pattern 16c, and is also formed by a single layer or double layer damascene method. In the interlayer insulating film 16E, the Cu pattern 16eR corresponds to the aforementioned anti-15 moisture ring 12A, contacts the underlying Cu pattern (not shown), is continuously formed by a double damascene method, and has a 双层The Cu wiring pattern 16e of the via plug contacts the aforementioned Cu wiring pattern (not shown) and is formed by a two-layer inlay method. Further, in the interlayer insulating film 16F, the Cu pattern 16fR corresponds to the aforementioned moisture-proof ring 12A, and contacts the aforementioned Cu pattern 16eR, and is continuously formed in the circuit region 13 by a double damascene method, and has a through hole. The Cu wiring pattern 16fR of the plug contacts the corresponding Cu wiring pattern 16e below it, and is also formed by a double damascene method. In the foregoing interlayer insulating film 16G, the W pattern 16gR corresponds to the aforementioned tidal ring 12A, and the aforementioned Cu pattern 16fR which is in contact therewith is continuously formed by a damascene method in which the W channel plug i6g contacts the aforementioned Cu. The wiring pattern 16f is also formed by a damascene method. Here, it should be noted that the Cu wiring patterns 16b to 16f and the Cu pattern 5: 161^~16 are covered by a barrier metal film such as 1^, and the above-mentioned \¥ via plugs 16a, 16 and ~ pattern 16aI ^, 16gR is covered by a barrier film such as TiN. Further, on the interlayer insulating film 16G, the gossip pattern 18A held by the adhesion film of the Ti/TiN structure corresponding to the moisture-proof ring contacts the above-mentioned w-figure 16gR to form a 'detection in the uranium channel On the i6g, the electrode 10 塾 18B having the same configuration is formed by contacting the aforementioned channel plug I6g. The A1 pattern 18A and the electrode pad 8B are covered on the interlayer insulating layer 16 by a yttrium oxide film 18 deposited by a high-density plasma CVD method, and a purified film 19 made of a SiN film is further formed thereon. . In the aforementioned defect 19 and the oxidized oxide film 18, an opening 19 15 19A for exposing the electrode 塾丨 8B is formed. In the structure of Fig. 2, as indicated by the arrow, in the left end of the figure, ® performs the cutting of the wafer cutting machine to form the previous first picture on the outer side of the moisture-proof ring in order to prevent the crack conduction at this time. The protective groove portion 丨 4 A is described. On the other hand, in the semiconductor device of the structure of Fig. 2, since the left end portion of the _ middle 20 is exposed to the atmosphere, as shown in Fig. 3, in the interlayer sensation 16A to 16F, the moisture invades the moisture-proof ring. In the portion on the outer side of the 12A, the intrusion of the moisture to the circuit region 13 is prevented by the aforementioned moisture-proof ring π, and therefore, the load of the moisture-proof ring 12 is large and corrosion is problematic. When a portion of the moisture-proof ring 12 is defective, moisture is conducted in this portion and invades the semiconductor device. 8 200839938 In Fig. 3, it is surrounded by a broken line and constitutes a moisture-proof ring 12AiCu pattern 16 (^ such a defect occurs. The problem of the negative % of such moisture-proof ring 12 is the use of a low dielectric constant film having a low density, that is, the so-called The Low-K film is particularly remarkable as the interlayer insulating films 16A to 16F. Fig. 4 is a view showing the structure of a related art semiconductor device for mitigating the load of such a moisture-proof ring. However, in Fig. 4, the previously described portion is shown. Referring to Fig. 4, in the configuration of Fig. 4, the protective groove portion 14A is formed to a depth of 10 to reach the surface of the ruthenium substrate 15, and further covers the surface thereof to continuously form the SiN passivation film 19. As a result, the respective end portions of the interlayer insulating films 16A to 16F and the interlayer insulating film 16G are covered by the SiN passivation film, and the load on the moisture-proof ring is substantially reduced, and the reliability of the semiconductor device can be expected to be improved. When the structure of the fourth embodiment is formed, it is necessary to form the deep trench 14A in the laminate composed of the interlayer insulating films 16A to 16G, and in particular, the photoresist pattern is transferred to the mask W, and the pattern transfer precision is produced. Further, the SiN passivation film 19 is a film in which stress is stored, and in particular, when the interlayer insulating films 16A to 16F are low dielectric constant films, the adhesion force drop is low and easy to be peeled off. The passivation film 19 is formed by a oxidized oxide film formed by a high-density plasma CVD method, in particular, if the interlayer insulating films 16A to 16F are organic: a low dielectric constant film or a low dielectric constant film containing many organic groups, In the case where the oxygen in the film is invaded by the interlayer insulating film, it is difficult to apply the method. 9 200839938 In the structure of Fig. 4, when the passivation film 19 is composed of a SiN film in which the application is applied, when it is cut, The truncation is transmitted to the passivation film 19, and the inside of the moisture-proof ring 12A is reached, and the reliability of the semiconductor device is lowered. Patent Document 1: Japanese Patent Laid-Open Publication No. 2004-47575 No. 5 Patent Document 2: Japanese Patent Laid-Open Publication No. 2004-134450 Document 3: Japanese Patent Laid-Open Publication No. Hei. No. 4-79596 Patent Document 4: Japanese Patent Laid-Open Publication No. Hei No. 3-273-43 Japanese Patent Laid-Open Publication No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. No. Hei. According to one aspect, the present invention provides a semiconductor device including: a substrate; a laminate including a multilayer wiring structure formed on the substrate; 15 in the laminate, surrounding an element region in which an active element is formed and continuous And a moisture-proof ring extending; and the protective layer portion formed on the outer side of the moisture-proof ring along the moisture-proof ring so as to expose the surface of the substrate. The layered system is composed of a laminate of interlayer insulating films having a dielectric constant lower than that of the Si〇2 film, and the surface of the side wall and the bottom surface of the protective layer portion are not limited to the electrode pads of the multilayer wiring structure. The protective film is continuously covered, and an interface film mainly composed of Si and C is formed between the protective film and the side wall surface of the protective groove portion. According to another aspect, the present invention provides a semiconductor device including: a substrate; a laminate 10 200839938 formed on the substrate and having a multilayer wiring structure; and the component region in which the active element is formed is continuous in the laminate And a moisture-proof ring extending; and the laminated body is continuously formed on the outer side of the moisture-proof ring along the moisture-proof ring so that the surface of the substrate is exposed to the groove portion. The first and second metal mask patterns on the surface of the laminate extend along the outer edge and the inner edge of the protective groove portion, respectively. According to another aspect, a bow X/3 is provided for a semiconductor device, and the package 10 15 20 includes: a substrate; a layered body formed on the substrate and having a multilayer wiring structure; and the laminated body is surrounded by the laminated body a moisture-proof ring extending in parallel with the element region of the active element, and extending in the shell, and in the laminated body, the moisture-proof ring (4) is continuously formed along the aforementioned ring, so that the surface of the substrate is exposed. The body is covered with a protective film except for the electrode pad on the multilayer wiring structure, and the protective film continuously covers the inside of the protective layer from the upper surface of the laminated body to the side wall of the groove: =:= part ' The protective film is partially removed from the outer surface of the protective groove portion to the outer side. According to the present invention, in the deep protection of the layered semiconductor structure having the semi-conducting structure of the field body on the substrate, the formation of the portion of the substrate is formed by the outer side of the moisture-proof ring to form a portion of the second layer. The main part of the semiconductor device inside the ring is at least the inside of the turtle 4 . At this time, 'the protective layer covers the semiconductor element of the protective trench, which prevents the moisture from invading into the stacking surface from the side wall of the protective layer. The wiring structure is exposed by the layer surface of the low dielectric constant interlayer insulating film. It is known that there is a gap between the end faces of the interlayer insulating film on the side of the protective groove portion, and the present invention is used to cover the side wall surface with an interface film of 11 200839938 y « 5 Si and c as a main component, thereby avoiding the formation of the protective film. The problem of erosion of the side wall surface of the groove at the time. Further, according to the present invention, when the protective groove portion is formed in the laminate, the metal pattern formed on the surface of the laminate is used as a hard mask to form a protective groove portion, and even if it reaches the deep groove portion of the surface of the substrate, Stabilize the formation of the protection groove. According to the present invention, the protective film is removed on the outer side surface of the protective groove portion or the outer side of the protective groove portion, that is, when the semiconductor device is cut by the cutting step, the crack can be suppressed from being transmitted in the protective film in which the deformation is stored, and 10 is invaded to Inside the semiconductor device, the manufacturing yield of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view showing a portion of a surface of a semiconductor wafer of the related art of the present invention. Fig. 2 is a cross-sectional view showing a portion of a semiconductor device of the related art of the present invention. Fig. 3 is a cross-sectional view showing a part of a semiconductor device of another related art of the present invention. Figure 4 is a cross-sectional view showing a portion of a semiconductor device of another related art of the present invention. Fig. 5 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. Fig. 6A is a diagram showing one of the processes of the semiconductor device of Fig. 5. Fig. 6B is a diagram showing the process of the semiconductor device of Fig. 5 (Part 2). Fig. 6C is a diagram showing the process of the semiconductor device of Fig. 5 (part 3). 12 200839938 Figure 6D is a diagram showing the process of the semiconductor device of Figure 5 (Part 4). Fig. 6E is a diagram showing the process of the semiconductor device of Fig. 5 (Part 5). Fig. 6F is a diagram showing the process of the semiconductor device of Fig. 5 (sixth). Fig. 7 is a cross-sectional view showing a modification of a semiconductor device of Fig. 5. Fig. 8A is a diagram showing one of the processes of the semiconductor device according to the second embodiment of the present invention. Fig. 8B is a diagram showing the manufacture of the semiconductor device according to the second embodiment of the present invention (Part 2). 10C is a process (third) of a semiconductor device according to a second embodiment of the present invention. Fig. 9 is a view showing a modification of the second embodiment of the present invention. Fig. 10 is a view showing another modification of the second embodiment of the present invention. Fig. 11 is a view showing a structure of a semiconductor device according to a third embodiment of the present invention. Fig. 12 is a view showing a modification of the semiconductor device of Fig. 11. Φ Fig. 13 is a view showing a modification of the semiconductor device of Fig. 11. Fig. 14 is a view showing a structure of a semiconductor device according to a fourth embodiment of the present invention. 20 Fig. 15 is a view showing a modification of the semiconductor device of Fig. 14. Fig. 16 is a view showing a structure of a semiconductor device according to a fifth embodiment of the present invention. L. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 13 200839938 1 5 Fig. 5 shows a structure of a semiconductor device 2 according to a first embodiment of the present invention. Referring to Fig. 5, the semiconductor device 20 is formed on the germanium substrate 25 on which the element isolation region 251 and the transistor 25Tr are formed. The transistor 251Y is covered by the SiN film 27A, and the transistor 25Tr is covered on the germanium substrate 25 and In the SiN film 27, a laminate in which the interlayer insulating films 26, 26, 26, 26G are alternately doped with the etching stopper films 27B, 27C, ..., 27F composed of SiN or Sic and has a multilayer wiring structure is formed. . In the example shown in the figure, in the interlayer insulating film 26A, the via pattern 26aR composed of W or the like 10 corresponds to the moisture-proof ring 22A, and is formed continuously in contact with the surface of the ruthenium substrate 25, in the above-mentioned moisture-proof ring. In the circuit region 23 surrounded by 22A, the via plug 26a is formed in contact with the lithofe layers 25c and 25d covering the diffusion regions 25a and 25b of the transistor 25Tr. Further, in the interlayer insulating film 26B, the Cu pattern 26bR corresponds to the above-mentioned moisture-proof ring 22A, contacts the through-hole pattern 26aR, and is continuously formed by a single-layer damascene method. In the circuit region 23, the Cu wiring pattern 26b contacts. The aforementioned W pattern 26a is also formed by a single layer damascene method. Further, in the interlayer insulating film 26C, the Cu pattern 26cR corresponds to the moisture-proof ring 22A, and the Cu pattern 26bR which is in contact therebelow is continuously formed by the double-layer damascene 20 method, and has a via plug in the circuit region 23 The Cu wiring pattern 26c is in contact with the Cu wiring pattern 26b, and is also formed by a single layer or double layer damascene method. Further, in the interlayer insulating film 26D, the Cu pattern 26dR corresponds to the moisture-proof ring 22A, and the Cu pattern 26cR which is in contact therebelow is formed continuously by a single layer or 14 200839938 double-layer damascene method, and has a pass in the circuit region 23 The Cu wiring pattern 26d of the via plug contacts the Cu wiring pattern 26c, and is also formed by a two-layer mounting method. Further, in the interlayer insulating film 26E, the Cu pattern 26eR corresponds to the first five-described moisture-proof ring 22A, and contacts the underlying pattern (not shown), and is continuously formed by a double-layer mosaic method in the above-mentioned circuit. In the region 23, the Cu wiring pattern 26e having the via plug is in contact with the aforementioned Qi wiring pattern (not shown), and is also formed by a two-layer damascene method. Further, in the interlayer insulating film 26F, the Cu pattern 26fR corresponds to the 10 moisture-proof ring 22A, and the Cu pattern 26eR which is in contact therebelow is continuously formed by a double-layer damascene method, and has a via plug in the circuit region 23 The Cu wiring pattern 26f is in contact with the Cu wiring pattern 26e, and is also formed by a two-layer damascene method. Further, in the interlayer insulating film 26G, the W pattern 26gR corresponds to the moisture-proof ring 22A, and the C11 pattern 26fR that is in contact therebelow is formed continuously by the damascene method 15, in which the W-via plug 26g contacts the Cu. The wiring pattern 26f is also formed by a damascene method. Here, it is to be noted that the Cu wiring patterns 26b to 26f and the Cu patterns 26brR to 26fR are covered by a barrier metal film such as a Ta film or a Ta/TaN laminated film, and the W through hole plugs 26a, 26g and W patterns are used. 26aR and 26gR are covered by 20 barrier films such as TiN. Further, in the interlayer insulating film 26G, the Ai pattern 28A sandwiched by the Ti/TiN structure adhesion film corresponding to the moisture-proof ring is formed in contact with the W pattern 26gR, and the same structure is formed on the via plug 26g. The electrode pad 28B is formed in contact with a through-hole check plug 26g. In the example shown in the figure, the interlayer insulating film 26G of the first 15 200839938 is formed of an oxidized stone film. Further, the aforementioned A1 pattern 28A and the electrode pad 28B are covered by the yttrium oxide film 28 deposited by the high-density plasma CVD method on the interlayer insulating film 26G, and further formed thereon by the plasma CVD method. A passivation film 5 29 is formed. In the passivation film 29 and the yttrium oxide film 28, an opening portion 29A through which the electrode pad 28B is exposed is formed. As the interlayer insulating films 26A to 26F, a hydrocarbon-based insulating film, an organic or inorganic siloxane film, or a porous film which is commercially available under the names of Flare or SiLK can be used. The interlayer insulating film can be formed by a plasma Cvd 10 method or a coating method. The interlayer insulating films 26A to 26D are formed to have a film thickness of about 200 to 40 Å. The interlayer insulating films 26E and 26F have a film thickness of about 400 to 600 nm. In the present embodiment, in the laminate, the protective groove portion 24 that reaches the surface of the ruthenium substrate 25 on the outer side of the moisture-proof ring 22A is similar to the protective groove portion 14A of the uranium of FIG. The moisture-proof ring 22A is continuously formed, and the oxidized dicing film 28 and the passivation film 29 continuously cover the inner wall surface, the bottom surface, and the outer wall surface of the protective groove portion 24a. Further, the protective groove portion 24A is formed by laminating a laminate in which the interlayer insulating films 26A to 26G are laminated with a photoresist pattern as a mask to the surface of the substrate 25 to be exposed. In the present embodiment, a SiC interface film 281 having a film thickness of 5 to 200 nm is formed between the inner surface, the bottom surface and the outer wall surface of the ruthenium oxide film 28 and the protective groove portion 24A by a plasma cvd method. When the interface film 281' is formed on the inner wall surface of the protective groove portion 24a and the bottom surface of the bottom surface of the protective layer portion 24a and the outer wall surface, the low dielectric constant interlayer insulating film 26a to 26F exposed to the inner wall surface or the outer wall surface can be suppressed. damage. Further, the composition of the interface film 281 is not limited to the Sic film, and even if it is a SiCH film or a SiOC film or a Si〇CH film mainly composed of Si and C, the low dielectric constant can be suppressed as long as the film is formed on the 5 interface film. The damage of the interlayer insulating defects 26A to 26F can be used. When the interface film 281 is formed from the SiC film, tetramethyl cerium is provided as a raw material, and this is formed by a plasma CVD method of 350 to 40 (the substrate temperature of rc is excited by electrification). According to the present embodiment, the protective groove portion 24A is continuously covered by the interface film 281 before the oxide oxide film 28 is formed on the surface of the protective groove portion 24A, that is, the inner side wall surface, the bottom surface, and the outer side wall surface by a high-density electric cvd method. The surface of the surface of the protective groove portion 24A of the oxidized stone film can be inhibited from being damaged by the formation of the oxidized stone portion 24A. Since the formation of the interface film 15 281 is performed under conditions of low oxygen, substantially no The damage of the exposed end faces of the protective trench portions 24A of the interlayer insulating films 26A to 26F is generated. Further, by forming the oxides 28 directly under the SiN film 29, the peeling of the passivation film 29 of the SiN which is easy to store stress can be suppressed.
在圖中所示之例中，圖中，左端被切割，端面露出大 20氣，而大氣中之水分主要在前述保護溝部24Λ中為前述SiN 鈍化膜29所阻止，而大幅減輕防潮環22八之負荷。 以下，參照第6A圖〜第6G圖，說明前述半導體裝置2〇 之製程。 參照第6A圖，於形成有活性元件25Tr之矽基板乃上形 17 200839938 成層疊有前述層間絕緣膜26A〜26G之層疊體’在前述層疊 體中，對應於前述防潮環22A而形成層疊有W或Cu圖案 26aR〜26gR之構造，於最上部形成A1圖案28A。又，在層疊 體中，對應於前述電路區域23中之多層配線構造，形成層 5 疊有\¥或(：\!圖案26a〜26g之構造，在第6B圖之步驟中，於前 述防潮環22A外側，以將CF系氣體及〇2、At·等之混合氣體 作為蝕刻氣體之之乾蝕，形成保護溝部24A，而使前述矽基 板25露出。在第6B圖之步驟中，前述乾蝕步驟以在前述層 疊體表面中去除前述保護溝部24A之形成區域，以光阻罩保 1〇 護之狀態下實施。 在前述第6B圖之步驟中，隨著前述保護溝部24A之形 成，前述層間絕緣膜26A〜26F在前述保護溝部24A曝露於大 氣中，雖然前述層間絕緣膜26A〜26F在切割前之狀態，但 在前述防潮環22A之外側吸濕，而在第6C圖之步驟中，將 15前述第6B圖之構造脫水處理，進一步於前述第6B圖之構造 上以先前說明之電漿CVD法，將前述Sic膜281以先前說明 之膜厚形成。當前述Sic膜281之膜厚在5nm以下時，無法獲 得W述SiC膜281之界面膜之效果，當前膜之膜厚在 200nm以上時，處理時間不需太長。 2〇 接著’在第6D圖之步驟中，於前述第6C圖之構造上， 使用石夕院及氧作為原料，以7〇OW左力之電漿功率 ，在400它 之基板皿&下，一面施加4kw左右之基板偏壓，一面形成 1200 15G0nm之膜厚之前述氧化石夕膜％，進一步，在第 ®之步驟中’於前述第6D圖之構造上，使用魏及氨作為 18 200839938 原料’在400C之基板溫度下，以750W左右之電漿:功率， 形成500nm之膜厚之鈍化膜29。 進一步，在第6F圖之步驟中，於前述siN鈍化膜29中形 成使前述電極墊28B露出之開口部29A。 5 在第6F圖之步驟後，藉沿第1圖之切割道，將前述石夕晶 圓切割，可獲得第5圖之半導體裝置20。 此外，當於前述SiN鈍化膜29獲得足夠之密合性時，於 形成前述保護溝部24A前，形成前述氧化矽膜28，對應於前 述保護溝部24A，形成到達基板25之溝後，如第7圖所示， 10亦可在前述保護溝部24A直接接觸前述界面膜281而形成 SIN鈍化膜29。 [第2實施形態] 接著，參照第8A圖〜第8C圖，說明本發明第2實施形態。 其中’在第8A圖〜第8C圖中，對應於先前說明之部份 15 的部份附上同一參照標號，省略說明。 在之前之實施形態中。在第6B圖之步驟中，以乾钱形 成前述保護溝部24A係使用光阻製程，而若要形成如此深之 保護溝部24A時，乾蝕之時間增長，特別是層間絕緣膜數多 之半導體裝置中，產生光阻圖案無法承受長時間之乾#之 20 問題。 本實施形態係假設此種多層配線構造中之層間絕緣膜 數多，前述保護溝部24A之形成需長時間之情形者，如第8A 圖所示，在前述最上層之氧化矽膜26G上，為劃分前述保婼 溝部24A之形成區域，乃使用同一光罩，同時形成前述乂 19 200839938 圖案28A及28B與A1圖案28C及28D，以此A1圖案28C及28D 為硬式光罩，將前述層間絕緣膜26A〜26G之層疊體在前述 - 圖案28C及28D間乾姓，而形成前述保護溝部24A。 . 在本實施形態中，在第8B圖之步驟中，將前述第8A圖 5 之構造脫水處理後，與前述之第6C圖之步驟同樣地形成前 ‘ 述界面膜281，進一步，在第8C圖之步驟中，前述鈍化膜29 與前述第6E圖之步驟同樣地形成於前述界面膜281上。此 外，第8C圖顯示半導體裝置切割之狀態。 Φ 根據此結構，如先前所說明，前述保護溝部24A穩定地 10 形成，而可避免形成前述保護溝部24A之乾蝕製程在單邊進 行，使防潮環22A露出等之問題。 在第8A圖〜第8C圖中，說明了 SiN鈍化膜29直接接觸前 述界面膜281之情形，本實施形態不限於此特定之情形，在 前述界面膜281與SiN膜29間存在以高密度電漿CVD法形成 15且與前述氧化矽膜28同樣之氧化矽膜存在時亦同樣有效。 如此’即使形成前述A1圖案28C及28D，光罩片數亦不 ® 增加，半導體裝置之製程不致複雜。 第9圖顯示前述第8A圖之變形例。 參知弟9圖’在本實施形態中，前述A1圖案28A兼用第 • 20 8(A)圖之A1圖案28D，藉此，在第9圖中，如箭頭貨所示， 可使晶片尺寸較第8(A)圖減少。 第10圖係顯示前述第8A圖之另一變形例。 參照第ίο圖，在本實施形態中，於前述保護溝部24A 外侧形成由Cii或W圖案26Ap〜26Bp之層疊形成且與前述防 20 200839938 潮環22A相同之另一防潮環22B，前述A1圖案28C形成作為 前述防潮環22B之最上部圖案。 此結構亦可藉以前述A1圖案28A及28C作為光罩，進行 . 乾蝕，而可正確地控制前述保護溝部24A之形狀。 5 此另一防潮環228可與前述防潮環22A同樣地形成，步 驟數不致增加。又，因防潮環較前述保護溝部24A位於更外 侧’界面傳導之龜裂因此追加之防潮環構造，而可抑制其 進行。 • [第3實施形態] 10 第11圖係顯示本發明第3實施形態之半導體裝置40之 結構，其中，圖中對應先前所說明之部份的部份附上相同 之參照標號，省略說明。 參照第11圖，在本實施形態中，前述SiN鈍化膜29直接 覆蓋前述保護溝部24A之内側侧壁面及底面，而在前述鈍化 15 膜29中，覆蓋前述溝部24A之外侧側壁面之部份係藉使用將 形成前述溝部24A所用之光罩資料於切割道方向稍微偏離 ® 而形成之光罩圖案，進行與形成前述溝部24A相同之乾餘步 驟而予以去除。此乾餘步驟之結果，在第11圖之例中，於 ， 前述保護溝部24A之外側側壁面形成段部24a。 • 20 藉此結構，將前述半導體裝置從切割步驟分離時，可 使用儲存了變形之SiN鈍化膜29，阻止侵入至1防潮環22A 内側之電路區域。 又，在本實施形態中，與使前述電極墊28B露出之開口 部29 A之形成步驟同時地進行前述保護溝部22A之SiN鈍化 21 200839938 膜29之去除步驟，藉此，可避免光罩片數之增加。此時， 月述開口部29A中，蝕刻係在前述電極墊22B露出之時間點 實質停止，僅在保護溝部24A之外側側壁面進行蝕刻。 在第11圖之例中，前述層間絕緣膜26A〜26F由氧化石夕 5膜構成，前述SiN鈍化膜29在前述保護溝部24A中與前述層 間絕緣膜26A〜26F直接接觸，而如先前第5圖或第7圖所說 明，前述層間絕緣膜26A〜26F為較Si〇2之介質常數低之低介 質常數膜時，在前述保護溝部24A中，宜於前述SiN鈍化膜 29與保護溝部表面間存在氧化矽膜28與界面膜281。 10 第12圖係前述第11圖之一變形，顯示於前述保護溝部 24A之外侧侧壁面一部份殘留前述SiN膜之情形。 本實施形態為亦包含此種情形者。 又，第13圖係前述第11圖之另一變形例，顯示當蝕刻 前述保護溝部24A外側之側壁面時，殘留SiN鈍化膜29之一 15 部份而形成突出部之情形。 本實施形態係亦包含此種情形者。 第14圖係顯示本發明第4實施形態之半導體裝置60之 結構。 參照第14圖，在本實施形態中，前述SiN純化膜29連續 20 覆蓋前述保護溝部24A之内側側壁面、底面及外側側壁面， 在前述層間絕緣膜26A〜26G之層疊體表面中，在前述溝部 24A之外側，開口部29B與前述開口部29A同時地連續形 成，而包圍前述保護溝部24A。 藉此結構，在前述半導體裝置之切割步驟中’即使於 22 200839938 前述SiN鈍化膜29產生龜裂，龜裂傳導為前述開口部29b所 阻止，而不致侵入至防潮環22A内侧之電路區域。 第14圖顯示前述半導體裝切割前之狀態，可知從前述 開口部29B，在前述層疊體中之前述保護溝部24A外側之部 5 份產生水份之侵入。此部份於切割時亦曝露於大氣中，而 使水份侵入，而在前述保護溝部24A之内側，藉前述SiN鈍 化膜29阻止水份之侵入，大幅減輕防潮環22A之負荷。 在第14圖之例中，前述層間絕緣膜26A〜26F由氧化矽 膜構成，前述SiN鈍化膜29在前述保護溝部24A中與前述層 10間絕緣膜26A〜261?直接接觸，而如先前第5圖或第7圖所說 明’前述層間絕緣膜26A〜26F為較Si02之介質常數低之低介 質常數膜時，在前述保護溝部24A中，宜於前述SiN鈍化膜 29與保護溝部表面間存在氧化石夕膜28與界面膜281或界面 膜 281 〇 15 第15圖係前述第丨4圖之一變形例，在前述層疊體上， 對應前述開口部29C，A1圖案28E與前述A1圖案28A及28B 同時地形成，而連續包圍前述保護溝部24A。 在本實施形態中，形成前述開口部29C時，由於於該部 伤形成前述A1圖案28E，故形成前述開口部29C之乾蚀在此 20 A1圖案29C停止，而不致侵入至層疊體内部。 又，在前述層疊體中，前述保護溝部外側之部份在切 割前之狀態下不產生水份之侵入。 [第5實施形態] 弟15圖係顯示本發明第5實施形態之半導體裝置8〇之 23 200839938 結構。惟，圖中對應於先前說明之部份的部份附上相同之 參照標號，省略說明。 • 參照第15圖，在本實施形態中，於石夕基板25上以層間 _ 絕緣膜26A〜26G之層疊而形成之層疊體中，形成於前述防 5 潮環22A外側之保護溝部24A以SiN純化膜29連續覆蓋，進 - 一步，在此鈍化膜29上形成水溶性樹脂等之樹脂層3〇，以 填充前述保護溝部24A。 在本實施形態中，由於在形成此樹脂層30之狀態下實 φ 施矽晶圓之切割，故龜裂之能量為此樹脂層30所吸收，而 10 可抑制龜裂傳達至電路部份23。 此外，此樹脂層30不限於第15圖之結構，先前所說明 之所有實施形態皆可適用。 以上，就較佳實施形態說明了本發明，本發明不限於 此特定之實施形態，在申請專利範圍記載之要旨内，可進 15 行各種變形及變更。 【圖式簡單説明】 ^ 第1圖係顯示本發明相關技術之半導體晶圓表面一部 份之平面圖。 . 第2圖係顯示本發明相關技術之半導體裝置一部份之 20 截面圖。 第3圖係顯示本發明另一相關技術之半導體裝置一部 份之截面圖。 第4圖係顯示本發明另一相關技術之半導體裝置一部 份之截面圖。 24 200839938 第5圖係顯示本發明第1實施形態之半導體裝置結構之 截面圖。 - 第6A圖係說明第5圖之半導體裝置的製程者(之一）。 . 第6B圖係說明第5圖之半導體裝置的製程者(之二）。 5 第6C圖係說明第5圖之半導體裝置的製程者(之三）。 • 第6D圖係說明第5圖之半導體裝置的製程者(之四）。 第6E圖係說明第5圖之半導體裝置的製程者(之五）。 第6F圖係說明第5圖之半導體裝置的製程者(之六）。 • 第7圖係顯示第5圖之半導體裝置之一變形例之截面 10 圖。 第8A圖係顯示本發明第2實施形態之半導體裝置之製 程者（之一）。 第8B圖係顯示本發明第2實施形態之半導體裝置之製 程者（之二）。 15 第8C圖係顯示本發明第2實施形態之半導體裝置之製 程者（之三）。 • 第9圖係顯示本發明第2實施形態之一變形例者。 第10圖係顯示本發明第2實施形態之另一變形例者。 . 第11圖係顯示本發明第3實施形態之半導體裝置之結 、 20 構者。 第12圖係顯示第11圖之半導體裝置之一變形例者。 第13圖係顯示第11圖之半導體裝置之一變形例者。 第14圖係顯示本發明第4實施形態之半導體裝置之結 構者。 25 200839938 第15圖係顯示第14圖之半導體裝置之一變形例者。 第16圖係顯示本發明第5實施形態之半導體裝置之結 構者。 【主要元件符號說明】In the example shown in the figure, in the figure, the left end is cut, the end face is exposed to a large gas, and the moisture in the atmosphere is mainly blocked by the SiN passivation film 29 in the protective groove portion 24, and the moisture-proof ring 22 is greatly reduced. The load. Hereinafter, the process of the semiconductor device 2A will be described with reference to FIGS. 6A to 6G. Referring to Fig. 6A, the substrate in which the active element 25Tr is formed is formed in a shape of a substrate. The layered product in which the interlayer insulating films 26A to 26G are laminated is formed in the laminated body in accordance with the moisture-proof ring 22A. Or the structure of the Cu patterns 26aR to 26gR forms the A1 pattern 28A at the uppermost portion. Further, in the laminated body, corresponding to the multilayer wiring structure in the circuit region 23, the layer 5 is formed with a structure of \¥ or (:\! patterns 26a to 26g, and in the step of FIG. 6B, the aforementioned moisture-proof ring On the outer side of 22A, dry etching is performed by using a CF gas and a mixed gas of 〇2, At, etc. as an etching gas to form the protective groove portion 24A, and the ruthenium substrate 25 is exposed. In the step of FIG. 6B, the aforementioned dry etching The step of removing the formation region of the protective groove portion 24A on the surface of the laminate is carried out in a state where the photoresist mask is protected. In the step of FIG. 6B, the interlayer is formed along with the formation of the protective groove portion 24A. The insulating films 26A to 26F are exposed to the atmosphere in the protective groove portion 24A, and the interlayer insulating films 26A to 26F are in a state before cutting, but are moisture-absorbed on the outer side of the moisture-proof ring 22A, and in the step of FIG. 6C, The structural dehydration treatment of the foregoing Fig. 6B is further carried out by the plasma CVD method described above in the above-described structure of Fig. 6B, and the Sic film 281 is formed by the film thickness described above. When the film thickness of the Sic film 281 is When it is below 5nm, it cannot The effect of the interface film of the SiC film 281 is obtained. When the film thickness of the current film is 200 nm or more, the processing time does not need to be too long. 2〇 Then, in the step of FIG. 6D, in the structure of the above FIG. 6C, Using Shi Xiyuan and oxygen as raw materials, using a plasma power of 7 〇 OW left force, a substrate bias of about 4 kw was applied under 400 substrates and under the surface, and the oxidized stone having a film thickness of 1200 15 G0 nm was formed on one side.约%%, further, in the step of the step of 'in the above-mentioned 6D diagram, using Wei and ammonia as the 18 200839938 raw material' at a substrate temperature of 400C, with a plasma of about 750W: power, forming 500nm Further, in the step of FIG. 6F, an opening portion 29A for exposing the electrode pad 28B is formed in the SiN passivation film 29. 5 After the step of FIG. 6F, by the first figure The dicing street is diced to obtain the semiconductor device 20 of Fig. 5. Further, when sufficient adhesion is obtained in the SiN passivation film 29, the oxidation is formed before the formation of the protective groove portion 24A. The diaphragm 28 corresponds to the aforementioned protection groove After forming the groove reaching the substrate 25, as shown in Fig. 7, the SIN passivation film 29 may be formed by directly contacting the interface film 281 in the protective groove portion 24A. [Second embodiment] Next, reference is made to the eighth embodiment. In the second embodiment, the second embodiment of the present invention will be described. In the eighth to eighth embodiments, the same reference numerals will be given to the portions corresponding to the portions 15 described above, and the description will be omitted. In the step of Fig. 6B, the protective groove portion 24A is formed by dry money using a photoresist process, and when such a deep protective groove portion 24A is formed, the time of dry etching increases, in particular, the number of interlayer insulating films is large. In the semiconductor device, the photoresist pattern is not able to withstand the problem of a long time. In the present embodiment, it is assumed that the number of interlayer insulating films in the multilayer wiring structure is large, and the formation of the protective groove portion 24A takes a long time, as shown in Fig. 8A, on the uppermost yttrium oxide film 26G. The formation region of the protective groove portion 24A is divided by the same mask, and the patterns 28A and 28B and the A1 patterns 28C and 28D are formed at the same time, and the A1 patterns 28C and 28D are hard masks, and the interlayer insulating film is formed. The laminate of 26A to 26G is formed between the above-described patterns 28C and 28D to form the protective groove portion 24A. In the present embodiment, in the step of Fig. 8B, after the structure of Fig. 8A and Fig. 5 is dehydrated, the interface film 281 is formed in the same manner as the step of Fig. 6C, and further, in the eighth In the step of the drawing, the passivation film 29 is formed on the interface film 281 in the same manner as the step of the sixth embodiment. Further, Fig. 8C shows the state in which the semiconductor device is diced. According to this configuration, as described earlier, the protective groove portion 24A is stably formed 10, and the problem that the dry etching process for forming the protective groove portion 24A is performed on one side and the moisture-proof ring 22A is exposed is avoided. In the case of the 8A to 8C, the case where the SiN passivation film 29 is in direct contact with the interface film 281 is described. The present embodiment is not limited to this specific case, and there is a high density between the interface film 281 and the SiN film 29. The slurry CVD method 15 is also effective in the presence of the ruthenium oxide film similar to the ruthenium oxide film 28. Thus, even if the A1 patterns 28C and 28D are formed, the number of masks is not increased, and the process of the semiconductor device is not complicated. Fig. 9 shows a modification of the above Fig. 8A. In the present embodiment, the A1 pattern 28A also uses the A1 pattern 28D of the Fig. 20 (A), whereby in Fig. 9, as shown by the arrow, the wafer size can be made smaller. Figure 8(A) is reduced. Fig. 10 is a view showing another modification of the aforementioned Fig. 8A. Referring to Fig. 00, in the present embodiment, another moisture-proof ring 22B formed by laminating Cii or W patterns 26Ap to 26Bp and being the same as the above-mentioned anti-20 200839938 moisture ring 22A is formed outside the protective groove portion 24A, and the aforementioned A1 pattern 28C is formed. The uppermost pattern as the aforementioned moisture-proof ring 22B is formed. In this configuration, the A1 patterns 28A and 28C can be used as a mask to perform dry etching, and the shape of the protective groove portion 24A can be accurately controlled. 5 This other moisture-proof ring 228 can be formed in the same manner as the aforementioned moisture-proof ring 22A, and the number of steps is not increased. Further, since the moisture-proof ring is located on the outer side of the protective groove portion 24A, the crack is transmitted at the interface, so that the moisture-proof ring structure is added, and the progress can be suppressed. [Embodiment 3] FIG. 11 is a view showing a configuration of a semiconductor device 40 according to a third embodiment of the present invention, and the same reference numerals are attached to the portions in the drawings, and the description thereof will be omitted. Referring to Fig. 11, in the present embodiment, the SiN passivation film 29 directly covers the inner side wall surface and the bottom surface of the protective groove portion 24A, and the passivation 15 film 29 covers the outer side wall surface of the groove portion 24A. The reticle pattern formed by slightly forming the reticle material for forming the groove portion 24A in the scribe line direction is removed by the same dry steps as the formation of the groove portion 24A. As a result of the remaining steps, in the example of Fig. 11, the segment side portion 24a is formed on the outer side wall surface of the protective groove portion 24A. According to this configuration, when the semiconductor device is separated from the dicing step, the SiN passivation film 29 in which the deformation is stored can be used to prevent entry into the circuit region inside the moisture-proof ring 22A. Further, in the present embodiment, the step of forming the opening 29A for exposing the electrode pad 28B is performed simultaneously with the step of removing the SiN passivation 21 200839938 of the protective groove portion 22A, thereby preventing the number of the masks from being removed. Increase. At this time, in the opening portion 29A of the month, the etching is substantially stopped at the time when the electrode pad 22B is exposed, and etching is performed only on the outer side wall surface of the protective groove portion 24A. In the example of Fig. 11, the interlayer insulating films 26A to 26F are made of a oxidized oxide oxide film, and the SiN passivation film 29 is in direct contact with the interlayer insulating films 26A to 26F in the protective groove portion 24A, as in the previous fifth. As shown in FIG. 7 and FIG. 7, when the interlayer insulating films 26A to 26F are low dielectric constant films having a dielectric constant lower than that of Si〇2, it is preferable that the protective trench portion 24A is between the SiN passivation film 29 and the surface of the protective trench portion. The ruthenium oxide film 28 and the interface film 281 are present. 10 Fig. 12 is a view showing a modification of the eleventh embodiment, showing a state in which the SiN film remains in a part of the outer side wall surface of the protective groove portion 24A. This embodiment also includes such a case. Further, Fig. 13 is a view showing another modification of the eleventh embodiment, showing a case where one of the portions of the SiN passivation film 29 is left to form a projection when the side wall surface outside the protective groove portion 24A is etched. This embodiment also includes such a case. Fig. 14 is a view showing the structure of a semiconductor device 60 according to a fourth embodiment of the present invention. With reference to Fig. 14, in the present embodiment, the SiN purification film 29 continuously covers the inner side wall surface, the bottom surface, and the outer side wall surface of the protective groove portion 24A, and the surface of the laminated body of the interlayer insulating films 26A to 26G is On the outer side of the groove portion 24A, the opening portion 29B is continuously formed simultaneously with the opening portion 29A, and surrounds the protective groove portion 24A. With this configuration, in the dicing step of the semiconductor device, even if the SiN passivation film 29 is cracked, the crack conduction is prevented by the opening portion 29b without intruding into the circuit region inside the moisture-proof ring 22A. Fig. 14 is a view showing a state before the semiconductor package is cut, and it is understood that moisture is intruded from the opening portion 29B in the outer portion of the protective groove portion 24A in the laminate. This portion is also exposed to the atmosphere during cutting, and the water is intruded, and the inside of the protective groove portion 24A prevents the intrusion of moisture by the SiN passivation film 29, and the load of the moisture-proof ring 22A is greatly reduced. In the example of Fig. 14, the interlayer insulating films 26A to 26F are made of a hafnium oxide film, and the SiN passivation film 29 is in direct contact with the interlayer insulating film 26A to 261 in the protective trench portion 24A. 5 or 7, when the interlayer insulating films 26A to 26F are low dielectric constant films having a lower dielectric constant than SiO 2 , it is preferable that the protective trench portion 24A is present between the SiN passivation film 29 and the surface of the protective trench portion. The oxidized stone film 28 and the interface film 281 or the interface film 281 〇 15 Fig. 15 is a modification of the above-mentioned fourth embodiment, in which the opening portion 29C, the A1 pattern 28E and the A1 pattern 28A are 28B is formed simultaneously, and continuously surrounds the aforementioned protective groove portion 24A. In the present embodiment, when the opening portion 29C is formed, the A1 pattern 28E is formed by the portion of the opening portion 29C. Therefore, the dry etching forming the opening portion 29C stops at the 20 A1 pattern 29C without invading the inside of the laminated body. Further, in the laminate, the portion outside the protective groove portion does not invade moisture in a state before cutting. [Fifth Embodiment] Fig. 15 shows a structure of a semiconductor device 8 according to a fifth embodiment of the present invention. It is to be noted that the same reference numerals are attached to the parts of the drawings which are the same as In the laminated body in which the interlayer-insulating films 26A to 26G are laminated on the Shih-hsing substrate 25, the protective groove portion 24A formed outside the anti-5 moisture ring 22A is SiN. The purification film 29 is continuously covered, and a resin layer 3 of a water-soluble resin or the like is formed on the passivation film 29 to fill the protective groove portion 24A. In the present embodiment, since the wafer is cut by the actual φ in the state in which the resin layer 30 is formed, the energy of the crack is absorbed by the resin layer 30, and the crack is transmitted to the circuit portion 23 by 10 . Further, the resin layer 30 is not limited to the structure of Fig. 15, and all of the embodiments described above are applicable. The present invention has been described with reference to the preferred embodiments. The present invention is not limited to the specific embodiments, and various modifications and changes can be made without departing from the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS ^ Fig. 1 is a plan view showing a part of a surface of a semiconductor wafer of the related art of the present invention. Fig. 2 is a cross-sectional view showing a portion of a semiconductor device of the related art of the present invention. Fig. 3 is a cross-sectional view showing a part of a semiconductor device of another related art of the present invention. Figure 4 is a cross-sectional view showing a portion of a semiconductor device of another related art of the present invention. 24 200839938 Fig. 5 is a cross-sectional view showing the structure of a semiconductor device according to a first embodiment of the present invention. - Fig. 6A is a diagram showing one of the processes of the semiconductor device of Fig. 5. Fig. 6B is a diagram showing the process of the semiconductor device of Fig. 5 (Part 2). 5 Fig. 6C is a diagram showing the process of the semiconductor device of Fig. 5 (Part 3). • Fig. 6D is a diagram showing the process of the semiconductor device of Fig. 5 (Part 4). Fig. 6E is a diagram showing the process of the semiconductor device of Fig. 5 (Part 5). Fig. 6F is a diagram showing the process of the semiconductor device of Fig. 5 (sixth). • Fig. 7 is a cross-sectional view showing a modification of one of the semiconductor devices of Fig. 5. Fig. 8A is a diagram showing one of the processes of the semiconductor device according to the second embodiment of the present invention. Fig. 8B is a diagram showing the process of the semiconductor device according to the second embodiment of the present invention. Fig. 8C is a diagram showing the process of the semiconductor device according to the second embodiment of the present invention (part 3). Fig. 9 is a view showing a modification of the second embodiment of the present invention. Fig. 10 is a view showing another modification of the second embodiment of the present invention. Fig. 11 is a view showing a structure and a structure of a semiconductor device according to a third embodiment of the present invention. Fig. 12 is a view showing a modification of the semiconductor device of Fig. 11. Fig. 13 is a view showing a modification of the semiconductor device of Fig. 11. Fig. 14 is a view showing a structure of a semiconductor device according to a fourth embodiment of the present invention. 25 200839938 Figure 15 shows a modification of the semiconductor device of Figure 14. Fig. 16 is a view showing a structure of a semiconductor device according to a fifth embodiment of the present invention. [Main component symbol description]
10…半導體裝置 11八〜110...元件區域 12A...防潮環 12B...防潮環 12C…防潮環 12D...防潮環 13...電區域t 14A...保護溝部 15…半導體基板 15Tn..電晶體 15a...擴散區域 15b...擴散區域 15c…石夕化物層 15d...矽化物層 16A〜16G...層間絕緣膜 16aR…通孔圖案 16a···通孔栓塞 16b...Cu配線圖案 16cR...Cu 圖案 16c...Cu配線圖案 16dR…Cu圖案 16d...Cu配線圖案 16eR...Cii 圖案 16e...Cu配線圖案 16fR...Cu 圖案 16f.. .Cu配線圖案 16gR...W圖案 16g…W通孔栓塞 17A〜17F...蝕刻阻擋膜 18…氧化石夕膜 18A...A1 圖案 18B...A1電極墊 19…SiN鈍化膜 20…半導體裝置 22A...防潮環 16bR...Cu 圖案 26 20083993810...Semiconductor device 11 ～110...Component region 12A...moisture-proof ring 12B...moisture-proof ring 12C...moisture-proof ring 12D...moisture-proof ring 13...electrical region t 14A...protective groove portion 15... Semiconductor substrate 15Tn.. transistor 15a...diffusion region 15b...diffusion region 15c...lithium layer 15d...antimony layer 16A to 16G...interlayer insulating film 16aR...through hole pattern 16a··· Through-hole plug 16b...Cu wiring pattern 16cR...Cu pattern 16c...Cu wiring pattern 16dR...Cu pattern 16d...Cu wiring pattern 16eR...Cii pattern 16e...Cu wiring pattern 16fR.. .Cu pattern 16f..Cu layout pattern 16gR...W pattern 16g...W via plug 17A~17F...etch barrier film 18...oxidized oxide film 18A...A1 pattern 18B...A1 electrode pad 19...SiN passivation film 20...semiconductor device 22A...moisture-proof ring 16bR...Cu pattern 26 200839938
23...電路區域 24A…保護溝部 25…半導體基板 25Tr...電晶體 251…元件分離區域 25a...擴散區域 25b...擴散區域 25c...矽化物層 25d...矽化物層 26A〜26G…層間絕緣膜 26aR…通孔圖案 26a"·通孔栓塞 26bR…Cu圖案 26b... Οι配線圖案 26cR...Οι 圖案 26c...Cu配線圖案 26dR...Cxi 圖案 26d...Cii配線圖案 26eR...Cu 圖案 26e...Cu配線圖案 26ΑΙ...Οι 圖案 26f...Oi配線圖案 26gR..；W 圖案 26g".W通錄塞 26aP〜26bP...W圖案 27A〜27F…蝕刻阻擋膜 28…氧化石夕膜 28A...A1 圖案 28B...A1電極墊 28C...A1 圖案 28D...A1 圖案 28E...A1 圖案 281.. .界面膜 29…SiN鈍化膜 29A...開口部 30···樹脂層 40…半導體裝置 60.··半導體裝置 80.. .半導體裝置 2723...circuit area 24A...protection groove portion 25...semiconductor substrate 25Tr...transistor 251...element separation region 25a...diffusion region 25b...diffusion region 25c...antimony layer 25d...telluride Layers 26A to 26G... Interlayer insulating film 26aR... Via pattern 26a " Through-hole plug 26bR...Cu pattern 26b... Οι wiring pattern 26cR...Οι Pattern 26c...Cu wiring pattern 26dR...Cxi Pattern 26d ...Cii wiring pattern 26eR...Cu pattern 26e...Cu wiring pattern 26ΑΙ...Οι pattern 26f...Oi wiring pattern 26gR..;W pattern 26g".W recording plug 26aP~26bP.. .W pattern 27A to 27F...etching barrier film 28...oxidized oxide film 28A...A1 pattern 28B...A1 electrode pad 28C...A1 pattern 28D...A1 pattern 28E...A1 pattern 281.. Interface film 29...SiN passivation film 29A... Opening portion 30···Resin layer 40...Semiconductor device 60.·Semiconductor device 80.. Semiconductor device 27