TW200837963A - Memory unit structure and operation method thereof - Google Patents

Abstract

A memory unit is proposed. The memory unit includes a Si substrate, a trapping layer formed on the Si substrate, a first and a second doping regions formed in the Si substrate on either side of the trapping layer, a gate formed on the trapping layer, a first oxide layer formed between the gate and the trapping layer, a high interface trap density (Dit) material layer formed between the Si substrate and the trapping layer, and a second oxide layer formed between the high-Dit material layer and the trapping layer, wherein an interface trap density between the high-Dit material layer and the Si substrate is in a rang from 10<SP>11</SP>cm<SP>-2</SP>eV<SP>-1</SP>to 10<SP>13</SP>cm<SP>-2</SP>eV<SP>-1</SP>.

Description

200837963 P950202 22692twfdoc/n IX. Description of the Invention: [Technical Field] The present invention relates to a memory unit structure, and more particularly to a method of reducing a swing degradation after operation ( Impact memory cell structure and its operation method. [Prior Art] φ Current non-volatile memory products have the ability to store, read, erase, etc. multiple data, and can perform one-bit (2 bit) operation in one memory unit. The SONOS memory unit has become a memory component widely used in personal computers and electronic devices. In general, a SONOS memory cell is a polysilicon floating gate that replaces a conventional flash memory with a charge trapping layer, and usually has a charge trap layer on top of each other. A layer of ruthenium oxide is formed to form a stacked structure composed of a layer of yttrium oxide/yttria/yttria (〇N〇). Furthermore, the source and the drain are in the substrate on both sides of the 0N0 layer, and the gate is provided on the layer. Since the bottom oxide layer in the germanium layer of the conventional SONOS memory cell is directly formed on the substrate by thermal oxidation, it has a low interface trap density (Dit) between the substrate and the substrate of the germanium wafer. , about l〇iGcnr2eV-i, but this Dit value is found to increase gradually as the number of cycles of the memory cell increases, as shown in Figure 1, where either the initial erase state or the initial stylized state ( The initial program state) is _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Therefore, the crane performance (swing (cyde endurance) ^ ... w - r is reduced from the Pei can perform), the operation of the memory unit is affected, and the structure can be stabilized after the loop operation.

‘ Maintainable Memory The present invention provides a memory cell structure, swing performance. Yuan Zuo === unit operation method, can be used to remember the memory single voltage type, and the bribe is determined to start the inferior beauty supply--memory unit structure to reduce the pendulum after operation. The present invention further provides data retention of a method of operating a memory unit. - The present invention further provides a method of complementing the memory unit for performing a single bit operation and improving the cyclic persistence of the memory unit. The invention provides a memory unit, comprising a stone slab base, a stone trapping layer, a capturing layer, a first and second doping regions in the enamel base respectively located on both sides of the capturing layer, and a gate on the capturing layer. The layer, the first layer of the oxide layer between the gate and the capture layer, and the layer of the interface between the % substrate and the capture layer capture the temperature (the interface trap knows the Dit material layer, and is located at the high interface). A layer of a first oxide layer between the layer of the density material and the capture layer is captured, wherein an interface capture density between the high interface capture density material layer and the germanium substrate is between 1〇Η~l〇l3cnf2eV-l. 200837963 P950202 22692twfdoc/n In an embodiment of the invention, the interface capture density between the high interface capture density material layer and the germanium substrate is 10^cm^eV-1. In one embodiment of the invention, the high interface capture density material layer The thickness of the high-interface capture density material layer comprises a nitrided hair. In one embodiment of the invention, the high interface captures the density material layer. material The materials include cerium oxide (Hf02), cerium oxide (Zr〇2), cerium oxynitride (ZrOxNy), cerium oxynitride (Hf〇xNy), bismuth citrate (HfSixOy), strontium ruthenate (ZrSix〇y), Nitrogen oxide (HfSix〇yNz), aluminum oxide (Al2〇3), titanium dioxide (Ti02), tantalum pentoxide (Ta205), antimony trioxide (La2〇3), ceria (Ce〇2) , bismuth citrate (9) ❸ 2 2), tungsten oxide (w〇3), yttrium oxide (ΥΛ), lanthanum strontium (LaAl〇3), barium titanate (Bai_xSrxTi03), barium titanate (BaTi〇3), zirconium Lead acid (pbZr〇3), lead bismuth citrate (ρι^ζΤ&amp;〇3, abbreviated as pst), lead zinc sulphate (pbZnzNbi z〇3, PZN for short), lead strontium titanate (PbZr (VPbTi〇3, abbreviation for short) PZT) or lead magnesium niobate (PbMgzNbi z〇3, abbreviated as PMN). In one embodiment of the invention, the germanium-based germanium-based germanium substrate, and the first doped region and the second doped region are n-doped The invention further provides a method for operating a memory unit, which is suitable for applying the first positive voltage to the gate when the interface captures the stylized memory unit between the high density interface material layer and the germanium substrate. Applying a second positive charge to the second doped region Pressing, and making the first doped region 〇Vot: use channel hot electron (CHE) to program the bit on one side of the memory cell with 200837963 P950202 22692twfdoc/n; when erasing the memory cell, Applying a first negative voltage to the pole, applying a third positive voltage to the second doped region, and making the first doped region a volt volt to utilize a quotation band quoting hot hole (BTBTHH) The mode erases the bit on the side of the memory unit. The present invention further provides a method of operating a memory cell suitable for use in the above-described memory cell between the high interface capture density interface material layer and the germanium substrate interface density (Dit). The operation method includes: applying a fourth positive voltage to the gate and making the first doped region and the second doped region 0 volts to utilize the Fuller_Nudehan (Fmvl^^i〇rdheim, FN) way to program the memory unit; and when erasing the memory unit, applying a second negative voltage to the gate, and the first doped region and the second doped region It is 0 volts to erase the memory unit by means of the Fuller_Nordheim method. In an embodiment of the invention, the first doped region is a source, and the first doped region is a drain. In the present invention, the first doped region is recorded and first doped. The voltage is in the present invention. The voltage is in the present invention, the first positive voltage is greater than the second Zhengshi Ximei ^ Μ proposed - a kind of fresh elements, including - the base, the located layer, respectively located on both sides of the capture layer In the base of the 矽 ” 弟 ( ( 四 四 四 弟 弟 弟 弟 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 37 37 37 37 37 37 37 37 37 37 37 37 37 2008 2008 2008 2008 2008 37 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 2008 Layer 2 dielectric layer 'the interface density between the second dielectric layer (Dit) is between ι 〇 ι~. - In another embodiment of the invention, the interface capture density between the second dielectric layer and the lithium substrate is . Soil &amp; In another embodiment of the invention, the second dielectric layer comprises an oxide layer. In another embodiment of the invention, the 11 substrate is a p-type Shi Xiji and a The second doped region is an n-type doped region. Layer In another embodiment of the present invention, the first dielectric layer includes a memory cell that oxidizes the memory cell as a branch, between the above 10 to 10 cm eV-i. When it is dropped into a memory cell, a second positive voltage is applied to the first region, and the first doped region is made. Volt = sub- (cafe) way to program the side of the memory cell; 'one, in the second doping area = W__TBTHH) to erase the side of the memory cell "in the first operation of a memory cell The method is applicable to the interface between the above-mentioned I bottom capture density _ is a memory unit between ~1〇Cm'eV. The operation method includes: Cheng 9 200837963 When 22692twfd〇c/n is used to learn the unit, Applying a fourth positive electric friction on the gate, and making the first and second doped regions G volts to utilize the Fuller_Nodham (4)) ft-type § memory unit; while erasing the memory unit, Applying to the interpole: a second negative voltage 'and the first doped region and the second doped region are squatting to erase the memory cell by using Fuller Nordhorn (FN). In another embodiment of the present invention, the first doped region is a source, and the first impurity-doped region is a drain. • In the other aspect of the present invention, the f-doped region is a immersed brother. A doped region is a source. In another embodiment of the invention, the first positive voltage is greater than a positive voltage. The interface between the substrate and its upper layer is set to a high interface capture density (Dit) between /~y^cn^eV-1, so when the number of operations is gradually increased, the swing performance can be maintained in a certain range. =* Therefore, the operation of the memory unit, the cycle persistence, and the data retention are maintained as far as possible within the allowable range without invalidating the memory. The above features and advantages of the present invention are more apparent. BRIEF DESCRIPTION OF THE DRAWINGS The preferred embodiments are described below in detail with reference to the accompanying drawings, in which: FIG. It can be practiced in many different forms, and should not be construed as limited to the embodiments set forth in the specification. In the drawings, the dimensions of the various layers and regions may be exaggerated for clarity, and not according to actual 200837963 P950202 22692twfdoc/n In addition, in the 5 children's book, the statistic η uses the embodiment 'and is not used to limit the hair of the second paragraph; = the following applies: ί:", ""ΐ二" and other terms, just use To bring a -: domain Or the order of operations. The mind (4) represents the order in which it is formed. The first embodiment and Fig. 2A are schematic cross-sectional views of a first embodiment of the present invention, in which the bit is programmed. Figure 2A, the memory unit of the first embodiment includes a Shi Ximeidi 200, a layer capture layer 202, a first-inferior region pulse The pole 206, a first oxide layer 2〇8, a high interface high-dit material layer 210 and a second oxide layer 212. In the present embodiment, the germanium substrate 200 is a p-type germanium substrate, and the first doping region 2, for example, and the second doping region 204b are n-type doping regions. The capture layer 2〇2 is located on the germanium substrate 200, and the first and second doped regions 204a and 204b are respectively the germanium substrate 200 on both sides of the capturing layer 202, and the gate 206 is located on the capturing layer 2〇2, An oxide layer 208 is between the gate 206 and the capture layer 202. The south interface capture density material layer 210 is located between the 5th substrate 200 and the capture layer 202, and the dioxide layer 212 is located between the high interface capture density material layer 210 and the capture layer 202, wherein the high interface captures the density material layer. The interface indentation trap density (Dit) between 21〇 and the broken substrate 200 is between 1011 and 1013 cmW; preferably ic^cmW. In addition, the thickness of the high interface capture density material layer 210 is, for example, 1 〇 7 7 〇 11 11 200837963 P950202 22692 twfdoc / n

Between; preferably 30 angstroms. As for the material of the high interface capturing density material layer 21〇, it may be tantalum nitride; or, cerium oxide (Hf〇2), zirconium dioxide (Zr〇2), cerium oxynitride (ZrOxNy), cerium oxynitride (Hf〇) xNy), HfSix〇y;, ZrSix〇y, HfSixOyNz, Al2O3, Titanium Dioxide ^Antimony trioxide (La203), cerium oxide (Ce〇2), strontium sulphate, oxidized crane (W〇3) 'yttrium oxide (Y2〇3), barium aluminate (LaA1〇3), barium titanate Barium (BanSrxTiO3), barium titanate (BaTi〇3), lead citrate (pbZr〇3), lead bismuth citrate (PbSCzTai-z〇3, pST for short), zinc lead citrate (PbZnzNbuO3, simple % PZN), Lead bismuth titanate (PbZr〇3_pbTi〇3, abbreviated as ρζτ) and magnesium citrate (PbMgzNbkC^, abbreviated as ΡΜΝ). Continuing to refer to FIG. 2A, when the memory unit of the embodiment is operated as shown in FIG. 2Α, the first positive voltage (eg, vg=i〇volt) can be applied to the gate 2〇6. The second doping region 2〇4b (which can be used as a drain) can apply a second positive voltage (eg, 5 volts and (10) (which can be used as a source) to ^) volts to utilize the channel khannd hot elect_, CHE) The way to program the memory unit: _ and the extreme side bit) 'and the cut-off base · is grounded, so stand ysubJ gang. On the other hand, the first junction region 上述 can be 正 正 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Further, the above-mentioned first-positive voltage is shown in Fig. 2B as a cross-sectional view of the memory cell structure of Fig. 2, which is subjected to a two-bit erase operation 12 200837963 P950202 22692twfd 〇〇 / n . Society 2: Money Figure 2B, when performing the -bit on the memory cell of this embodiment, it is necessary to apply a first negative ^^ vL volt on the closed-pole 2〇6: f): Apply a first in the second doped region Three positive voltages (such as 4 ±, inch), the first doped region 2 〇 4a is 0 volts (such as v (four) volts m (band-to-band tunneling hot e ΒΤΒΊΉΗ) Age element

兀). In addition to the two-bit operation, the memory cell structure of the first embodiment is also performed in the manner of _early-bit operation, as shown in Figs. 2C and 2D. 2C is a schematic diagram of a single-bit stylized operation of the memory cell structure of FIG. 2A. Referring to the figure 兀 '# For the memory single-single-bit stylized operation of the embodiment, it is necessary to apply a fourth positive voltage (such as Vg=20 volts) on the gate 206 and make the first doping. The region 2 〇 4a 盥 = doping region 204b is 0 volts (Vs = 0 volts, Vd = 〇 volts) to program the memory cell map using the Fowler-Nordheim 'FN method. 2D is a cross-sectional view of the memory cell structure of FIG. 2A for a single bit erase operation. Please refer to FIG. 2D. When performing the single-bit erase operation on the memory unit of this embodiment, a second negative voltage (such as Vg 2-20 volts) is applied to the gate sequence, and the first blend is applied. The impurity region 2〇4&amp; and the second doped region 204b are 0 volts (Vs-0 volts, V(H) volts) to erase the memory cells using a Fuller-Nordheim (FN) method. To confirm that the memory unit of the first embodiment can still maintain stable swing performance after multiple cycles 13 200837963 P950202 22692twfdoc/n, please refer to FIG. 3A and FIG. 3B.

&quot; Fig. 3A is a diagram of the memory unit structure of Fig. 2A after the two-bit stylized operation is initially performed with a cycle of 15,000 (15K) times and 30,000 (30K) cycles. Fig. 3B is an I-V graph of the memory cell structure of Fig. 2B after the two-bit erase operation is initially performed with 15K cycles and 30K cycles. As can be seen from FIG. 3A and FIG. 3B, whether it is the initial program state in FIG. 3A or the initial erase state (four) stat^) in FIG. 3B is a program that cycles 15K times and 3〇κ times. The slope of the state and the erase state is similar. In other words, the memory unit of the first embodiment can maintain stable swing performance after a plurality of operation cycles. SECOND EMBODIMENT Fig. 4 is a schematic cross-sectional view showing a memory cell junction in accordance with a second embodiment of the present invention. The memory unit of the second embodiment includes a Shiyake base fj0, a capture layer 4〇2, a first doped region 404a, and a second doped region. The first dielectric layer 408 and the second layer of electricity 410. In the present embodiment, the stone substrate 400 is a p-type base, ^, a region 404a and a second doped region 4〇4b*n-doped region, and the first intermediate layer 408 is, for example, an oxide layer. As for the second dielectric layer _ i ® i &amp; between the high interfaee traP, ιη ΙΤ 特性 feature interface 412, the interface capture density (Dit) between the human 4 dcm eVl; preferably In addition, the second "package" ίο can be an oxide layer; for example, it can be selected with the worst heat 14 200837963 ry^uzu^ 22692twfdoc/n, chemical coating or in thermal oxidation system (10) planting people ^ (4)咖 〇 〇 ) = 412 = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = The region 4〇4b is, for example, an n-type doped region. Please continue to refer to FIG. 4A, and (4) the actual positive charge is performed. When the program is operated, the first positive ink can be applied to the gate 4〇6. (eg, 简}, on the second doped region side (this can be applied as the τ' volts), and the first doped region 4〇4a (which can be used as the source) is Vs=0 Volt to utilize channel hot electrons to chelate the bit on one side of the memory cell (ie, the drain side bit), and typically V 〇 volt. Further, the first doped region is just a and the second doped Miscellaneous area It can be replaced with wire and miscellaneous, and is limited to the second embodiment; in other cases, when a first positive voltage is applied to the gate, a second positive voltage is applied to the source, and j is G volts, the memory unit can be programmed. The source side bit indicates that the first positive voltage is generally greater than the second positive voltage. The figure is the memory cell structure of FIG. 4 and the two-dimensional eraser is shown in FIG. 4B, when the memory of the embodiment is used. When the cell performs the second erasing operation, a first negative voltage (such as ^^ volts) is applied to the gate 4〇6, and a third positive voltage (such as Vdy, special) is applied to the second doping region 404b, and the first A doped region 404a is a volt-volt (such as a % volt, a valence band with a thermal hole (BTBTHH) method to erase the quotation: the benefit bit (ie, the unequal side bit). The memory cell structure of the second embodiment can be programmed and erased by means of the operation of the single-bit one 15200837963 P950202 22692twfdoc/n, as shown in FIG. 4c" is the memory cell structure of FIG. 4A-bit' diagram=show' Schematic diagram of the cross section of the operation. For the early position, please refer to Figure 4C for the privateization and erasing, in the gate ^. Volt, and Torting the first doped region with a positive voltage (such as 0 volts (〇, volt VL, VL 404a, and doped region 404b is a way to program the miscellaneous (10) single ^), then Xiangfu (four) Dehan Tao • Please refer to Figure 4D On the gate 404, a flute-containing * ν§ &quot;^20 volts is applied, and a negative voltage (such as 〇 ' '' is used to make the doped region 404a and the second doped region 404b The memory unit is erased by means of VsK volts, Vd = 〇 匕 U4b (4). ) 卩 Μ Μ 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右 右After the number of traitors has gradually increased, the value of Dit has not changed much. Therefore, the swing performance is not slightly reduced by 0, so the operation and the tiltability of the memory unit can be obtained after the bribe is added. Although the present invention has been disclosed as a difficult embodiment, it is not used for = The scope of the present invention is defined by the scope of the appended claims, and the scope of the present invention is defined by the scope of the appended claims. By

Standard D [Simplified Schematic] FIG. 1 is an I_V graph of a conventional SONOS memory cell after initial operation and after 10,000 cycles of 16200837963 P950202 22692twfdoc/n. Fig. 2A is a diagram showing the simplification of a two-element stylized operation of a memory cell structure in accordance with a first embodiment of the present invention. Fig. 2B is a schematic cross-sectional view showing the structure of the memory cell of Fig. 2A in a two-bit erase operation. Fig. 2C is a cross-sectional view showing the memory cell structure in a single bit stylized operation.

Fig. 2D is a schematic cross-sectional view showing the memory cell unit of Fig. 2 in a single bit erase operation. Fig. 3A is a Ι-ν graph of the memory cell structure of Fig. 2A after two-bit stylized operations and 15K cycles and 30K cycles. Fig. 3B is a diagram showing the π curve of the memory cell structure of Fig. 2A at the beginning of the two-bit erasing operation and after 15K times and 30K cycles. Fig. 4 is a cross-sectional view showing a memory cell junction lamp-bit 7L program according to a second embodiment of the present invention. The sound is a cross-sectional view of the memory cell structure of FIG. 4 when performing a two-bit erase operation. FIG. 4C is a schematic cross-sectional view of the memory cell structure of FIG.冓 冓 仃 - - - - 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图Early 7^ structuring single-bit erase operation [main component symbol description] 200, 400: 矽 substrate 17 200837963 P950202 22692twfdoc / n 202, 402: capture layer 204a, 404a: first doped region 204b, 404b: Two doped regions 206, 406: gate 208: first oxide layer 210: high interface capture density material layer 212: second oxide layer 408: first dielectric layer 410: second dielectric layer 412: interface

18

Claims (1)

200837963 ry^uzuz 22692twfdoc/n X. Patent application scope: 1. A memory cell structure comprising: a base substrate; a capture layer on the germanium substrate; a first doped region and a second doped region , respectively located in the enamel substrate on both sides of the capture layer; a gate on the capture layer; 10 a first oxide layer between the gate and the capture layer; a 咼 interface capture density (high- a material layer between the germanium substrate and the trap layer, wherein an interface trap density (Dit) between the high interface trap density material layer and the germanium substrate is 1011 〜l〇13 cmf2e\ri And a second oxide layer between the high interface capture density material layer and the capture layer. 2. The memory cell structure of claim 1, wherein the interface capture density between the interface-trapped density material layer and the germanium substrate is 1012cnT2eV]. 3. The memory cell structure of claim 1, wherein the high interface capture density material layer has a thickness between 10 and 7 angstroms. 4. The memory cell structure of claim 1, wherein the material of the high interface capture density material layer comprises tantalum nitride. 5. The memory cell structure of claim 1, wherein the material of the high interface capture density material layer comprises hafnium oxide (Hf〇2), cerium oxide (Zr〇2), and cerium oxynitride (Zr). 〇xNy), bismuth oxynitride (Hf〇xNy), 矽19 200837963 P950202 22692twfdoc/n bismuth hydride (HfSixOy), bismuth citrate (ZrSix〇y), oxynitride (HfSixOyNz), bismuth dioxide (AI2O3) ), - oxidized chin (了 〇 2), pentoxide group (Ta2 〇 5), antimony trioxide (La203), cerium oxide (Ce02), bismuth citrate (Bi4Si2012), oxidized crane (WO3), Oxidation (Y2〇3), lanthanum strontium (LaA103), barium titanate (BaLxSrxTiC^), barium titanate (BaTi03), wrong acid (PbZr03), bismuth citrate (PbSCzTai_z03, PST for short), 铌Zinc acid lead (PbZiizNbkC^, abbreviated as PZN), lead barium titanate (pbZrCVPbTiO3, abbreviated as PZT) or lead magnesium niobate (PbMgzNbkC^, referred to as PMN). 6. The memory cell structure of claim 1, wherein the germanium substrate is a p-type germanium substrate, and the first doped region and the second doped region are n-type doped regions. 7. A method of operating a memory unit, suitable for a memory unit, the memory sheet το having a substrate, a capture layer on the substrate, and a substrate in each of the two sides of the capture layer a first doped region and a first doped region, a gate on the capture layer, a first oxide layer between the gate and the capture layer, between the germanium substrate and the capture layer The w interface captures a layer of density material and a second oxide layer between the high interface capture density layer and the capture layer, the high interface capturing the interface capture density between the layer of the material and the substrate (Dit) between 101 and ιο13·\ν_ι, the operation method includes: β is applied to the memory cell, and a first positive voltage is applied to the gate. (4) The second doping region is applied with a second positive voltage. And causing the first tamper to be 0 volts 4 inches to program the bit on one side of the side using the channel hot electrons (channei h〇t eiectr〇n, che); 20 200837963 ryDvzuz 22692twfdoc/n In addition to the memory unit, applying -first on the gate a voltage, applying a third positive voltage to the second doped region, and erasing the memory cell by using a valence band valence band thermal hole (band_t〇_bandtun_ng, hothole BTBTHH) The bit on this side. For example, an operation method for a memory unit of the seventh aspect is applied, wherein the first doping is a source, and the second doping is a pole. 9. The method of operating a memory unit according to claim 7, wherein the first doping (four) is a poleless and the second doping is a source. The method of operating the memory unit of claim 7, wherein the first positive voltage is greater than the second positive voltage. 11. A method for operating a 5-cell unit, suitable for a memory unit, wherein the memory unit has a silk bottom, a capture layer on the substrate, and a first one in the substrate on both sides of the capture layer. a doped region and a second doped region, a gate on the capture layer, a first oxide layer between the gate and the capture layer, and a first layer between the germanium substrate and the capture layer a high interface capture density material layer and a "second oxide layer" between the high interface capture density material layer and the capture layer, wherein the high interface captures the interface capture density between the if degree material layer and the germanium substrate (Dit Between 1011 and 1013 CmW, the method includes: when the memory unit is programmed, a fourth positive current is applied to the gate, and the first doped region and the second doped region are volts To program the memory unit by means of Fowler-Nordheim (FN); &amp; when erasing the memory unit, apply a second negative voltage to the gate, 21 200837963 P950202 22692twfdoc/n Making the first doped region and the second doped region ^ The Nordford (FN) method erases the memory unit.乂牙』用备勒- 12. If you apply for the scope of the patent, the first item of the law, you can talk about the pure wide S view, the operation of the mouth, the early operation, and the middle of the Extremely, and in the patent of the first method, the first-(four) P m is an operation of the first doping zone, and the second doping 卩a Μ, the seeding of the fresh-earth structure, including: pole. a substrate; a capture layer on the substrate; a first doped region and a second doped region, the side of the hybrid; "four (4) capture layer two gates, located on the capture layer a j-dielectric layer between the gate and the capture layer; and a layer between the (four) financial substrate and the germanium layer, wherein; the interface between the two layers and the germanium substrate capture density _ at 10 〜 Between 1 〇cm kv·1. The second memory unit structure as described in item 14 of the patent scope, the interface capture density between the io12'C% layer and the dream substrate is cm eV J 〇φ兮The structure of the memory unit according to item 14 of the patent scope, wherein the electric layer comprises an oxide layer. The memory unit structure according to item 14 of the patent scope, the broad stone, the type of silk bottom, and the The first-doped region and the second doped &amp; n-type doped region. 22 200837963 P950202 22692twfd〇c/n The material-element structure of the 14-material material, wherein the 5 ping dielectric layer includes an oxide layer. , L9 single 'fit, unit, vaf 矽 substrate, a capture layer on the 矽 substrate, the capture layer Of - - within the fiscal base side with a doped region heteroaryl ::: ,, a gate located on the trapping layer, the gate located at the a gate of the second dielectric layer and an electrical layer located between the Wei and the capture layer, wherein the second dielectric layer and the bite substrate = capture_it are at 1〇11~1〇1Wev—, The operation method includes: when the memory unit is programmed, a first positive voltage is applied to the gate and a second positive voltage is applied to the second doped region, and the first replacement is 0 volts 'programs one side of the memory early element by _ channel hot electron (CHE) method; when erasing the memory unit, applying a first negative voltage to the gate, in the far second doping region Applying a third positive voltage and causing the first scatter region to be 〇 volt, to erase the bit on the side of the symmetry band by means of a valence band versus a thermal hole (ΒΤΒΤΗΗ). The method of operating the memory unit of claim 19, wherein the first doped region is a source and the second doped region is a drain. The method of operating a memory unit according to claim 19, wherein the first doped region is a drain and the second doped region is a source. 22. The method of operating a memory unit as recited in claim 19, wherein the first positive voltage is greater than the second positive voltage. 23 200837963 P950202 22692twfdoc/π The operation method of the memory unit is applicable to a memory of the memory unit, the dream substrate, the capture sound on the substrate, and the inside of the substrate on both sides of the capture layer. a gate of τ= of the first doped region I:i S, located between the closed pole and the center of the occlusion of the capture layer == capture (10), the operation equations the memory In the case of a cell, a fourth positive emperor is applied to the gate, and the first doped region and the second doped region are Q volts, to program the memory cell by using a Le-Nordheim (FN) method. When the memory cell is erased, the dummy electrode is applied to the idle electrode. The first doped region and the second doped region are Q volts to be erased by using the private Fuller-Norw and Han (FN) method. The memory unit. 24. As in the middle item, the squaring element described in item _23 falls into the square. (4) The doped area is secret, and the second doped area is immersed. 25. For example, please refer to the operation method of (4) 23-characteristics, wherein the first doped region is a non-polar, and the second doped region is a source. twenty four