TWI683420B - Hybrid storage memory having vertical type of fet - Google Patents

Abstract

This invention provide a hybrid storage memory having vertical type of FET, formed a storage stacked structure by stacking a negative capacitance ferroelectric layer and an anti-ferroelectric layer within the vertical type of FET, thereby effectively improving the leakage current, lowering program/erase voltages and enhancing endurance cycling.

Description

Hybrid storage memory with vertical field effect transistors

The present invention relates to a memory, especially a hybrid storage memory.

The conventional non-volatile memory structure includes a substrate, an insulating layer formed on a part of the surface of the substrate, a source electrode, a drain electrode formed on the substrate, and located on both sides of the insulating layer, and A charge trapping layer, an insulating barrier layer, and a gate electrode in the insulating layer sequentially upward. In order to effectively reduce the device operating voltage, the aforementioned insulating barrier layer often uses oxides with high dielectric constants (such as silicon oxide, hafnium oxide, and aluminum oxide) as materials. Therefore, the memory device write/erase operating voltage is large And the write/erase operation speed is also slow (about 100μs~1ms), which leads to poor device durability.

Therefore, the inventor published the Republic of China Patent Publication No. TW201824456A in 2018, which discloses a flash memory structure with a vertical field effect transistor, which is used to form a negative ferroelectric capacitor layer with the vertical field effect transistor. The stacked structure of the charge trapping layer reduces the leakage current of the memory and improves the operation speed of the device. It can be seen from the disclosure content of its specification that it can improve the subcritical swing and increase the speed of reading and writing operations to about 800ns.

Therefore, the purpose of the present invention is to provide a hybrid storage memory of vertical field effect transistors, which has a lower write/erase than the conventional charge storage type non-volatile memory In addition to operating voltage, and superior memory operating speed (50ns) and other characteristics.

Therefore, the hybrid storage memory of the present invention includes a plurality of storage cells, and each storage cell includes a vertical field effect transistor.

The vertical field effect transistor includes a semiconductor substrate, a first insulating layer, a source electrode, a drain electrode, a storage stack structure, and a gate unit.

The semiconductor substrate has a bottom and a channel portion extending away from the bottom.

The first insulating layer covers the surface of the channel portion, and exposes two surfaces of the channel portion relatively away from the ends.

The source electrode and the drain electrode are formed at two relatively distant ends of the channel portion, and are respectively located on both sides of the first insulating layer.

The storage stack structure is disposed on the surface of the first insulating layer opposite to the channel portion, has a charge trapping layer, and a ferroelectric composite layer, the ferroelectric composite layer has a negative capacitance ferroelectric layer stacked and connected to each other, and An antiferroelectric layer, the negative capacitance ferroelectric layer is composed of doped hafnium oxide with an orthorhombic phase as the main crystal phase and has negative capacitance characteristics, and the antiferroelectric layer is composed of a tetragonal crystal phase (Tetragonal) is a doped zirconia-based material with the main crystal phase.

The gate unit is formed on the surface of the storage stack structure opposite to the channel portion, and has at least one gate electrode made of a conductor or a half body material.

The effect of the present invention is to use the vertical field effect transistor of the memory to form a storage stack structure obtained by stacking a negative capacitance ferroelectric layer and an antiferroelectric layer, which can effectively improve the memory device leakage current and writing Input/erase the operating voltage and increase the operating speed of the memory device.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same number.

The hybrid storage memory of the present invention is formed by stacking a vertical field effect transistor of the memory cell of the hybrid storage memory with a negative capacitance ferroelectric layer and an antiferroelectric layer, thereby effectively Improve memory device leakage current, write/erase operation voltage, and increase memory device operation speed.

Referring to FIGS. 1 and 2, the embodiment of the hybrid storage memory of the present invention includes multiple storage cells. Each storage element includes a vertical field effect transistor 2 (1T), and at least one capacitor (1C) (not shown). The vertical field effect transistor 2 of only one storage cell is shown in FIG. 1.

The vertical field effect transistor 2 includes a semiconductor substrate 21, a source electrode 22, a drain electrode 23, a first insulating layer 24, a storage stack structure 25, a gate unit 26, and an insulating pillar 27.

The semiconductor substrate 21 has a bottom portion 211 and a channel portion 212 extending from the bottom portion 211 along an axis Z toward a direction away from the bottom portion 211, the insulating pillar 27 is formed on the bottom portion 211 and away from the bottom portion 211 The bottom portion 211 extends in the direction, and the channel portion 212 is formed on the surface of the insulating pillar 27. Taking the insulating pillar 27 as a cylindrical shape as an example, the channel portion 212 also covers the surface of the insulating pillar 27 in a ring shape.

The first insulating layer 24 covers a part of the surface of the channel portion 212 opposite to the insulating pillar 27, and exposes the surfaces of the channel portion 212 at opposite ends.

The source electrode 22 and the drain electrode 23 are formed at two relatively distant ends of the channel portion 212, and are located on opposite sides of the first insulating layer 24, respectively.

The storage stacked structure 25 is disposed on the surface of the first insulating layer 24 opposite to the channel portion 212, has a charge trapping layer 251, and a ferroelectric composite layer 252, and the ferroelectric composite layer 252 has a negative capacitance ferroelectric Layer 2521, and an antiferroelectric layer 2522.

The gate unit 26 is formed on the surface of the storage stack structure 25 opposite to the channel portion 212, and has a plurality of gate electrodes 261 and a plurality of gate insulating layers 262 interlaced with the gate electrodes 261. It should be noted that in this embodiment, the gate unit 26 has a plurality of gate electrodes 261 and a plurality of gate insulating layers 262 as an example. However, in actual implementation, it may have only one gate electrode 261, and Not limited to the structure of FIG. 1.

In detail, the semiconductor substrate 21 can be monocrystalline silicon, polycrystalline silicon, germanium, or other suitable semiconductor materials. The insulating pillar 27 and the first insulating layer 24 may be formed by stacking a single layer or multiple layers of insulating material, and the insulating material may be selected from, for example, silicon oxide or aluminum oxide.

The charge trapping layer 251 of the storage stack structure 25 may be selected from a conductor, a semiconductor, or an insulating material with a high dielectric constant. Wherein, the insulating material with high dielectric constant can be selected from silicon nitride (SiNx), silicon carbide (SiC), or non-orthorhombic phase (Orthorhombic) high dielectric constant oxide insulating material (relevant technical personnel) It is well known that the crystal phase of high dielectric constant oxide insulating materials is mainly Monoclinic or Tetragonal crystal phase), for example, zirconium oxide (Z _r O ₂ ), hafnium oxide (H _f O ₂ ), titanium oxide (T _i O ₂ ), tantalum oxide (TaO), aluminum oxide ( _{Al 2} O ₃ ), hafnium oxynitride (HfON), zirconium oxynitride (ZrON), aluminum oxynitride (AlON), silicon oxynitride (SiNO), nitrogen Titanium oxide (TiON), tantalum oxynitride (TaON), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO).

The negative capacitance ferroelectric layer 2521 and the antiferroelectric layer 2522 of the ferroelectric composite layer 252 are layered and connected to each other.

It should be noted that the HfO ₂ series materials that do not have an orthorhombic phase do not have ferroelectricity and negative capacitance characteristics. Therefore, the negative capacitance ferroelectric layer 2521 of the present invention is selected to have an oblique Orthorhombic phase is the main crystalline phase and doped hafnium oxide with ferroelectric negative capacitance is composed of materials, such as, but not limited to: aluminum hafnium oxide (HfAlOx), silicon hafnium oxide (HfSiOx), strontium hafnium oxide ( HfSrOx), zirconium hafnium oxide (HfZrOx), lanthanum hafnium oxide (HfLaOx), yttrium hafnium oxide (HfYOx), or hafnium oxide hafnium (HfGdOx), etc.

The antiferroelectric layer 2522 is selected from doped zirconia-based materials with a tetragonal crystal phase (Tetragonal) as the main crystal phase. The doped zirconia-based materials are, for example, but not limited to: zirconia (ZrO ₂ ), silicon oxide Zirconium (ZrSiOx), aluminum zirconium oxide (ZrAlOx), germanium zirconium oxide (ZrGeOx), yttrium zirconium oxide (ZrYOx), hafnium zirconium oxide (ZrHfOx), or zirconium oxynitride ZrNOx, etc.

In addition, the doping ratio of the aforementioned ferroelectric material with negative capacitance characteristics (doped hafnium oxide) and antiferroelectric material (doped zirconium oxide) depends on the characteristics of the doped element and the crystal to be achieved The phase requirements are different, and the doping ratio is also different. Taking the aforementioned doped hafnium oxide as an example, the doping ratio of aluminum (Al) is between 2 and 10 mol%; the doping ratio of silicon (Si) is between 2 and 10 mol%; the doping ratio of zirconium (Zr) is between At 1~50 mol%; yttrium (Y) doping ratio is between 2~15 mol%; gadolinium (Gd) doping ratio is 2~15 mol%; lanthanum (La) doping ratio is 2~15 mol %; strontium (Sr) doping ratio is between 2~15 mol%. Taking the aforementioned doped zirconia-based material as an example, the doping ratio of silicon, aluminum, germanium, yttrium, hafnium, and nitrogen is greater than 0 mol and not greater than 50 mol%. Since these doping ratios are known to those skilled in the art through general experiments, they will not be repeated here.

The gates 261 can be selected from metal or semiconductor materials. Wherein, the metal may be a metal nitride or a metal carbide, such as, but not limited to: tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), tantalum carbide ( TaC), titanium aluminum carbide (TiAlC), titanium carbide (TiC), or tantalum aluminum carbide (TaAlC), etc. The material of the gate insulating layer 262 can be selected from, for example, silicon oxide or aluminum oxide. In some embodiments, the gate electrodes 261 and the gate insulating layer 262 are arranged alternately and spaced from each other, and the surfaces of the gate electrodes 261 and the gate insulating layer 262 in the axial Z direction are quadrangular.

In the present invention, by making the ferroelectric composite layer 252 of the storage stack structure 25 have the negative capacitance ferroelectric layer 2521 and the antiferroelectric layer 2522 stacked on each other, the negative capacitance characteristic of the negative capacitance ferroelectric layer 2521 is used to improve electricity The sub-critical swing of the crystal reduces the switching energy consumption and off-state current of the transistor, and is further matched with the antiferroelectric layer 2522. The antiferroelectric layer 2522 has a larger coercive electric field ( coercive field), which can effectively maximize the saturation polarization of the negative-capacitance ferroelectric layer 2521 during high-field writing and erasing operations, while reducing the negative-capacitance ferroelectric layer 2521 and the charge trapping layer 251 Across the electric field to reduce possible defects and derived leakage currents during repeated read and write operations. Therefore, it can effectively improve the memory device leakage current, write/erase operation voltage, and increase the operation speed of the memory device.

It should be noted that the storage stack structure 25 in FIG. 1 is described by taking the charge trapping layer 251 and the ferroelectric composite layer 252 sequentially formed upward from the surface of the first insulating layer 24 as an example. However, when actually implemented Alternatively, the ferroelectric composite layer 252 may be formed before the charge trapping layer 251 is formed.

In addition, it should be further explained that in FIG. 1, the ferroelectric composite layer 252 is formed by first forming the negative capacitance ferroelectric layer 2521 and then forming the antiferroelectric layer 2522. However, in actual implementation, it may be first Forming the antiferroelectric layer 2522 and then forming the negative-capacitance ferroelectric layer 2521, the relative formation order does not affect the objective and effect to be achieved. That is to say, the storage stack structure 25 can also be a charge trapping layer 251/antiferroelectric layer 2522/negative capacitance ferroelectric layer 2521, or an antiferroelectric layer 2522/negative capacitance ferroelectric layer 2521/charge trapping layer 251 Is formed upward from the surface of the first insulating layer 24.

Referring to FIG. 3, in some embodiments, the vertical field effect transistor 200 may further include a second insulating layer 28 interposed between the storage stacked structure 25 and the gate unit 26, and the storage stacked structure 25 also A third insulating layer 253 between the charge trapping layer 251 and the ferroelectric composite layer 252 may be included. The second insulating layer 28 and the third insulating layer 253 are selected from insulating materials, and the insulating material may be a non-orthorhombic high dielectric constant material. In addition, it should be noted that the second insulating layer 28 and the third insulating layer 253 can be selected according to the characteristics and requirements of the device, or set at the same time, and there is no particular limitation.

In some embodiments, the thickness of the charge trapping layer 251, the negative-capacitance ferroelectric layer 2521, and the antiferroelectric layer 2522 are between 1 and 30 nm. In addition, in order to maintain the negative ferroelectric layer 2521 with better ferroelectric characteristics, the thickness of the negative capacitor ferroelectric layer 2521 is between 3-20 nm.

It should be further explained that, in some embodiments, the insulating pillar 27 may not be formed. In this case, the channel portion 212 may be formed as a solid pillar or a hollow ring pillar extending from the bottom 211.

Referring to FIG. 4, FIG. 4 is a hysteresis curve diagram of general ferroelectric (FE) and antiferroelectric (AFE) memory capacitor elements. It can be seen from FIG. 4 that the antiferroelectric memory capacitor can have a larger coercive field (Coercive Field). Therefore, when the AFE/FE double-layer stacked structure is used in this case, the characteristics of the antiferroelectric having a larger coercive electric field can be used. Therefore, when the memory device in this case is operated in a high electric field, it can effectively increase the ferroelectric saturation polarization (Saturated Polarization).

Referring again to FIGS. 5-7, FIGS. 5-7 are the memory characteristic test results of the memory having the AFE/FE/CT storage stack structure of the present invention. Among them, AFE represents the antiferroelectric layer, FE represents the negative capacitance ferroelectric layer, and CT represents the charge trapping layer. Substrate: Silicon (Si); Thickness of each layer: AFE layer material is zirconium oxide (ZrO ₂ )/thickness 10 nm, FE layer material is zirconium hafnium oxide (HfZrOx), zirconium doping ratio is 40 mol%/thickness 10 nm, CT layer material It is hafnium oxynitride (HfON)/thickness 3nm.

FIG. 5 is a result of writing/erasing the gate voltage V _G (V) to the drain current I _D (A) obtained by simulation. It can be seen from the measurement results in FIG. 5 that under the write/erase operation conditions of ±10V@50ns, a memory device with an AFE/FE/CT stacked structure can obtain a memory window of more than 2V. Fig. 6 is the measurement result of time (μs) on the gate operating voltage (V) and the drain electric current (A). From the measurement results of the drain current (I _D ) response shown in Fig. 6, the ferroelectric and antiferroelectric effects can be clearly observed, which also confirms that the current output characteristics of the AFE/FE/CT stacked transistors will be affected by the double layer The effect of the transient behavior of the AFE/FE stack structure.

According to the reading and writing speed measurement results of FIG. 7, the memory of the present invention integrates the AFE/FE double-layer stack structure and is equipped with a thinner CT. Therefore, the operation write/erase (Prog/Erase) ) The speed can reach 50ns, which is nearly a hundred times faster than the operation speed of traditional CT flash memory, and can have extremely superior read and write speeds.

In summary, the present invention integrates the charge trapping layer 251 and the ferroelectric composite layer 252 in the hybrid storage memory, and further enables the ferroelectric composite layer 252 to form a negative capacitance ferroelectric layer 2521 and an antiferroic layer stacked on each other The electric layer 2522 uses the negative capacitance characteristic of the negative-capacitance ferroelectric layer 2521 to improve the sub-critical swing of the transistor, reduce the switching energy consumption and off-state current of the transistor, and further match with the The antiferroelectric layer 2522 stacked by the negative capacitance ferroelectric layer 2521 can not only effectively improve the memory device leakage current, and reduce the write/erase operation voltage, but also further improve the operation speed of the memory device, so it can indeed reach the cost The purpose of the invention.

However, the above are only examples of the present invention, and should not be used to limit the scope of the present invention. Any simple equivalent changes and modifications made according to the scope of the patent application of the present invention and the content of the patent specification are still classified as This invention covers the patent.

200‧‧‧Vertical field effect transistor

2521‧‧‧Negative capacitance ferroelectric layer

21‧‧‧Semiconductor substrate

2522‧‧‧Antiferroelectric layer

211‧‧‧Bottom

253‧‧‧The third insulation layer

212‧‧‧Channel Department

26‧‧‧Gate unit

22‧‧‧Source

261‧‧‧Gate

23‧‧‧ Jiji

262‧‧‧Gate insulation

24‧‧‧The first insulating layer

27‧‧‧Insulation column

25‧‧‧Storage stack structure

28‧‧‧Second insulation layer

251‧‧‧ Charge trapping layer

Z‧‧‧axial

252‧‧‧Ferroelectric composite layer

Other features and functions of the present invention will be clearly presented in the embodiment with reference to the drawings, in which: FIG. 1 is a schematic diagram illustrating the embodiment of the present invention; FIG. 2 is a schematic top view illustrating the embodiment of the present invention FIG. 3 is a schematic top view illustrating the vertical field effect transistor of this embodiment further has a second insulating layer and a third insulating layer; FIG. 4 is a hysteresis illustrating a memory capacitor element having an AFE/FE/CT storage stack structure Characteristic measurement results; FIG. 5 is a measurement data diagram illustrating gate voltage (V _G ) versus drain current (I _D ) of a memory capacitor element with an AFE/FE/CT storage stack structure; FIG. 6 is a diagram illustrating AFE/FE/CT storage stack structure memory capacitor device current response measurement results; and FIG. 7 is a diagram illustrating the device operation speed measurement result of the AFE/FE/CT storage stack structure memory capacitor device.

200‧‧‧Vertical field effect transistor

21‧‧‧Semiconductor substrate

211‧‧‧Bottom

212‧‧‧Channel Department

22‧‧‧Source

23‧‧‧ Jiji

251‧‧‧ Charge trapping layer

252‧‧‧Ferroelectric composite layer

2521‧‧‧Negative capacitance ferroelectric layer

2522‧‧‧Antiferroelectric layer

26‧‧‧Gate unit

261‧‧‧Gate

24‧‧‧The first insulating layer

25‧‧‧Storage stack structure

262‧‧‧Gate insulation

27‧‧‧Insulation column

Claims (11)

A hybrid storage memory with vertical field effect transistors includes a plurality of storage elements, and each storage element includes a vertical field effect transistor. The vertical field effect transistors include: A semiconductor substrate having a bottom portion and a channel portion extending from the bottom portion away from the bottom portion; A first insulating layer covering the surface of the channel portion and exposing the surfaces of the channel portion relatively away from the ends; A source electrode and a drain electrode formed at two relatively distant ends of the channel portion and respectively located on both sides of the first insulating layer; A storage stack structure, which is arranged on the surface of the first insulating layer opposite to the channel part, has a charge trapping layer, and a ferroelectric composite layer, the ferroelectric composite layer has a negative capacitance ferroelectric layer stacked and connected to each other, And an antiferroelectric layer, the negative capacitance ferroelectric layer is composed of doped hafnium oxide with an orthorhombic crystal phase as the main crystal phase and having negative capacitance characteristics, and the antiferroelectric layer is composed of a square crystal phase as the main phase Crystalline phase doped zirconia-based materials; and A gate unit is formed on the surface of the storage stack structure opposite to the channel portion, and has at least one gate electrode made of a conductor or a half body material. The hybrid storage memory according to claim 1, wherein the charge trapping layer is selected from silicon nitride, silicon carbide, or a non-orthorhombic phase high-dielectric-constant oxide, for example, zirconium oxide, hafnium oxide, Aluminum oxide, titanium oxide, tantalum oxide, zirconium oxynitride, hafnium oxynitride, silicon oxynitride, aluminum oxynitride, titanium oxynitride, tantalum oxynitride, hafnium silicon oxide, silicon zirconium oxide. The hybrid storage memory according to claim 1, wherein the doped hafnium oxide is selected from aluminum hafnium oxide, silicon hafnium oxide, strontium hafnium oxide, zirconium hafnium oxide, lanthanum hafnium oxide, yttrium hafnium oxide, or hafnium hafnium oxide . The hybrid storage memory according to claim 3, wherein the aluminum doping ratio of the hafnium aluminum oxide is between 2 and 10 mol%, and the silicon doping ratio of the hafnium silicon oxide is between 2 and 10 mol%, the The zirconium doping ratio of hafnium zirconium oxide is between 1~50 mol%, the yttrium doping ratio of the yttrium hafnium oxide is between 2~15 mol%, and the hafnium doping ratio of the hafnium oxide is between 2~15 mol% The lanthanum doping ratio of the lanthanum hafnium oxide ranges from 2 to 15 mol%, and the strontium hafnium oxide doping ratio of strontium ranges from 2 to 15 mol%. The hybrid storage memory according to claim 1, wherein the doped zirconia-based material is selected from zirconia, silicon zirconia, aluminum zirconia, germanium zirconia, yttrium zirconia, hafnium zirconia, or oxynitride Zirconium, and the doping ratio of silicon, aluminum, germanium, yttrium, hafnium, nitrogen is greater than 0mol and not greater than 50mol%. The hybrid storage memory according to claim 1, wherein the thicknesses of the negative-capacitance ferroelectric layer, the antiferroelectric layer, and the charge trapping layer are respectively 1-30 nm. The hybrid storage memory according to claim 1, further comprising a second insulating layer interposed between the storage stack structure and the gate. The hybrid storage memory according to claim 1, wherein the storage stack structure further includes a third insulating layer interposed between the charge trapping layer and the ferroelectric composite layer. The hybrid storage memory according to claim 8, wherein the third insulating layer is a dielectric insulating material and does not have an orthorhombic phase. The hybrid storage memory according to claim 1, further comprising an insulating pillar extending from the bottom of the semiconductor substrate away from the bottom, and the channel portion is formed on the surface of the insulating pillar. The hybrid storage memory according to claim 1, wherein the gate unit includes a plurality of gates and a plurality of gate insulating layers, and the gates and the gate insulating layers are arranged alternately at intervals.

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