TWI338375B - Memory unit structure and operation method thereof - Google Patents

Description

P950202 22692twfdoc/n IX. Description of the Invention: [Technical Field] The present invention relates to a memory unit structure, and in particular to a method of reducing a swing degradation impact after operation (impact Memory cell structure and its operation method. [Prior Art] Currently, non-volatile memory products have SONOS that can perform multiple data storage, reading, erasing, etc., and can perform two-bit (2 bit) operation in one memory unit. The memory unit has become a memory component widely used in personal computers and electronic devices. In general, a SONOS memory cell is a polysilicon floating gate that replaces a conventional flash memory with a charge trapping layer and has a layer of deuteration above and below the charge trapping layer. The tantalum layer is formed to form a stacked structure composed of a tantalum oxide/tantalum nitride/yttria (ON〇) layer. Furthermore, the source and the drain are in the substrate on both sides of the 0N0 layer, and the gate is provided on the 0Ν0 layer. Since the bottom oxide layer in the 0Ν0 layer of the conventional SONOS memory cell is directly formed on the substrate by thermal oxidation, it has a low interface trap density (丨nterface trap density) between the substrate and the base of the Shixi wafer. Dit) 'about】 〇 wcm-2eV ·〗, but this Dit value is found to increase with the number of cycles of the hex element, as shown in Figure 1, which is the initial erase state (initial erase state) Or the initial program state is very different from the 10,000-time erase state and the P950202 22692twfdoc/n state ride rate. According to the material, perf〇rma(4)) is reduced, which in turn affects the memory unit's fall end (ceend end ce) and data retention (4) mailing durability. SUMMARY OF THE INVENTION The present invention provides a memory cell structure, swing performance. #了 ^ After the operation of the object = provide - the operation method of the memory unit, can be a one-dimensional and persistent operation on the memory. The heart... The operation method of the voltage type memory unit, the start of the process to reduce the pendulum after the operation. The present invention further provides a memory cell structure, the impact of dynamic degradation. The invention further provides an operation method of the memory unit, and data retention of the unit. The present invention further provides a method of operating a memory cell that operates in a bit and improves the persistence of the memory cell. The memory can be maintained for a single memory unit, including a substrate, a trap layer in the layer, a first and second doped regions respectively located on the sides (4) of the capture layer, and a gate on the capture layer. Located on the 2nd floor of the gate? The inter-layer-oxide layer, the interface trap density (Dit) material at the base of the Shixia substrate and the trap layer: and a layer of oxide layer between the high-interface capture density material layer and the capture layer Wherein the interface capture density between the high interface capture density material layer and the germanium substrate is between 1 and LoWv-1. P950202 22692twfdoc/n In one embodiment of the invention, the high interface captures the density material layer and The interface capture density between the ruthenium substrates is. In one embodiment of the invention, the high interface capture density material layer has a thickness between 10 and 70 angstroms. In one embodiment of the invention, the high interface capture density is The material of the material layer includes nitrite. In one embodiment of the present invention, the material of the high interface-capture material layer includes cerium oxide (Hf〇2), dioxin (Zr〇2), zirconium oxynitride ( ZrOxNy), bismuth oxynitride (Hf〇xNy), bismuth ruthenate (H(5) Α), zirconium ruthenate (Δsixoy), bismuth oxynitride (Hfsix〇yNz), bismuth hydride (A丨2〇3), Titanium dioxide (Ti〇2), pentoxide button (Ta2〇5), trioxide镧(La2〇3), bismuth telluride (Ce〇2), bismuth ruthenate (BLtSbO)2), tungsten oxide (w〇3), cerium oxide (Υζ〇3), lanthanum strontium (LaAl〇3) , barium titanate (% χδΓχΤί〇3), barium titanate (BaTi03), lead citrate (pbZr03), lead acid sharp lead (pbSCzTai z〇3, referred to as PST), zinc citrate lead (pbZi^Nb^O3 'PZN for short), lead zirconate titanate (PbZr〇3_PbTi〇3 'abbreviated as PZT) or lead magnesium niobate (PbMgzNbi z〇3, abbreviated as PMN) 〇 In one embodiment of the invention, the ruthenium substrate is p-type 矽a substrate, and a first doped region and a second doped region doped region. The present invention further provides a method for operating a memory cell, which is suitable for the interface capture density between the density interface material layer and the germanium substrate at the interface ( Dn) is a memory unit between 1 〇 11 〜 1 〇 13 ^ ^. The operation method includes: when the memory unit is programmed, a first positive voltage is applied to the gate, and a second positive voltage is applied to the second doped region. And the first doped region is 〇Vot, and the channel hot electron (CHE) is used to program the bit on one side of the memory cell by using P950202 22692twfd〇c/n; erasing In the cell, a first negative voltage is applied to the gate, a third positive voltage is applied to the second doped region, and the first doped region is 0 volts to utilize the valence band valence band thermal hole (band-to- The band tunneling hot hole (BTBTHH) method erases the bit on the side of the memory unit. The invention further proposes a method for operating a memory cell, which is suitable for the memory cell between the high interface capture density material layer and the germanium substrate having an interface capture density (Dit) of 1011~i〇Bcm-2evi. The method of operation includes: when programming the memory cell, 'applying a fourth positive voltage to the gate and making the first doped region and the second doped region 〇 volts' to utilize Fowler-Nordheim (Fowler-Nordheim) The 'FN) mode stylizes the memory cell; and when the memory cell is erased, a second negative voltage is applied to the gate, and the first doped region and the second doped region are volts to utilize the Fuller - The Nordhan (FN) mode erases the memory unit. In an embodiment of the invention, the first doped region is a source and the first doped region is a drain. In an embodiment of the invention, the first doped region is a drain and the second doped region is a source. In an embodiment of the invention, the first positive voltage is greater than the second positive voltage. The invention further provides a memory unit comprising a germanium substrate, a capture layer on the bottom of the substrate, first and second doped regions in the germanium substrate respectively located on both sides of the capture layer, and a gate on the capture layer. In the gate P950202 22692twfdoc/n pole of the capture layer _-layer [dielectric layer and layer between the layers of the second layer, the second dielectric layer of the substrate, the interface density (Dit) in the ι 〇η~i〇13cm-2eV-i between. In another embodiment of the present invention, the interface capture density between the second dielectric broad and the stone eve is l〇12cm-2eV-i. In another embodiment of the present invention, the second dielectric layer comprises an oxidized shield 0. In the present invention, the above-mentioned hetero-substrate is a p-type stellite substrate, and the first doped region and the second doped region The impurity region is an n-type doped region. Soil In another embodiment of the invention, the first dielectric layer comprises an oxide layer. The invention further proposes a method for feeding the aeronautical memory unit, wherein the interface between the second electric layer and the broken substrate captures money (10) is a memory unit between ~j〇 cp2eV-i. The method includes the following steps: applying a first positive voltage to the gate, applying a second positive voltage to the second doped region and making the first doped region 0 volts to utilize the passer. (CHE) mode stylizes one of the bits on the side of the memory cell; when erasing ^jj, applying a -first-negative voltage on the open-pole, and adding a positive voltage to the second doped region The first doping area is $0 volt, in order to utilize the valence band to measure the hot t-hole (BTBTHH) material. γ Mouyue proposes a method of operating a memory cell, which is suitable for the memory cell between the above-mentioned interface and the germanium substrate f-density_between 10~1013cnr2eV-i. The operation method includes: when the process P950202 22692twfdoc/n 2 = ”, the fourth positive voltage is applied to the gate, and the first product is doped to be a volt, so as to use the way to program the fresh element ^ Age ~ / Mo (FN) ^) You are outbound. When it is already early, a negative voltage is applied to the gate and the first doped region and the second doped region are 0 volts to erase the memory cell using the Fuller-Nordheim (FN) method. f is the P of the present invention, wherein the first doping is the source, the first doping region is > and the pole. In another embodiment of the invention, the first doped region is a drain, and the dipole region is a source. In another embodiment of the invention, the first positive voltage is greater than the second positive voltage. According to the invention, since the interface between the ruthenium substrate and the upper layer is set to a high interface capture density (Dit) between 〜10in^eV1, the swing performance can be maintained at a certain level when the number of operation cycles is gradually increased. To the extent that the operation of the memory unit, cycle persistence, and data retention are maintained as far as practicable, without causing the memory unit to fail. The above features and advantages of the present invention will become more apparent from the following detailed description. [Embodiment] Hereinafter, embodiments of the present invention will be described more fully with the accompanying drawings. However, the invention may be practiced in many different forms and should not be construed as limited to the embodiments set forth herein. Moreover, in the drawings, the dimensions of the various layers and regions may be exaggerated for clarity, and are not drawn to the actual P950202 22692twfdoc/n ratio. Use: Ϊ: The terms used in the book are only used to describe the following terms such as "--" and "second", but only to distinguish a-d part from another-area, layer or part, and Not = or the order of operations. The first embodiment is a schematic cross-sectional view of a memory cell structure in the first embodiment of the present invention. Referring to FIG. 2A, the memory unit of the first embodiment includes a stone substrate 200, a layer capture layer 2, a first doped region 2〇4a and a second doping region 204b, and a gate write. a layer of first oxide layer 2〇8, a layer of high interface capture high-Dit material layer 21〇 and a second oxide layer 212. In the present embodiment, the germanium substrate 200 is a p-type germanium substrate, and the first doping region 2, for example, and the second doping region 204b are n-type doping regions. The capture layer 2〇2 is located on the germanium substrate 200, the first and second doped regions 2 are known, and the second and second doped regions 2 are respectively located on both sides of the capture layer 202, and the gate 206 is located on the capture layer. The upper and first rolling layers 208 are located between the gate 206 and the capture layer 202. As for the high interface capture density material layer 210 is located between the germanium substrate 200 and the capture layer 202, the second oxide layer 212 is between the high interface capture density material layer 210 and the capture layer 202, wherein the high interface captures the density material layer 21〇 The interface trap density (Dit) between the stone and the base substrate 200 is between ΙΟ11~l〇13cm-2evi; preferably lOimiv-丨. In addition, the thickness of the high interface capture density material layer 210 is, for example, 1 375 〇 7 〇 之 1338375 P9 50202 22692 twfdoc/n

Between; preferably 30 angstroms. The material of the high interface capture density material layer 210 may be tantalum nitride; or, hafnium oxide (Hf02), zirconium dioxide (Zr〇2), niobium oxynitride (ZrOxNy), niobium oxynitride (HfOxNy) 'tannic acid铪(HfSix〇y), zirconium citrate (ZrSixOy), oxynitride (HfSix〇yNz), bismuth oxide (AI2O3), oxidized bismuth (Ti〇2), pentoxide group (Ding & 2〇5 ), antimony trioxide (La203), cerium oxide (ce〇2), bismuth ruthenate (Bi4si2〇12), tungsten oxide (W03), cerium oxide (γ2〇3), lanthanum aluminate (LaA1〇3) , barium titanate (Ba, -xSrxTi〇3), barium titanate (BaTi〇3), bismuth acid (pbZr〇3), lead acid (PbSCzTakO) 'pst), zinc lead citrate (PbZnzNbl) Z〇3, simple handle PZN), lead barium titanate (PbZr〇3_pbTi〇3, abbreviated as ρζτ) and magnesium citrate (PbMgzNbi_z〇3 'abbreviated as ρμν). Referring to FIG. 2A, when the memory unit of the embodiment is operated by the two-digit stylization of FIG. 2, a positive voltage (eg, Vg, volt) can be applied to the gate 2〇6. The second push zone 2 (when the bungee is applied) applies a second positive voltage (such as Vd = 5 volts) and makes the first

204a (which can be used as the source at this time) is v (four) volts to utilize the channel demon power; k annd hot electron ' CHE) way to program one of the memory cells usually! The base 200 is grounded, so its pole, the second _ £ 2Q4lf ' The t-doped region 204a may also be a 汲❹-positive voltage and a second positive voltage at _σ second positive. And the above-mentioned brother - positive voltage Figure 2β is the memory cell structure of Figure 2-8 for two-bit erase operation

12 P950202 22692twfd 〇c / n schematic diagram. Referring to FIG. 2B, when the memory cell of the embodiment is subjected to the two-bit erase operation, it is required to apply a first negative voltage (eg, vg 10 volts) on the gate 162% to the hidden application of the first doped region. Third positive voltage (eg

Vd 5 volts) 'and the first doped region 2 〇 4a is 〇 volt (such as volts)' to erase the memory cell by means of a band*band _eiing h〇t hole 'BTBTHH' Side bit (ie, no side bit). In addition to the one-bit operation, the memory cell structure of the first embodiment can also be performed by a single bit operation, as shown in Figs. 2A and 2D. Figure 2C is a cross-sectional view of the memory cell structure of Figure 2A for a single bit stylized operation day. Referring to the figure, when performing the single bit stylization operation on the memory sheet of the embodiment, it is necessary to apply a fourth positive voltage (such as Vg=20 volts) on the gate 2〇6 and make the first doping. The region 2, for example, and the second doped region 204b are 0 volts (Vs = 0 volts, Vd = 〇 volts) to program the memory cells using the Fowler-Nordheim (FN) approach. Figure 2D is a cross-sectional view showing the memory cell structure of Figure 2A in a single bit erase operation. Referring to FIG. 2D, when a single bit erase operation is performed on the memory of the embodiment, a second negative voltage (such as Vg=-20 volts) is applied to the gate 2〇4 and the first doping is performed. The impurity region 2 〇乜 and the second doping region 2 〇 4b are 0 volts (Vs = 0 volts, VdW volts) to erase the memory cell by using a Fuller-Nordheim (FN) method. To confirm that the memory unit of the first embodiment can maintain the oscillating performance of 敎·13 P950202 22692 twfdoc/n after multiple cycles, please refer to FIG. 3A and FIG. 3β. Fig. 3A is the ^»,|•立...-仏 of Fig. 2A, and the first two-dimensional stylized operation with the -500 thousand (1^Γ^)

* (4) θ buckle 曰 ) 1-V curve after 30,000 (3 s) cycles. Figure 3Β is the memory unit of Figure 2

The initial i-v curve after 15 times, 3GK, fresh w T f Κ 抹 _ 闰叩叮 μ μ μ μ 。 。 。 。 。 。 。. From the initial stylized state in Figure 3A ":U official map 3Α (initial program s ate also in the initial erase state of Figure 3B * (four) ^ ^ ^ ^ ^ ^ 15K ^ and the stylized state of the order And in the evening, in other words, the memory unit of the first embodiment can perform the (10) continuous swing performance in the evening (four). The first embodiment n FIG. 4A is the second embodiment of the present invention. A cross-sectional schematic diagram of a memory unit in a one-dimensional stylized operation. π Referring to FIG. 4A' The second embodiment of the memory unit includes a Shi Xiji II 400, a layer capture layer, and a first holding area. In the second embodiment, the second layer of the gate is 400, the layer-dielectric layer 4〇8, and the second layer of the second layer 220. In this embodiment, the stone basal willow is a p-type stone slab base, The impurity region 4G4a and the second doping region 4Q4b are n-type doped regions, wherein the dielectric layer 408 is, for example, an oxide layer. As a result, the second dielectric layer 41〇=the bottom of the silt soil has a high interface capture. (high interface trap, 101; interface f of the special f, the interface capture density (Dit) is between two ~ 1 〇 (10) eV; preferably H)] W2eV-]. In addition, the second 1 'layer 410 For example, the worst thermal U3S375 P950202 22692twfdoc/n can be selected, or the process of the thermal oxidation process or the secret mode of the thermal oxidation process (impla blessing) can make the Dlt of one side 412 between 10]]~ l OUcn^eV·1. In the present embodiment, the description is given to the radiant substrate 40 (the M column is a p-type slab substrate, and the first variator region a4a and the second doping region 〇4b are, for example, Type change zone.

_Continue to refer to FIG. 4A 'When the two-bit π-stylization operation is performed on the memory unit of the embodiment, a first positive voltage (eg, a g 10=special) may be applied to the second doping region 4 〇4b (which can be used as a drain) can apply a positive-positive voltage (eg, Vd=5 volts) and make the first doped region 4 known (which can be used as a source) D is a Vs=0 volt to Use channel hot electron (CHE) mode to program. The bit on one side of the cell (ie, the non-polar side bit), and usually volts. Furthermore, the first doping region a and the second doping region 10 are also used as the drain and the source, and are not limited to the second embodiment; in other words, when the gate is applied - The source voltage of the memory cell can be programmed when a positive voltage, a second positive voltage is applied to the source, and is volts. The first positive voltage is generally greater than the second positive voltage.

Fig. 4B is a schematic cross-sectional view of the figure. The memory cell structure of 4A performs a two-bit erase operation operation for more than one month, and prepares a page for the first time to perform a second memory operation. When the music operation is performed, a first-negative voltage (such as Vg volt) is applied to the gate 406. Applying a third positive voltage (eg, special) to the first doped region 404b and making the first doped region 4〇4a 0 volts (eg, Vs==〇Vot is valence band valence band thermal hole (BTBTHH))愔 兀 兀 汲 汲 汲 汲 汲 汲 。 。 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于 关于

15 1338375 P950202 22692tNvfd〇c/n == proceeding; characterization and erasing, as shown in the figure and figure milk, operation 2 = unit structure for single-bit 裎 及 and erase = reference о 4C, Applying a fourth positive undulation on the gate 4〇6: Γη)' and applying a first doping region 4〇4a and a second doping region to the dynamite #$reference® 4D' The second negative is ^^^), and the first doping region _ and the second doping region (Vs=0 volts 'v (four) volts) can be erased by the Fuller_Nordheim (FN) method. The memory unit. After the number of operations of the interface between the W substrate and its upper layer is gradually increased, the Dlt_'2 memory can not be reduced, and the operation of the handsome unit is improved. . & Poor retention can be limited by the gradual increase in the number of cycles. The above example has been disclosed in the preferred embodiment, but it is not based on any paste technique. x Guardian's stipulations, please define the patent scope [Simplified illustration] Figure 1 is a conventional SONOS memory unit after the initial operation and after 10,000 times ^ :·.. 16 1338375 P950202 22692twfdoc / n cycle Iv chart. Fig. 2A is a schematic cross-sectional view showing a memory cell structure in a two-bit stylized operation in accordance with a first embodiment of the present invention. Fig. 2B is a schematic cross-sectional view showing the structure of the memory cell of Fig. 2A in a two-bit erase operation. Figure 2C is a cross-sectional view showing the memory cell structure of Figure 2A in a single bit stylized operation. Figure 2D is a cross-sectional view showing the memory cell structure of Figure 2A in a single bit erase operation. Fig. 3A is an I-V graph of the memory cell structure of Fig. 2A after the two-element stylized operation is initially performed with 15K cycles and 30K cycles. Fig. 3B is an I-V graph of the memory cell structure of Fig. 2A after the two-bit erase operation is performed at the beginning and after 15K times and 30K cycles. Fig. 4A is a cross-sectional view showing a memory cell structure in a two-element stylization operation in accordance with a second embodiment of the present invention. Fig. 4B is a schematic cross-sectional view showing the structure of the memory cell of Fig. 4A in a two-bit erase operation. Figure 4C is a cross-sectional view showing the memory cell structure of Figure 4A in a single bit stylized operation. Figure 4D is a cross-sectional view showing the memory cell structure of Figure 4A in a single bit erase operation. [Main component symbol description] 200, 400: germanium substrate 17 1338375 P950202 22692twfdoc/n 202, 402: capture layer 204a, 404a: first doped region 2〇4b, 404b: second doped region 206, 406: gate 208: first oxide layer 210: high interface capture density material layer 212: second oxide layer 408: first dielectric layer 410: second dielectric layer 412: interface

18

Claims (1)

99-11-11 1338375 X. Patent application garden: 1. A memory cell structure comprising: a germanium substrate; a germanium charge trapping layer on the germanium substrate; a first doped region and a second doped region respectively located a 闸 〇Ν〇 charge trap layer on both sides of the substrate; a gate on the 0 Ν 0 charge trap layer; and a high interface capture density (high-Dit) material layer, located on the 矽 substrate and Between the charge trapping layers, wherein the interface trap density (Dit) between the high interface capture density material layer and the stone substrate is between 1011 and lOAm^eV·1. 2. The memory cell structure of claim 1, wherein the interface capture density between the high interface capture density material layer and the germanium substrate is lOUcn^eV·1. 3. The memory cell structure according to item 1 of the patent application, wherein the south interface captures a thickness of the street material layer between 1 〇 and 7 〇. 4. The memory cell structure of claim 1, wherein the ifj interface captures a material of the late material layer comprising nitriding. 5. The memory cell structure according to claim 1, wherein the material of the interface to capture the density material layer comprises: (2), (2, 2, 2, 2, 2, 2, 2, 2, 2 〇xNy), Hf〇xNy, HfSixOy, ZrSix〇y, Hfsix〇yNz, Al2O3, Titanium Dioxide 〇2), bismuth pentoxide (Ta2〇5), antimony trioxide (La203), cerium oxide (Ce〇2), bismuth ruthenate (Bi4Si2〇丨2), 19 1338375 99-11-11 tungsten oxide ( W03), yttrium oxide (Y2〇3), lanthanum aluminate (LaA103), barium titanate (Ba-xSrxTi03), barium titanate (BaTi03), lead zirconate (PbZr03), lead acid sharp lead (PbSczTai. Z〇3, abbreviated as PST), lead bismuth citrate (PbZnzNbkC^, PZN for short), lead bismuth titanate (PbZrOrPbTi〇3, PZT for short) or lead bismuth citrate (PbMgzNb)-z〇3, referred to as PMN). 6. The memory cell structure of claim 1, wherein the germanium substrate is a p-type germanium substrate, and the first doped region and the second doped region are n-type doped regions. 7. A method of operating a memory cell, the memory cell having a germanium substrate, a germanium charge trapping layer on the germanium substrate, respectively located in the germanium substrate on both sides of the germanium charge trapping layer a first doped region and a second doped region, a gate on the 0Ν0 charge trap layer, and a high interface capture density material layer between the germanium substrate and the germanium charge trap layer, Wherein the interface capture density (Dit) between the high interface capture density material layer and the germanium substrate is between 1011 and H^cm'V·1, and the operation method comprises: privately arranging 5 Applying a 'positive positive waste' to the second doped region, applying a second positive voltage to the second doped region, and making the first doped region 0 volts' to utilize channel hot electrons (channei hot electron , CHE) mode stylizes a bit on one side of the memory cell; when erasing the memory cell, applying a first negative voltage to the gate, applying a third positive voltage to the second doped region, and The first doping region is 0 volts' to take advantage of the valence band The hole (jt〇-band tunneling hot hole 'BTBTHH) method erases the bit on the side of the memory unit. 20 1338375 99-11-11 The operation unit of the memory unit described in item 7 of the patent scope is The first doped region is a source, and the second doped region is a drain. 9· The operating unit of the memory unit described in claim 7 of the patent scope, wherein the first doped region is secret The method of operating the memory unit of claim 7, wherein the first positive voltage is greater than the second positive voltage. 11· Operation of a memory unit The method is applicable to a memory unit, wherein the memory unit has a substrate, and a capture layer on the substrate, respectively located in the substrate on both sides of the charge trap layer. a first doped region and a second doped region, a gate on the germanium charge trap layer, and a high interface capture density material layer between the germanium substrate and the germanium charge trap layer, wherein The high interface captures the boundary between the layer of density material and the substrate The capture density (DU) is between 1011 and ΙΟΑπΓ2^1. The operation method includes: when the memory unit is programmed, applying a fourth positive voltage to the gate, and the first doped region and the second doping The miscellaneous area is 0 volts to program the hate unit using the Fowler-Nordheim 'FN method; ... when erasing the & early memory, a second negative is applied to the gate The voltage, and the δ 第一 first mismatch region and the second doped region are 〇 volts, to erase the memory cell by using a Fuller_Nordheim (FN) method. The method of operating a memory cell, wherein the first doped region is a source and the second doped region is a drain. 13. The method of operating a memory cell of claim U, wherein the first doped region is a drain and the second doped region is a source. twenty one