200836607 U61IUH ^898fwf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種電路板，且特 有埋入式電容元件之電路板。 &有關於-種具 【先前技術】 以電路板可_於封餘板或域組板中。 =封衣基板為例，隨著線路層數的增加鱗路的密隹化， ，裝基板中傳遞之電性訊號，其電阻電 ^ 或串音效應（e聰驗）所造成的影響也越ϋ明 ^。^此，為考量縣基板之電性功能，在製作封裝基板 性ί於雌基㈣部增設鶴元件㈣善封裝基板之電 圖ία至圖m是習知之—種具有埋入式電容元 笔路板製㈣俯視圖，其讀示電容元件。圖2 = =別繪示沿圖1A至圖1H2A_a，線的剖面圖。請參考圖 與圖2A ’此種習知具有埋人式電容元件之電路程 巧下列步驟。首先，提供—第—㈣⑽，並在第 ’自110上形成一電容介電材料層12〇。此外，電容恭二 ，層m具有-凸出部12Ga。為了便於計算電容值，= 介電材料層120-般具有規則的外形，例如是矩形。^ 請參考S 1B與圖2B，在電容介電材料層12〇上 —電極層130，其中電極層13〇具有一凸出部13如，且 出部130a與第一銅箔110相連。 凸 請參考圖1C與圖2C (為了便於說明，圖lc未繪示 200836607 0611011 22898twf.doc/n 核心層140與第二銅箔15〇)，然後，提供一核心層l4〇 與一第一銅箔15〇,並壓合此核心層140、第二銅箔ι5〇 與圖1B或圖2B所示之電容元件半成品。此時，核心層 140位於第二銅箔150與第一銅箔110之間，且電容介電 材料層120與電極層130埋入核心層140内。 請參考圖1D與圖2D (為了便於說明，圖1D未繪示 核層140與第—線路層i5〇a)，然後，對於一 與第二銅心G進行—圖案化製程，以形成—第一線路層0 110a，H路層15Ga，而圖案化製程包括微影製程與 ㈣f程。此外’第一線路層110a具有—第-電極112 二Ϊ極114 ’其中第-電極112與第二電極114相 nf I絕，且電極層130的凸出部130&連接至第一電極 核心圖」E與圖2E(為了便於說明，圖1E未繪示 _第二介層撕、第三㈣I第四鋪 第四銅落174、_：第i+然後，提供—第三輔⑺、- ^ Λ 呆一介電層162與一第二介兩爲、， 三銅落口乂間而第電層八162位於第—線路層_與第 與第四_174〗之^二介電層164位於第二線路層池 ^考圖1F與圖2F (為了便於 核心層14〇、笫-妗々 口 1F未繪不 m與第_介;=a、第三銅箱172、第四銅猪 卑層⑹），然後，進行一鑽孔製程，以形成 200836607 υο ι ιυ i 1 z2898twf.doc/n 多個貫孔（through hole) 100a。值得注意的是，依照目前 的設計規範，貫孔l〇〇a避免貫穿電容介電材料層，且 貝孔100a與電谷介電材料層12〇相隔一預定距離。 請參考圖1G與圖2G (為了便於說明，圖未絡示 核心層140、第二線路層150a、第三銅箱172 ^ 174與第二介電層164)，然後，進行—電鍍製程，以這些 貫孔100a内形成多個鍍通孔（plated如〇11执以^， 180。 請參考圖m與圖2η(為了便於說明，圖m 核心層140、第二線路層150a、第三線路層ma、第二線 ，層174a與第二介電層164)，缝，對於第三銅落m ^四㈣174進行—圖案化製程，以 侧衣程。至此’ Α致完成習知具有埋人式電容元件 之电路板100的製造過程。 度的料，貫孔刚a之間的距離也就越 =越近。然而’由於貫孔驗避免貫穿電容介電材料層 ‘埋因此Λ孔_之_距離也就無法縮小而限制習知 ’【發明2】电谷70件之電路板100的線路佈局設計。 加提供—種具有埋人式電容元件之電路板，以增 加、、泉路佈局設計上的彈性。 曰 件之ΐίΐ =，本發日出—種具有埋人式電容元 电路板，其包括—第—線路層、—電容介電材料層、 7 200836607 uoiwu zz898twUoc/n 包yw興至少一導 層具有一第一電極與相互電性隔絕其中，第—線路 電材料層配置於第一電極金 命 罘一電極。電容介 層具有至少-凹口。電極層配一置二且電容介電材料 上，並與第一電極相連接，且電接频刀第1介電材料層 =。介電層配置於第—線路層上，曰並互電性 與電極層内埋入於介電層中。導带 ^各介電材料層 所暴露之第一線路層。 电貝L貝穿介電層與凹口 在本發明之-實施例中 接觸。 十$貝孔與電容介電材料層 在本發明之-實施例中， 之間相隔一間隙。 貝札…兒各介電材料層 在本發明之一實施例中，凹立> 在本發明之—實施例中，具有^二=分第二電極。 板更包括一第-甘$ 、里入式电容兀件之電路 乐一、、、泉路層，其配置於介 本發明之一實施例中， 曰杠 (讲啊g)或核心層。 ”屯層包括半固化樹脂片 : 線路層的材質包括銅。 膏或其他導電材料二$極層的材質包括銅膏、銀 為解決上述問題，本發明 件之電路板，其包括 ^ I有埋入式電容元 一 Φ托恳 人 路層、一電容介電材料S、 迅極層、-介電層與至少1 ^ I材枓層 層具有-第，-電極邀相互電性^貝其中，第一線路 ㈣絕之—第二電極。電容介 200836607 1 j u j i zz898twf.doc/n %材料層配置於第一電極蛊 層具有至少-開口。上，且電容介電材料 上，並與第一電極相連接，且♦於邛分電容介電材料層 隔絕。介電層配置於第—1極層與第二電極相互電性 ^ 一^银路層μ 與電極層内埋入於介電層中。、▼泰二亚將電容介電材料層 所暴露之第一線路層。 $龟貝孔貝穿介電層與開口 在本發明之一實施例中，I 接觸。 、氣貝孔與電容介電材料層 在本發明之-實施例中， 之間相隔一間隙。 、貝孔與电容介電材料層 在本發明之一實施例中， 在本發明之-實施例中，^ 口暴露出部分第二電極。 板更包括-第二線路層 =有埋入式電容元件之電路 在本發明之-實施4配;::電層上。 核心層。 W %層包括半固化樹脂片或 在本發明之一實施例中， 在本發明之一實施例中，㊆f路層的材質包括銅。 膏或其他導電材料。 兒D層的材質包括銅膏、銀 基於上述，由於本發明採 圖案的電容介電材料層，以避口或開口等不規則 蜮，因此相較於相較於習知;、ι貝孔所預定通過的區 具有較小的間距。此外，本發:直導電貫孔之間 介電材料層，並與電容介電材料芦接=电貫孔貫穿電容 於習知技術，本發明在線路佈局3觸’因此相較於相較 。口又叶上具有較大的彈性。 200836607 uoiiuu z2898twf.doc/n 為讓本發明之上述特徵和優點能更明 舉較佳實施例，並配合所附圖式，作詳細說明如下# 【實施方式】 第一實施例 ，3A至圖3H是本發明之第一實施例之— 入式電容it件之電路板製程的俯視圖， 干j里 件。_至圖4H分猶示沿圖3A至圖 ，面圖。請參考圖3A與圖4A，本實施例之具有埋入式電 谷兀件之電路板製程包括下列步驟。首先，提供—第一導 =層=0，而此第一導體層210可以是铜荡或其他導電薄 在第—導體層21G上形成—電容介電材料層 如，=成電容介電材料層22〇的方法可以是網版印刷製 私。此外，電容介電材料層22G具有凹口 2咖幻勘， 鐵孔製㈣形成的貫孔將會贫穿凹口 22加 厅恭路的弗一導體層21〇，其詳述如 電容介電材料層22。僅具有一個二不 :定二⑽的數量。另外’本實施例之電容介電材料層 〇 =艮定需具有凹口 220b ’而電容介電材料層22〇的 代。22〇b也可以由目1A之凸出部伽或其他圖案所取 一圖3B與圖4B，在電容介電材料層22〇上形成 制r ° ^ 〇。形成電極層230的方法可以是以網版印刷 容介電材料層220上塗佈銅膏層、銀膏層或其 叫包材#，然後再固化形成電極層23q。此外，電極層 10 200836607 ^898twf.doc/n UUllUi j 一H接至电谷介電材料層220的凹口22〇t>所暴露出之第 咬=210並暴路出電容介電材料層220的凹口 220a。 明苓考圖3C與圖4C (為了便於說明，圖3C未繪示 =層240與第二導體層250)，在形成電極層230之後， 棱i、-介電層240與一第二導體層25〇，其中介電層· 脂片或核心層，而第二導體層250可以是 岸Γο盥= 電薄膜。然後’壓合介電層240、第二導體 嫩所示之由第一導體層210與其上的 = '，料層220與電極層23Q所形成之電容元件半成 二：厂二電層位於第-導體層训與第二導體層 之間，且電容介電材料層22〇 層MO内。此外，太審认办丨、， 甩位層230埋入介電 纽甘外本A例亚不限定第—導體層210舆來 、/、上的電容兀件半成品、介電層24〇與 舄同時壓合；箆—蔞鲈爲，1A a 層250 成口二 ¥體層21G與形成於其上的電容元件半 ^也可賴由—半固化樹脂片_合至另 = 或多層線路板（未繪示）。 早層、、泉路板 請參考圖犯與圖仙（為了便於說明，圖4 _ 二笔層240與-第二線路層25〇a)，然後，董 “210與第二導體層250進行、；弗寺體 ―線路層職與-第二線路幻圖^化製程，以形成—第 微影製程與剛程。此外，；;5:例=^^ ^ 250 ： ^ 序。舉例而言，本實施例也可以對;的先後顺 圖案化製程，'然後才對第-導體^^二2 250進行 210進行圖案化製程。 200836607 υυιιυιι ^2898twf.doc/n ϊ ί ¥體層21G進行随化製程，然後才對 體層250進行圖案化製程。若第一導體層21〇與形 成於，、上的電谷兀件半成品只壓合至介電層時 對於第一導體層21〇進行圖案化製程。 /、 人請參考圖3E與圖4E(為了便於說明，圖兕未 =層240、第二線路層25〇a、第三導體層27二 2 274與介電層264)，在形成第一線路層施與第二 274層—it之後，提供—第三導體層272、—第四導體層 逑制介電層262與—介電層264，並壓合這些膜層與上 (圖3D或圖4D所示）所形成的結構物。此時，介 =262位於第-線路層贏與第三導體層奶之間，而 此=層2⑷立於第二線路層25〇a與第四導體層说之間。 他壤’，三導體層π與第四導體層274可以是鋼羯或其 月旨片電薄膜，而介電層264與介電層尬可以是半固化樹 介略4苓考圖3F與圖4F (為了便於說明，圖3F未繪示 2層240、帛二線路層25〇a、帛三導體層272、第 成二27^與介電層264)，然後，進行一鑽孔製程，以形 =個貫孔200a，且這些貫孔2〇〇a貫穿電容介電材料層 徐的凹口 22〇a所暴露出的第二電極214。然而，在另一 只施貫孔200a也可以貫穿第一電極212(未繪示）。 介泰4芩考圖3G與圖4G (為了便於說明，圖3G未繪示 =層240、第二線路層25〇a、第三導體層272、 —_ 274與介電層264)，然後，在這些貫孔2〇如内形成 12 200836607 8 9 8 twf. doc/n uoiιυιi ^固導電貫孔彻，其中導電貫孔細可以是鍍通孔或是 ¥電柱。在本實施例中，導電貫孔彻為導電柱。此外， ，成=貫孔28〇的方法可以是電鍍製程。值得注意的 =貝&例並不限定需形成第三導體層奶與第四導體 層別，而在壓合第一導體層2ί〇與介 剧 可以=接進行形成貫孔2〇〇a與導電貫孔。 介-C3H與圖4H(為了便於說明，圖3h未奢示 二if!、弟二線路層2他、第三線路層272a、第_ 第^導/岛、介電層Μ，然後，對於第三導體層272鱼 2 广于一圖案化製程，以形成-第三線路層 程盘層274a。此外，圖案化製程包括微影製 272與第四導體声二例亚不限定對於第三導體層 而言H ^ 進灯圖案化製程的先後順序。舉例 程，缺對於第三導體層272進行圖案化製 …、俊才對弟四導體屏974、各> π + 對於第四導體層274 ; 二圖-化敁程。或者，先 層功進行圖案化製程。=化然後才對第三導體 埋入式電容元件之電路杯的=、，大致完成本實施例之具有 入式電主容元件之電路板的結構進行詳細說：將就此具有埋 巧繼續參考圖3iJ盥 容元件之電路板包括―第之具有埋入式電 層220、_電極層 ;^層21〇a、-電容介電材料 28〇。其中，第—線_二=_與至少—導電貫孔 電性隔絕之-第二電極加與相互 包合；I電材枓層220配置於 13 200836607 υυι iui i ^898twf.doc/n 第电極212 第一电極214上，且電容介電材料層⑽ ^有-凹口 220a與220b’其中凹π 2施暴露出部分第一 =212。電極層.230配置於部分電容介電材料層22〇上， =接J凹口2施所暴露出之第—電極212，且電極層23〇 =極2M相互電性隔絕。此外，介電層·配置於 二0肉!：層MM上，亚將電容介電材料層220與電極層 230内埋入於介電層240中。 之第導^^L 28G貝穿介電層24G與凹口漁所暴露出 而，導帝二ί 〇與電極層230為不相連。然 導電貫H /與極214也可以不相連。同樣地， 三味路芦279 ^限疋需電性連接至第二線路層25〇a、第 線路層心。值得注意的是，導電 換言之;::介電材料層220的凹口㈣相隔-間隙。 、在本實二^綱與電容介電材料層22G並未接觸。 包括-第二纟具有埋,人式電容元件之電路板更可以 274a、介二2 " ^、第三線路層27以、第四線路層 於介電芦24曰0卜 其中，第二線路層25〇a配置於 與第二線路層25〇a之間。；於第四線路層274a 2仏與第-線路層21Ga之間2於第三線路層 第二線路層25Ga、第三線路^2外’ W貫孔貫穿 介電層初舆264。簡單而_：，H、弟四線路層274a、 容元件之電θ °本貫施例的具有埋入式電 路板為具有四層線路的電路板，然而本實施例 14 200836607 uoiiun z2898twf.doc/n 的具有埋入式電容元件之電路板也可以具有單芦、 二層線路或其他多層線路的電路板。 又、 舉例而言，本實施例的具有埋入式電容元件之 也可以僅具有第—線路層210a。或者，本實施 甩路 )式電容元件之電路板也可以僅具有第—線路‘有^ 弟二線路層挪。或者，本實施例的具有埋人式電i ^ ，電路板也可以僅具有第—線路層2衞、第二二二J 輿第三線請a。或者，本實 式 之電路板也可以僅具有第—線路層21 ^谷兀牛 輿第四線路274a。 、、果路層250a ^ a)因此導電貫孔280的間距就不祐帝6人 %材料層220的圖幸所限制’ 被包谷" 氣右不# _ * 制^之，電容介電材料層220 ;= 則圖案，以避開後續製程所形成的 疋通過的位置。因并，鈿祕 rff™ 土里入式希六- 乂； _知技術，本實施例的具有 性。⑨谷兀之電路板在線路佈局設計上能夠更為彈 复二實 d是ί發明之第二實施例之-種具有埋入式電容 二圖，示電容元件。…示 似，盆不η μ /的剖面圖°本實施例與第一實施例相 奶，其於乂電容介電材料層㈣具有一開口 八5。 口P刀第一電極214，而電極層23〇具有—開 200836607 uonim z2898twf.doc/n 口 232暴露出部分電容介電材料層22〇與開口 222。此外， 導電貫孔貫穿開^ 222戶斤暴露出部分第二電極214。 在本實施例中，導電貫孔280與第二電極214相連，且導 ，貫孔280與電極層23G不相連。同樣地，本發明並不限 ^導電貫孔彻與其他構件的連接關係。值得注意的是， f電貫孔280與電容介電材料層22()之間相隔—間隙。換 $之，導電貫孔280與電容介電材料層22〇不相連。 羞_士貫施例 元件:二:::明之弟三實施例之-種具有埋入式電容 讀之㈣板的俯，其鱗示電容 :圖二ΓΓ線的剖面圖。伽 /、不?之處在於：電容介電材料層22。，不具有凹口 a。換言之，在本實施例中，電容介 — 整的圖案。此外，導電貫孔280直接貫穿電容；料二 逝，並與電容介電材料層22Q，接觸。換言之;^ 280與電容介電材料層22〇,相連。 、包貝孔 1四實笼座 元件式電容 沿圖7A之C_C，線的剖面圖。圖心會示 似，其不同之處在於：f容介貫施例相 孤。換言之，在本實施射不具有開口 I各介電材料層220,為完 16 200836607 U011U11 ^898twf.d〇c/n 整的圖案。此外，導電貫孔28〇直接貫穿電容介 220，，並鱼雷完合兩丨f? i材料層 糊才料層220,接觸。換言之，導恭勺， 280與電谷介電材料層220,相連。 ^^貝孔 基於上述，本糾之具有埋4 少具有下列優點： 开之电路板至 :、由於本發明採用具有不規則 層，其例如具有凹槽_口，二 ί;= 立置’因此相較於習知技街，二 ¥患貝孔之間此夠具有較小的間距。 二、本發接將導孔貫穿電容介電材料層 =較於習知技術，本發明的導電貫孔的能夠具有二小的 雖然本剌已啸佳實_減如上，然其並 發明’任何所屬技術領域中具有通常知識者，在不 ==明之精神和範圍内，當可作些許之更動與潤飾， 2本發明之絲範圍當視_0請專絲_界定者 【圖式簡單說明】 •圖ία至圖m是習知之-種具有埋入式電容元件之 龟路板製程的俯視圖，其僅繪示電容元件。 圖2A至圖2H分別繪示沿圖1A至圖1H之冬A 剖面圖。 w 圖3A至圖3H是本發明之第一實施例之一種呈有埋 入式電容元件之電路板製程的俯視圖，其僅繪示電容元件。 17200836607 U61IUH ^898fwf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board, and particularly to a circuit board of a buried capacitor element. & related - species [previous technology] The board can be used in the enclosed board or domain group board. = Sealing substrate as an example. As the number of circuit layers increases, the scale of the circuit is dense, and the electrical signal transmitted in the substrate is affected by the resistance or crosstalk effect (e-conformity). ϋ明^. ^In this case, in order to consider the electrical function of the substrate of the county, in the production of the package substrate, the addition of the crane element to the female (four) part (four) the electrical diagram of the good package substrate ία to the figure m is a well-known type of embedded capacitive element Plate (4) top view, which reads the capacitive element. Figure 2 = = Do not draw a cross-sectional view along the line of Figure 1A to Figure 1H2A_a. Please refer to the figure and FIG. 2A' for the following steps of the electrical path of the buried capacitive element. First, a - (4) (10) is provided, and a layer of capacitive dielectric material 12 is formed on the first '110. Further, the capacitor has a second portion, and the layer m has a projection 12Ga. In order to facilitate the calculation of the capacitance value, the dielectric material layer 120 generally has a regular shape, such as a rectangular shape. Referring to S1B and FIG. 2B, on the layer of capacitor dielectric material 12, an electrode layer 130, wherein the electrode layer 13A has a protrusion 13 such as, and the outlet portion 130a is connected to the first copper foil 110. Referring to FIG. 1C and FIG. 2C (for convenience of explanation, FIG. 1c does not show 200836607 0611011 22898twf.doc/n core layer 140 and second copper foil 15〇), and then, a core layer 14b and a first copper are provided. The foil 15 is pressed and the core layer 140, the second copper foil ι5 〇 and the capacitor element semi-finished product shown in FIG. 1B or FIG. 2B are pressed. At this time, the core layer 140 is located between the second copper foil 150 and the first copper foil 110, and the capacitor dielectric material layer 120 and the electrode layer 130 are buried in the core layer 140. Please refer to FIG. 1D and FIG. 2D (for convenience of illustration, FIG. 1D does not show the core layer 140 and the first circuit layer i5〇a), and then, for a second copper core G, a patterning process is formed to form a first A line layer 0 110a, an H layer 15Ga, and the patterning process includes a lithography process and a (four) f process. In addition, the first circuit layer 110a has a first electrode 112 and a second electrode 114, wherein the first electrode 112 and the second electrode 114 are nf, and the protrusion 130& of the electrode layer 130 is connected to the first electrode core. E and Figure 2E (for convenience of illustration, Figure 1E does not show _ second layer tear, third (four) I fourth shop fourth copper 174, _: i + then, provide - third auxiliary (7), - ^ Λ The dielectric layer 162 and the second dielectric layer are separated from each other, and the third dielectric layer 162 is located at the first circuit layer _ and the fourth and fourth 174 layers. The second circuit layer pool ^Fig. 1F and Fig. 2F (in order to facilitate the core layer 14〇, 笫-妗々口1F not painted m and the first 介介; = a, the third copper box 172, the fourth copper pig layer (6) Then, a drilling process is performed to form a plurality of through holes 100a of 200836607 υο ι ιυ i 1 z2898twf.doc/n. It is worth noting that, according to current design specifications, the through hole l〇〇a The through hole dielectric material layer is avoided, and the via hole 100a is separated from the electric valley dielectric material layer 12 by a predetermined distance. Please refer to FIG. 1G and FIG. 2G (for convenience of explanation, the figure does not show the core The core layer 140, the second circuit layer 150a, the third copper box 172^174 and the second dielectric layer 164) are then subjected to an electroplating process to form a plurality of plated through holes in the through holes 100a (plated as 〇11 Referring to FIG. 2 and FIG. 2n (for convenience of explanation, FIG. m core layer 140, second wiring layer 150a, third wiring layer ma, second line, layer 174a and second dielectric layer 164) , slit, for the third copper drop m ^ four (four) 174 - the patterning process, to the side of the garment process. So far to complete the process of manufacturing the circuit board 100 with buried capacitive components. The distance between the a and the a is closer to the nearest one. However, 'the hole is prevented from penetrating through the layer of the dielectric material, so the distance of the pupil_the distance cannot be reduced and the conventionality is limited. [Invention 2] Electric Valley The circuit layout design of the 70-piece circuit board 100. The circuit board with a buried capacitor element is added to increase the flexibility of the layout design of the spring road. 曰 ΐ ΐ , , 本 本 本Buried capacitor element circuit board, including - the first circuit layer, the capacitor dielectric material layer, 7 20 0836607 uoiwu zz898twUoc/n The at least one conductive layer has a first electrode electrically isolated from each other, wherein the first-line electrical material layer is disposed on the first electrode, and the capacitor dielectric layer has at least a notch. The electrode layer is disposed on the capacitor dielectric material and is connected to the first electrode, and the first dielectric material layer is electrically connected to the first circuit layer. The dielectric layer is disposed on the first circuit layer, and is electrically connected. The electrode layer is buried in the dielectric layer. Conductor band ^ The first circuit layer exposed by each layer of dielectric material. The electric shell and the recess are in contact with each other in the embodiment of the invention. Ten $Boop and Capacitive Dielectric Material Layers In the embodiment of the invention, there is a gap between them. In the embodiment of the present invention, the recessed body > The board further comprises a circuit of a first-in-one, a immersed capacitor element, and a spring layer, which is disposed in an embodiment of the invention, a crowbar or a core layer. The enamel layer includes a semi-cured resin sheet: the material of the circuit layer includes copper. The material of the paste or other conductive material includes a copper paste and silver. To solve the above problems, the circuit board of the present invention includes a buried The input capacitor element Φ 恳 恳 恳 、 、 、 一 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少The first line (four) is absolutely the second electrode. The capacitor layer 200836607 1 juji zz898twf.doc / n % material layer is disposed on the first electrode layer has at least - opening, and the capacitor dielectric material, and the first electrode Connected, and ♦ is separated from the dielectric material layer of the bipolar capacitor. The dielectric layer is disposed between the first electrode layer and the second electrode, and is electrically embedded in the dielectric layer. The second circuit layer exposed by the capacitor dielectric material layer. The turtle shell hole penetrates the dielectric layer and the opening. In one embodiment of the invention, the I contact, the gas hole and the capacitor In the embodiment of the invention, the layers of electrical material are separated by a gap. Electrical Material Layer In one embodiment of the present invention, in the embodiment of the present invention, a portion of the second electrode is exposed. The board further includes a second circuit layer = a circuit having a buried capacitive element in the present invention - The implementation of 4:;: on the electrical layer. Core layer. W% layer comprises a semi-cured resin sheet or in an embodiment of the invention, in one embodiment of the invention, the material of the seven-way layer comprises copper. Paste or other conductive material. The material of the D layer includes copper paste and silver. Based on the above, the layer of the capacitor dielectric material of the pattern of the present invention is irregularly smashed by avoiding openings or openings, and thus is relatively conventional. ;, the area through which the ι beacon is intended to pass has a small spacing. In addition, the present invention: a dielectric material layer between the straight conductive via holes, and a reflow connection with the capacitor dielectric material = electrical through hole through the capacitor The present invention has a greater flexibility in the layout of the circuit 3 and thus has greater flexibility in the mouth and leaves. 200836607 uoiiuu z2898twf.doc/n In order to make the above features and advantages of the present invention more exemplified, the preferred embodiment And with the accompanying drawings, a detailed description is as follows # MODES FOR CARRYING OUT THE INVENTION The first embodiment, 3A to 3H, is a plan view of a process of a circuit board of an input capacitor in accordance with a first embodiment of the present invention, which is shown in FIG. 3A to FIG. Referring to FIG. 3A and FIG. 4A, the circuit board process with the embedded electric grid element of the present embodiment includes the following steps. First, the first conductive layer is provided, and the first conductive layer is provided. 210 may be copper or other conductive thin formed on the first conductor layer 21G - a layer of a capacitor dielectric material, such as = a layer of capacitive dielectric material 22, may be screen printing. In addition, the capacitor dielectric material The layer 22G has a notch 2, and the through hole formed by the iron hole (4) will be poorly passed through the notch 22 and the conductor layer 21 of the hall, which is detailed as the layer 22 of the capacitor dielectric material. There is only one two no: the number of two (10). Further, the layer of the capacitor dielectric material of the present embodiment has a recess 220b' and a dielectric material layer 22'. 22〇b can also be taken from the lumps or other patterns of the head 1A. Fig. 3B and Fig. 4B form r ° ^ 在 on the layer of the dielectric material 22 of the capacitor. The electrode layer 230 may be formed by coating a copper paste layer, a silver paste layer or a cladding material # on the screen printing dielectric material layer 220, and then curing to form an electrode layer 23q. In addition, the electrode layer 10 200836607 ^898twf.doc/n UUllUi j -H is connected to the recess 22 of the electric valley dielectric material layer 220 and the first bite is exposed 210 and the capacitive dielectric material layer 220 is violently discharged. Notch 220a. 3C and FIG. 4C (for the sake of convenience, FIG. 3C does not show the layer 240 and the second conductor layer 250), after forming the electrode layer 230, the rib i, the dielectric layer 240 and a second conductor layer 25 〇, wherein the dielectric layer is a grease film or a core layer, and the second conductor layer 250 may be a bank Γ 盥 = an electric film. Then, the dielectric layer 240 and the second conductor are shown by the first conductor layer 210 and the upper portion of the '=, the material layer 220 and the electrode layer 23Q are formed in two: the second layer of the factory is located at the second - between the conductor layer and the second conductor layer, and the layer of capacitive dielectric material 22 within the layer MO. In addition, too much review, 甩 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 230 Simultaneously pressing; 箆-蒌鲈, 1A a layer 250 into two layers 21G and the capacitive element formed thereon can also be used - semi-cured resin sheet - combined to another = or multilayer circuit board (not Painted). For the early layer, the spring road board, please refer to the figure and figure (for convenience of explanation, Figure 4 _ two-layer layer 240 and - second circuit layer 25〇a), then, "210" and the second conductor layer 250, ;fu Temple body - line layer job and - second line magic map ^ process, to form - the first lithography process and the straight process. In addition,;; 5: example = ^ ^ ^ 250: ^ order. For example, This embodiment can also be used to perform a patterning process for the first-conductor ^ 2 2 250. Then, the patterning process is performed on the bulk layer 250. The first conductor layer 21 is patterned by the first conductor layer 21 and the formed nano-products formed on the dielectric layer. /, please refer to FIG. 3E and FIG. 4E (for convenience of explanation, the layer is not = layer 240, the second circuit layer 25A, the third conductor layer 27 2 274 and the dielectric layer 264), in forming the first line After the layer is applied to the second 274 layer-it, the third conductor layer 272, the fourth conductor layer, the dielectric layer 262 and the dielectric layer 26 are provided. 4, and press the film layer and the structure formed on the upper (shown in Figure 3D or Figure 4D). At this time, the mediation = 262 is located between the first circuit layer and the third conductor layer milk, and this = layer 2(4) is located between the second circuit layer 25〇a and the fourth conductor layer. The third conductor layer π and the fourth conductor layer 274 may be a steel crucible or a thin film of the dielectric layer, and the dielectric layer 264 The dielectric layer 尬 can be a semi-cured tree. FIG. 3F and FIG. 4F (for convenience of explanation, FIG. 3F does not show the two layers 240, the second two-layer layer 25 〇 a, the third three-conductor layer 272, and the first layer. And a dielectric layer 264), and then performing a drilling process to form a through hole 200a, and the through holes 2〇〇a are exposed through the notch 22〇a of the layer of the capacitor dielectric material The second electrode 214. However, the other through hole 200a can also penetrate the first electrode 212 (not shown). The reference to Fig. 3G and Fig. 4G (for convenience of explanation, Fig. 3G is not shown = The layer 240, the second circuit layer 25A, the third conductor layer 272, the — 274 and the dielectric layer 264) are then formed in the through holes 2, such as 200836607 8 9 8 twf. doc/n uoiιυιi ^ Solid conduction In the embodiment, the conductive through hole is a plated through hole or a power column. In this embodiment, the conductive through hole is completely a conductive column. In addition, the method of forming the through hole 28〇 may be an electroplating process. The example of the shell & .介-C3H and Figure 4H (for convenience of explanation, Figure 3h does not show the second if!, the second circuit layer 2, the third circuit layer 272a, the _th guide / island, the dielectric layer Μ, then, for The three-conductor layer 272 fish 2 is wider than a patterning process to form a third line layering disk layer 274a. In addition, the patterning process includes a lithography 272 and a fourth conductor sound, which are not limited to the third conductor layer. In the case of H ^ into the patterning process of the lamp patterning process, for example, the patterning of the third conductor layer 272 is performed, and the fourth conductor screen 974, each > π + for the fourth conductor layer 274; The patterning process is performed. Alternatively, the layering process is performed on the layering process. Then, the circuit cup of the buried conductor type capacitor element of the third conductor is finally completed, and the input type electric main capacity element of the embodiment is substantially completed. The structure of the circuit board is described in detail: the circuit board which will continue to refer to FIG. 3iJ for the capacitive component includes: the first has a buried electrical layer 220, the _ electrode layer; the layer 21 〇 a, the capacitor dielectric material 28〇. Among them, the first line _ two = _ and at least - the conductive through hole is electrically isolated - the second electrode plus The I electrode material layer 220 is disposed on the first electrode 214 of the first electrode 212, and the capacitor dielectric material layer (10) has a recess 220a and 220b' Wherein the concave π 2 application exposes a portion of the first = 212. The electrode layer .230 is disposed on the portion of the capacitor dielectric material layer 22, = the junction of the J-notch 2 to expose the first electrode 212, and the electrode layer 23 〇 = The pole 2M is electrically isolated from each other. Further, the dielectric layer is disposed on the layer MM: the capacitor dielectric material layer 220 and the electrode layer 230 are buried in the dielectric layer 240. The ^L 28G shell-through dielectric layer 24G is exposed with the notch fishing net, and the conductive layer is not connected to the electrode layer 230. However, the conductive cross H / the pole 214 may also be disconnected. Similarly, the three-flavored road reed 279 ^Limited to be electrically connected to the second circuit layer 25A, the first layer of the line. It is worth noting that the conduction is in other words;:: the recess (4) of the dielectric material layer 220 is separated by - gap. ^ The interface with the capacitor dielectric material layer 22G is not in contact. Included - the second 纟 has buried, the circuit board of the human capacitive element can be 274a, 介二 2 " ^, The circuit layer 27, the fourth circuit layer is in the dielectric reed 24b, the second circuit layer 25A is disposed between the second circuit layer 25A, and the fourth circuit layer 274a 2 - between the circuit layer 21Ga 2 in the third circuit layer, the second circuit layer 25Ga, and the third line ^2 outside the through hole through the dielectric layer initial 264. Simple and _:, H, the fourth circuit layer 274a, the capacity The circuit board of the present embodiment has a buried circuit board which is a circuit board having four layers of lines. However, the circuit board having the buried capacitor element of the embodiment 14 200836607 uoiiun z2898twf.doc/n may also have Single reed, two-layer line or other multi-layer circuit board. Further, for example, the buried capacitor element of the present embodiment may have only the first wiring layer 210a. Alternatively, the circuit board of the circuit type capacitive element of the present embodiment may have only the first line ‘the second line layer. Alternatively, in the embodiment, the buried circuit type i ^ may be used, and the circuit board may have only the first circuit layer 2 and the second circuit 2 舆 third line. Alternatively, the circuit board of the present embodiment may have only the first line layer 21, the valley line 274a. , fruit road layer 250a ^ a) Therefore, the spacing of the conductive through-hole 280 is not limited to the 6-member material layer 220 of the emperor Layer 220; = pattern to avoid the position of the enthalpy formed by subsequent processes. Because of this, the secret rffTM soil into the Greek six- 乂; _ know the technology, the nature of this embodiment. 9 Gu Yu's circuit board can be more flexible in the layout design. d is the second embodiment of the invention - a type of buried capacitor, showing the capacitive element. The cross-sectional view of the basin is not η μ /. This embodiment is milked with the first embodiment, and has an opening 八 5 in the tantalum capacitor dielectric material layer (4). The first electrode 214 of the P-pole is formed, and the electrode layer 23 has an opening. The opening 222 exposes a portion of the capacitor dielectric material layer 22 and the opening 222. In addition, the conductive through hole exposes a portion of the second electrode 214 through the opening. In this embodiment, the conductive via 280 is connected to the second electrode 214, and the via 280 is not connected to the electrode layer 23G. Similarly, the present invention is not limited to the connection relationship between the conductive vias and other members. It should be noted that the f-electrode hole 280 is separated from the capacitor dielectric material layer 22 () by a gap. In other words, the conductive via 280 is not connected to the capacitor dielectric layer 22A. Shame _ Shi Guanshi Example Component: Two::: Ming's three-in-one embodiment - a type of embedded capacitor Read (4) board's pitch, its scale capacitance: Figure 2 ΓΓ line profile. The gamma /, is not: the capacitor dielectric material layer 22. , does not have a notch a. In other words, in this embodiment, the capacitance is a uniform pattern. In addition, the conductive via 280 directly penetrates the capacitor; the material dies and contacts the capacitive dielectric material layer 22Q. In other words; ^ 280 is connected to the layer of capacitive dielectric material 22 。. , Baobeikong 1 four solid cage seat component capacitor along the C_C of Figure 7A, the cross-sectional view of the line. The heart of the picture will be similar. The difference is that the f is the same as the case. In other words, in the present embodiment, the dielectric material layer 220 is not provided with the openings I, and is a complete pattern of 16 200836607 U011U11 ^898twf.d〇c/n. In addition, the conductive through hole 28 〇 directly penetrates the capacitor dielectric 220, and the torpedo finishes the two layers of the material layer 220, and contacts. In other words, the guide 280 is connected to the electric valley dielectric material layer 220. ^^贝孔 Based on the above, this correction has the following advantages: The circuit board is opened to: Since the invention adopts an irregular layer, it has, for example, a groove_port, a ί; Compared with the conventional technology street, there is a small gap between the two holes. Second, the present invention connects the via hole through the capacitor dielectric material layer. Compared with the prior art, the conductive via hole of the present invention can have two small size, although the 剌 剌 has been 佳 佳 _ _ Those who have ordinary knowledge in the technical field, in the spirit and scope of the === Ming, when some changes and refinements can be made, 2 the scope of the invention is to be regarded as a _ _ definer [simple description] • Figure ία to Figure m are top views of a conventional turtle board process with embedded capacitive elements, which only show capacitive elements. 2A to 2H are cross-sectional views along the winter A of FIG. 1A to FIG. 1H, respectively. Fig. 3A to Fig. 3H are plan views showing a process of a circuit board having a buried capacitor element according to a first embodiment of the present invention, which only shows a capacitor element. 17
200836607 υυ i 1 u 1 j ^z,898twf.d〇c/B 圖4A至圖4H分別繪示沿圖3A至圖3H之B-B’線的 剖面圖。 圖5A是本發明之第二實施例之一種具有埋入式電容 元件之電路板的俯視圖，其僅繪示電容元件。 圖5B繪示沿圖5A之C-C’線的剖面圖。 圖6A是本發明之第三實施例之一種具有埋入式電容 元件之電路板的俯視圖，其僅繪示電容元件。 圖6B繪示沿圖6A之B-B’線的剖面圖。 圖7A是本發明之第四實施例之一種具有埋入式電容 元件之電路板的俯視圖，其僅繪示電容元件。 圖7B繪示沿圖7A之C-C’線的剖面圖。 【主要元件符號說明】 100:習知具有埋入式電容元件之電路板 100a :貫孔 150a :第二線路層 110 :第一銅箔 162 :第一介電層 110a :第一線路層 164 :第二介電層 112、212 :第一電極 172 :第三銅箔 114、214 :第二電極 172a :第三線路層 120 :電容介電材料層 174 :第四銅箔 120a :凸出部 174a :第四線路層 130 :電極層 180 :鍍通孔 130a :凸出部 200a :貫孔 140 :核心層 210 :第一導體層 150 :第二銅箔 210a :第一線路層 18 200836607 fH 7 …u v u ^2898twf.doc/n 220、220’ ：電容介電材料層 222、232 :開口 220a、220b :凹口 230 :電極層 240、262、264 :介電層 250 :第二導體層 250a :第二線路層 272 :第三導體層 272a :第三線路層 274 :第四導體層 274a :第四線路層 280 :導電貫孔200836607 υυ i 1 u 1 j ^z, 898 twf.d〇c/B FIGS. 4A to 4H are cross-sectional views taken along line B-B' of FIGS. 3A to 3H, respectively. Fig. 5A is a plan view showing a circuit board having a buried capacitor element according to a second embodiment of the present invention, which only shows a capacitor element. Fig. 5B is a cross-sectional view taken along line C-C' of Fig. 5A. Fig. 6A is a plan view showing a circuit board having a buried capacitor element according to a third embodiment of the present invention, which only shows a capacitor element. Fig. 6B is a cross-sectional view taken along line B-B' of Fig. 6A. Fig. 7A is a plan view showing a circuit board having a buried capacitor element according to a fourth embodiment of the present invention, which only shows a capacitor element. Fig. 7B is a cross-sectional view taken along line C-C' of Fig. 7A. [Description of Main Component Symbols] 100: A circuit board 100a having a buried capacitive element is known: a through hole 150a: a second wiring layer 110: a first copper foil 162: a first dielectric layer 110a: a first wiring layer 164: Second dielectric layer 112, 212: first electrode 172: third copper foil 114, 214: second electrode 172a: third wiring layer 120: capacitor dielectric material layer 174: fourth copper foil 120a: protrusion 174a The fourth circuit layer 130: the electrode layer 180: the plated through hole 130a: the protruding portion 200a: the through hole 140: the core layer 210: the first conductor layer 150: the second copper foil 210a: the first circuit layer 18 200836607 fH 7 ... Uvu ^2898twf.doc/n 220, 220': capacitor dielectric material layers 222, 232: openings 220a, 220b: recess 230: electrode layers 240, 262, 264: dielectric layer 250: second conductor layer 250a: Two wiring layers 272: third conductor layer 272a: third wiring layer 274: fourth conductor layer 274a: fourth wiring layer 280: conductive via holes
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