TW200835923A - System and method for detecting non-cathode arcing in a plasma generation apparatus - Google Patents

Abstract

A system and method for detecting the potential of non-cathode arcing in a plasma generation apparatus, such as a physical vapor deposition chamber. The system and method involve computing a statistical parameter of cathode-arcing event data in the chamber and performing a pattern recognition technique to a moving average of the statistical parameter.

Description

200835923 IX. INSTRUCTIONS OF THE INVENTION [Technical Fields of the Invention] The present invention relates to systems and methods for detecting the risk of non-cathode arcing in a plasma generating apparatus, and more particularly to correlating the sensed cathode arcing The data performs a multivariate statistical analysis to determine the system and method for the risk of non-cathode arcing in the physical vapor deposition chamber. [Prior Art] Sputter deposition such as physical vapor deposition (PVD) is a process for depositing a thin and highly uniform layer of various materials onto a plurality of objects, for example, depositing a metal layer onto a substrate, such as forming an integrated body. A wafer or the like used in the circuit (1C). In direct current (DC) sputtering, the material to be deposited (target) and the substrate that will receive the deposited material (wafer) are placed in a dedicated vacuum chamber. The vacuum chamber is evacuated and then purged with a low pressure such as argon at a low pressure. The wafer is electrically connected to the anode (or its vicinity) of the high voltage power supply, which is typically at or near ground potential. The wall of the sputtering chamber is also at this potential. A target, typically formed of metal, is placed in a vacuum chamber and electrically connected to a cathode of a high voltage power supply. The target can also be formed from an insulating material. An electric field is generated between the target (cathode) and the anode with a power supply. When the potential between the anode and the cathode reaches 200-400 volts, a glow discharge is established in the blunt gas of the superconducting region of the well-known Paschen curve. When the glow discharge is operated in the superconducting region of the Paschen curve, the bidding electrons are split from the gas and flow to the anode (ground), and the last positively charged ionized gas atoms (ie, the electric paddle) are accelerated across the electric field. Potential and -4- 200835923 impact the cathode (target) with sufficient energy to allow the molecules of the target material to be physically separated from the target 'or 'sputtered'. The ejected atoms actually travel unimpededly through the low pressure gas and plasma, some of which land on the substrate and form a coating of the target material on the substrate. Under ideal conditions, the result is a large group of uniform target molecules in the chamber, leaving a final thickness of uniform deposition on the chamber and its contents (eg, wafer). This coating is generally isotropic and conforms to the shape of the object in the chamber. The natural result of this action is that the target material becomes thinner as more material is sputtered with 0. The processing of the integrated circuit depends on the uniformity of the coating due to the glow discharge treatment. The vacuum chamber containing the discharge and target material is carefully designed to attempt to maintain a uniform electric field, and again according to the Paschen curve, the glow discharge can be maintained over a range of electric field forces. However, the uniformity of the electric field cannot be fully maintained, and some factors affect the uniformity and wear and tear of the glow discharge on the target, including the thermal current generated in the room and other mechanical anomalies such as misalignment of the target. To compensate for these anomalies, commercial PVD sputtering machines are often combined with a mechanism that rotates large magnets at a fixed speed on the 'target. This rotation is used to disturb the electromagnetic field in the chamber, and the area where the plasma is hit in the target is concentrated on the smaller and moving areas. Maintaining the fixed power in the chamber while rotating the magnet at a fixed rate increases the uniformity of target wear, increases target life, and generally maintains a more uniform distribution of molecular target materials in the chamber. Local geometry, heat, and other changes cause changes in the lumped electrical impedance of the chamber as the magnet rotates over the target. The relationship between the chamber voltage and the current required to maintain the fixed power changes depending on the impedance change due to the power supply that is assembled to carry the fixed power to the glow discharge. If the monitoring room voltage and the current -5-200835923 flow, a clear periodic change of the chamber voltage and current can be observed, and the period is equal to the rotation period of the magnet. Even with a rotating magnet mechanism properly attempting to stabilize the glow discharge, certain conditions still result in local concentration of the electric field, enabling the glow discharge to pass through the superconducting region of the Paschen curve to the arcing region. Arcing during PVD results in unwanted low impedance paths from the anode to the target via electrons or ions in the plasma. Unwanted paths typically include grounding, and arcing due to a number of factors, such as contamination of the target material ( That is, inclusions, inclusions in the structure of the target (eg, surface), improper target alignment (eg, improper alignment of the cathode and anode), vacuum leaks, and/or from such as vacuum grease Other sources of pollution and other factors. Target contamination includes si〇2 or ai2o3. Arcing during PVD is one of the reasons for reduced yield defects when forming integrated circuits on semiconductor wafers. Although general metal deposition is typically less than 1 micron thick, arcing results in locally thicker deposits of metal on the wafer. When arcing occurs, the energy of the chamber's electromagnetic field concentrates in areas that are smaller than the desired target (eg, , near the target defect, this will remove the solid fragment of the target. The solid segment of the removed target material is larger than the expected uniform coating thickness on the wafer, and if a large segment falls on the wafer, it may cause failure of the integrated circuit to be formed at that location. Subsequent photolithography processes etch away various areas of the deposited metal layer depending on the desired circuit pattern, leaving a metal conductor path. Since arcing results in local defects (regions) having a thickness greater than that of the surrounding metal, it is not possible to completely etch the defective regions in subsequent processing, resulting in unwanted circuit paths (i.e., short circuits) on the wafer. The semiconductor wafer has a plurality of metal layers separated by an insulator layer, and respective metal levels are formed by depositing, patterning, and etching metal layers as described above in -6-200835923. Local defects in one layer can also distort the overlay pattern imaged onto the wafer during subsequent photolithography steps, thus resulting in defects in the overlay. Wafers that make current integrated circuits contain thousands of individual processing steps, with the increasing number of individual wafers and the final individual integrated circuit dies. Arcing in PVD sputtering equipment used to process wafers into integrated circuits may render portions of the wafer unusable for its intended purpose&apos; thus increasing manufacturing costs. The use of target materials that do not produce arcing inclusions is one of the ways to minimize manufacturing circuit defects, and the target material may be contaminated during or after its manufacture. Target contamination is detected prior to the sputtering operation to prevent arcing defects, both in terms of time and expense. It is also expensive to find the arcing defect in an instant manner, which is equally expensive, for example, by the manufacturer operating the deposition chamber until the target content that produces the arc is completely sputtered. Moreover, when the solid segment of the target is removed during the arcing, the surface of the target is further destroyed, and the possibility of future arcing in the vicinity increases. Lack of instant arc detection and improved action based on available parameter data. Measuring the number of defective layers due to arcing is relatively expensive, such as by an electrical test designed to find a short circuit, or by scanning the surface of the wafer with a laser after metal deposition. These tests take time to operate, delay production, or cause unwanted yield losses due to prolonged time. Since defects such as any degree of short circuit may affect the function of the integrated circuit, it is desirable to avoid damage caused by arcing during sputtering deposition. Therefore, real-time arc detection can identify the source of production loss faster, and the circuit manufacturing application is more effective in 200835923 and in detecting the initial failure of the processing tool or the target itself. As noted above, arcing may deposit solid material into the chamber, and any such segment of the solid material on the wafer of the integrated circuit may be less than the height of the integrated circuit. Therefore, a statistical indication of the damage to the integrated circuit is the assumption that occurs during the processing step because the violent arcing may be to a wider area than the relatively "mild" arcing solid material, so The expected damage caused is that the single energy delivered to the arc is reasonable. Therefore, it can be estimated that the number of arcs in the PVD sputtering process step and the severity of the instantaneous arcing are both effective in the possible damage caused by the system PVD sputtering step, and it is known that when the glow discharge process is performed The total number of impedances in the arc is rapidly decreasing. When this occurs, the series electricity in the drive point impedance of the power delivery system containing the power mechanism causes the voltage observed between the anode and cathode of the chamber to 値 the chamber voltage and compares it to the fixed threshold to detect arcing. The pass method can be done quickly by attaching a general oscilloscope to the cathode and attaching the ground wire to the chamber. With an average estimate that can be seen with the naked eye by observing the voltage, the oscilloscope's trigger point can be set to be higher than expected (the voltage observed in this way is relative to the oscilloscope). When the oscilloscope is triggered, the shape due to arcing can be observed, and the product hypothesis can be lowered by the appropriate current sourcing to the number of arcs that can be destroyed to the wafer. Extending more of the bulk circuit wafers to increase the function also occurs during the estimation of special features. At the time, the existence of the collection and interconnection of the room will decrease rapidly. The existence of the view of the oscilloscope probe with a free operating room to handle the voltage of the voltage of the voltage is the last voltage wave pin to observe the current -8- 200835923. This method of simulating the detection of arcing has been issued and the number of systems thus obtained in the course of the processing step has been calculated. A known disadvantage of this approach is that the fixed trigger level must be carefully set as the chamber voltage periodically changes as the magnet rotates as described above, as well as during the PVD processing steps due to heat and other considerations. As a result, such systems may miss a small number of arcs that still cause damage. Systems that can more closely follow the true, instantaneously expected chamber voltage enable these arcs to be detected more quickly, and φ provides a more accurate estimate of damage. In the PVD process for producing integrated circuits, arcing conditions of less than 1 microsecond are generally observed. Arcing during the duration of these short circuits is often referred to as micro-arcing. An electronically controlled analog or switched power supply is unable to react to this rapid change in chamber impedance during micro-arcing. Due to the natural consequence of series inductance, the power supply delivers nearly constant current to the chamber during micro-arcing. It is assumed that during the arcing condition, all the energy transported by the power supply is concentrated on the arc, and the energy delivered to the individual arcs can be multiplied by the voltage supplied by the power supply (presumably fixed) during the arcing interval. Estimate by the integer of the product. In addition, there are digital oscilloscopes that are capable of capturing room voltage and current waveforms during arcing conditions. There are computer software such as Tektronix "Wavestar" that enable digitally stored waveforms to be uploaded to a computer, where the captured voltage and current waveforms can then be doubled point by point to calculate the instantaneous power combined during the arc duration and that The power waveform is used to determine the total energy delivered by the arc. Although useful for understanding the arcing environment when adding PVD applications, the use of oscilloscopes and post-processing computers to calculate the arcing and arcing energy is only a bit of a price for production applications. Even modern portable oscilloscopes are quite large appliances, and the real estate of integrated circuit cleaning rooms is extremely expensive. The stand-alone post-processing computer also takes up expensive floor space and may have to be connected to the oscilloscope via a network outside the clean room, increasing the potential for data transfer between the oscilloscope and the computer. Moreover, there is no way to tell the frequency of an individual arc to understand or arc, leaving a question of how to accurately set the control of the oscilloscope. Oscilloscopes also have limited waveform storage capabilities, so when there is a lot of arcing activity during processing, the oscilloscope tends to lose information when it is most needed. Such a system will make actual control and decision impossible. The various aspects of the present invention address the above disadvantages and also provide arc detection methods and configurations that are also useful for other applications. In addition to the issues discussed, when calculating arcing is only a voltage critical violation, if the power supply reacts to arcing with reduced transport power, some information may be lost or ambiguous. The result of lowering the power tests the drop in both pressure and current. Although the severity of the cathode anode or target arc is a major consideration in the physical vapor deposition chamber, the occurrence of non-cathode arcing (NCA) in the chamber is also a major problem. When NCA occurs, the energy associated with monitoring cathode arcing is typically maintained at zero. Such NCAs are believed to be due to the charging of electrically insulating chamber components (i.e., deposition rings or cover rings) and the sudden release of charge to the wafer or chamber components adjacent to the wafer. There is a question of how to identify the possible and occurrence of such an NCA. The present invention is directed to solving the above problems and other problems, and for the use of the advantages and viewpoints not provided by the conventional system of this type for use in -10 - 200835923. The detailed description of the features and advantages of the present invention is set forth in the <RTIgt; SUMMARY OF THE INVENTION In accordance with the present invention, the present invention is directed to an apparatus and method for detecting arcing during plasma generation, which presents the above challenges and provides a feedback method for controlling film deposition. The invention is illustrated by some implementations and applications, some of which are summarized below. In accordance with an exemplary embodiment of the present invention, a plasma generating apparatus includes a cathode sensing configuration that is communicatively coupled to a power supply circuit. The power supply circuit has a cathode enclosed in the chamber and is designed to generate power related parameters. The arc detection configuration is designed to access the arcing severity in the chamber by comparing the power related parameters with at least one boundary. According to other aspects of the invention, the arc detection configuration is designed to estimate #arc intensity, arc duration, and/or arc energy. In accordance with another exemplary embodiment of the present invention, an arc detection configuration is implemented using a programmable logic controller (PLC). According to another exemplary embodiment of the present invention, the PLC cooperates with the arc detection configuration to calculate an adaptive arcing threshold to reflect a general change in the impedance of the PVD chamber. The instantaneous adaptive arcing threshold is approximated by the PLC. Instantly communicate to the arc detection device. According to another exemplary embodiment of the present invention, the adaptive arcing critical system that reacts to the resistance of the PVD chamber is determined by the arc detection configuration itself -11 - 200835923 using near-instantaneous communication to the PLC Statistics about arcing activities and adaptive arcing critical functions are calculated. The actual micro-arc (e.g., as captured on an oscilloscope) shows a rapid decrease in the voltage 値 (after returning to normal 値) and a rapid increase in the current 値 (and then back to normal 値). Therefore, viewing the peak current level and the voltage level at which the viewing is reduced significantly increases the success rate or confidence level of the "correct" arc detection. The present invention provides an embodiment of a method and apparatus for detecting such arcing events and for detecting and classifying other arcing events. According to another aspect of the invention, the output of the current converter is fed to a programmable threshold comparator of the arc detection unit. In this embodiment, the arcing event is measured by the arc detecting unit as to how many times the current stays above the critical enthalpy and the time at which the current dies above the critical enthalpy. Additional information about the severity of arcing can be counted and eliminated by placing more than one critical threshold (each at a different level) above the nominal operating point and for different critical levels than φ. The time to get it. According to another aspect of the invention, the apparatus includes logic to classify arcing events based on a combination of voltage and current paths from the power supply interface. In addition, the device calculates scan energy and arc energy for events that occur in a particular level of arcing events. In accordance with an illustrative embodiment of the present invention, a method for detecting and classifying arcing in a physical vapor deposition process is provided. The method includes monitoring the power supply voltage and current of the plasma generating device. According to this monitoring, the method includes detecting each instance when the voltage drops below a predetermined first voltage threshold, and the voltage drops -12-200835923 to a predetermined first voltage threshold, and the duration of each instance is peaked. Each instance is detected when a predetermined first current threshold is reached, and the duration of each instance is sequenced when the current peaks above a predetermined first current threshold. The duration of the voltage drop and the duration of the peak on the current can be measured by the clock cycle. The method then includes each instance when the classification voltage drops below a predetermined first voltage threshold and each instance when the current peaks above a predetermined first current threshold as an arcing event. Therefore, a zero arc event can occur from the detected voltage drop and/or current peak. The method additionally includes determining whether the power supply voltage is one of a steady mode, a rising transition mode, or a falling transition mode. Arc events can be calculated or analyzed separately for each of these categories. For example, the method can include maintaining an arcing event and a corresponding duration count when the voltage is in the stable mode, maintaining an arcing event and a corresponding duration count when the voltage is in the rising transition mode, and voltage Is the count of arcing events and corresponding durations that occur when the transition mode is dropped. φ classifies arcing events into different categories based on information obtained from monitoring the power supply voltage and current of the plasma generating equipment. According to an example, during a fixed time period, such as a PLC or other computing device or a scan configuration of a logic configuration or circuitry, the method includes assigning an instance of arcing events in which the voltage drop and current peaks are matched to the first category. Moreover, the method additionally includes assigning an arc event instance having one or more voltage peaks corresponding to one or more voltage peaks having a corresponding duration of less than a predetermined time to the second category 'and will have no accumulation greater than the predetermined time The corresponding instance of the arc event corresponding to one or more voltage drops of the current peak is assigned -13-200835923 to the third category. The method for sensed current arcing event similarly includes assigning an arcing event instance that does not have a corresponding one or more current peaks corresponding to a voltage drop below a cumulative duration of a predetermined time to a fourth category, And assigning an arcing event instance that does not have one or more current peaks corresponding to the voltage drop corresponding to the cumulative duration of the predetermined time to the fifth category. For each of the various categories, the method can include calculating scan energy for the specified arcing event. Detecting arcing events usually results in a drop in power supply (ie, entering the transition mode). In order to avoid including or calculating the transient result as being in the stable mode while the transition mode is lowered, the method additionally includes a transition retention period detection that cannot be detected after each detection of the voltage drop below the predetermined first threshold. The voltage drop below the first threshold and the current peak of the predetermined first threshold cannot be detected for the transition retention period after each detection of the current peak above the predetermined first threshold. Information can still be retained if further analysis is performed for the transition mode. The method also takes into account the slow change in supply voltage (i.e., relative to the arcing event) during the sputtering deposition process that occurs in the stable mode. In this regard, the method additionally includes adjusting a predetermined first voltage threshold during the scan cycle to track a slow change in the supply voltage. According to an example, a method can be established to provide additional information about the severity of the arc. In this regard, the method can include detecting instances of arcing events that fall below a predetermined second voltage threshold, and detecting instances of arcing events where the current peaks reach above a predetermined second current threshold. Similarly, other thresholds can be used to provide even more accurate information. -14- 200835923 According to another example of the present invention, a method of determining an arcing event in a plasma generating apparatus includes monitoring a power supply current, obtaining a current signal indicative of the monitored current, and determining whether the current signal is indicative of an arcing event A step other than the predetermined current threshold. Likewise, the method can additionally include monitoring the voltage of the power supply, obtaining a voltage signal indicative of the monitored voltage, and determining whether the voltage signal is outside of a predetermined voltage threshold indicative of an arcing event. The other method may include sequencing the duration of each arcing event that occurs when the current is outside the predetermined current threshold and when the voltage is outside the predetermined voltage threshold. Furthermore, each arcing event can be classified, and the scanning energy and the arcing energy can be calculated. According to another example of the present invention, a method for detecting arcing in a plasma generating apparatus includes providing power supply to a plasma generating apparatus to establish an ionized gas between a target and a wafer, and providing for detecting supply The interface between voltage and supply current, compare voltage and voltage thresholds at a set frequency, and compare current and current thresholds at a set frequency. In addition, the method includes Φ to determine whether the arcing event occurs from comparing the voltage to the voltage threshold and from comparing the current to the current threshold. The method additionally includes delaying the comparison voltage and the voltage threshold and the current and current threshold by a transition delay period after each detection of the arcing event. Additionally, the method can include viewing other parameters (in addition to voltage or current critical crossing points) to provide further information on any arcing. This can include further information about the severity of the arcing event. According to an example, the method may additionally include generating a power related parameter, comparing the power related parameter with at least a threshold of -15-200835923 to determine an arcing severity comparison power related parameter in the plasma generating device and at least one critical arc; Another aspect of the invention is to provide an apparatus for an arcing event in use. The device includes power supply for detecting a power supply arc detecting unit applied to the plasma generating chamber, and is communicatively coupled to the power supply measuring unit including a critical comparator circuit, the critical ratio being compared with the first voltage threshold The arcing current is compared with the first current threshold to determine that the arc detecting unit includes an analog to digital converter; (DSP) is preferred. In addition, the arc detection unit of the device includes an or system that is configured to determine an arcing event based on the presence. A logic circuit system can be a PLC (PLC) or other similar computing device. In the case of a DSP, the DSP may include performing some of the disclosures disclosed herein. The threshold comparator circuit can be programmed to make the voltage threshold and the initial current threshold better. This uses separate components. The critical comparator circuit is class-level generated in the DSP and converted to digital by analogy in the DSP. The DSP contains parameters that are firmware of the software controlled by the circuitry or configuration. The logic circuitry of the device is used for some of the functions and steps of measuring the response during the duration. To detect the plasma generation chamber interface module, the voltage and current are grouped; and the interface module, the arc detector circuit is configured to determine whether an event occurs and the ratio occurs. The arc-connected digital signal processor is coupled to the logic circuit. The output of the comparator circuit is a programmable logic control, and the voltage and current comparable circuits are better when the logic of some or all of the functions can be set initially. . The critical log converter will send a PLC or other logic. For example, the logic system -16-200835923 is configured to determine whether the voltage is one of a steady mode, a rising transition mode, and a falling transition mode. Additionally, the logic circuitry is configured to maintain a count of arcing events that occur when the voltage is in the stable mode, maintain a count of arcing events that occur when the voltage is in the rising transition mode, and maintain the voltage when The count of arcing events that occur while in the transition mode. The logic circuit system is also configured to determine the duration of the arcing event according to the voltage falling below the threshold of the first voltage, and determine the duration of the arcing event according to the current above the peak of the first current threshold. period. The duration is typically measured in a clock cycle that can be converted to a frequency based on the time unit. The logic circuitry is additionally configured to classify arcing events based on the output of the threshold comparator circuit and the duration of each arcing event. The classification is a predetermined time cycle, such as a PLC scan cycle. The logic circuitry can be configured to assign, for example, an arcing event instance that matches the voltage drop to the current peak to the first category, and that there is no one or more of the coincident current peaks corresponding to φ that is lower than the first predetermined time period. The arcing event instances of the voltage drop are assigned to the second category, and no arcing event instances having one or more voltage peaks corresponding to the current peaks greater than the first predetermined time period are assigned to the third category, and there will be no An arcing event instance having one or more current peaks that correspond to a voltage drop below a cumulative duration of the second predetermined time period is assigned to the fourth category, and will have no cumulative duration greater than the second predetermined time period An instance of the arcing event corresponding to one or more current peaks corresponding to the voltage drop is assigned to the fifth category during the period. The logic circuit can also calculate various parameters of the arc. This can include sweeping energy and arcing energy from 17-200835923. According to another aspect of the invention, an apparatus for detecting arcing in a plasma generating apparatus includes an arc detecting unit communicatively coupled to a current of a power supply. The arc detection unit includes a threshold comparator circuit that is configured to compare the current with the first current threshold, and a logic circuit configured to detect the current and current thresholds in the threshold comparator circuit. Arcing event. The Φ arc detection unit can also be communicatively coupled to the voltage of the power supply. In this example, the threshold comparator circuit is additionally configured to compare the voltage with the first voltage threshold, and the logic circuit system is additionally configured to detect the arc according to the comparison of the voltage in the threshold comparator circuit with the voltage threshold 値event. The arc detection unit additionally includes a timing circuit configured to calculate a duration of the detected arc event based on a comparison of the current and the current threshold. The timing circuit is also configured to calculate the duration of the detected arcing event based on a comparison of the voltage to the voltage threshold. The φ critical comparator circuit can be configured to compare the current with a second current threshold (or a plurality of other critical levels) different from the first current threshold. The critical comparator circuit can also be combined to compare the voltage with one or more other thresholds. The duration of the current or voltage outside of a particular threshold can be calculated straight for each threshold. According to another aspect of the present invention, an apparatus for detecting an arcing event in a plasma generating apparatus includes a power supply interface module that is communicatively coupled to a voltage and current of a power supply for a plasma generating apparatus; The arc detection unit 'has been used to receive fingers. a first channel of the signal indicating the voltage, and a second channel for receiving the signal indicating the current of -18-200835923; and a threshold comparator circuit, located in the arc detecting unit, configured to compare the voltage signal and the voltage Critical 値 and comparison current signals with current critical 値. The device can additionally include logic circuitry to determine whether an arcing event occurs based on the output of the critical comparator circuit. The logic circuitry can also be configured to calculate relevant parameters of the power supplied to the plasma generating apparatus. The logic circuitry can also compare the power related parameters with at least one threshold to determine the severity of the arc in the plasma generating apparatus. The present invention increases the ability to instantly determine when an arc occurs to take an improvement action. This can improve wafer throughput and reduce defects. In some instances, the device that primarily views voltage and current will calculate both the arcing and the final voltage drop (i.e., the reduced power supply from the reaction to the arcing), which will result in an inaccurate count. The present invention additionally provides methods and apparatus for more accurately calculating and classifying arcing. That is to say, by calculating the arc as a current critical violation, even in the presence of a power reduction event, φ will more accurately present the arc in arc count and time statistics. According to another aspect of the embodiment, a method for detecting the risk of non-cathode arcing in a physical vapor deposition chamber is disclosed. The chamber is used to deposit metal on substrates such as germanium wafers or glass panels. The method comprises the steps of: monitoring supply voltage and supply current to a physical vapor deposition chamber; generating a set of cathode arcing event data for each of the plurality of substrates processed in the physical vapor deposition chamber; and according to the group for each substrate Cathodic arcing event data is used to calculate parameters for each of the plurality of substrates. The method additionally includes determining the possible risk of non-cathode arcing based on parameters. 19 - 200835923 After determining the possible risk of non-cathode arcing, the method may include an indication of the risk of non-cathode arcing or the risk of non-cathode arcing. This can be done, for example, by sending a message to a computer display or by turning on appropriate light (e.g., LED). The step of generating a set of cathode arcing event data for each of the plurality of substrates processed in the physical vapor deposition chamber includes obtaining a enthalpy for a plurality of cathode arcing variable types. These may include, for example, "stable arc count stabilization", "arc count up φ liter (or down) transition", and various times and the like. Then, the generating step may include calculating a variable type average for each variable type of each group of cathode arcing event data for each of the plurality of substrates, and for each group of cathode arcing event data for each of the plurality of substrates Variable type calculates the number of variable type standard deviations. The variable type mean and the variable type standard deviation number can be used to generate a set of normalized data for each set of cathodic arcing event data for each of the plurality of substrates. The step of calculating parameters for each of the plurality of substrates based on the group of cathode arc event data includes calculating parameters for each of the φ substrates based on a set of normalized data. Moreover, this may additionally include a variable type that weights the normalized data of the set. The method may additionally include the step of calculating a moving average of the parameters. In this example, the step of determining the possible risk of non-cathode arcing according to the parameter step includes performing a pattern recognition technique on the moving average of the parameters. This may additionally include monitoring the moving average for the increase in the baseline of the moving average. In accordance with another embodiment of the present invention, a method for determining a possible risk of non-cathode arcing in a physical deposition chamber is provided. The method comprises the steps of: coupling a cathode arc detecting unit to a physical vapor deposition chamber; generating a set of cathode arcing event data for each of the plurality of substrates in the chamber -20 - 200835923; and generating an arc according to the cathode Event data to determine the possible risk of non-cathode arcing in the chamber. Generating a set of cathode arcing event data for each of the plurality of substrates processed in the chamber may include monitoring a primary (ie, primary) supply voltage and a primary supply current using a cathode arc detection unit for cathode arcing event data, and Secondary (ie, slave) supply voltage and secondary supply current. The Φ method may additionally include an indication of one of the risks of non-cathode arcing and no risk of non-cathode arcing, depending on the decision step. In addition, the method may additionally include the steps of: generating statistical parameters from the generated cathode arcing event data; calculating a moving average of the statistical parameters; and performing pattern recognition techniques on the moving average. In accordance with another embodiment of the present invention, a system for detecting the risk of non-cathode arcing is provided in a physical vapor deposition chamber for processing a substrate. The system includes a cathode arc detecting unit that is communicatively coupled to monitor the main supply voltage of the physical vapor deposition chamber; a processor 'is coupled to the cathode arc detecting unit (as part of the unit or unit) Communication), which is configured to generate cathode arcing data for each wafer processed in the chamber. The processor is additionally configured to determine the risk of non-cathode arcing in the chamber based on the resulting cathode arcing data. The cathode arc detection unit is additionally communicatively coupled to monitor the main supply current, the secondary supply voltage, and the secondary supply current of the physical vapor deposition chamber. The system may additionally include a first sensor for monitoring the main supply voltage, a second sensor for monitoring the main supply current, and a third sensing-21 - 200835923 for monitoring the secondary supply voltage And a fourth sensor for monitoring the secondary supply current. The processor is configured to generate respective senses for a set of complex variable types from signals received from the respective sensors. The processor can also be configured to calculate an average 値 for each variable type, a standard deviation 各个 for each variable type, and a set of normalized data using the average 値 and standard deviation 値. The processor can also be configured to calculate parameters from a set of normalized materials for each substrate, and to calculate a moving average of the parameters. The system can also include a visible indicator controlled by the processor. In this regard, the processor provides an indication of the possible risk of non-cathode arcing to the visible indicator. Other features and advantages of the present invention will become more apparent from the description of the appended claims. The present invention has been described in detail with reference to the preferred embodiments of the invention The invention is not to be limited to the illustrated embodiments. The present invention is believed to be applicable to different types of electric paddle generating devices and has been found to be particularly useful for film deposition applications which benefit from the technique of arcing detected during the generation of the plasma environment. The illustrative embodiments described herein include PVD sputtering techniques; however, the invention can be implemented in conjunction with various systems, including those using plasma generation techniques such as plasma engraving or plasma enhanced chemical vapor deposition systems (PECVD). . -22- 200835923 Although it has never been possible to completely avoid arcing events, some details on the severity of the arcing that occurs during the sputtering process provide useful information to determine the compensation process. For example, via the instant detection of a single arc of decimals, it is suspected that the presence of minimal defects due to arcing on the affected integrated circuit die. Conversely, the detection of a large number of arcs, or the arcing of a high severity, can be suspected of the existence of many defects, perhaps even reaching a conclusion that the entire processing step is defective. Instantaneous arc detection according to the present invention allows instant or near real-time permission to make manufacturing decisions. For example, if the processing step is considered to be defective due to the detection of arcing severity or a significant amount of arcing, the PVD processing step can be terminated before further damage occurs. At the end of the PVD processing step, termination or normal completion may be determined based on the decision to remediate or discard the wafer before beginning further processing steps. If the initial processing steps are flawed by the apparent detection of the apparent arcing, the processing cost of manufacturing the wafer at this stage is low, and discarding the wafer is cost effective. If arcing occurs during subsequent processing steps, it is cost effective to chemically etch or wafer the wafer to remove the defective deposited layer and reprocess the wafer. In addition, the detection of arcing activity from wafer-to-wafers of individual PVD systems that observe no or minimal previous arcing activity can be an indication of the initial development of equipment error conditions that can be planned during planned equipment inactivity. Proper equipment repair to correct. The focus is on identifying the potential for defects due to arcing in a timely manner. In the case of a particular PVD system, the power supply that drives the process attempts to adjust the power delivered to the chamber. The impedance of the chamber element including the anode, the cathode, and the chamber environment between the anode and the cathode is in series with the impedance of the plasma generating power supply circuit -23-200835923. The relationship between the voltage and current that maintains a fixed power in the plasma is dependent on the impedance of the components of the chamber, including the conductivity of the particular target material itself as a function of the sputtering process. When the arc is developed in the sputtering chamber, the impedance 値 of the chamber drops rapidly, thus changing the impedance of the plasma generating power supply circuit. The power supply and distribution circuitry contains significant series inductance that limits the rate at which current can vary in the circuit. Therefore, due to this sensing component, the rapid drop in chamber impedance causes the impedance of the chamber Φ voltage to decrease rapidly. This collapse of the chamber voltage 値 is usually sufficient to cause the arcing condition to disappear and re-establish the glow discharge before severe damage to the chamber, power supply, or target may occur. Typically, an arcing event occurs (or disappears) faster than an electron that can react to regulate the power supply, so even if the electrons begin to improve the action, there may still be some damage to the wafer. As noted above, due to various arcing events, the likelihood that the coated item will suffer from some form of defect such as uneven coating on the wafer may increase. Since the room voltage drops rapidly as the arcing event occurs, the occurrence of arcing conditions can be defined using an unexpected voltage drop below the predetermined or adaptive φ voltage threshold. According to an exemplary implementation, the voltage threshold describing the presence of an arcing event is applied (i.e., non-arcing), or time, based on the nominal change in chamber voltage. The non-arc chamber voltage applied to the production of glow discharges is based on a number of factors, including the target's conditions and composition (affecting circuit impedance). All other circuit impedances remain fixed, and the use of a relatively low-conducting target material to produce a glow discharge requires a high chamber voltage, whereas conversely, the use of a relatively high-conductivity target material to produce a glow discharge requires a lower chamber voltage. For example, in a sputtering chamber implementation, the chamber voltage required to deposit aluminum uniformly is almost twice the chamber voltage required to deposit copper -24-200835923. The chamber voltage required for uniform deposition may also vary from chamber to chamber, depending on the balance of the circuit impedance including the power supply and other chamber components. Moreover, as the target ages and more material is sputtered, the power required to maintain a uniform deposition rate must be modified (β卩, increase). When the required application voltage changes, the associated threshold voltage that determines the arcing condition should then be changed. In accordance with a general exemplary embodiment of the present invention, a plasma generating apparatus includes an arc detecting configuration that is communicatively coupled to a power supply circuit by φ. The power supply circuit has a cathode enclosed in the chamber, and the power supply circuit is designed to generate power related parameters (e.g., voltage signals). The arc detection configuration is designed to evaluate the arcing severity in the chamber by comparing the power related parameters with at least one threshold. The parameters that determine the severity of the arc are processing dependent, including arcing, arcing rate, arcing intensity, arcing duration, and/or arcing energy, but are not limited thereto. According to one implementation, the arc detection configuration for the sputter treatment monitors the sputtering chamber voltage and detects arcing conditions whenever the chamber voltage 値 falls below the preset arcing voltage by φ 値. According to one point of view, the threshold of power-related parameters (eg, voltage) is variable over the range of power-related parameters. Any threshold can be programmed and can be controlled by a logical configuration, for example, electronically controlled by a remote logic configuration. In an exemplary embodiment, the voltage threshold for the occurrence of arcing is calculated to estimate the nominal chamber voltage 値, and the nominal chamber voltage 値 is required to produce a glow discharge (ie, generate plasma) during non-arcing conditions. Room voltage. In an exemplary embodiment, any threshold may be hysteresis or may be programmed to be -25-200835923 with a "reset" that is different from "over" 値. According to one aspect of the invention, the arc detection configuration is calculated by an additional threshold to calculate the arcing condition (event). The rate of arcing conditions can be determined from this. According to another aspect, the arc detection configuration is additionally designed with force-related parameters and at least one threshold to measure the arc duration. In an implementation, the arc detection configuration includes clock and digital calculations. Φ provides a clock signal with a fixed period. And digital calculations are performed by comparing power-related parameters with at least one threshold to calculate a clock. According to another aspect of the invention, the duration of the arcing condition is estimated by comparing the power-related reference thresholds. The duration of the condition is cumulative during the fixed period according to an example. The root implementation, the duration of the arcing condition is accumulated until it reaches the hold, or until the cumulative duration is reset. According to another aspect, the arc detection configuration is additionally designed with a force correlation parameter and at least one threshold to measure the arc strength. In this case, the arc detection configuration is designed to compare the complex threshold of the power-related parameter arrangement to determine the extent or extent of the power change (from the nominal) during the arcing event. In an example, the critical supply estimate for the maximum observed voltage 値 drop is shown, while the next larger voltage drop threshold (the system is being) provides the upper boundary for the energy estimate. In accordance with another exemplary embodiment of the present invention, the arcing detection is designed to compare the power-related parameters with at least one threshold to the detected ones to compare the electricity. For example, in configuration. The clock is designed to be a signal period. The number and the at least one implementation, the arc is calculated according to another example of the non-continuation period, and the lower boundary is configured to observe the non-arranged design arc duration. -26- 200835923 and strength. In one implementation, the arc detection configuration is additionally designed to measure the arc energy by comparing the power related parameter with at least one threshold, the arc energy is proportional to the product of the arc duration and the arc intensity, and the arc is generated. The estimate of severity is a function of the arc energy (ie, the product of the arcing intensity and the duration of the arc). According to a particular implementation, the complex threshold is used to determine the complex duration to estimate the region-to-upper time φ defined by the power-related parameter (ie, room voltage) during the voltage drop due to arcing (ie, approximating or integrating) Plotting. The arcing energy of each arc event proportional to the defined area is used to estimate the severity of the arc. According to another implementation, the arc detection configuration is additionally designed to accumulate arc energy through a plurality of arcing events, for example, by summing the product of the arcing intensity and the duration of the arc to estimate the arcing severity. According to another exemplary implementation, the arc detection configuration includes a power related parameter band limiting filter as an aliasing prior to preventing digitized power related parameters. A commonly known digital signal processing technique is applied to this digital power • related parameters to reduce or highlight certain frequency response characteristics of power related parameters. This digital signal processing parameter can then be directly compared to at least one critical, identically digitized version. According to another exemplary implementation, the digital signal processing parameters described above are used to calculate at least one time to change the threshold 以 by some of the observed characteristics of one or more of the power related parameters during the PVD process. In accordance with another exemplary embodiment of the present invention, the plurality of power related parameters and the complex threshold are compared when estimating the arcing severity. For example, in addition to the chamber voltage, the power supply current is monitored and used to detect arcing events, which determine the arcing event whenever the current 値 exceeds the preset current threshold. In accordance with another exemplary embodiment of the present invention, the logic configuration is communicatively coupled to the arc detection configuration and is designed to process the arcing data collected by the arc detection configuration. In one implementation, the logic configuration is designed to interface with an arc detection configuration having a data network and other external devices such as a processing controller, a monitor, and a logic configuration. In a particular application, the logical configuration is a programmable logic controller (PLC). According to another exemplary embodiment of the present invention, the arcing duration derived by comparing the power related parameter with the at least one arcing intensity threshold, and the arcing duration are increased to the cumulative arc duration by sequencing. To estimate the severity of arcing in the plasma generation chamber. Another exemplary implementation of the method includes measuring power-related parameters during non-arcing plasma generation and automatically adjusting arcing intensity thresholds by measuring power-related parameters; calculating arcing occurrences; and/or estimating arcing severity as Arcing intensity, a function of the duration of the arc, and/or its product. According to another exemplary embodiment of the present invention, the arc is determined by comparing the arcing intensity derived from the comparison of the power related parameter with the at least one arcing intensity threshold, comparing the power related parameter with the at least one arcing intensity threshold. During the duration, the arc energy is calculated as a function of the arcing intensity and the duration of the arc, and then the arcing energy is increased to the accumulated arc energy to estimate the severity of the arc in the plasma generating chamber. Another exemplary implementation of the method includes measuring power related parameters during non-arc plasma generation and automatically adjusting at least one arc intensity threshold by measuring power related parameters; comparing power related parameters with at least one arc intensity threshold Calculate the arcing occurrence; and/or use the hysteresis arc -28-200835923 intensity threshold; and/or transmit the information representing the arcing to the logical configuration through the shared data path, the information is selected from the amount including the arcing occurrence, the accumulation One of the durations of the arc. In a particular implementation, the power related parameter is a function of the plasma generating chamber voltage; in another implementation, the power related parameter is formed as a digital representation of the operational characteristics of the plasma generating chamber. In describing the following specific exemplary implementations of the invention, reference is made to Figures 1-27 of the drawings in which like numerals represent like features. φ Figure 1 illustrates an exemplary embodiment of the arc detection configuration 1 of the present invention. The arc detection configuration 100 is used, for example, in a pressure vapor deposition (PVD) process step of integrated circuit fabrication or other processing where uniform material deposition is desired. The PVD sputtering system includes a low pressure chamber 15 (vacuum) chamber 10 containing a gas such as argon. The target 20 formed of metal is placed in the vacuum chamber 10 and electrically coupled to the power supply 30 as a cathode through a separate power supply interface module (PSIM) 40. According to an exemplary implementation, coaxial power interconnect cable 35 is used to couple power supply 30 and chamber 10. The substrate (wafer) 25 is coupled as an anode to the power supply 30 via a Φ connection. Typically, the vacuum chamber is also referred to as ground potential. According to another exemplary implementation, the anode is directly in contact with the power supply 30. This includes rotating the magnet 27 to manipulate the plasma to maintain uniform target wear. The PSIM 40 includes a buffer voltage attenuator 44 that is designed to sense the chamber voltage and that provides an analog signal to the arc detection unit (ADU) 50 through the voltage signal path 42 to react to the chamber voltage. The PSIM also includes a Hall effect based current sensor 46 that is designed to sense the current flowing to the chamber and provide an analog signal to the ADU through the current signal path 48 to react to the chamber current. In another exemplary implementation, the target is formed by an insulating material -29-200835923. The ADU 50 is communicatively coupled to the logic configuration 60 via a local data interface 70, such as a programmable logic controller (pLC) or a communication header. The logic configuration can be coupled to the data network 8 〇, for example, a high-order processing control network such as EG Modbus-Plus TCP-ΙΡ on the Ethernet. An electric field is generated between the target (cathode) and the anode by ionizing the gas in the vacuum chamber by the power supply. The ionized gas atoms (i.e., the plasma) are accelerated across the potential of the electric field and impact the target at a high velocity, enabling the molecules of the target material to be physically separated from the target, or, by sputtering,. The ejected molecules actually travel unimpeded through the low pressure gas and plasma, some of which land on the substrate and form a coating of the target material on the substrate. A typical target voltage for sputtering aluminum is approximately 450 volts per second (VDC) steady state.

FIG. 2 illustrates an exemplary embodiment of a PSIM 40. The psiM 40 derivative represents the voltage and current signals of the chamber. Coaxial cable 3 5 is electrically coupled to the φ chamber. Cable 35 has an outer conductor 210 nominally at ground (ground) potential and a center conductor 2 15 that is negatively biased relative to the outer conductor. The current in the cable 35 is measured using a Hall effect converter 220 or other current conversion device. Converter 220 is configured to selectively measure the current flowing in central conductor 215 (representing the total current flowing to the chamber). The central conductor 2 15 of the cable 35 passes through the aperture 225 of the Hall effect converter 220. To expose the center conductor 215, the outer conductor 210 is interrupted near the converter 220, and the current conductor current 230 is coupled to the outer conductor 210 to direct the outer conductor current around the aperture 225. The configuration of the Hall effect converter 220 simplifies the packaging of PSIM -30-200835923 while providing a high degree of galvanic isolation between the cable 35 and the output signal of the converter 220. The invention is not limited to the use of a Hall effect converter. Other mechanisms for deriving a signal that reflects the current flowing from chamber 1 to power supply 30 may also be considered, including configurations with current shunts with appropriate voltage isolation, and mechanisms depending on the particular piezoresistive current converter, but Not limited to this. Converter 220 has a first output terminal 222 with signal I- and a second output terminal 224 with signal +1. The first and second converter output terminals are electrically coupled to the Isense circuit configuration 240, the first converter output terminal 222 is affinityd to the Ishens circuit first input terminal 242, and the second converter output terminal 224 is coupled To the second input terminal 244 of the Isense circuit. The Isense circuit configuration 240 also has a first output terminal 246 with a signal IPSIM- and a second output terminal 248 with a signal IP SIM+. The Isense circuit receives the current signals 1 + and 1 and generates a differential voltage between the signals IPSIM + and IPSIM - to reflect the current flowing from the chamber to the current supply.

The Vsense circuit 250 measures the potential difference between the center conductor 215 and the outer conductor 210 and produces a differential that is reflected in the potential difference. The Vsense circuit includes a first input terminal 252 coupled to the inner conductor 215 and having a voltage signal V-. The Vsense circuit in turn includes a second input terminal 254 coupled to the outer conductor 210 and having a voltage signal V+. The Vsense circuit has a first output terminal 256 with an output voltage signal VPSIM- and a second output terminal 258 with an output voltage signal VPSIM+. In an exemplary implementation, the coaxial cable 35 connecting the power supply 30 to the vacuum chamber 10 is terminated with a standard commercial UHF type connector. According to one aspect of the present invention, the mechanical package of the PSIM 40 is configured and assembled such that the cable 35 can be terminated at one end, inserted through the aperture 225 of the PSIM 40, and re-terminated to complete the power supply 30 and the chamber 10. Circuit between. In another implementation, the PSIM 40 includes a UHF type connector such that the PSIM 40 can be inserted into the circuit of the cable 35 between the power supply 30 and the chamber 10. Figure 3 illustrates providing a differential output voltage signal to reflect the cathode of the PVD system. One of the Vsense circuits 25 0 that differs from the instantaneous voltage between the anode and the anode is exemplified. The exemplary Vsense circuit shown in Figure 3 provides a very high impedance between the voltage signal present at its input terminal and the voltage signal provided at its output terminal. A positive input voltage signal 254(V+) is derived from the outer conductor 210, and a negative voltage signal 252(V-) is derived from the inner conductor 215 of the power supply cable 35. According to the illustrated example, the dream plane 'GNDANALOG, Resistor networks R3 and R4 provide a 500:1 attenuation factor for each respective input voltage signal. Each resistor network R3 and R4 has a nominal resistance of approximately 20 million ohms between the network sensing terminal (pin 1) and the reference plane (pin 3). Resistive networks R3 and R4 can be implemented using, for example, a thick film divider network such as 〇hmcraft P/N CN-470. The 1 000 volt application voltage between 252( + ) and 2 5 4(-) allows 25 microamps of current to flow into pin 1 of R4 and out of pin 1 of R3. Pin 3 of each of these voltage attenuators (ie, the resistor network) is coupled to the reference plane, GNDANALOG. Because each voltage attenuator provides 500:1 fading -32-200835923 minus, the differential voltage measured between pins 2 of each resistor network is attenuated by 5 00:1 (ie, in pin 2 of R4) The attenuation signal VPSA + and the attenuation signal VPSA- in pin 2 of R3), and this measurement is independent of the voltage difference between V + and GNDANALOG or V- and GNDANALOG. In an exemplary implementation, the PVD sputtering chamber 1 has applied radio frequency (RF) energy to stabilize the plasma. The capacitors C2, φ C3, and C5 of the Vsense circuit 25 0 significantly attenuate (ie, filter) this high frequency "noise". According to an exemplary implementation, the combination of C2 and C3 has an effective magnetic pole in approximately 22 kHz. As mentioned above, the differential voltage between VPSA- and VPSA+ is a limited representation of the frequency band of the signal appearing between V- and V+ with a nominal DC attenuation factor of 5 00:1. The equivalent DC Thevenin source impedance between VPSA- and VPSA+ is high (at 80 kOhms) and therefore not suitable for transmission between large distances or into low impedance loads. Therefore, a differential instrumentation operational amplifier U2 such as the LT 1 920 instrumentation amplifier is incorporated in the Vsense circuit to act as an impedance voltage follower. Operational amplifier U2 provides a high impedance input (pins 2 and 3) that will not be significantly loaded into the outputs of attenuators R3 and R4. Pin 2 of resistor network R3 is coupled to the inverting input of U2 (pin 2), and pin 2 of resistor network R4 is coupled to the non-inverting input of U2 (pin 3). In an exemplary embodiment, resistor RG2 sets the voltage gain of U2 and is selected to produce a gain of 1 V/V. The final output of U2 (pin 6) is a single end low impedance voltage source relative to GNDANALOG that closely follows the developed voltage between VPSA- and VPSA+. -33- 200835923 The output of U2 (pin 6) is coupled to the central terminal of BNC type connector J2 with signal VPSIM+ 258. The external connector of the BNC type connector J2 carries the signal VPSIM-256 and is coupled to the reference plane GNDANALOG. The final differential voltage between the signals VPSIM+ and VPSIM- is the frequency band limited by the differential input signals V+ and V- and has a nominal DC response of 2 mV/V. In one embodiment, the Hall effect type DC current converter 220 reacts to flow in the internal power supply conductor 2 when coupled to a suitable load impedance between the signals 244(1+) and 242(1-). The current of the current in 1 5 . In a particular embodiment, a model LA25_P Hall effect type DC current converter fabricated by LEM is used, the current signal developed by DC current converter 220 is approximately 1 000:1 ratio of the total current through aperture 220. Thus, within the limits of the DC current converter design, a constant current of 1 mA through the impedance between 244 (1 + ) and 242 (1-) is generated by the 1 amp signal of aperture 220. Figure 4 illustrates an exemplary implementation of a current sensing configuration. The Isense circuit 240 generates a voltage that is responsive to the current developed by the exemplary LA25-P Hall effect type DC current converter. In this example, signal I- is coupled to the reference plane GNDANALOG of PSIM40. An impedance comprising a 100 Ohm resistor R6 in parallel with a low pass filter comprising resistor R7 and capacitor C10 is coupled between 1 + and I-. Neglecting the relatively high impedance of the low pass filter, current 1 + is flowing through the crystal grouper R6 and back to the current converter 220 via I-. The net result of the circuit comprising current converter 220 and resistor R6 is a voltage across R6 that is proportional to the current flowing through aperture 222, and has a proportionality constant of 100 mV/Ampere. Include resistors -34- 200835923 The R7 and CIO low-pass filters have a nominal 3 dB cutoff frequency of 23 kHz to remove any spurious noise from the current signal, including some of the RF components included above. Glow discharge is stable. The low pass filter output (VIL in Figure 4) is a limited representation of the frequency band developed by current converter 220 across the voltage of R6. Instrumentation amplifier U3, such as LT 1 920, acts as a low impedance voltage follower coupled to the VIL of the non-inverting input (pin 3) of VIL to U3, which is coupled to φ GNDANALOG via resistor R5. The reverse input of U3 (pin 2). In this example, resistor RG1 is used to set the gain of instrumentation amplifier U3 to 1 V/V. The output terminal of U3 (pin 6) carries the signal IPSIM + and is coupled to the central conductor of the BNC type connector J3. The external conductor of the BNC type connector J3 is coupled to GNDANALOG and specifies the signal IPSIM-. The voltage developed between IP SIM+ and IPS IM- is therefore a signal that reflects the current flowing in aperture 220, is limited to a frequency band of a cutoff frequency of about 23 kHz and has a proportionality constant of about 100 mV/Ampere. φ Figure 5 illustrates an exemplary implementation of a PSIM power supply circuit 500 (not shown in Figure 2) and requires biasing of the operational amplifiers U2 and 113. For example, the dual power supply module U1 of the Astrodyne model FDC10-24D15 generates a nominal + 1 5 VDC and -1 5 VDC for biasing the PSIM amplifiers U2, U3 and the current sensor CS1. Module u 1 derives its bias power from an external nominal 24 VDC power supply via connector J1, pins i and 3, and pin 1 is biased to a more positive direction than pin 3. The pin 3 of the connector J1 is coupled to the -Vin terminal of the power supply module U1. Coupling the -35-200835923 pin 3 of the connector J1 to the +Vin terminal of the power supply module U1 via the Schottky barrier diode D2 to protect the module U1 from being accidentally reversed due to the polarity of the power supplied to the connector J1 Broken. The power supply module U1 has three output terminals +Vo, -Vo and Com. The +15 VDC signal is provided at the terminal +Vo and the -15 VDC signal is provided at the terminal-Vo. The terminal Com is coupled to the reference plane GNDANALOG. In an application, pin 2 of connector J1 is also coupled to GNDANALOG as a common potential as needed. Resistors R1 and R2 and light emitting diode D1 are coupled in series between a +15 VDC bias and a -15 VDC bias to provide an indication of operation of PSIM power supply circuit 500. The arc is defined as the collapse in the number of chamber voltages that intersect the threshold voltage. When arcing occurs, the chamber (target) voltage 値 decreases rapidly (i.e., closer to the ground potential) from steady state (i.e., non-arc) conditions, and the chamber current increases more slowly due to the series inductance. The programmed threshold voltage is a predetermined chamber voltage at which the arcing state is determined in or below the predetermined chamber voltage. The predetermined chamber voltage can be a fixed or nominal time varying function, and the expected, potentially time varying chamber voltage. A non-arcing state is determined when the chamber voltage is above the threshold voltage. According to another exemplary implementation, the threshold voltage is determined from a period including a non-arcing state, and an arcing state is defined whenever the chamber voltage is below a voltage threshold. Multiple threshold voltages can be used to determine the number of arcs (ie, voltage drop or "severity"). For example, the severity of an arc that is critical to -200V critical but not -100V critical can be considered to be less severe than the arcing of the two critical crossings. The ADU 50 includes a digital signal processor to process the -36 - 200835923 signals received from the PSIM to provide a digitally filtered representation of the room voltage and current signals (e.g., digital signals) to a logical configuration. According to an exemplary implementation, the ADU includes an analog-to-digital converter (A/D). The ADU is additionally designed to set at least one programmable arcing critical voltage. In another implementation, the ADU is also designed to set at least one hysteresis threshold voltage. According to one aspect, the individual thresholds can be set at any point along the continuous spectrum; this can be affected by the potentiometer setting controlled by the comparator circuit. According to another exemplary implementation, the individual thresholds are digitally set by digital-to-analog converters or by complex separation thresholds achieved by switching specific circuit components into comparator circuit configurations, such as by selecting a resistor network. Combination. To identify the hysteresis threshold, the ADU provides a programmable hysteresis function to detect the arcing of the slow proof itself. Both the arcing (voltage) threshold and the hysteresis function can be directly programmed or programmed into the ADU, or can be selectively controlled by a remote device communicatively coupled to the ADU, for example, via an Ethernet network. Standard Momentum Communication Top Cap, Modbus Plus, • Devicenet, or other data network. In an exemplary implementation, the ADU is firmly coupled to a programmable logic controller (PLC), such as momentum M1-E through a high-speed dedicated serial interface, and the PLC can be programmed to be continuously and continuously employed based on an instant adaptive algorithm. Arcing voltage critical and hysteresis function. 6 illustrates an exemplary embodiment of an arc detection unit (ADU) in accordance with a digital signal processor and controller (DSpc) 63, including a digital signal processor (DSP) integrated circuit, such as available from Dallas, Texas, USA The model TMS320F2407 purchased by Texas Instruments Inc., and other commercially available integrated circuit devices for developing and controlling the -37-200835923 signal to control and communicate with external devices. An example of such a device is an address decoder, which is generally used to divide the address space of the DSP into a plurality of ranges, and select one of the plurality of external integrated circuit devices for data transfer to and from the DSP. The development of these signals using integrated circuits is based on the timing requirements of digital signal processors when accessing external devices, and is known to those skilled in the art of designing and implementing microprocessor- and microcontroller-based systems. . The DSP illustrated by φ includes 16 analog input channels that can be digitized and sampled by the integrated 1 类 bit class analog digital converter 63 5 . Signals such as signals Ich 616 and VCH 614, which will be discussed later, will be digitized and sampled by the DSP at a user programmable rate. In an exemplary implementation, the programmable rate can be increased to 10 kHz per channel. In another exemplary implementation, the software program executable within the DSP provides for selection and application of one of the complex digital finite impulse response filters to the sampled data signal. The DSPC 630 also provides a control signal to the programmable φ-type critical comparator function 620 to set the threshold and hysteresis of the programmable threshold comparator. In addition, the DSPC 63 0 provides control and data paths to and from the High Speed Arc Detection Logic (ADLU) 640, which operates in conjunction with the programmable threshold comparator 620 to accumulate arc statistics, such as the number of arcs and the total arc. Time and so on. The DSPC 63 0 communicates with an external logic interface 60, such as a networked communication top hat or a programmable logic controller (PCL), via a local data interface 70, such as a proprietary ATII interface. Examples of information that can be supplied from the ADU to the external logic configuration 60 are the filtered chamber voltage and current, the number of individual arcing events, and other defects that indicate the severity of the arc, such as the arc-38-200835923 detector unit 64 〇 determined by the person. Examples of data that can be received by an ADU from an external logic configuration are the instantaneous arcing threshold voltage and hysteresis&apos; and the logic control signals that control the arc detection logic unit. The basic sensing processing inputs of the arc detecting unit 50 are differential output signals from the Vsense circuits (VPSIM+ and VPSIM-) of the PSIM 40 and the Isense circuits (IPSIM + and IPSIM-). Referring again to Figure 6, these signals drive analog signal conditioner 6 1 0. The analog signal conditioner 6 10 converts the individual micro-classification ratio signals into signal end signals that can be used by the remainder of the ADU. The signal conditioner 610 also provides a band limiting filter for each input analog signal, such that the DSPC 63 0 can apply digital signal sampling and processing algorithms without the need to be referred to as an "aliased" environment. The analog signal conditioner 6 1 0 includes a three-output terminal: an output terminal 614 that provides a signal VCH, an output terminal 614 that provides a signal VCH, and an output terminal 616 that provides a signal ICH. The signal VCH, which is a single end version of the signal originating from the PSIM and derived from the signal VPSIM + and the signal VPSIM_, is supplied to the programmable threshold comparator 620. The signal VCH is a band-limited, single-end version of the differential signals VPSIM+ and VPSIM_ developed by the Vsense circuit 250 of the PSIM 40. The signal Ich is a band-limited, single-end version of the differential signals IPSIM+ and IPSIM- developed by the Isense circuit 240 of the PSIM 40. The signals Ich and VCH are input to the analog-to-digital converter 63 5 of the DSPC 63 0 . The processing performed by the digital signal processor and controller 630 on these analog signals will be discussed in more detail later. Figure 7 illustrates an exemplary implementation of a voltage chopper portion 700 of a signal conditioner -39-200835923 610 using a commercially available four operational amplifier integrated circuit, such as the analog model AD824 for U27:A-D. Amplifier U27A and resistors R108, R107, RU5, and R116 form a differential amplifier' which converts the differential voltage between VPSIM1 + and VPSIM_ into a single end voltage relative to the reference plane GNDANALOG of the output of amplifier U27A (pin 1) . The output of amplifier U27 A is signal 612 in Figure 6 and is designated VCH'. The VCH' is coupled to an internal network comprising amplifying φ U27B, U27C, and U27D forming a six-pole Butterworth filter having a 3 dB crossover of about 2500 Hz and the remaining passive resistors. The output of this filter, designated 614 (VCH) in Figure 6, is the signal supplied to the analog-to-digital converter 63 5 of DSPC 63 0 . Assuming a 10 kHz sample rate of the analog-to-digital converter 63 5, the 6-pole Butterworth filter shown in Figure 7 will attenuate the signal above the N yquist ratio of 5 kHz above -80 dB, thus minimizing The effect of aliasing signals on the sampled voltage signal. The current filter portion of the signal φ regulator 6 10 from the PSIM signal IPSIM + and IPSIM-generating signal ICH is identical in topology to the voltage filter, but does not use the current signal equivalent to VCH' in the illustrated embodiment. . The output of the current filter (ICH) is likewise band limited by an identical Butterworth filter with a 3 dB crossing of approximately 2500 Hz. Referring again to Figure 6, functional programmable threshold comparator 620 compares the programmable voltages set and controlled by signal VCH' and DSPC 630 to reflect the difference 値 between the chamber voltage signals from the PSIM. The output 622 of the programmable threshold comparator 620 is the signal \ARC. Whenever the sensed micro-40-200835923 compartment voltage exceeds the stylization threshold 可 the programmable threshold comparator 622 establishes \ARC as logic "1" 値 'when the sensed differential chamber voltage is lower than the program The programmable threshold comparator 622 asserts \arc as a logical "〇". The programmable hysteresis is applied to the stylized threshold in a manner to be described later, thereby minimizing the noise VCH' signal applied to the programmable threshold comparator 620. In the following, the signal \ARC (ie, "non-ARC") is the condition in the logic state (the chamber voltage is below the predetermined threshold) is called the ARCING condition, and the \ARC signal is the condition in the logic "1" state (chamber voltage) Above the predetermined threshold) is called the NON - ARCING condition. FIG. 8 illustrates an exemplary implementation of a programmable threshold comparator 620. The critical comparator 620 includes a commercially available analog comparator integrated circuit U12:A, such as the LM319M. GNDANALOG is the analog reference plane; DGND is the digital reference plane used by the logic signals of the DSPC 630 and other devices, and the integrated circuit bias is at +5V. Functionally, the analog comparator U12:A has an output terminal (pin 12), a reverse input terminal 1IN- (pin 5), and a non-inverting input terminal 1IN + (pin 4). The output terminal (pin 12) of U12:A produces signal 622 in Figure 6 and is labeled as \ARC. Nominally, whenever the signal in the non-inverting input is in a voltage higher than the voltage of the signal of the reverse input terminal, the logic signal present at the output terminal is represented as a logical "1". Conversely, whenever the signal in the non-inverting input is in a voltage lower than the voltage of the signal of the inverting input terminal, the logic signal present in the output terminal is logic, 〇, . The signal present in the output terminal is undefined whenever the two respective signals in the input terminal are identical. In an embodiment of the present application, device U12:A is configured to have an open collector output of -41 - 200835923. Resistor R27 is a boost resistor that is coupled to a +3.3¥ bias supply for supplying 08?, 八01^, and other circuitry power. Resistor R25 is nominally 200 k-ohms and provides a minimum hysteresis level to analog comparator U12:A to achieve a smooth logic state transition without oscillation when U12:A encounters a slowly varying input signal. Resistor R28, R29, and R26, coupled to the accuracy of the 3.00 volt reference voltage source connected to R26, provide a proportional conversion of the form, instantaneous chamber voltage signal VCH':

Vcs = 〇.6Vch+1.〇 (Equation 1) where VCS is the pin 4 of the analog comparator U12:A appearing in Figure 8, the non-inverting input signal. Therefore, according to Equation 1, the 2.5V signal at 乂0^' appears as a 2.5V signal in pin 4 of the analog comparator U12:A. Linear operation is guaranteed by the analog comparator manufacturer in the range of chamber operating voltages between 〇 and 1.25 volts to apply this affine transformation to maintain the analog comparator U12: A input within the desired range . In a particular embodiment, a 3.00 volt reference for an internal analog-to-digital converter is provided using a commercially available regulator model REF 193 manufactured by National Semiconductor (International Semiconductor). Provides a programmable threshold voltage signal VTH to the analog input U12:A (pin 5) inverting input to set the ADU transition between the NON - ARCING and ARCING state of the chamber voltage. The programmable hysteresis generated by the method described later allows the VTH to become a model. -42- 200835923 User specified parameters can be programmed to set the voltage of the system from NON_ARCING to ARCING state 値 V ΤΗΝA 5 and the second voltage 値 ν ΤΗΑΝ to set the system to transition from ARCING to NON_ARCING. The device U13 is a dual 14-bit digital-to-analog converter (DAC), for example, Analog Model, Inc., Model A 5322 manufactured by Analog Devices, Inc., which is used to set two VTHs. It has two output terminals, designated V〇_A and V0 B, which are set by a DSP using a standard φ quasi-series peripheral interface (SPI) feature integrated into the DSP. The signals nominally SPIIMO, SPICLK, \DAC1 - SELECT, and \丄〇8 are the signals used by the DSPC 630 to be used for each of the two DAC channels with a stylized range between 〇 and 4095. The above accurate 3.00 volts is applied to U13, and as a result each DAC output produces an independent, analog output in the range of 0-3.00 volts, which is proportional to the ratio of the programmed digits to a maximum 値 4 095. The output terminal V〇_b (pin 6) generated from the DAC B of U13 is affinityd to the non-inverting input of the operational amplifier U14:A, which is labeled V0B. As is not usual later, the signal V 〇 B determines the voltage critical VTHNA at which the comparator U12:A transitions from NON_ARCING to the ARCING state. The signal V 〇 a generated by the output of DAC A of U13 (pin 5) is coupled to the input terminal of analog switch U 1 5 : D, and as shown subsequently, together with signal V0B is used to set comparator U12 : A transition from ARCING to NON - ARCING state voltage critical VTHAN. According to an exemplary implementation, U15:D is a four analog switch, such as DG201HS manufactured by Intersil and others. The output of such a ratio switch appears at pin 15 of U15:D and is labeled Vsw in Figure 8. -43- 200835923 The state transition threshold voltage VTH is generated in the output pin 1 of the operational amplifier U14:A. With the ideal operational amplifier U14:A, it is easy to show the relationship between the output signal VTH and the signal V0B and the signal Vsw: V th = 2V 〇_b~V sw (Equation 2) The instantaneous tick of the signal Vsw is based on U1 5 :D The switch controls the logic state of the input (pin 16) φ. When the signal in the switch control input (pin 16) of the analog switch U15:D is in the logic state, VSW follows the signal V0A generated by the DAC U13 and connected to the input terminal pin 14 of U15:D. When the control signal in the switch control input (pin 16) of the analog switch U1 5 :D is in the logic "1" state, the circuit drive output terminal (pin 15) of the analog switch U1 5 :D is very high. The impedance state, and due to the low resistance of resistor R30 and the minimum input bias current of op amp U 1 4, Vsw closely follows V0B. The signal of the φ communication to the switch control input of u 1 5 _.D is provided by the logic or gate U16:A. The input signal to 〇R gate U16:A is the hysteresis enable control output (\HYSEN) from DSPC 63 0 and the output from analog comparator U12:A (pin 12). The logic state of the signal \HYSEN is generated under the control of the DSP software and is maintained in a logic "〇" state under normal operation. The signal \HYSEN is set to a logic "1" state only during certain manufacturing system calibration and test procedures to isolate the delayed generation of signals V〇a and Vsw. As described above, since the state of the analog switch U1 5 :D is modeled as Vsw 44-200835923 and thus VΤΗ, the state of the analog switch U 1 5 : D is based on the output terminal of the analog comparator U12:A (pin 12) The status of the digital signal \ARC in the middle. The relationship between the signals VOA and VOB developed by DAC U 1 3 and the comparator thresholds 値VTHNA and VTHAN will now be derived. First assume that the output signal of U12:A is initially in a logic high state. By defining the NON-ARCING state, the level shift chamber voltage signal Vcs on pin 4 of U12:A needs to be higher than the target φ front threshold voltage VTH on pin 5 of U12:A. In this scheme, the output terminal of analog switch U15:D exhibits high impedance, and as described above, Vsw is forced to use 値V0B due to the low impedance of R3 0 and the low input bias current of operational amplifier U14:A. Under this condition, the signal in the output terminal of operational amplifier U14:A follows V0B, and from Equation 2, VTH also uses 値VOB. Therefore, according to Equation 3, the voltage signal V0B is directly set to the ratio of the comparator U12: A transition from NON_ARCING to the ARC IN G state, the level shift voltage:

Vthna = V〇b (Equation 3) Once the ratio, shift chamber voltage 値VCS falls below the stylized NON_ARCING to ARCING state transition 値VTHNA according to the threshold voltage VTH generated by Equation 3, the comparator U12: The signal in the output of A transitions from the logic "1" state (NON ARCING) to the logic, '0' (ARCING) state. Assume that the \HYSEN control signal is in the logic "0" state (to make the programmable hysteresis function take effect As above, the analog switch U15:D is turned off and the output Vsw of the analog switch U15:D is followed by the input V〇A of the analog switch U15:D established by the DAC A of U13. It is set from V〇b In Vthna's equation 2, the final critical 値VTH becomes:

Vth = 2VThna-V〇a (Equation 4) If the hysteresis stylized 値 (proportional to reflect the PSIM gain and level shifting network) is VhYSS, then V〇A is set according to Equation 5: V〇a = Vthna-Vhyss (Equation 5) and the substitution into Equation 4 provides:

Vthan = Vthna + Vhyss (Equation 6) φ Set V0A according to Equation 5 to increase the fixed hysteresis voltage 値VHYSS to NON_ARCING to ARCING state transition voltage VTHNA when the ADU is in the ARCING state to generate ARCING to NON — ARCING transition Voltage 値 VTHAN. In summary, in this embodiment, according to Equation 1, the DAC B output signal VOB is used to directly set the room voltage of the programmable comparator from NON_ARCING to the ARCING state, and in Equation 5, the algorithm is determined to be used for decision. DAC of DAC A to increase hysteresis to Vthna to produce a transitional voltage from ARCING to NON-ARCING state but possibly higher V THAN 0 -46 - 200835923 According to one implementation, programmable comparator 620 transitions from NON_ARCING to ARCING The desired chamber voltage chamber threshold voltage of the state and the desired voltage to be added to the chamber voltage threshold to define the room voltage for the programmable comparator to transition from ARCING to NON-ARCING state. Configuration 60 communicates to DSPC 630, and DSPC 630 calculates the correct digits for transmission to DAC U13, thereby generating appropriate results by using an appropriate affine transformation of the proportional and offset constants φ that are stored and integrated into the DSP memory. Signals V0A and ν0Β. In an exemplary embodiment, 'in order to provide a critically accurate threshold 为' for the individual module g, the proportional and offset constants are calculated to account for the calibration of the electronic components (eg, resistor tolerance 値) The general deviation from the nominal enthalpy encountered. These calibration constants are stored in a serial EEPROM integrated into the DSPC 630. According to an exemplary implementation, the sampling rate of the analog-to-digital converter of the DSP 630 is a complete sample of the filtered room voltage and current signals VCH and ICH at a level of 10 kHz per channel, or every 〇〇uS. In this ratio, the probability of a randomly occurring micro-arc in the duration of luS or less being detected by the DSP is less than 1%, and as mentioned above, micro-arcs on the 1 uS level are common and may be Destruction occurs in the manufacture of integrated circuits. In order to reliably detect micro-arcs on a 1 US or less level during the duration, the ADU 50 includes a High Speed Arc Detector Logic Unit (ADLU) 640 that operates in conjunction with the programmable threshold comparator 620 and It is controlled and monitored by DSPC 63 0 to generate statistics on arcing during PVD processing. Referring to Figure 6, DSPC 630 provides control signals and system clock signals SYS CLK 650 to ADLU 640 and reads -47-200835923 data and writes data to ADLU 640 from ADLU 640 in a manner that will be discussed later. The ADLU 640 includes a first high speed counter designed to count the number of times the \ARC signal transitions from the NON_ARCING logic state to the ARCING logic state, as can be the programmed voltage threshold of the programmable threshold comparator 620 and the cathode and anode of the chamber 1 〇 The voltage between them is determined in general. As mentioned above, the duration of the arc is an indication of its severity, as is the case with voltage drops and current increases. Thus, the ADLU 640 also includes a timer that is designed to measure the duration of the programmable threshold comparator from the last timer set in the manner discussed later in the ARCING state. According to an exemplary implementation, the timer is a counter that cyclically formats the clock signal. According to a particular exemplary implementation, a fixed clock is operated at 30 MHz. The counter accumulation chamber has been proportional to the total time (from the last reset) in the arcing conditions during the production cycle (count). The operational count that maintains the number of system clock cycles that have occurred in the ARCING state provides a measure of the total time spent on the sputtering process in the arcing conditions. According to a particular example, the ADLU includes an address and data bus in the form of an interface to the DSPC 630 and receives control signals from the DSPC 630 such that the DSPC 63 0 can read and write data from the device. The ADLU includes a scratchpad that allows the DSPC 63 0 to control certain ADLU functions, such as reset, enable, and disable of the counter, and also includes additional registers and control logic to enable the DSPC 63 0 to pass from the ADLU. Read status information. Figure 9 illustrates an exemplary implementation of the present invention - 48-200835923 A DLU 640 using a universal field programmable logic array (FPLA) that has been programmed using the well-known FPLA design tool. The signal illustrated in Figure 9 outside of the ADLU 640 represents a signal present on the physical pin of the FPLA, the signal being pre-assigned to the particular pin of the F p LA during manufacture of the FPLA or used at the time of manufacture. The integrated FPLA program interface 910 is defined by the running DSP download to the FPLA "FPLA" program. The ADLU 640 includes a counter unit (CU) 920, a counter control register (CCR) 93 0, and a counter status buffer (CSB) 940 coupled to the DSP interface logic configuration 960 by an internal data bus structure 950. As noted above, the signal \person ruler 0 622 is the logical input to the ADLU generated by the programmable threshold comparator 620. The system clock signal SYSCLK 650 is 30 MHz. The logic square wave signal is provided by DSPC 630 and provides a time base to the ADLU. FIG. 10 illustrates an exemplary implementation of a CU 920 of the present invention. CU 920 includes 16-bit asynchronous binary counter (ACC) IOIO, 32-bit asynchronous binary counter (ATC) 1 020, three 16-bit latches (ACC locker 1300, ATC high locker 1 040, And ATC low locker 1 050) 'and three 16-bit three-state buffers (ACC three-state buffer 1 060, ATC high-three state buffer 1 070, and ATC low-state buffer 1 080). A three-digit signal is provided from the counter control register 930: counter setting (CRST), enable (ENB), and snapshot (SNP) to control the operation of the ACC and ATC counters, respectively. When asserted by CCR 930, the CRST signal enables the ACC and ATC counters to be reset to zero and the counter is retained in the reset condition while asserted. When the CCR 930 releases the CRST signal, the respective enable counters, and their respective clock (CLK) signals are each high -49-200835923 for increasing inputs on low transitions. By counting their maximum capacity and returning to zero, each counter has its own (and locked) individual overflow bit (OVF). The OVF signal remains high until cleared by the assertion of the CRST signal. The ACC counter 1010 is driven by the signal ACCLK, which is derived from the output terminal 1 092 of the D flip-flop 1 090. The ATC counter 1 020 is driven by the signal ATCLK, which is derived from the NAND (reverse) gate 1 0 9 4 output terminal.

Figure 11 is a timing diagram of the relationship between the various signals of the ADLU 640. Referring to Figures 10 and 11, inverter 1096 negates DSPC system clock signal SYSCLK 650 and becomes \S YSCLK U 2 0. The signal \ S Y S C LK drives the clock input terminal 1091 of the D flip-flop 1090. On each high-to-low transition of the SYSCLK signal from the DSP, the 出现 appearing in the D input terminal 1 0 93 is locked to the D flip-flop, and the Q output appearing in the flip flop 1 090 after a short propagation delay Terminal 1 092. The signal present at the D input terminal 1 093 of the flip flop 1 090 is driven by the AND gate 1 098. The input signal to AND 1098 is a negation from the signal ENB 1130 provided by the counter control register 93 0 and the signal \ARC 622 (\\ARC 1150) from the inverter 1 097. The signal \ARC 622 is available. Stylized comparator 620 provides. The signal in the D input terminal 1 093 is in a logic low state when the signal ENB 1 130 is in the logic low (FALSE) state or when the \ARC signal is in the high state (indicating the detection of the NON_ARCING room condition). Conversely, when the ENB signal is in a logic high state (by which the count is asserted), and the \ARC signal is in a logic low state (indicating the detection of ARCING room conditions), the signal in the D input terminal 1 093 is -50- 200835923 In a logic high state. Therefore, assuming that the count is enabled (signal ENB 1 130 is in a logic high state), the ACCLK signal 1160 will be in a logic low state on the subsequent high-to-low transition of SYSCLK when the chamber is detected in the NON_ ARCING condition. When the ARCING condition is detected, for example as indicated by 1 1 80 in Figure u (and the hypothetical count is still enabled), the \ARC signal is asserted low. On the next high-to-low transition of the SYSCLK signal (as indicated by 1 182 in Figure 11), the ACCLK signal will transition from low to high logic state and remain in a high logic state after the subsequent SYSCLK cycle. Until the ARCING condition is no longer detected (and the \ARC signal returns to the general logic high state as indicated by 1 1 84 in Figure 11.). The ACC counter 1010 is incremented during each low-to-high transition of the signal at its CLK input terminal whenever the CRST signal is asserted low. Therefore, while the ENB signal is asserted high (making the count active), the ACC counter 1010 effectively counts the number of chamber transitions from the NON_ARCING condition to the ARCING condition. In an exemplary embodiment, the ACC counter 1010 φ can decompose the micro-detection detected by the programmable comparator 620 (generating the \ ARC signal) in a short as 33 nS using a SYSCLK signal having a frequency on the 30 MHz level. Arcing. A higher degree of decomposition can be achieved by increasing the clock rate.

The ATC counter 1 020 is used to estimate the total time of the chamber determined by the programmable comparator 620 in the ARCING condition. The ATC counter 1 020 is incremented during each low-to-high transition of the signal at its CLK input terminal whenever the CRST signal is asserted low. The CLK input terminal of the ATC counter 1 020 is driven by the signal ATCLK 1170 provided by AND 200835923 Gate 1 094 with ACCLK and SYSCLK signal inputs. Whenever the count is enabled (ENB signal 1130 is high) and the chamber ARCING condition is detected (\ARC signal 1140 is low), signal ATCLK 1170 begins tracking SYS CLK signal 1 1 1〇, for example in Figure 1. 1 186 in 1. Thereafter, the ATC counter 1 020 counts the clock cycle of the ATCLK signal 1170 held while the programmable threshold comparator is in the ARCING state (indicating the arcing in the PVD chamber). With a 30 MHz system clock, the duration of each ARCING condition of φ can be decomposed into 33 nS increments. ACC 1 03 0, ATC high 1040, and ATC low 1 050 Lock Snapshot Scratch allows ACC counter 1010値, ATC counter 1 020 high-order characters, and ATC counter 1 020 low-order characters 値 can be immediately and immediately commanded capture. This enables the DSPC 630 to read the state of the counter at a particular instant, retaining those that are subsequently retrieved by the DSPC 63 0, while allowing the ACC and ATC counters to continue to operate according to their respective logic sets. As will be discussed in general, under the control of DSPC 63 0, each of these three 16-bit registers is configured and assembled to capture the instantaneous response of the low-to-high transition of the SNP signal provided by the counter control register 930. Counter 値. The output signals of each snapshot register are buffered by ACC 1 060 to internal data bus 950, ATC high 1 070 and ATC low 1 080 three state buffers. The DSP interface logic 960 asserts an enable signal on the RACC 1 086 of the ACC tristate buffer 1 060 to provide the captured ACC lock snapshot register 1 030 on the internal bus 95 0; asserted to the ATC high three state buffer The enable signal on RATH 1087-52-200835923 of device 1 070 to provide the captured AT of the ATC high-lock snapshot register 1 040 on the internal bus 950; and the RATL established to the ATC low-three state buffer 1 080 The enable signal on 1 088 is provided to capture the captured ATC low lock snapshot register 1 050 on the internal bus 950. Referring again to Figure 9, the CCR lock register 93 0 generates SNP, CRST, and ENB signals. The DSP interface logic 960 provides appropriate address decoding and timing signals, asserts the SNP, CRST, and ENB signals on the internal data bus 95, and generates a signal WCCR when the DSPC 63 0 command is used to do so. Lock these cockroaches into the CCR. The counter status buffer (CSB) 940 is configured and configured to assert CRST, ENB, ACCLK, COVF, and TOVF signals to the internal data bus 950 when commanded by the DSP interface logic 960 via the acknowledgment signal RCSB. Currently the three state buffers. The DSP interface logic 960 then asserts these signals used by the DSPC 630 onto the DSPC data bus.

Referring again to FIG. 9, according to the signals established by the DSP 63 0 to facilitate communication with external devices such as the ADLU 640, \STRB, W/R, and address lines AD0-AD15, data bus lines DB0-SB15 are used. Formally supplied signals provide bidirectional communication into and out of the DSPC 63 0 data. These data lines are effectively integrated internally from the internal data bus 950 of the ADLU 640. When attempting to communicate with any external peripheral device such as the ADLU 640, the DSPC 630 asserts that the \STRB signal is low. When attempting to read from the device, DSPC 630 also asserts that the signal W/R is low and is high when attempting to write to the device. These are established by DSPC 630 -53- 200835923

The universal signal communicates with any device. Especially when reading data from the ADLU 640 or writing data to the ADLU 640, the signal \ADLU_CS is asserted low by the DSPC 630. The DSP interface logic 960 is included in the ADLU M0 to generate timing and control signals WCCR, RCSB, according to the operation of the control signals \STRB, W/R and the decoding of the address signals AD0 and AD1 by the DSPC 63 0 - command, RACC, RATL, and RATH. The signal WCCR is used to lock into the CCR 930 between the ENB, CRST, and SNP established by the DSPC 63 0 to the internal data bus 950. The signal RCSB enables the 値 in the CSB 940 to be asserted to the internal data bus that the DSPC 630 will read. The signals RACC, RATL, and RATH are respectively enabled with the ACC tristate buffer 1060, the ATC high tristate buffer 1080, and the ATC low tristate buffer 1 070 as described above to establish an internal data bus that will be subsequently read by the DSPC 630. The locks on the 950 are among the ACC LATCH 1030, ATC LOW LATCH 1050, and ATC HIGH LATCH 1040.

Figure 12 illustrates an exemplary implementation of DSP interface logic 960 of ADLU 640 of the present invention that produces the signals WCCR, RCSB, RACC, RATL, and RATH shown in Figure 9. Inside the DSP interface logic 96 0, the control logic unit (CLU) 1210 inverts the \8 Ding 113 signal asserted by 〇8? 63 0 through the inverter 1 220 to form the internal signal \\STRB. When DSPC 63 0 is attempting to communicate with any external device, signal WSTRB is logic high. When attempting to write to an external device, the asserted high signal W/R and signal \\STRB' from the DSPC 630 provides a WR signal at the AND gate 1230. The W/R signal is inverted by inverter 1 240 to form a signal -54-200835923 \W/R, which is asserted high when DSP interface logic 960 is attempting to read from any external device. When the DSPC 63 0 is being read from an external device, the RD signal result provided in the output of the AND gate 1 250 from the input signals WSTRB and \W/R is asserted to be high. The address decoded to generate the control signal for the ADLU 640 is functionally provided by the address decoder, for example, the 2 to 4 binary address decoder 1 260 shown in FIG. As noted above, when reading from or writing to the ADLU 640, the DSPC 63 0 asserts that the logic on the ADLU 640's \ADLU__C S terminal is 〇. When the \ADLU_CS signal is set to the logic high state, all four signals Q?, ..., Q3 in the output terminal of the decoder 1 260 are set to a logic low state. When the \ADLU_CS signal is asserted in the logic state by the DSPC 630, the decoder 1 260 accurately sets one of the signals in the output terminal to a logic high state, the current A0 and A1 bits established from the DSPC 630. As determined and according to Table 1, the specific output is set to logic high, where "〇" in Table 1 is logic low, "1" is logic high, and "X" is unrelated. Table 1 Input Input I/O\ADLU_CS A1 A0 Output is asserted 1 XX Μ j\w 0 0 0 Q0 0 0 1 Q1 0 1 0 Q2 0 1 1 Q3 -55- 200835923 Using the above decoder logic 'Table 2 The logic defining the signals in the various function selection outputs in Figure 12, and the operations performed by the DSPC 630 on the ADLU. Table 2 Signal Name Logic DSPC 630 Function WCCR Q 0 and WR Write Counter Control Register RCSB Q0 and RD Read Counter Status Buffer RACC Q1 and RD Read ACC Locker 値RATL Q2 and RD Read ATC Low Lock値RATH Q3 and RD Read ATC High Lock 値 The processing of signals Ich and VCH generated by analog signal conditioner 610 will now be discussed in detail. Referring again to Figure 6, the signals Ich and VCH generated by the analog signal conditioner 610 are reflected in the chamber voltage and current, but are adjusted by the analog signal conditioner 6 10 to minimize the sampling frequency greater than about 1 〇 kHz. Aliasing. The TMS3 20F2407 DSP integrated into the DSPC 630 is a 16-channel, dual 10-bit analog-to-digital converter module that converts the voltage in its input channel to a number between 0 and 1 023. It is proportional to the reference voltage and can be sampled at a fixed rate up to the internal timing mechanism under software control of the 16 input voltage. In a particular embodiment, the reference voltage for the internal analog-to-digital converter is provided by a commercially available bandgap regulator model REF 193 manufactured by National Semiconductor (International Semiconductor - 56-200835923). . This regulator provides a stable, accurate 3.00 volt source to analog-to-digital converter. Therefore, the integrated analog-to-digital converter provided in the digital signal processor of the DSPC 630 converts the time-varying signals 〖CH(t) and VCH(t) into a number ranging between 0 and 1 023 according to the following equation. Sequence {nich} and { N VC Η }:

NicH(n) = FIX(IcH(nT)/VREF)* 1 02 4) (Equation 8) and NVCH(n) = FIX((VCH(nT)/VREF)* 1 024) (Equation 9) The function FlX(arg) turns the truncated bit of its argument "arg" into the nearest integer, η indicates the nth sample taken by the DSPC 6 3 0 from the reference time, and Τ is the sample period. In a particular embodiment, the DSP is programmed to convert the analog signals VCH and ICH at a ratio of 10 kHz to produce a sample sequence of data of {NVCH} and {NICH} to reflect the chamber voltage and current. In a particular embodiment, the software internal to the DSP provides a user selectable digital finite impulse response (FIR) filter applied to the sequence to produce filtered sequences {FVCH} and {FICH}, respectively, but other signal processing can be applied. Techniques go to this sequence without compromising generality. In a particular embodiment, an affine transform is applied to the sequences {FVCH} and {FICH}, producing a sequence of numbers {SFVCH} and {SFICH}, which is a scaled integer estimation sequence of chamber voltage and current. In one example, the affine transformation is such that a continuous application chamber voltage of 1 000 volts produces a series of integers each having 値1 000, and other voltages scaled down. Similarly, the affine transformation applied to the sequence derived from the sampled and converted ICH signal in this example takes into account the various gains and offsets of the PSIM and analog signal conditioning circuits, producing a current of 10.00 amps as an integer. 1 000, while other 値 is proportional to the transformation. In an exemplary implementation, the current sequence of sequences is communicated to the logical configuration 6 through the high speed communication interface 70, wherein the logic configuration 60 uses the current and past φ 値 calculations to program the adaptive comparator 620 to use the adaptive arcing The threshold voltage is 値. This adaptive arcing threshold voltage 値 and the desired hysteresis level are then communicated back to the DSPC 63 0 from the logic configuration 60 via the high speed communication interface 70. The DSPC 63 0 then converts the desired threshold 成 to the appropriate DAC 根据 based on the operation of the programmable threshold comparator 620. This approach produces near-instant adaptive thresholds. In another illustrative embodiment, the algorithm that generates the adaptive boundary resides in the DSPC 630 itself, producing an adaptive voltage threshold with minimal delay. Φ An example of the algorithm for generating an adaptive arcing voltage threshold is based on the calculated threshold of the moving average of the voltage sequence calculated by DSPC 63 0. The length of the moving average is selected to be longer than the expected duration of the arc, but It has a shorter rotation period than the steering magnet. At a 1 〇 kHz sample rate, a uniform weighted 64-point FIR filter can be used to calculate the moving average, and the sequence in the filter output presents the average of the previous 6.4 rnS of the voltage measurement. In one implementation, the adaptive arcing threshold is calculated by subtracting the fixed voltage from the moving average. In another exemplary implementation, the adaptive threshold is calculated as a fixed percentage of the moving average. -58-

200835923 These filtered, transformed sequences can also be used to provide information on the overall health status of the finger. In an example, the instantaneous sequence of current sequences is multiplied by a voltage sequence 値 to provide an instantaneous power sequence that can demonstrate that the actual power delivered to the vacuum chamber is delivered by the power supply. The sequence of species can be used to determine, for example, that cable damage occurs. The vacuum chamber flows current. Another example of the use of these sequences is that they can be independently mechanismd to estimate the rotational speed of the steering magnet. As mentioned above, as the chamber impedance changes due to geometric and other considerations, the chamber current periodically changes as the magnet period is manipulated. In one example, the voltage or current sequence of the example is passed through a digital high pass filter to remove the points. Then track the final AC sequence by the digital phase lock loop! J Estimate the rotational frequency of the steering magnet. In another exemplary implementation, the off-the-shelf transformation is applied to a voltage or current sequence and from the last spectral magnet rotation frequency. If the estimated rotational speed is significantly different from the pre-rotation speed, mechanical or electrical problems may be the cause. This information can detect initial defects in a mechanical or electrical system. In accordance with another exemplary embodiment of the present invention, the above-described composition is replicated to monitor a plurality of chambers or to detect ARCING based on application to a single chamber voltage and an electrical threshold. The four-compartment version of the four independent operational ADU ADUs controlled by a single DSPC 63 0 in a particular exemplary embodiment can be configured to simultaneously blue-independent rooms through four PSIMs, or by corresponding to multiple chambers The VPSIM+, IPSIM+, and IPSIM-ADU input signals are connected in parallel to the electrical spoke PSIM to drive multiple ADU chamber inputs. In the illustrated embodiment, the instant of processing is used. This four-week division is used as the observed pressure and the electricity will be proportional to the DC. From then on, the rotation is used to determine the period and the signal is used to provide the function. Consider four VPSIM-, single when all -59-

200835923 Four ADU functions monitor a single room through a single PSIM and connect the wires in a way that can be programmed into a single room to program a combination of four different thresholds corresponding to the programmable comparator 620 and ADLU 640. The number of arcs in the cymbal and the count of the duration of the arcing. In one embodiment, the DSPC 63 0 has a function to all four ADLU functions, and the arcing condition can be decomposed into four levels corresponding to four independent programs. one of them. For example, in a four separate system attached to a single PSIM, and a programmed critical number of 〇〇, 200, 300, and 400 volts, a single discovery with a minimum voltage of 値250 volts has A critical monitor that is programmed with 300 and 400 volts is not critically monitored at 100 and 200 volts. If the system is capturing a single arc in this way, the chamber voltage is 300 volts. The next cycle will occur simultaneously in the ADLU arcing time counter corresponding to the 300 volt level, while the period between the chamber voltage collapse field of 300 and 400 volts will only appear in the ADLU arcing time counter corresponding to 400 § . Then, the arcing time of the arcing event can be taken from the arcing time of the ADLU corresponding to the criticality of 300 volts, and the arcing time taken between the 200 and 300 volts is added. The arcing time spent between 3 0 0 and 400 volts is calculated using the difference between the ADLU arcing detectors corresponding to 400 volts and 300 volts, respectively. This algorithm can be repeated for different intensity sequences as needed. In a particular exemplary implementation, the DSPC 630 is at 10 kHz. By each. The voltage at the critical threshold will be out, but above. The collapse of 400 is in the special position of the two instruments. By the other sample -60-200835923, four ADLU register settings, and through the high-speed communication interface 70 for all four channels will count the arc and arc time Count the communication to logic configuration 60. The DSPC 630 also samples and shifts the nominally filtered chamber current ICH, and the filtered chamber voltage VCH, to a logic configuration 60 that performs the arithmetic operations required to resolve the arcing and calculates an estimate of the arc energy. All four arc voltage thresholds can be adaptively calculated from the extension described above. In another exemplary embodiment, DSPC 63 0 performs calculations internally, transmitting final estimates of arcing related parameters, such as arcing times in respective critical Φ 和, and estimated arcing energy to logic configuration 60. According to an exemplary implementation, logic configuration 60 is an external logic configuration, such as a programmable logic controller (PLC), a top hat, or the like. According to a more specific embodiment, the logical configuration 60 is a Schenider Automation Ml-E PLC. According to one aspect of the invention, the ADU is incorporated into the momentum form factor and is designed to communicate with the momentum top hat and programmable logic controllers (PLCs). % In one implementation, the data collected by the logic configuration 60 is recorded. The software executed on the logical configuration 60 records the data, graph data, and provides network-based alerts to reflect the data. The system controller provides instant control of the plasma generation application. When the arc count and/or arc duration exceeds a selected amount of each deposit, the logic configuration 60 determines, according to a predetermined algorithm, that the arc is damaging the substrate during material deposition and communicates with the system controller to terminate the deposition. The logic configuration 6〇 also indicates that the substrate being processed is reduced in output due to arcing. In addition to the cumulative duration of arcing and arcing for individual deposition counts -61 - 200835923, the 'in other implementations' logic configuration 60 is used to perform other real-time analysis of arcing information. For example, such as recording the total number of targets (and duration), recording arcing intensity (refer to near ground potential, indicating direct short circuit) and detecting continuous arcing, which indicates that possible defects in the target need to be closed. Remove all tools for repair. In another implementation, the system controller determines the rate of change of the arc rate/duration during the arcing duration, or the arcing, quality, and duration, amount, and arcing intensity φ (in accordance with the arcing rate) That is, the number of sounds or the severity (for example, the measurement obtained by the product of the arc duration and the number of turns) is proportional to the arcing quality to provide a signal. According to another exemplary embodiment of the present invention, the method integrates immediately The arc detector is a hardware that needs to inform the user that the sputtering source is problematic and that the newly processed wafer yield is reduced. Accordingly, various embodiments of the present invention can be implemented to provide arc detection in other plasma generation control applications. Measured, such as box hardened steel, etc. Generally, the circuit configuration and method of the present invention can be applied regardless of whether the plasma generating chamber or its equivalent is implemented. φ According to another embodiment of the present invention, the arc detecting unit 5 0 ' (shown in Figure 27) is configured to detect arcing events by observing the peaks in the current applied to the plasma generating device 1300. Based on this information and the arcing event from the detected voltage drop Information The detecting unit 50' classifies the arcing events into various categories. The device can also calculate the scanning energy and the arcing energy for the specific arcing event category. The basic configuration of the components shown in Fig. 1 and the ADU 50' of Fig. 27 are For the implementation of this embodiment. Figure 13 illustrates a typical basic chamber set of a PVD-treated plasma generating apparatus for depositing a thin, highly uniform layer of various materials onto a substrate - 62 - 200835923 Typically, helium, ionized to form electricity @ 1 302 and accelerated from the anode surface 1 304 (chamber wall and substrate) to the cathode bias target of the source material 1 3 06 (the cathode is illustrated as 1 3 08 The final atomic level of the target material is spray coated onto all of the proximity surfaces, including the fabricated substrate and the dome 1310. Typical anode-cathode voltages fall within the range of 300V-600V (with peaks up to 1 500V), while current ranges From 2A to 100 A. The final power delivered to the chamber can be as low as a few kW and as high as 80 kW. φ One of the main applications of this process is to deposit a metal layer on the germanium wafer when manufacturing integrated circuits (ICs). This process is easy to "arc". The target emits a large amount of particle contamination. Some of this contaminated material will land on the wafer, resulting in uneven production defects and coatings, which will negatively affect the profit of the manufacturer. The arcing system can be (i) target impurities or inclusions. , (ii) target or accessory aging and physical tolerance changes, or (iii) wafer calibration. The arcing during PVD processing results from an unintentional low impedance path from the anode to the target. When arcing occurs, The number of chamber impedances is rapidly reduced, and the φ is often too fast for the power supply to react. The rapid decrease in the voltage 値 between the anode and cathode of the chamber can be observed. As a result, the comparison chamber voltage and critical threshold can be provided early. Detection of arcing. Through this early detection, the manufacturer can solve the root cause of arcing without having to withstand the high yield loss caused by the arcing defects. As shown in Figure 4, a detrimental arc condition 1 402 on the order of 1 microsecond is typically observed. These short duration arcs 1 402 are commonly referred to as micro-arcs. Because of the very short duration, detecting high frequency arcs requires high speed electrons. In addition to micro-arcing, a massive power supply event with a duration of -63-200835923 on the order of milliseconds or tens of milliseconds also occurs in the PVD system. Figure 14 illustrates a typical PVD cell voltage 1 404 versus time plotted. The number of voltages 1404 is also illustrated because the cathode voltage is negative relative to ground. Where there is an arc 1 402, there is a sudden and rapid decrease in voltage towards ground. Once the short circuit event is over, the voltage returns to the nominal room voltage again. Possible transcendence and understanding during the recovery are not shown in the drawings. During the arcing event, the current reacts equally, although it increases rapidly and then decreases, knowing a φ but seeing the end, the condition returns to normal. The PSIM 40 is used to convert high voltage and high current readings from the power supply 30 into a range of 0-10V for input to the ADU 50'. The 0-10V signal is linearly proportional to the room voltage and current. This provides a voltage signal indicative of the voltage of the power supply 30 and a current signal indicative of the current of the power supply 30. Referring to Figure 27, the ADU 50' is designed to monitor 0-10V signals for high speed transients (whether up or down). Within the ADU 50', the high speed analog φ comparators 620, 621 determine if the voltage signal has crossed the line. Internal logic unit 640 converts analog comparator output 622, 623 to a logical level indicating whether the line has been crossed. Moreover, it counts the number of logical unit clock cycles (i.e., duration) that have crossed the line (an indication of the severity of the arc). Among its many functions, a programmable logic controller (PLC) or other logic configuration or circuitry 60 reads data from the ADU, converts the DSP clock cycle into a microsecond 'reset arc counter, and makes the data available. On the Ethernet. The PLC also sends command parameters to the ADU—when to find the arc event, what is the critical threshold, and whether the swim should be critical or critical. -64 - 200835923 Figure 15 depicts the typical chamber voltage 値 1500 pairs of time relative to the critical level of 1 502. In the case of voltage, the arcing condition 1 402 occurs when the instantaneous voltage reading drops below the threshold 値1 5 02. The room to be noted, the critical 152 is adaptive because it does track the slow change in the chamber voltage of 15 00. The number of ADU 50' counts and the number of critical 1 502 passes, and the duration during which the voltage is below 30 MHz. To account for the effects of noise or jitter, the arcing event does not end until the transient voltage rises above the critical 1 502 plus hysteresis. Figure 16 is a state transition diagram when the ADU 50' enters an arcing condition and when the same condition exists. Following path A, the voltage begins at nominal 値 VNOM. Once it falls below the threshold voltage VTH, following the path B, the ADU logic level transitions to TRUE. Path C is followed when the voltage rises again to return to the nominal condition. Once the voltage crosses the critical plus the hysteresis barrier VTH + VHYS, following the path D, the ADU logic level transitions to FALSE. As time travels, the chamber is at path A after the nominal voltage and ADU are waiting to be routed to transition B. Preferably, the hysteresis is determined by a small fixed hardware that cannot be adjusted via software. For the above embodiment, the hysteresis is about 6 mV on a scale of 1 0000 mV. However, for some embodiments, the hysteresis can be set to zero. The ADU 5 0' has four transition monitoring (arc) channels and four auxiliary channels. (Auxiliary channels can be used to record relevant data but cannot count arcs, and auxiliary channels are used for data collection in upgraded systems). Referring to Figure 27, the first arcing channel is formed by a relative voltage difference between 2700 and 2702, and the second arcing channel is formed between 2704 and 2706 (the remaining two -65-200835923 channels can be used Monitor another voltage and current). As mentioned above, the ADU 5 0 ' is compared to the P SIM signal with a threshold and reports whether the run is above or below. For arcing channels 2700/2702 and 2704/2706, the signal propagation and filtering is shown in Figure 17, in Figure 17, the voltage delivered by the power supply 30 to the chamber and measured by the PSIM converter. V and current I are illustrated on the left side of the pattern entering system 1 700. Both voltage and current converters have associated analog bandwidths, however, both of them are in the output φ of PSIM 40 over several tens of kHz filters, suitably designed to reduce DC power supply. The impact of the exchange of noise. The 40 kHz cutoff is arbitrary and can be adjusted at the factory by changing the output proportional resistor. This signal is fed directly to the analog programmable threshold comparator 1 704 which determines if there is a critical violation or is not in the ADU logic level form. At a ratio of 33 ns or 30 MHz, the portion of the ADU that performs the arc count logic reads the ADU logic level from the analog comparator. The PSIM V and I signals are also transmitted via analogy to a sixth level Butterworth filter 1 706. The purpose of this filter 1 706 is to prevent signals from being aliased when the signal is fed into the digital portion of the ADU. The cutoff frequency of this filter is 2.5 kHz. The ADU then runs the V and I signals through a set of selectable FIR filters 1 70 8 . The preset coefficients are set such that each of the eight filters is a moving average having a varying length. The PLC reads V and I as band-limited, filtered signals, and since then, calculates the critical enthalpy at a ratio of approximately 30 Hz. The basis for these calculations is an exponentially weighted moving average (EWMA) filter 1710. These are fed back by the ADU comparator controller -66 - 200835923 1712, which is operated at a factory-settable ratio of 2.5 kHz (this same controller performs FIR filtering). Preferably, the factory standard PLC 60 used in this embodiment is a MomentumTM M1E 9603 0 processor. The signal connection to the ADU 50' (from the PSIM BNC connector) is made via a standard 18-pin MomentumTM connector with an RG-178 coaxial cable. The PLC 60 is bonded to the ADU 50 via a standard MomentumTM ATII hardware interface. ATII interface Supports the 32 registers in all directions. The b32 register is divided into four identical groups of 8 temporary φ registers, one for each channel. The PLC 60 is operated by the principle of a scan cycle. During a scan cycle, PLC 60 executes the individual instructions once and updates its I/O registers (via which it communicates with ADU 50') once. Therefore, the PLC 60 controls the ADU 50' by first reading the 32-state register and writing the 32-command register, and then executing its own control program based on the most recently read data from the status register. The PLC program contains logic that repeats four times, once per ADU channel (primary voltage, main current, slave voltage, and slave current). The program also includes logic that is executed on each pair of channels (primary and slave) because each power supply combines data from two channels (current and voltage). When the PLC 60 reads the status register from the ADU 50' (8 registers per ADU channel), the PLC program relies on the four main segments of the data for each ADU channel. The four variables are the state register (in particular, bit 9, whether the ADU is measuring the time of the arc or not), the PSIM signal, the arc count, and the arcing time. It should be noted that the PSIM signal 1714 (shown in Figure 17) is a 64-point moving average of the actual room voltage or current that is band-limited by the two low-pass analog filters (25.6 ms window at 2.5 kHz), the first has -67- 200835923 Cutoff frequency 40 kHz and second with cutoff frequency 2.5 kHz. Referring to the block diagram of Fig. 18, the stable band monitor 1 802 compares the latest PSIM signal 1 804 with the stable upper band (SUB) and the stable lower band (SLB) 値 1 8 06. If the PSIM signal 1 804 falls above the SUB, the system treats that as an indication of step increase and logic processing in the rising transition mode. If the PSIM signal 1 804 is lower than the SLB, it is assumed that the power supply is turned off or reduced, and the program is operating in the falling transition mode. If the PSIM signal φ 1804 falls within the range defined by SUB and SLB, the mode of operation is stable (unless waiting for the transition to hold the delay period). When the system enters one of the two transition modes, it exceeds the transition mode of the transition retention delay period when the PSIM signal 1 804 falls within the limits of SUB and SLB again. As long as the PSIM signal 1804 falls outside the range defined by SUB and SLB, the stability flag falls from logic correct (値1) to logic error (値〇), regardless of whether the system enters a rising transition or a falling transition mode. The stability flag is maintained at a logic error until the PSIM signal 1 804 falls within the SUB-SLB range and maintains # throughout the transition retention delay. As will be discussed in detail below, the SUB and SLB are calculated based on the filtered version of the EWMA of the PSIM signal as seen by the PLC (adding another filter to the voltage or current reading). The filter will track the slow changes in the stable mode in the PSIM signal and the faster changes in either of the two transition modes. In contrast to the two subsequent power steps (second greater than the first), the temporal evolution of the stability flags SUB and SLB are illustrated in Figure 19 along with the notation of the transition retention delay 1902. It should be noted that the stable band monitor 1802 is the arc count and time (the voltage channel below the threshold) separating the inevitable steps -68-200835923 with true arc count and time. The arc count and time category logic section 1 8 0 8 uses the latest arc count and arc time reading 1810 from 50', and if the new arc count and arc time have occurred, they are added to the three PLC counts and One of the types of time (only if the status register 9 of the status register must read a logic error, then ADU 5 0 'is not between the end of the arc and the end). The three types are stable, transitional, and transitional. If the stability flag is logically correct, the new arc count is increased to the total number of steady arc counts and the new arcing time is increased to the stable arcing time. The flag is a logic error, and the PLC 60 tracks whether the transition is or is falling. According to the transition is occurring, the arc count and arcing time are increased to the appropriate number of arcing count transitions and arcing time transitions. It is important to note that the reason for the stabilization and transition modes is that the system does not know in advance when the electrical step changes or turns off. φ ADU 50' is looking for arcing on the voltage channel as the voltage drops to the next point. When it can lower the criticality or make the ADU 50 unable to count, it will always generate the arc count and some arcing time until The PLC scans until the loop. The arcing time from a falling event during a true microsecond arcing event is typically significantly greater than the arcing time. Therefore, there is a self-explanatory method or step continuous information. PLC 60 enters and separates the arcing time found during the transition and the arcing time found during the stabilization process. Transition Hold Delay 1 902 is intended to provide a blank period during the ignition transition. The transition reserve delay 1 902 parameter ADU's firing arc bit begins to drop. The number of issued. Increase or decrease the power supply because of the arcing of the next power, no plasma during the mode and the -69-200835923 mode is a method to reduce the number of errors in the data. The unit conversion portion 1812 multiplies the PSIM signal by only the corresponding calibration constant and the calibration percentage 以 to convert the 0-1 0000 mV PSIM signal into a real world engineering unit of volts or amps (e.g., 〇-1 〇V as described above). Calibration Constant parameters are a function of the PSIM hardware and should only be changed if the PSIM divider resistor changes or if the current converter and its gain change. If the calibration percentage parameter is to match voltage and current (or power) reading terms from different sources φ heads, similar readings from the P.VD device itself, or other components, the Adjust Calibration Percent parameter will be adjusted. The EWMA filter 1710 provides a method to track the PSIM signal. The output 1814 of the EWMA filter is used to adjust the critical SUB and SLB. In steady mode, the tracking is slow, so that the four adjusted parameters are also slowly adaptively drifting or slowly changing in the PSIM signal set point. In transition mode, tracking is faster because the setpoint has changed and the PSIM signal jumps up or down quickly to reach a new set level. The equation for controlling EWMA filter A is as follows: y(k)=X/100*PSIM Signal(k)+(lX/100)*y(kl) where y is after the output of the filter and k is the PLC scan Cycle index (increasing k by 1 each time the PLC starts a new scan), and λ is the filter coefficient. If the stability flag is logically correct, then λ is the stable filter coefficient. If the stability flag is a logic error, then λ is equal to the transition filter coefficient. It should be noted that λ can use 値 between 0 and 100, indicating the percentage level. Λ-70-200835923 Close to 100 ′ The more recent readings, the PSIM signal (k) affects the filtered output y(k), and the filter tracks the rapidly changing voltage or current level more quickly. The closer λ is to 0, the fewer recent samples of the PSIM signal affecting y(k), the more the PSIM signal determines the exponential decay average of the previous samples of y(k), and the filter will follow the steps in the PSIM signal very slowly. Variety. It should be noted that the 'PSIM signal is interpreted as two voltages and the current is positive (ie, the absolute voltage of the chamber voltage is non-negative when measured from cathode to anode). The YTH and YHYS calculation section 1816 uses the output y of the filter 1710, and calculates a threshold 値 in the next read/write phase of the PLC scan cycle to write to the ADU 5 0'. The critical level is equal to the appropriate percentage determined by the stability flag multiplied by y, the stability threshold percentage or the transition critical percentage. In the stable band calculation 1818, the output y of the EWMA filter 1710 is multiplied by the stable band percentage and then applied to y to generate and subtract from y to produce SLB. If the product of y and the stable band percentage is lower than the stable band minimum (SBM), the SBM is added to y and subtracted from y to produce SUB and SLB, respectively. The ENB/CRST block 1 820 performs three functions: (1) telling the ADU 50' whether to look for arcing, (2) resetting the ADU 50' to the end of the wafer 1310, and (3) recording the total processing time. To perform the first function, the ENB/CRST block 1 820 sets the ADU control register enable bit ENB (bit 1) high when the PSIM signal is greater than the enable level. The ENB bit is set low as long as the PSIM signal is below the enable level. The second function resets the ADU 5 0', which is done when the ADU 5 0' is not energized for a period of time to reach the reset delay. In most PVD processes, the time between -71 - 200835923 between wafers 1 3 1 0 exceeds the time of the method steps during wafer processing during which the power supply is turned off. Therefore, in order to properly reset the ADU 50' between the wafers 1310, the reset delay should be set to be greater than the internal method power-off time and less than the power-off time between the wafers (in seconds). The third function is to track the total processing time, from the first power on until the last power is turned off. After terminating the above logic (and other logic parts, although they do not affect any variables written to ADU 5 0 '), the critical and control are temporarily stored in the next read/write phase of the scan cycle. Write to ADU 5 0 '. Other logic executed by the PLC 60 is illustrated in Figures 20 and 22. Its illustrated system calculates the power for the power supply (primary or slave) from the voltage and current readings produced by the unit switching logic for the individual channels. In addition, the ignition time is calculated by measuring the time difference between the voltage enable and the power rise to 90% of the power set point. In Figure 21, the ignition time is plotted as opposed to the voltage versus its energizing level, current, power, and its 90% power setpoint level. Figure 22 depicts the final part of the logic. This section looks at one of the arc statistics for a single power supply (primary or slave) and one of the five levels of arcing, as shown in the table in Figure 23. The arc count and time from voltage channel 2202 and current channel 2204 are fed to arcing class logic portion 2206. Since the last PLC scan, the arc counts on the two voltage and current channels 2202, 2204 show an increase, regardless of their corresponding arcing time (and the arcing bit, state register, bit 9 is not high), The PLC 60 increases the arc level 1 count and calculates the scan energy by the following equation: -72- 200835923

Scan Energy where k is the PLC scan cycle index, yV is the EWMA filter output for the voltage channel, YVTH is the threshold for the voltage channel, yi is the EWMA filter output for the current channel, and YITH is the threshold for the current channel値, tarcV is the arcing time for the voltage channel (for the most accumulative latest PLC scan), and t ar c I is the arcing time 0 for the current channel (again for the latest PLC scan). The scan energy is actually the product of the area under the voltage curve from which they are decoupled from their nominal (or EWMA filtered) and the area under the current curve. The time factor in the scan energy calculation is the average of the time visible on both channels. The arcing energy is the cumulative sum of the scanning energies. If only the voltage arc count has changed since the last scan, check the arcing time for the boundary at 500. (This boundary is hard code in the PLC.) If the arcing time is lower than the boundary 値, the arc level 2 counter is incremented. If the arcing time is greater than or equal to the boundary 値, the arcing level 3 φ counter is incremented. If only the current arc count register has changed since the last PLC scan, the arc time is checked and the arc level 4 or arc level 5 counter is incremented, depending on whether the arc time is below the boundary or greater than or equal to Depending on the border. In Figure 23, an entity interpretation of each of the five levels is given. The arc energy and all five arc levels are reset at the end of the wafer. To summarize how the PLC program works, Figure 24 gives a timing diagram for a complete wafer (wafer 1) and the beginning of the next wafer (wafer 2), showing 4 steps (relative to the power supply voltage). The first step has a voltage that moderates the level, the second step is the high voltage step, the third step has the power off -73-200835923, and the fourth step has the lowest voltage in the three power turn steps. The total processing time counted by the sensor is from the beginning of the first step to the end of the fourth step. It should be noted that wafer 1 enters the chamber before the start of the step and is present in the chamber for a short time after the end of step 4. When the voltage transitions from one level to the next, PLC 60 sees large step changes (beyond the stable frequency band) and makes the system transition mode, from logic correct to error drop stability flags. The stability flag is maintained incorrectly, and the system is in transition mode until the time is equal to the transition retention delay after the voltage is stable in the new stable frequency band. The purpose of this delay is (1) to avoid counting the ignition transition as a stable arc, and (2) to speed up the tracking of the processing voltage level (which affects how fast the critical level follows the processing) so that once stabilized, the threshold voltage is reached It is at the level you want. Although not shown in Figures 3, 4, 6, the system differs between the ascending and descending transitions. The ADU 50' is generally enabled as indicated by the ADU enable bit, and the ADU enable bit is high all the time when the voltage exceeds the enable level. The arcing energy is counted by a voltage, and the arc energy is shown as a limited set of data. The arc level 1 and the arc level 2 are depicted at the bottom of the graph. In the middle of step 1, the arcing count on the two voltage and current (not shown) channels occurs simultaneously (within the same PLC scan), so the voltage arc count is shown as increasing, such as the arc level 1 . Correspondingly, the energy increases in the calculation in each (2). In the middle of step 2, another arc event occurs, this only on the voltage channel. Since the arcing time (not shown) is less than 500 ps, the event is temporarily stored as an arc level 2 event. It is necessary to pay attention to how the arc count is the cumulative sum of the arc counts from the beginning of the crystal circle. When the power supply is turned off for a period of reset delay _ period, the ADU reset becomes high and the -74-200835923 all arc event related variables are reset. The reset variables shown in Fig. 24 are the arc count, the arc energy, the arc level 1, and the arc level 2. When the crystal 2 begins (as seen by the sensor as the first increased voltage transition), the ADU reset back to logic error and the ADU enable becomes logically correct. Finally, Figure 25 illustrates the adaptation to the criticality of the processing voltage. At the beginning of the diagram, the voltage is turned off (the reading is very close to zero), and the critical threshold is stable. The critical value of the EWMA filter output is also very close to zero (because ADU is not energized, the criticality is treated as ADU 50' It doesn't matter if you don't count the arc.) SUB and SLB are above and below the voltage and may be dominated by a stable frequency band rather than a stable frequency band percentage. When the voltage used for the first time increases, the system enters a rising transition mode, applying a transitional filter factor and a transition critical percentage. Since the transition filter coefficient is a large 値, the EWMA filter is weighted on the most recent sample of the PSIM signal, so the critical fast rises to reflect the step change in the voltage. Once the voltage is stable, the criticality is also stabilized at the level specified by the transition critical percentage. When the processing voltage falls within SUB and SLB for a period equal to the transition retention delay, the system returns to the stable critical percentage and the stable mode of the applied filter coefficient application. Switching from transition mode to stable mode is accomplished by a critical percentage transition from a critical transition to a transitional transition. A similar advance is seen in the second rising transition of the voltage. When the voltage drops to the off state, the forward repeats again. In the down transition, the only difference is that any transitional arc counts and times generated during this period are written as a log as part of the statistics of the falling transition arc event. In the absence of information on the system's handling of information on when the transition occurs, see the drop transition arc/count and time on the voltage channel is normal. It is also normal to see the rising transition arc count and time on the current path. In both examples, the signal suddenly moves in the direction in which the ADU 50' seeks a sudden transition. Until the PLC 60 (at 30 Hz) can catch up with the ADU 50' (30 MHz) and give a command to change the criticality, the ADU 50' will count the step change as an arc. Therefore, the data needs to be divided into stable and transitional components. The system parameters should be adjusted to the arc count, arcing time, arc energy φ amount, arc level, processing transition, ignition time, and processing time data (ie, the remainder of the output data 'but the above settings contain critical data points) Both are reported by the system for optimization. The target captures the “true arc” that affects wafer quality. The various variables and parameters contained in the system are illustrated graphically in Figure 26. The important variables of the two sins are the critical and stable flags. The arc count, arcing time, arc energy, and arc level variable are all based on the criticality. If the criticality is too close to the operating voltage or current' then the system will report an erroneous alarm arcing event. φ If the criticality is too far from the operating voltage or current, the system may miss reporting some short micro-arc events. The stability flag affects the criticality in two ways, via the selection of the critical percentage (stability or transition) and by adjusting the bandwidth of the EWMA filter, which is fed directly to the critically calculated output. Figure 26 reveals several paths of logic, power and ignition time paths, ADU energization paths, critical paths, processing time paths, and stability flags/arc count/arc energy/arc-level paths. The starting point for each path is one or more 读取 read from the ADU (read from) scratchpad. The end point of each path will be one or more 値 to write to the ADU (write) register or the system variable -76- 200835923, the statistical description of one or more arcing events. It should be noted that in Figure 26, the current channel logic is illustrated as an abbreviation because it follows the same structure and flow-action voltage channel logic. This similar part is defined by a rectangular dashed line. In the power and ignition time paths, the voltages and currents for the primary power supply PSIM (or slave) are combined to produce the calculated power. It is then used to calculate the ignition time. The parameters used in the calculation of each φ variable are shown in italics in Fig. 26. Both current and voltage are generated by multiplying the PSIM signal by the calibration constant and the calibration percentage. The ignition timing is appropriate as a result of the time difference between the ADU energization and the 90% of the power set point for the calculated power rise. Calibration constants and calibration percentages are used to adjust current and voltage. The calibration constants reflect the PSIM hardware and should not be changed unless the PSIM hardware is changed. If the current and voltage need to be fine-tuned to match data from another source, such as a tool controller, only the calibration percentage is adjusted. The power set point should be adjusted to be equal to the power level (in watts) of step φ of the method. (The ignition time can be calculated for each step in the method. However, the PLC program will have to be corrected from the version described in this document). The ADU enablement path determines when the ADU is actively looking for arcing. It is controlled by the enable level and the enable delay parameter. When the PSIM signal rises above the enable level, the PLC will command the ADU 50' to begin looking for an arc by setting the enable bit in the control register. The enable level should be above the off state reading and below the lowest voltage or current level in the method operated by the PVD tool (equal PSIM signal unit). If you want to keep the ADU 50' inactive for a period of time after the -77-200835923 rises to the enabling level on the PSIM signal, increase the enabling delay. In fact, the enabling level condition (combined with the stable up-and-down transition mode) is sufficient, so in PVD applications, the enabling delay will probably never be adjusted. In the critical path, the PSIM signal is fed into an EWMA filter dominated by a stable filter coefficient or a transition filter coefficient, as determined by the state of the stability flag. The filter coefficient parameter can vary from 0 to 100. The 値 φ increases the bandwidth of the filter, allowing fast response tracking step changes (bad noise emission). When in steady state, or during steady mode, the system should be set to have a critical (remember critical = critical percentage * filter output), where the noise in the criticality coupled with the noise in the DC power supply signal will not Generates an error arc count. The output of the filter is then fed to a stable upper band/stable lower band (SUB/SLB) calculated by multiplying the percentage of the stable band by the filter output. If the product is below the stable band minimum parameter, the stable band minimum is added to the chopper φ output and subtracted from the filter output to produce SUB and SLB, respectively. Otherwise, the product is added to the filter output and subtracted from the filter output to specify SUB and SLB. SUB and SLB are then used at the beginning of the next PLC scan to determine if the stability flag is correct or incorrect. The percentage of the stable band should be low enough to ensure that the minimum step change between method steps enables the system to enter transition mode and should be high enough that any power loss events that may exist do not allow the system to enter transition mode in the middle of a single method step. The stable band percentage is initially set from known method voltage and current conditions, but must be empirically varied by examining multiple wafers operated by each process. -78- 200835923 The stable band minimum should be set so that the stability flag does not change back and forth between correct and error when the system is in the power off state. It can be easily set by observing the off state noise and doubling the observed change. The filter output is also fed into the critical calculation. The stability flag determines which mode to apply, whether it is stable or a transition. Then, the threshold is multiplied by the filter output by a stable critical percentage or a transition critical percentage. The criticality is one of the two most important variables in the data. The threshold via the stability threshold percentage should be adjusted up and down during steady state operation of various processing methods and power set points to identify the power supply ripple, remembering that the ripple will change over time and chamber. The stability threshold percentage must be set to a critical value below the power supply ripple, but still high enough to capture a short duration arc. The PSIM is reminded to include a 60 kHz filter in its circuitry (by designing to mitigate the effects of power supply exchange noise) with a time constant of 2.6 μ8. The voltage transition specified for arcing uses a voltage from the processing setpoint to zero that is much less than 1 μ8, and the assumed arcing can be represented by a square wave function (relative direction and two-step variation of equal numbers), time constant And the stability threshold percentage will determine the shortest arc that can be detected by the system. For example, in Figure 5.4, an arc of 3 ps is illustrated as a power supply voltage and a band limited PSIM signal, relative to the critical. Even if the signal received by the ADU is band limited, the arc is still counted as a transition above the critical. By comparison, the arc that has been reduced to 1μ8 is not counted by the ADU having a 60% stable critical percentage. However, if the stable critical percentage is set to 80%, it should be counted as an arcing event. Therefore, the stability critical percentage should be set below the level of the ADU count noise when 79-200835923 is the arcing event. However, not so low to a large percentage of the true arcing event does not allow the PSIM signal to cross the critical. The transition critical percentage should be set as well, remembering that the ignition cycle is essentially a noise, so its enthalpy will probably be below the stability critical percentage. The transition retention delay can be used to extend or shorten the period of the transition critical percentage application. In the processing time path, the only calculation is the processing time itself. The processing time is from the time when the PSIM signal exceeds the enabling level until the PSIM signal falls below the enabling level, and is maintained at a time that is at least equal to the reset delay (note that when exceeded, the processing is performed The time reflects the reset delay from the processing time when the difference between the true condition of the first ADU for the wafer and the true condition of the last ADU is enabled. In the PLC program, another device can indicate that the wafer processing has ended and the data can be reset to replace the reset logic of the system, so that the reset delay is not required. Finally, the Stabilization Flag/Arc Count/Arc Energy/Arc Class path contains the last two parameters, the transition retention delay and the arc level boundary. The stability flag is again one of the important system variables of the two crimes. It is correct if the PSIM signal falls within the range defined by SUB and SLB from the previous PLC scan. Otherwise, it is erroneous and the error is maintained until the PSIM signal falls within the SUB-SLB range again for a transition retention delay time period. Stabilization flags affect the storage of EWMA filters, critical, and arc counts to stable, rising transitions, and descending transition types. In order to adjust the transition retention delay, all three categories of the 发 and compare arc count data are adjusted during and after the stability flag is wrong. If at the beginning of the process or step, the steady arcing -80-200835923 count occurs regularly after the stability flag becomes correct, the transition retention delay should be increased. Another aspect of the invention includes the detection of the likelihood of non-cathode arcing of the plasma generating apparatus 1300. Referring back to Figure 13, the main components of the PVD chamber are illustrated. The substrate or wafer 1310 is seated at the lowermost portion of the chamber of the chuck or pedestal 1312, which typically holds the wafer 1310 in place with electrostatic force. Above the wafer 1 3 1 0 is a target 1306dDC power supply made of metal deposited on the wafer 1 310, which is connected to the cathode 1 3 08 (or target 1 306) and anode near the wafer 1310. Between 1 and 304. When DC power is supplied, the gas between the cathode 1308 and the anode 1304 is ionized to form a plasma 103. The positively charged gas ions are swept away toward the target 1 306 in an electric field, wherein the moving collision enables the metal atoms or molecules to be released from the target 1306. The released metal is then coated on everything in the chamber, including the crystal 1 3 1 0. The sacrificial shield, also known as the kit, is located in the chamber to absorb deposits and is periodically replaced. Not shown in the drawings are some of the chamber components surrounding the wafer to protect the chuck from deposition. These components can include a deposition ring and a cover ring. The cathode, or target, arcing causes the presence of saliva or comet-shaped defects on the wafer 1 310 (the material composition is the same as the target) to span a random pattern of the surface of the wafer. Cathode arcing is characterized by microsecond voltage and current transitions in the DC power supply and can be quantified by the arcing energy described above. Figure 28 illustrates a typical cathode or target arcing defect pattern 2800, and Figure 29 illustrates a close-up of a star-shaped defect 2900 on the surface of wafer 1310. The non-cathode arcing originates from a component close to the wafer 1 310, which may be a shield 1314, a deposition ring, or a cover ring. These arcs are in the arcing area -81 - 200835923. The wafer is severely damaged or contaminated, or randomly discharged from the wafer 1310 away from the arc itself, and the following rain is generally contaminated. The composition of the contaminated material is the composition of the surrounding chamber components that occur in the arc. Figure 30 illustrates a typical non-cathode arcing pattern of 3 000. Figure 31 illustrates a close-up or enlarged view of wafer film damage 3100 due to non-cathode arcing, and Figure 32 illustrates wafer contamination 3200 of non-cathode arcing away from the middle of wafer 1310. Figure 33 illustrates wafer contamination 3 3 00 near arcing. The analysis of the data derived from the arc detecting unit 50 described above may determine the risk or likelihood of non-cathode arcing. Information can be provided for each of the four sensor channels associated with unit 50. These include the main supply voltage and current being monitored, as well as the slave room voltage and current. Figure 34 illustrates a sample set of samples 3400 collected for the channel of the arc detection unit 50. Multivariate statistical analysis of the data set is used to determine the likelihood of any non-cathode arcing in the plasma generating apparatus 1 300. Imagine organizing a data set into columns and rows, each wafer has a column, φ (identified by the timestamp for each process when processing begins), and the row contains certain types of data (see the table above the row header). That is, the arc count is stable or X 1). Therefore, the examples in the data group are specified in the "exemplary" line of the above table. If the points in the data set are represented as d(i,j), where i is the column index (or number of columns) and j is the row index (or number of rows) d(i,0) = wafer (i) Timestamp, i = l, 2, 3, ···, Ν In the wafer to the data set, likewise, d(i, l) = the total arc count of the wafer (i), i = l, 2, 3,···,Ν -82- 200835923 For its part, the row average dm(j) will use this form dm(j) = [d(l,j)+ d(2,j) +... +d(N,j)]/N,j = l,2,3,.·.,Μ where Μ is the number of non-timestamp rows in the data. For example, if the analysis is performed on the subgroup data listed in the above table, and the subgroup is specified by the variables xi, χ2, . . . , χ9, then Μ will be 36 because of the four sensor channels (main voltage, main Each of the current, the slave voltage, and the slave current is repeated 9 times. Similarly, the standard deviation ds(j) is specified by the following equation: ds(j) = V[Z(d(i,j)-dm(j))2/(Nl)],j = l,2,3 ,···,Μ and their total sums are from i == 1 to Ν Now, as indicated by the following equation, use the points in the data set (except for the timestamp), subtract the line average and divide by Standard deviation to form a standardized data set dn(i,j): dn(i,j) = [d(i,j)-dm(j)]/ds(j),i=l,2, 3,·· ·, N and j = l, 2, 3,..., 需 Note that if ds(j) = 〇, Bay ij dn(i,j) is set =〇 because there is no deviation and specificity in the data set The data points should not contribute to the single statistical parameters defined below. If ds(j) = 0, then for all j, dn(i,j) = dm(j), and mitigate the problem of dividing by 〇 by zero. The next step is to set the side statistics do(i,j) do(i,j) = dn(i,j) ifdn by setting all 値 of dn (i,j) below zero to zero -83- 200835923 (i,j)&gt;〇0 if dn(i9j)&lt;0 The last data set d〇(i,j) now contains statistically normalized (and rounded out less than zero) data. This data was used to calculate a single statistical parameter that reflects the results of the multivariate analysis ^. Finally, a single statistic dp (i) is calculated for each wafer based on a set of normalized data do(i,j). This wafer statistic is specified as follows: dp(i) = w(l)*do(i,l) + w(2)*do(i,2)+&quot;. + w(M)*do(i , M) where w(1) is the relative weighting of each of the data lines used to form the sum of dp(i). Pattern recognition techniques can be performed on the moving average of statistical parameters. This produces another statistical parameter that indicates the level of error. To illustrate this technique, consider the following example. Data set d(u) d(l,2) ...d(l,M) d(2,l) d(2,2) ...d(2,M) d(N,l)d(N,2) ... ··· ...d(N,M) will contain information 84- 200835923

MV S 9 9 MV MV MV MV MV MV MV .. x9 xl x9 xl... x9 xl... x9 The data of each substrate spans one column and X 1 in the data set and is repeated four times for the main voltage (MV), main current (MA), (SV) And the slave current (SA) each time. Therefore, narrow lines. After the normalization and calculation of one side of the statistics, a single per-each wafer is formed by weighting ^ j = 1, 2, ..., Μ. For the information in this example, the specific weighting is as follows: w(l) = w(10) = w(19) = w(28) = 1 w(2) = w(l 1) = w(20) = w (29) = 5 w(3) = w(12) = w(21) = w(30) = 1 w(4) = w(13) = w(22) = w(31) = 1 w(5 ) = w(14) = w(23) = w(32) = 5 w(6) = w(15) = w(24) = w(33) = 1 w(7) = w(16) = w (25) = w(34) = 1 w(8)=w(17) = w(26) = w(35) = 0 w(9) = w(18) = w(27) = w(36) = 0 These The weighting can be optimized differently and based on the chamber conditions. For the chamber conditions in this example, these weightings produce the result of the identification of the type 4 (note that the last two equations of c are used to set the weighting, The data set should only contain xl,...,x7, because the line replaces line 3 6). Finally, when compared with the time stamp used for the processing chamber, the moving average of 30 points covers the time covering dozens of thousands of wafers. The result is shown in Fig. 35. The statistics dp(i) have been normalized, or: ..., x9 variable slave voltage ‘ 3 6 data - substrate, or

3 arbitrarily. Lan's error map f is zero. This is only 28 painted dp (i)! The longest period, 3 largest --85- 200835923 split to form dpn(i), so that the points in the plot range from 〇 to 1 : dpn(i) = dp(i)/max[dp(i)] where i=l, 2, 3, ···, Ν Furthermore, the number of points in the moving average can be changed. The gap in the data corresponds to the time period in which the process chamber is to be serviced and no wafers are run through the tool. It is known that on 2/1 6 , just before the φ time, the 1 1 wafer is discarded due to the non-cathode arcing. The identified pattern is an increase in the baseline (minimum 値) of the normalized NCA statistic dpn(i), which indicates the risk of NCA due to the indication of the charging chamber conditions, which is necessary to destroy or contaminate the substrate via NCA. factor. When this increase in the baseline is coupled to one or more large turns of dpn(i), the likelihood of subsequent NC A is even greater. The baseline statistic in this example is the minimum 以上 above the 150° window. Furthermore, the length of this window can vary with the characteristics of the chamber, and the 5x factor of the difference in length between the baseline and the moving average operates in this example φ and can be a good and practical rule for thumbnails. Baseline statistics are shown as black lines that are usually at the lower end of normalized NCA statistics. By comparison, the data for another chamber in the same time frame is illustrated in Figure 36. This chamber without discarded wafers showed no increase in baseline statistics far below the high (&gt;0.4) normalized moving average non-cathode arcing statistics. If some additional information from Room A is taken into account, a new level of error will occur. As shown in Figure 37, data from 1 /1 to 1 /1 7 has been added to the data set. During this time period, the baseline statistical level is significantly higher than they were -86-200835923 when there was an NCA event. It happened that the sensor was incorrectly calibrated and did not function properly. Therefore, baseline statistics at different levels characterize different types of errors. If expressed in a long strip chart format, the different errors indicated by the normalized baseline statistics can be seen more clearly, as shown in Figure 38. For Room A, the largest peak in the distribution of the baseline statistics for the long bar chart appears to be closest to zero in the baseline statistics. This peak indicates normal and error-free processing. The next peak indicates the risk of non-cathode arcing. Peaks that appear above 0.06 indicate calibration problems during the first two weeks of the year. In the case of chamber B, there is a peak in the distribution, which is expected to be in normal operation. While the invention has been shown and described with reference to the embodiments of the invention, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an exemplary embodiment of an arc detection configuration in accordance with the present invention; FIG. 2 is a block diagram of an embodiment of an arc detection configuration in accordance with the present invention; FIG. 3 is a block diagram showing an exemplary implementation of a power supply interface module (PSIM) portion of an arc detection configuration; FIG. 3 is a circuit diagram showing an exemplary implementation of a PSIM voltage sensing circuit portion of an arc detection configuration according to the present invention; 4 is a circuit diagram showing an example of a PSIM current sensing circuit portion of an arc detection configuration according to the present invention; -87- 200835923 FIG. 5 is an example of a PSIM power supply circuit portion of an arc detection configuration according to the present invention. FIG. 6 is a block diagram showing an exemplary implementation of an arc detecting unit (ADU) portion of an arc detecting configuration according to the present invention; FIG. 7 is an ADU voltage of an arc detecting configuration according to the present invention; A circuit diagram of an exemplary embodiment of a filter portion; FIG. 8 is a circuit diagram showing an exemplary embodiment of an ADU programmable φ critical comparator portion of an arc detection configuration according to the present invention; An exemplary embodiment of an ADU arc detection logic unit (ADLU) portion of an arc detection configuration of the present invention; FIG. 1 is an exemplary implementation of an ADU counter unit portion of an arc detection configuration according to the present invention; FIG. 11 is a timing diagram showing an exemplary implementation of a clock logic unit (CLU) clock generation according to the present invention; FIG. 12 is an ADLU digital bit φ number processing for an arc detection configuration according to the present invention. FIG. 13 is a cross-sectional view of a PVD chamber assembly; FIG. 14 is a plot of a typical PVD voltage signal with an arcing event versus time; FIG. The plot of the pvd voltage signal in the arc detection unit; FIG. 16 is a logic level state transition diagram of the arc detection unit when the arc is in and out; FIG. 17 is a block diagram of the signal propagation of the arc channel; -88- 200835923 Figure 18 is a block diagram of the main control of the PLC program; Figure 19 is a plot of the time between the stable monitor monitor variables; Figure 20 is a block diagram of the power and ignition logic; Figure 2 is a plot of the ignition timing Figure 22 shows the arc type Figure 23 is a table of arcing categories; Figure 24 is a wafer processing arcing variable timing diagram; % Figure 25 is a wafer processing critical timing diagram; Figure 2 is a logical execution arc detection sequence FIG. 2 is a block diagram showing another exemplary implementation of an arc detecting unit portion of an arc detecting configuration according to the present invention; FIG. 28 is a typical cathode or target of a wafer processed in a PVD chamber. Arcing defect pattern; Figure 29 is an enlarged view of the star-shaped defect on the wafer in Figure 28; ® Figure 30 is a non-cathode arcing defect pattern on the wafer processed in the PVD chamber; Figure 31 An enlarged view of the wafer film damage of the non-cathode arcing of the wafer in reference to FIG. 30; FIG. 32 is an enlarged view of the wafer contamination of the non-cathode arc away from the middle of the wafer; An enlarged view of the wafer contamination of the non-cathode arc of the arc; FIG. 34 is a multivariate statistical score of the data set of the wafer according to the present invention -89-

200835923 analysis chart; Figure 35 is a pvD normalized NCA chart for NCA events; Figure 36 is a PVD NCA chart for no NCA events; Figure 37 is a Figure 35 from an enlarged scale; and Figure 38 It is a statistical distribution map of the PVD chamber of Fig. 35 and the meter of Fig. 36. Although the invention has been illustrated by way of example in the drawings, the invention can still withstand various tests. However, it should be noted that the present invention is not intended to be an embodiment. On the contrary, it is intended to cover the invention and the scope of the invention in the spirit and scope of the invention as defined by the appended claims. [Main component symbol description] 10 : Vacuum chamber 15 : Gas 20 ·· Target 25 : Substrate 25 : Wafer 2 7 : Rotating magnet 3 0 : Baseline statistics of the power supply room and baseline statistics of the room and PVD room data PVD room Baseline specific details and details and other forms are limited to the described patent application variants, equivalents, 90-200835923 3 5: Coaxial Interconnect Cable 40: Power Supply Interface Module 42: Voltage Signal Path 44: Buffering Voltage attenuator 46: Hall effect-based current sensor 48: Current signal path 5 〇: Arc detection unit 5 〇': Arc detection unit 60: Logic configuration 70: Local data interface 8 0 : Data Network 1 〇〇: Arc Detection Configuration 2 1 0: External Conductor 215: Center Conductor 220: Hall Effect Converter 222: First Output Terminal 224: Second Output Terminal 225: Pore 2 3 0: Current Splitter 240: Isense circuit configuration 2 42: Isense circuit first input terminal 244: Isense circuit second input terminal 246: first output terminal 248: second output terminal -91 - 200835923 250: Vsense circuit 252: first input terminal 254: Second input terminal 256: first output terminal 25 8 : second output terminal 6 1 0 : analog signal conditioner 6 1 2 : output terminal 6 1 4 : output terminal 6 1 6 : output terminal 620 : programmable threshold comparison Function 621: analog comparator

622: Signal\ARC 622: Analog Comparator Output 623: Analog Comparator Output 63 0: Digital Signal Processor and Controller 63 5: Analog to Digital Converter 640: High Speed Arc Detection Logic Unit 65 0: Digital Signal Processing And controller system clock signal 9 1 0 : Integrated field programmable logic array program interface 920 : counter unit 93 0 : counter control register 940 : counter status buffer 950 : internal data bus structure 9 60 : Digital Signal Processor Interface Logic Configuration-92- 200835923

1 0 1 0 : 1 6-bit asynchronous binary counter 1 020 : 32-bit asynchronous binary counter 1 03 0: 1 6-bit asynchronous binary counter locker 1 04 0 : 32-bit asynchronous binary counter high lock 1 0 0 : 3 2-bit asynchronous binary counter low lock 1 060: 1 6-bit asynchronous binary counter three-state buffer 1070: 32-bit asynchronous binary counter high three state buffer 1 0 8 0 : 3 2-bit asynchronous binary counter low 3 state buffer 1 0 8 6 : RACC

1087 : RATH

1088 : RATL 1 090 : D flip-flop 1091 : Clock input terminal 1 092 : Output terminal 1093 : Inverting gate 1094 : and gate 1 096 : Inverter - 1 097 : Inverter 1 0 9 8 : Gate 1110: S YSCLK signal

112 0 : Signal \ S Y S C L K

1 130 : Signal ENB

1150: WARC 1160: ACCLK signal -93- 200835923

1170: Signal ATCLK 1 2 1 0 : Control logic unit 1 220 : Inverter 1230 : and gate 1 240 : Inverter 1 2 5 0 : and gate 1 260 : Decoder 1 3 0 0 : Plasma generating device 1 3 0 2 : plasma 1 3 04 : anode surface 1 306 : cathode bias target 1 3 0 8 : cathode 1 3 1 0 : wafer 1 3 1 2 : pedestal 1 3 1 4 : sacrificial shield 1 402 : Short duration arc 1404: Chamber voltage 1 500: Chamber voltage 1 5 02 : Critical 値 1700: System 1 7 04 : Analogizable programmable comparator 1 7 06 : Analog sixth and Bad Wies filter 1 708: Selectable FIR filter 1710: Exponentially weighted moving average (EWMA) filter 94 - 200835923 1 7 1 2 : Arc detector detector controller 1 7 1 4 : Power supply interface module signal 1 802 : Stable Band monitor 1 8 0 4 : Power supply interface module signal 1 806: stable upper band (SUB) and stable lower band (SLB) 値 1 80 8 : arc count and time category logic part 1 8 1 0 : arcing Counting and arcing time readings 1 8 1 2 : Unit conversion section 1814: Output 1816: YTH and YHYS calculation section 1 8 1 8 : Stable band calculation 1 8 2 0 : ENB/CRST Block 1 902 : Transition Hold Delay 2202: Voltage Channel 2 2 0 4 : Current Channel 2206: Arc Category Logic Part 2800: Target Arc Defect Pattern 2900: Hui Star Defect 3 000: Non-Cathode Arc Defect Pattern 3 100 : Wafer Membrane Destruction 3200: Wafer Contamination 3 3 00: Wafer Contamination 3 40 0 : Data R3: Resistor Network - 95- 200835923 R4: Resistor Network R6: Resistor R7: Resistor R26: Resistor R28: Resistor R29: Resistor R30: Resistor

R 1 0 8 : resistor R 1 0 7 : resistor R 1 1 5 : resistor R 1 1 6 : resistor U 1 : dual power supply module U2 : operational amplifier U3 : instrumentation amplifier U27A : amplifier U27B : Amplifier U27C: Amplifier U27D: Amplifier RG2: Resistor J2: BNC type connector J3: BNC type connector GNDANALOG: Analog reference plane DGND: Digital reference plane C 1 0 : Capacitor-96- 200835923 D2 : Schottky barrier diode D 1: Light-emitting diode 1IN+: Non-inverting input terminal Π N -: Inverting input terminal U12: A: Analog comparator U14: A: Operational amplifier U15: D: Analog switch

U16:A: logical "or" gate

-97

Claims (1)

200835923 X. Patent Application No. 1 · A method for detecting the risk of non-cathode arcing in a physical vapor deposition chamber used for depositing metal on a substrate, the method comprising the steps of: monitoring a supply voltage and a supply current to a physical vapor deposition chamber for depositing metal on a substrate; generating a φ group cathode arc event data for each of the plurality of substrates processed in the physical vapor deposition chamber; The set of cathode arcing event data is used to calculate parameters for each of the plurality of substrates; and the possible risk of non-cathode arcing is determined based on the parameters. 2 • According to the method of claim 1 of the patent application, the following steps are additionally included: According to the result of the decision step, an indication that there is no risk of non-cathode arcing is provided. φ 3 · According to the method of claim 1 of the patent application, the following steps are additionally included: According to the result of the determining step, an indication of the risk of non-cathode arcing is provided. 4. The method according to claim 1, wherein the step of generating a set of cathode arcing event data for each of the plurality of substrates processed in the physical vapor deposition chamber comprises: obtaining a variable type for a plurality of cathode arcing可变; calculating a variable type average for each of the set of cathode arcing event data for each of the plurality of substrates, and for each set of cathode arcing event data for each of the plurality of substrates Calculating a variable type standard deviation number for each variable type; and using the variable type average number and the variable type standard deviation number to generate a set of normalized data for each group of cathode arcing event data for each of the plurality of substrates . The method of claim 4, wherein the calculating the parameters for each of the plurality of substrates according to the φ group cathode arc event data comprises: calculating the basis for each substrate according to the normalization data of the group parameter. 6. The method of claim 5, wherein the step of calculating the parameter for each substrate based on the set of normalization data comprises: weighting the variable type of the set of normalized data. 7 · According to the method of claim 1 of the patent scope, the following steps are additionally included: • Calculate the moving average of the parameter. 8. The method of claim 7, wherein the step of determining the possible risk of non-cathode arcing based on the parameter comprises: performing a pattern recognition technique on the moving average of the parameter. 9. The method of claim 8, wherein the performing the pattern recognition technique step on the moving average of the parameter comprises: monitoring the moving average for the increase in the baseline 该 of the moving average. 10. The method of claim 1, wherein the substrate is a -99-200835923 矽 wafer. 11. The method of claim 1, wherein the substrate is a glass panel. 12. A method of determining a possible risk of non-cathode arcing in a physical deposition chamber, comprising the steps of: coupling a cathode arc detecting unit to a physical vapor deposition chamber; each of the plurality of substrates processed in the chamber A set of cathode arcing data is generated; and the possible risk of non-cathode arcing in the chamber is determined based on the generated cathode arcing event data. 13. The method of claim 12, wherein the step of generating a set of cathode arcing event data for each of the plurality of substrates processed in the chamber comprises: utilizing the cathode arcing detection for the cathode arcing event data The measuring unit monitors the main supply voltage and the main supply current, and the secondary supply voltage and the secondary supply current. 14. The method of claim 12, further comprising the step of: providing an indication of one of the risks of non-cathode arcing and no risk of non-cathode arcing in accordance with the determining step. 1 5 · According to the method of claim 12, further comprising the steps of: generating statistical parameters from the generated cathode arc event data; calculating a moving average of the statistical parameter; and -100 - 200835923 on the moving average Perform pattern recognition technology. 16. A system for detecting the risk of non-cathode arcing, wherein the non-cathode arcing system is in a physical vapor deposition chamber for processing a substrate, the system comprising: a cathode arc detecting unit coupled by communication The main supply voltage of the physical vapor deposition chamber is monitored; a processor coupled to the cathode arc detection unit, which is configured to generate cathode arcing data for each substrate processed in the chamber, The processor is additionally configured to determine the risk of non-cathode arcing in the chamber based on the resulting cathode arcing data. The system according to claim 16 wherein the cathode arc detecting unit is additionally communicatively coupled to monitor a main supply current, a secondary supply voltage, and a secondary supply current of the physical vapor deposition chamber. . 1 8 · The system according to claim 17 of the patent application, further comprising a first sensor for monitoring the main supply voltage; a second sensor for monitoring the main supply current; a third sense a detector for monitoring the secondary supply voltage; and a fourth sensor for monitoring the secondary supply current. </ RTI> A system according to claim 8 wherein the processor is configured to generate a sense for each of a plurality of variable types of signals from signals received from the respective sensors. . A system according to claim 19, wherein the processor is configured to calculate an average 値 for each of the variable types, for each of the variable types of standard deviation 値, and to utilize the average A set of normalized data for 値 and standard deviation 値. The system of claim 20, wherein the processor is configured to calculate a parameter from the set of normalized data for each substrate, and calculate a moving average of the parameter. 22. The system of claim 16 further comprising - a visible indicator, wherein the processor provides an indication of the possible risk of non-cathode arcing to the visible indicator. 2 3. The system of claim 16 wherein the substrate 0 is a sand wafer. 102-