TW200835042A - Electronic device and RF module - Google Patents

Electronic device and RF module Download PDF

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Publication number
TW200835042A
TW200835042A TW96146578A TW96146578A TW200835042A TW 200835042 A TW200835042 A TW 200835042A TW 96146578 A TW96146578 A TW 96146578A TW 96146578 A TW96146578 A TW 96146578A TW 200835042 A TW200835042 A TW 200835042A
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Taiwan
Prior art keywords
wiring pattern
wiring
signal
wiring layer
circuit
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TW96146578A
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Chinese (zh)
Inventor
Wataru Takahashi
Shigeru Tsuchida
Hiroshi Okabe
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Renesas Tech Corp
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Publication of TW200835042A publication Critical patent/TW200835042A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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    • H01L2224/4805—Shape
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/491—Disposition
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    • H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Transceivers (AREA)
  • Transmitters (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Filters And Equalizers (AREA)
  • Amplifiers (AREA)

Abstract

A parallel resonant circuit is realized by stacking first to fourth wiring patterns each having at least an inductance element. One of the adjacent first and second wiring patterns is set to a signal input node and the other thereof is set to a signal output node. Then, the signal input node is connected to the signal output node via inductance elements of the first wiring pattern, third wiring pattern, fourth wiring pattern and second wiring pattern in order. By adjacently forming wiring layers of the signal input and output nodes, a capacitance value between the input and output nodes is increased compared to that when they are separated. Also, by increasing the line width of the first and second wiring patterns, the capacitance value can be further increased. Therefore, it is possible to achieve a large capacitance value in a small area and downsizing of the electronic device.

Description

200835042 九、發明說明 【發明所屬之技術領域】 本發明’係有關於電子裝置，特別是有關於適用有包 含有將高頻波之歪斜減低的濾波器等之高頻模組（RF模 組）的有益之技術者。 【先前技術】200835042 IX. Description of the Invention [Technical Fields of the Invention] The present invention relates to an electronic device, and more particularly to a high-frequency module (RF module) to which a filter including a filter for reducing high-frequency waves is applied. By. [Prior Art]

在以行動電話爲代表之移動體通訊中，係存在有複數 的通訊方式。例如，在歐洲，除了作爲第2世代無線通訊 方式而普及之GSM、以及將GSM之資料通訊速度提昇後 的EDGE之外，更有在近年開始服務之第3世代無線通訊 方式的W-CDMA。又，在北美，除了身爲第2世代無線通 訊方式之DCS、PCS之外，身爲第3世代無線通訊方式之 pdmalx 亦係普及。另外，GSM，係爲 Global System for Mobile Communication 之略。EDGE，係爲 Enhanced Data rate for GSM Evolution 之略。W-CDMA，係爲 Wide — band Code Division Multiple Access 之略。DCS，係爲 Digital Cellar System 之略。PCS ，係爲 PersonalIn mobile communication represented by mobile phones, there are multiple communication methods. For example, in Europe, in addition to GSM, which is popular as the second-generation wireless communication method, and EDGE, which has improved the data communication speed of GSM, W-CDMA, which is the third-generation wireless communication system that has been in service in recent years. In addition, in North America, in addition to DCS and PCS, which are the second generation wireless communication methods, pdmalx, which is the third generation wireless communication method, is also popular. In addition, GSM is a part of Global System for Mobile Communication. EDGE is the Enhanced Data rate for GSM Evolution. W-CDMA is a Wide-band Code Division Multiple Access. DCS is a digital Cellar System. PCS, for Personal

Communication System 之略 。 edmalx ，係爲 Code Division Multiple Access lx 之略。 在對應於GSM以及EDGE之行動電話終端的高頻電 路中，於高頻電力放大器與天線之間’係被配置有天線開 關。天線開關，係實行將TDM A ( Time Division Multiple Access，時間分割多重存取）方式之送訊槽（slot)與受 -5- 200835042 訊槽作切換之功能。The Communication System is abbreviated. Edmalx, which is a Code Division Multiple Access lx. In a high frequency circuit corresponding to a mobile phone terminal of GSM and EDGE, an antenna switch is disposed between the high frequency power amplifier and the antenna. The antenna switch performs the function of switching between the TDM A (Time Division Multiple Access) transmission slot and the -5-200835042 slot.

另一方面’作爲在行動電話終端中之相關於高頻電路 構成的其他傾向’係爲對具備有高頻電力放大器之高頻電 力放大器模組的輸出電力檢測電路之內藏化。例如，在下 述非專利文獻1中，係記載有將檢測出藉由電力放大器所 產生的電力的方向性結合器，與電力放大器一同而積體化 在電力放大器模組中的記載。方向性結合器之主線路，係 被連接於電力放大器之輸出與天線之間，方向性結合器之 副線路’係被連接於終端電阻與電力準位控制部的輸入之 間。方向性結合器，係可檢測出從藉由電力放大器所產生 之進行波訊號而來的結合電壓與從藉由負載而被反射之反 射波訊號而來的結合電壓之兩者的向量和之檢測電壓。 又’在下述非專利文獻2中，係記載有：內藏有電力 放大器、放大控制器、送收訊開關、開關控制器、雙帶域 方向性結合器、解訊器（deplexer )整合電路、高頻波濾 ^ 波器的高積體四帶域送訊前端模組。四帶域，係爲UGSM (GSM850 ) 、EGSM ( GSM900 ) 、DCS ( DCS 1 8 80 )、 PCS ( PCS 1 900 )之行動電話的多帶域。此模組，係採用 有InGaP/ GaAs之HBT (異質接面雙極性電晶體）、和 AIGaAs/ InGaAs/AIGaAs 之 PHEMT、和 GaAs 之肖特基 /被動元件、和Si之肖特基/雙極/ CMOS半導體技術。 又，在非專利文獻2所揭示之前端模組中，係使用有 複數之電感或是電容器。例如，在專利文獻1之圖8中， 係揭示有：在層積多層基板之各層的表面上，形成C字形 200835042 之線圈用圖案，並將此各層之線圏用圖案，藉由層積通孔 來連接的構成。此構成，其全體係成爲螺旋狀之電感（一 般而言，係稱爲螺旋電感等）。On the other hand, "the other tendency to be related to the configuration of the high-frequency circuit in the mobile phone terminal" is to consolidate the output power detecting circuit of the high-frequency power amplifier module including the high-frequency power amplifier. For example, in the following Non-Patent Document 1, a directional coupler that detects electric power generated by a power amplifier is described as being integrated with a power amplifier in a power amplifier module. The main line of the directional combiner is connected between the output of the power amplifier and the antenna, and the sub-line of the directional combiner is connected between the terminating resistor and the input of the power level control unit. The directional coupler detects the vector sum of the combined voltage from the wave signal generated by the power amplifier and the combined voltage from the reflected wave signal reflected by the load. Voltage. In the following Non-Patent Document 2, a power amplifier, an amplification controller, a relay switch, a switch controller, a dual-band directional coupler, and a demultiplexer integrated circuit are incorporated. The high-integration four-band transmit front-end module of the high-frequency wave filter. The four-band domain is a multi-band domain of mobile phones of UGSM (GSM850), EGSM (GSM900), DCS (DCS 1 8 80), PCS (PCS 1 900). This module uses HBT (heterojunction bipolar transistor) with InGaP/GaAs, PHEMT with AIGaAs/InGaAs/AIGaAs, and Schottky/passive components of GaAs, and Schottky/bipolar for Si / CMOS semiconductor technology. Further, in the front end module disclosed in Non-Patent Document 2, a plurality of inductors or capacitors are used. For example, in FIG. 8 of Patent Document 1, it is disclosed that a pattern for a coil of a C-shape 200835042 is formed on a surface of each layer of a laminated multilayer substrate, and a line of each layer is patterned by lamination. The structure of the holes to connect. In this configuration, the entire system becomes a spiral inductor (generally, it is called a spiral inductor or the like).

在專利文獻2之圖1中，係揭示有：具備將構成層層 積所成之層積體、和被設置於構成層中之內部導體、和用 以將此內部導體作電性連接之通孔的構成。此構成，係與 專利文獻1同樣的成爲螺旋電感。又，在專利文獻2之圖 11中，係揭示有：具備將構成層層積所成之層積體、和被 形成於構成層上之平板狀的內部導體、和分別被設置於層 積體之兩側的端子電極，而相鄰之內部導體，係分別被連 接於相異之端子電極的構成。此構成，係成爲電容器。 在專利文獻3之圖1中，係揭示有：在5層之介電體 層中，於第2層與第3層形成線路狀導體，並於第4層形 成電容電極，於第5層形成2個的接地電容電極，並將第 5層之背面作爲接地電極的構成。在此構成中，第2層之 線路狀導體的其中一端，係經由貫通導體而被連接於第4 層之電容電極與第5層之其中一方的接地電容電極，而另 外一端，係經由貫通導體而被連接於第3層之線路狀導體 的其中一端。又，第3層之線路狀導體的另外一端，係經 由貫通導體而被連接於第5層的另外一方之接地電容電極 。此構成，係成爲由LC並聯共振電路與被連接於其兩端 之電容器所成的低通濾波器。 [專利文獻1]日本特開2005-268447號公報 [專利文獻2]日本特開2006-59999號公報 200835042 [專利文獻3]日本特開2004-296927號公報 [非專利文獻 l]Jelena Madic et al， “Accurate Power Control Technique for Handset PA Modules with Integrated Directional Couplers，’ ， 2003 IEEE RadioIn Fig. 1 of Patent Document 2, there is disclosed a laminate including a laminate formed of a constituent layer, an internal conductor provided in the constituent layer, and a connection for electrically connecting the internal conductor. The composition of the holes. This configuration is the same as that of Patent Document 1 as a spiral inductor. Further, in Fig. 11 of Patent Document 2, there is disclosed a laminate including a laminate in which a constituent layer is laminated, and a flat inner conductor formed on the constituent layer, and each of which is provided on the laminate. The terminal electrodes on both sides and the adjacent inner conductors are respectively connected to the different terminal electrodes. This configuration is a capacitor. In Fig. 1 of Patent Document 3, a wiring conductor is formed in the second layer and the third layer in the dielectric layer of the fifth layer, and a capacitor electrode is formed in the fourth layer, and a fifth layer is formed in the fifth layer. Each of the grounded capacitor electrodes has a back surface of the fifth layer as a ground electrode. In this configuration, one end of the line conductor of the second layer is connected to the grounded capacitor electrode of one of the capacitor electrode and the fifth layer of the fourth layer via the through conductor, and the other end is via the through conductor. And connected to one end of the line conductor of the third layer. Further, the other end of the line conductor of the third layer is connected to the other grounded capacitor electrode of the fifth layer via the through conductor. This configuration is a low-pass filter formed by an LC parallel resonant circuit and a capacitor connected to both ends thereof. [Patent Document 1] JP-A-2005-268447 [Patent Document 2] JP-A-2006-59999, JP-A-200835042 [Patent Document 3] JP-A-2004-296927 [Non-Patent Document 1] Jelena Madic et al , "Accurate Power Control Technique for Handset PA Modules with Integrated Directional Couplers,' , 2003 IEEE Radio

Frequency Integrated Circuits Symposium，Pp · 715—718Frequency Integrated Circuits Symposium, Pp · 715-718

[非專利文獻 2]P · DiCairlo et al，“ A Highly Integrated Quad — Band GSM TX — Front — End — Module”， 2003 IEEE Gallium Arsenide Integrated Circuit ( GaAsIC ) Symposium，2003，2 5th Annual Technical Digest，pp • 280 - 283 · 【發明內容】 [發明所欲解決之課題] 近年，在以行動電話爲代表之移動體·通訊機器中，對 於構件之小型化、高密度化以及低成本化之要求係日益提 高。在移動體通訊機器中，雖係具備有在其與天線之間進 行局頻訊號之送收訊的被稱爲筒頻（RF: Radio Frequency )模組之構件，但是’配合於移動體通訊機器之多功能化 、小型化、低成本化，係要求有高頻模組之小型化。 在高頻模組中，通常’係包含有天線開關電路、功率 放大電路、輸入輸出整合電路、及各種之濾波電路等。其 中，輸出整合電路或各種之濾波電路等，係可在被安裝有 半導體晶片（功率放大電路等）之多層配線基板上，利用 -8- 200835042 其配線圖案而形成之。故而，爲了實現高頻模組之小型化 又或是低成本化，追求此種配線圖案之小型化又或是低成 本化一事係特別有益。[Non-Patent Document 2] P · DiCairlo et al, “A Highly Integrated Quad — Band GSM TX — Front — End — Module”, 2003 IEEE Gallium Arsenide Integrated Circuit ( GaAsIC ) Symposium, 2003, 2 5th Annual Technical Digest, pp • 280 - 283. [Problems to be Solved by the Invention] In recent years, in mobile and communication equipment represented by mobile phones, the requirements for miniaturization, high density, and low cost of components are increasing. . In a mobile communication device, although it is a component called a radio frequency (RF) module that transmits and receives a local frequency signal between the antenna and the antenna, it is combined with a mobile communication device. The versatility, miniaturization, and cost reduction require miniaturization of high-frequency modules. In a high-frequency module, an antenna switch circuit, a power amplifier circuit, an input/output integration circuit, and various filter circuits are generally included. Among them, an output integrated circuit or various filter circuits can be formed by using a wiring pattern of -8-200835042 on a multilayer wiring board on which a semiconductor wafer (power amplifier circuit or the like) is mounted. Therefore, in order to achieve miniaturization or low cost of a high-frequency module, it is particularly advantageous to pursue such a miniaturization or low cost of the wiring pattern.

當在多層配線基板上形成輸出整合電路或是各種濾波 電路時，例如，係可考慮使用在專利文獻1〜專利文獻3 中所揭示一般之電感或是電容器。然而，若是將在專利文 獻1或專利文獻2中所揭示一般之螺旋電感以及電容器作 組合而構成各種濾波電路，則由於其電路面積係會增大， 且伴隨著配線之引繞，例如會有需要1 0層左右的配線基 板的情形，因此，小型化或是低成本化係成爲困難。又， 若是使用專利文獻3之技術，則雖然可以實現某種程度之 小型化又或是低成本化，但是由於電感係僅被形成有2層 ，因此電感係爲不足，在實用上，有僅能夠適用於對應較 高之頻率的濾波器之虞。進而，專利文獻3之構成，若是 從表面作投影並進行觀察，則係成爲在電感之旁被形成有 電容者，因此，係有電路面積增大之虞。 另一方面，作爲高頻模組之小型化、高密度化的進展 時之其他問題，係可想到有經由多層配線基板所產生的回 路（return path )之問題。例如，若是功率放大電路之輸 出訊號經由多層配線基板上之回路而回歸至輸入側，則會 產生震盪現象。此震盪現象，會在不必要之帶域上產生雜 訊，並對其他帶域之送收訊訊號造成妨礙，故會成爲錯誤 動作之原因，又，在電信法上亦會成爲問題。爲了追求高 頻模組之小型化、高密度化，解決此回路之問題一事係爲 -9- 200835042 重要。When an output integrated circuit or a plurality of filter circuits are formed on a multilayer wiring board, for example, a general inductance or a capacitor disclosed in Patent Documents 1 to 3 can be considered. However, if a general filter circuit is formed by combining a general spiral inductor and a capacitor disclosed in Patent Document 1 or Patent Document 2, the circuit area is increased, and the wiring is accompanied by, for example, there is a Since a wiring board of about 10 layers is required, it is difficult to reduce the size or cost. Moreover, if the technique of Patent Document 3 is used, it is possible to achieve a certain degree of miniaturization or cost reduction. However, since the inductance system is formed only by two layers, the inductance system is insufficient, and practically, only Can be applied to filters corresponding to higher frequencies. Further, in the configuration of Patent Document 3, if a projection is made from the surface and a capacitance is formed next to the inductance, the circuit area is increased. On the other hand, as a problem in the progress of miniaturization and high density of the high-frequency module, there is a problem that a return path is generated via the multilayer wiring board. For example, if the output signal of the power amplifying circuit returns to the input side via the loop on the multilayer wiring board, oscillation will occur. This turbulence will cause noise in unnecessary areas and hinder the reception of other terrestrial signals. This will be the cause of the wrong action and will become a problem in telecommunications law. In order to pursue the miniaturization and high density of high-frequency modules, the problem of solving this loop is -9-200835042.

進而，伴隨此種回路之問題，亦可能會產生下述一般 之回路的問題。例如，經由使用在前述非專利文獻1中所 記載一般之被積體化於電力放大器模組上的方向性結合器 ，係可檢測出從藉由電力放大器所產生之進行波訊號而來 的結合電壓與從藉由負載而被反射之反射波訊號而來的結 合電壓之兩者的向量和之檢測電壓。另一方面，藉由不僅 是將方向性結合器與RF電力放大器一同積體化於RF模 組中，而如同前述非專利文獻2 —般將RF電力放大器之 輸出整合電路、高頻波除去濾波器、天線開關亦一同積體 化，係期待能開發出如同前述一般之行動電話終端的更加 小型化之高功能RF模組。 本發明者等，係在本發明之前，已從事被搭載於可進 行 GSM850、GSM900、DCS 1 800、PCS 1 900 之多帶域的送 訊之行動電話中的RF模組之開發。 圖1 8，係爲展示在本發明之前之開發期間中，經由本 發明者們所檢討之RF模組的電路構成之圖。RF模組，係 包含有：RF電力放大器ΗΡΑ、和最終段之輸出整合電路 12c、和高頻波除去濾波器（LPF ) 14、和方向性結合器（ CPL) 13、和天線開關（ANT— SW) 15。天線開關15，係 在RF模組之外部，被連接於行動電話之天線（ANT ) 1 6 RF電力放大器係被構成於單石（Monolithic)半導體 積體電路之晶片中，並包含有：初段放大器1 〇a、初段偏 -10- 200835042 壓電路l〇b、第1段間整合電路10c、次段放大器lla、次 段偏壓電路lib、第2段間整合電路lie、最終段放大器 12a、最終段偏壓電路12b、增益控制單元17。Further, with the problems of such a circuit, the following general circuit problems may occur. For example, by using the directional coupler integrated in the power amplifier module as described in the above Non-Patent Document 1, it is possible to detect the combination of the wave signals generated by the power amplifier. The detected voltage is a vector sum of the voltage and the combined voltage from the reflected wave signal reflected by the load. On the other hand, by integrating not only the directional bonder and the RF power amplifier in the RF module, but also the output integration circuit of the RF power amplifier, the high-frequency wave removing filter, and the like, the non-patent document 2 described above. The antenna switch is also integrated, and it is expected to develop a more compact and high-performance RF module like the above-described general mobile phone terminal. Prior to the present invention, the inventors of the present invention have been engaged in the development of an RF module that is mounted in a mobile phone that can perform multi-band communication of GSM850, GSM900, DCS 1 800, and PCS 1 900. Fig. 18 is a diagram showing the circuit configuration of an RF module reviewed by the inventors during the development period prior to the present invention. The RF module includes: an RF power amplifier ΗΡΑ, and a final stage output integration circuit 12c, and a high frequency removal filter (LPF) 14, and a directional combiner (CPL) 13, and an antenna switch (ANT-SW). 15. The antenna switch 15 is external to the RF module and is connected to the antenna of the mobile phone (ANT). The RF power amplifier is formed in a monolithic semiconductor integrated circuit chip and includes: an initial stage amplifier 1 〇a, initial stage bias-10-200835042 voltage circuit l〇b, first stage integration circuit 10c, sub-stage amplifier lla, sub-stage bias circuit lib, second stage integration circuit lie, final stage amplifier 12a The final stage bias circuit 12b and the gain control unit 17.

在初段放大器之初段RF輸入端子中，係被供給 有RF放大訊號RFin，初段放大器1 〇a之初段RF放大輸 出訊號，係經由第1段間整合電路1 0c，而被供給至次段 放大器lla之次段RF輸入端子中。次段放大器lla之次 段RF放大輸出訊號，係經由第2段間整合電路i〗c，而 被供給至最終段放大器1 2a之最終段RF輸入端子處。 在增益控制單元1 7中，係被供給有：經由rf類比訊 號處理半導體積體電路而從基頻帶訊號處理單元而來之增 益控制訊號Vramp，和從方向性結合器（CPL ) 13而來之 檢測電壓V c p 1。另外，增益控制訊號V r a m p之準位，係 爲與基地台和行動電話之距離成比例者，從RF電力放大 器ΗΡΑ而被供給至天線（ANT) 16之RF送訊訊號RFout 的準位，係可藉由增益控制訊號Vramp之準位來作控制。 增益控制單元1 7，係以使從方向性結合器（CPL ) 1 3而來 之檢測電壓Vcpl準位追隨於增益控制訊號Vramp之準位 的方式，而對RF電力放大器ΗΡΑ之增益作控制，藉由此 ，而進行APC (自動電力控制）動作。此APC，係藉由以 增益控制單元1 7所控制之初段偏壓電路1 〇b、次段偏壓電 力lib、最終段偏壓電路12b所致的初段放大器10a、初 段放大器10a、最終段放大器12a之增益控制而被實行。In the initial stage RF input terminal of the initial stage amplifier, the RF amplification signal RFin is supplied, and the initial stage RF amplification output signal of the initial stage amplifier 1 〇a is supplied to the sub-stage amplifier 11a via the first stage integration circuit 10c. The secondary RF input terminal. The sub-stage RF amplification output signal of the sub-stage amplifier 11a is supplied to the final stage RF input terminal of the final stage amplifier 12a via the second inter-stage integration circuit i. The gain control unit 17 is supplied with a gain control signal Vramp from the baseband signal processing unit via the rf analog signal processing semiconductor integrated circuit, and from the directionality combiner (CPL) 13. The voltage V cp 1 is detected. In addition, the level of the gain control signal V ramp is proportional to the distance between the base station and the mobile phone, and is supplied from the RF power amplifier to the RF transmit signal RFout of the antenna (ANT) 16. It can be controlled by the level of the gain control signal Vramp. The gain control unit 17 controls the gain of the RF power amplifier 使 so that the detection voltage Vcpl level from the directional bonder (CPL) 13 follows the level of the gain control signal Vramp. By this, an APC (Automatic Power Control) operation is performed. The APC is an initial stage amplifier 10a, an initial stage amplifier 10a, and a final stage amplifier 10a, which are caused by a first stage bias circuit 1b, a second stage bias power lib, and a final stage bias circuit 12b controlled by a gain control unit 17. The gain control of the segment amplifier 12a is performed.

RF電力放大器ΗΡΑ之最終段放大器12a的最終段RF -11 - 200835042The final stage RF -11 - 200835042 of the final stage amplifier 12a of the RF power amplifier

放大輸出訊號，係經由單石半導體積體電路之晶片外部的 最終段之輸出整合電路12c’而被供給至局頻波除去濃波 器（LPF) 14之RF訊號輸入端子處。高頻波除去濾波器 (LPF ) 14，雖係將被供給至RF訊號輸入端子之RF訊號 的基本頻率成分以極小之減衰率而傳達至RF訊號輸出端 子，但是，2倍高頻波、3倍高頻波、4倍高頻波等之高頻 波成分，係以大的減衰率而被減衰。高頻波除去濾波器（ LPF ) 14之RF訊號輸出端子的RF訊號，係經由方向性結 合器（CPL ) 13之主線路，而被供給至天線開關（ANT_ SW) 15之其中一端，而天線開關（ANT— SW) 15之另外 一端，係被連接於天線（ANT )之其中一端。方向性結合 器（CPL) 13之副線路的其中一端與另外一端，係分別被 連接於終端電阻Rt與增益控制單元1 7之檢測電壓輸入端 子。 然而，藉由在本發明之前之本發明者等所致之檢討， 明顯的發現，於圖1 8中所示之RF模組的高頻波特性，係 並不能滿足設計之目標。RF模組之高頻波特性若是無法 滿足設計目標，則被包含在從行動電話所送訊而來之RF 送訊訊號中的高準位之高頻波成分，係會成爲對鄰接之頻 道的妨礙訊號。被包含於此RF送訊訊號中之高頻波成分 的準位，係藉由ACPR (鄰接頻道漏洩電流比）而被展示 〇 另夕f，ACPR，係爲 Adjacent Channel Leakage PowerThe amplified output signal is supplied to the RF signal input terminal of the local wave removing filter (LPF) 14 via the final stage output integrating circuit 12c' outside the wafer of the monolithic semiconductor integrated circuit. The high frequency wave removing filter (LPF) 14 transmits the fundamental frequency component of the RF signal supplied to the RF signal input terminal to the RF signal output terminal with a minimum attenuation rate, but 2 times of high frequency wave, 3 times of high frequency wave, 4 High-frequency wave components such as high-frequency waves are degraded by a large attenuation rate. The RF signal of the RF signal output terminal of the high frequency wave removing filter (LPF) 14 is supplied to one end of the antenna switch (ANT_SW) 15 via the main line of the directional bonder (CPL) 13, and the antenna switch ( The other end of the ANT-SW) 15 is connected to one end of the antenna (ANT). One end and the other end of the sub-line of the directional bonder (CPL) 13 are respectively connected to the terminal resistance Rt and the detection voltage input terminal of the gain control unit 17. However, by the review by the present inventors before the present invention, it has been apparent that the high-frequency characteristics of the RF module shown in Fig. 18 are not satisfactory for the design. If the high-frequency wave characteristics of the RF module fail to meet the design goals, the high-frequency components contained in the high-order RF signal transmitted from the mobile phone will become an obstruction signal to the adjacent channel. The level of the high-frequency component contained in the RF signal is displayed by ACPR (adjacent channel leakage current ratio). 〇 f, ACPR, is Adjacent Channel Leakage Power

Ratio之略。 進而，在本發明者進行了對圖1 8所示之RF模組的高 -12- 200835042Ratio is slightly. Further, the present inventors performed the high of the RF module shown in FIG. 18 - 200835042

頻波特性無法滿足設計目標之原因的解明之過程中，係達 成了下述一般之結論。亦即是，如同圖1 8之虛線HD— SP 所示一般，RF電力放大器ΗΡΑ之最終段放大器12a的最 終段RF放大輸出訊號中所包含之高頻波成分，係被傳達 至天線16。虛線HD一 SP的訊號路徑，係由方向性結合器 (CPL ) 1 3之副線路與增益控制單元丨7之間的訊號配線 、方向性結合器1 3之副線路以及主線路、天線開關1 5所 構成。在最終段放大器1 2a與方向性結合器1 3之主線路 之間’係被連接有將高頻波成分以大的減衰率來作減衰之 最終段的輸出整合電路1 2c與高頻波除去濾波器1 4。但是 ，虛線HD 一SP之訊號路徑，係旁通最終段之輸出整合電 路12c與高頻波除去濾波器14。其結果，最終段放大器 12a之輸出的高頻波成分，係成爲經由方向性結合器13之 副線路與增益控制單元1 7之間的訊號配線、方向性結合 器1 3之副線路以及主線路，而傳達至天線1 6者。 於此，本發明之其中一個目的，係爲實現RF模組等 之電子裝置之小型化又或是低成本化。又，作爲本發明之 其他目的之一，係爲避免RF電力放大器之輸出的高頻波 成分經由方向性結合器之副線路與增益控制單元之間的訊 號配線、方向性結合器之副線路以及主線路，而傳達至天 線，而實現RF模組之小型化。另外，本發明之前述目的 以及其之外的目的、還有新穎之特徵，係可由本說明書之 記述內容以及所添附之圖面而明嘹。 -13- 200835042 [用以解決課題之手段]In the process of clarifying the reason why the frequency characteristics cannot meet the design goals, the following general conclusions are reached. That is, as shown by the dotted line HD-SP of Fig. 18, the high-frequency wave component contained in the final stage RF amplified output signal of the final stage amplifier 12a of the RF power amplifier is transmitted to the antenna 16. The signal path of the dotted line HD-SP is the signal wiring between the sub-line of the directional bonder (CPL) 13 and the gain control unit 丨7, the sub-line of the directional combiner 13 and the main line, the antenna switch 1 5 components. An output integration circuit 1 2c and a high-frequency wave removal filter 14 are connected between the final stage amplifier 1 2a and the main line of the directional combiner 13 with a final stage in which the high-frequency wave component is attenuated with a large attenuation rate. . However, the signal path of the dotted line HD-SP bypasses the output integrated circuit 12c of the final stage and the high-frequency wave removing filter 14. As a result, the high-frequency wave component of the output of the final stage amplifier 12a is the signal line between the sub-line of the directional combiner 13 and the gain control unit 17, the sub-line of the directional coupler 13, and the main line. Communicate to antenna 16. Accordingly, one of the objects of the present invention is to achieve miniaturization or cost reduction of an electronic device such as an RF module. Further, as one of the other objects of the present invention, the high-frequency wave component of the output of the RF power amplifier is prevented from passing through the signal wiring between the sub-line of the directional combiner and the gain control unit, the sub-line of the directional coupler, and the main line. And communicated to the antenna to achieve miniaturization of the RF module. In addition, the foregoing and other objects and novel features of the invention are apparent from the description and appended claims. -13- 200835042 [Means to solve the problem]

本發明之其中一種實施形態所致之共振電路，係使用 複數配線基板，並將第1配線層的第1配線圖案，和鄰接 於此第1配線圖案之第2配線層的第2配線圖案，形成爲 至少具備有電感成分之形狀，並進而，將相異於此第1以 及第2配線層之配線層的第3配線圖案，形成爲具備有電 感成分之形狀（電感圖案），而被構成。而，此第1配線 圖案之其中一端，係被作爲輸入又或是輸出節點，而另外 一端，係經由通孔導體而被連接於前述之電感圖案的其中 一端。 另一方面，第2配線圖案之其中一端，係被作爲輸出 又或是輸入節點，而另外一端，係經由通孔導體而被連接 於前述之電感圖案的另外一端。 如此這般，藉由在相互鄰接之第1配線圖案與第2配 線圖案的其中一方設置輸入又或是輸出節點，並在另外一 方設置輸出又或是輸入節點，相較於設置在未鄰接之配線 層的情況，成爲能夠增加輸入節點與輸出節點間之電容値 。故而，由於能夠以小面積而確保充分的電容値，因此能 實現小型的又或是低成本的並聯共振電路，而藉由將此適 用於高頻模組之濾波電路等之中，成爲能夠實現該模組之 小型化又或是低成本化。另外，爲了更進而增大電容値， 可將第1配線圖案與第2配線圖案之最大線寬幅設爲較電 感圖案之最大線寬幅爲更大。 又，本發明之其中一種實施形態所致之共振電路，係 -14- 200835042In the resonant circuit according to the embodiment of the present invention, the plurality of wiring boards are used, and the first wiring pattern of the first wiring layer and the second wiring pattern of the second wiring layer adjacent to the first wiring pattern are used. In addition, the third wiring pattern which is different from the wiring layers of the first and second wiring layers is formed to have a shape (inductance pattern) having an inductance component, and is formed in a shape having at least an inductance component. . One end of the first wiring pattern is used as an input or an output node, and the other end is connected to one end of the aforementioned inductance pattern via a via conductor. On the other hand, one end of the second wiring pattern is used as an output or an input node, and the other end is connected to the other end of the above-described inductance pattern via a via conductor. In this manner, by providing an input or an output node in one of the first wiring pattern and the second wiring pattern adjacent to each other, and providing an output or an input node on the other side, the adjacent node is disposed adjacent to the adjacent node. In the case of the wiring layer, it is possible to increase the capacitance 输入 between the input node and the output node. Therefore, since a sufficient capacitance 値 can be secured in a small area, a small-sized or low-cost parallel resonant circuit can be realized, and by applying this to a filter circuit of a high-frequency module, etc., it is possible to realize the mode. The miniaturization of the group is either low cost or low cost. Further, in order to further increase the capacitance 値, the maximum line width of the first wiring pattern and the second wiring pattern can be made larger than the maximum line width of the inductance pattern. Moreover, the resonant circuit caused by one embodiment of the present invention is -14-200835042

被形成在包含有第1配線層、和被配置在前述第1配線層 之下層的第2配線層、和被配置在前述第2配線層之下層 的第3配線層、和被配置在前述第3配線層之下層的第4 配線層之複數配線層基板上，並具備有：（1 )第1配線 圖案，係以在前述第1配線層中包含有略迴路（loop )狀 之線路的方式而被形成，且於一端具備有將訊號輸入又或 是輸出之第1節點；和（2 )第2配線圖案，係以在前述 第2配線層中包含有略迴路（l〇op )狀之線路的方式而被 形成，且於一端具備有將訊號輸入又或是輸出之第2節點 :和（3 )第3配線圖案，係在前述第3配線層中被形成 爲板狀；和（4 )第4配線圖案，係在前述第4配線層中 被形成爲板狀。 而，前述第1配線圖案之另外一端與前述第2配線圖 案之另外一端，係經由第1通孔導體而被電性連接，前述 第3配線圖案與前述第4配線圖案，係以相互對向的方式 而被形成，前述第3配線圖案與前述第4配線圖案之其中 一方的圖案，係經由第2通孔導體而被電性連接於前述第 1節點，前述第3配線圖案與前述第4配線圖案之另外一 方，係經由第3通孔導體而被電性連接於前述第2節點。 進而，前述第1配線圖案、前述第2配線圖案、前述第3 配線圖案、以及前述第4配線圖案，係以相互重疊的方式 而被形成，前述第3配線圖案與前述第4配線圖案間之重 疊面積，係較前述第2配線圖案與前述第3配線圖案間之 重疊面積爲更大。 -15- 200835042The second wiring layer including the first wiring layer, the second wiring layer disposed under the first wiring layer, and the third wiring layer disposed under the second wiring layer are disposed in the first (3) The first wiring pattern is provided on the plurality of wiring layer substrates of the fourth wiring layer under the wiring layer, and the first wiring layer includes a loop-like line. And being formed at one end with a first node for inputting or outputting a signal; and (2) a second wiring pattern including a slightly looped shape in the second wiring layer a line is formed, and a second node that inputs or outputs a signal is provided at one end: and (3) a third wiring pattern is formed in a plate shape in the third wiring layer; and (4) The fourth wiring pattern is formed in a plate shape in the fourth wiring layer. Further, the other end of the first wiring pattern and the other end of the second wiring pattern are electrically connected via a first via conductor, and the third wiring pattern and the fourth wiring pattern are opposed to each other. The pattern of one of the third wiring pattern and the fourth wiring pattern is electrically connected to the first node via the second via conductor, and the third wiring pattern and the fourth portion are formed. The other of the wiring patterns is electrically connected to the second node via the third via conductor. Further, the first wiring pattern, the second wiring pattern, the third wiring pattern, and the fourth wiring pattern are formed to overlap each other, and between the third wiring pattern and the fourth wiring pattern The overlapping area is larger than the overlapping area between the second wiring pattern and the third wiring pattern. -15- 200835042

如此這般，藉由在相互鄰接之2個的配線層處形成輸 入節點以及輸出節點，與前述之內容相同的，成爲能夠增 加此些之節點間的電容値。又，藉由將此輸入節點以及輸 出節點連接於在第3以及第4配線層處而被形成於板狀之 配線圖案（電容圖案），能夠更進而使電容値增大。藉由 此，能實現小型的又或是低成本的並聯共振電路，而藉由 將此適用於高頻模組之濾波電路等之中，成爲能夠實現該 模組之小型化又或是低成本化。另外，爲了追求更進一步 的小型化，可將第1配線圖案、第2配線圖案以及電容圖 案之從上層而平面視之時之各別的佔有區域，設爲使任一 者之佔有區域包含有其他之佔有區域的關係。 又，本發明之其中一種實施形態所致之RF模組，係 包含有：RF電力放大器（ΗΡΑ )、和輸出整合電路（12c )、和方向性結合器（1 3 )、和高頻波除去濾波器（1 4 ) 。前述RF電力放大器之輸出放大訊號（Pout )係被供給 至前述輸出整合電路之輸入端子，前述輸出整合電路之輸 出端子的RF訊號，係經由前述方向性結合器之主線路， 而被供給至前述高頻波除去濾波器之輸入端子。從前述方 向性結合器之副線路而來的檢測訊號（Vcp 1 )，係被供給 至前述RF電力放大器（ΗΡΑ )之增益控制單元（17 )的 訊號輸入端子。前述高頻波除去濾波器之輸出端子的RF 訊號，係成爲可被傳達至天線（16)(參考圖19)。 若藉由此種構成，則就算是RF電力放大器之輸出放 大訊號（Pout)的局頻波成分，係成爲經由方向性結合器 -16- 200835042 (1 3 )之副線路與增益控制單元（1 7 )之間的訊號配線、 方向性結合器（1 3 )之副線路以及主線路而傳達，在方向 性結合器（1 3 )之主線路與天線（1 6 )之間，亦係連接有 高頻波除去濾波器（1 4 )。故而，能夠避免RF電力放大 器之輸出的高準位之高頻波成分，經由方向性結合器之副 線路與增益控制單元之間的訊號配線、方向性結合器之副 .線路以及主線路，而傳達至天線。As described above, by forming the input node and the output node in the wiring layers adjacent to each other, the capacitance 値 between the nodes can be increased as described above. Further, by connecting the input node and the output node to the wiring pattern (capacitance pattern) formed in the plate shape at the third and fourth wiring layers, the capacitance 値 can be further increased. As a result, a small-sized or low-cost parallel resonant circuit can be realized, and by applying this to a filter circuit of a high-frequency module or the like, it is possible to achieve downsizing or cost reduction of the module. In addition, in order to further reduce the size, the occupied area of each of the first wiring pattern, the second wiring pattern, and the capacitance pattern from the upper layer and the planar view may be included in any occupied area. Others occupy the relationship of the region. Furthermore, an RF module according to one embodiment of the present invention includes: an RF power amplifier (ΗΡΑ), an output integration circuit (12c), a directional combiner (13), and a high-frequency wave removal filter. (1 4 ). The output amplification signal (Pout) of the RF power amplifier is supplied to an input terminal of the output integration circuit, and an RF signal of an output terminal of the output integration circuit is supplied to the aforementioned main line via the directional connector. The input terminal of the high frequency wave removal filter. A detection signal (Vcp 1 ) from the sub-line of the above-described directional combiner is supplied to a signal input terminal of the gain control unit (17) of the RF power amplifier (ΗΡΑ). The RF signal of the output terminal of the high-frequency wave removing filter can be transmitted to the antenna (16) (refer to FIG. 19). With this configuration, even the local frequency component of the output amplification signal (Pout) of the RF power amplifier becomes the sub-line and gain control unit via the directional coupler-16-200835042 (1 3 ) (1) 7) The signal wiring between the directional connector (1 3 ) and the main line is communicated between the main line of the directional bonder (13) and the antenna (16). The high frequency wave removes the filter (1 4 ). Therefore, the high-frequency wave component capable of avoiding the high level of the output of the RF power amplifier is transmitted to the signal wiring between the sub-line of the directional combiner and the gain control unit, the sub-line of the directional combiner, and the main line. antenna.

[發明之效果] 藉由使用本發明之其中一種實施形態所致的電子裝置 以及高頻模組，成爲能夠實現小型化又或是低成本化。 【實施方式】 (代表性之實施形態） 首先，針對在本案中所揭示之發明的代表性之實施形 φ 態的槪要作說明。在對於代表性的實施形態之槪要說明中 之附加有括弧並作參考的圖面之參考符號，係僅爲將被包 含於附加有該符號之構成要素的槪念中之物作例示者。 (1 )本發明之代表性的實施形態中之電子裝置，係 藉由包含有第1配線層（LY1)、和被配置在前述第1配 線層之下層的第2配線層（LY2 )、和被配置在前述第2 配線層之下層的第3配線層（LY3 )之複數配線層基板而 實現。於此，該電子裝置，第1配線圖案，係具備有：在 前述第1配線層中作爲略迴路（loop)狀之線路而被形成 -17· 200835042 ，且於一端具備有第1節點（Nin )的第1配線圖案（ MS21 );和在前述第2配線層中作爲略迴路（l〇op )狀之 線路的方式而被形成，且於一端具備有第2節點（N 〇 u t ) 的第2配線圖案（MS22) •，和在前述第3配線層中、或[Effects of the Invention] By using the electronic device and the high-frequency module according to one embodiment of the present invention, it is possible to achieve downsizing or cost reduction. [Embodiment] (Representative Embodiment) First, a brief description will be given of a representative embodiment of the invention disclosed in the present invention. The reference numerals of the drawings to which the parentheses are attached and which are referred to in the description of the representative embodiments are merely exemplified as objects included in the complication of the constituent elements to which the symbols are attached. (1) An electronic device according to a representative embodiment of the present invention includes a first wiring layer (LY1) and a second wiring layer (LY2) disposed under the first wiring layer, and It is realized by a plurality of wiring layer substrates disposed on the third wiring layer (LY3) under the second wiring layer. In the electronic device, the first wiring pattern is formed as a loop-like line in the first wiring layer, and a first node (Nin) is provided at one end. a first wiring pattern (MS21); and a second circuit layer having a second loop (N 〇 ut ) at one end thereof; 2 wiring pattern (MS22) •, and in the aforementioned third wiring layer, or

是從前述第3配線層而橫跨至更爲下層，而作爲單數次又 或是複數次之略迴路（loop )狀之線路而被形成的電感圖 案（MS2 3以及MS24);和將前述第1配線圖案之另外一 端與前述電感圖案之其中一端電性連接的第1通孔導體（ VH1 3a);和將前述第2配線圖案之另外一端與前述電感 圖案之另外一端電性連接的第2通孔導體（VH24a)，前 述第1配線層與前述第2配線層，係成爲相互鄰接之配線 層（參考圖2)。 於此，由更具體之實施形態所致之電子裝置，係成爲 :前述複數配線層基板係更進而具備有被配置在前述第3 配線層（LY3 )之下層的第4配線層（LY4 )，在前述第3 φ 配線層內，係具備有作爲略迴圈狀之線路而被形成且成爲 前述電感圖案之一部分的第3配線圖案（MS23 )，在前 述第4配線層內，係具備有作爲略迴圏狀之線路而被形成 且成爲前述電感圖案之另外一部分的第4配線圖案（ MS24)。於此，前述第3配線圖案之其中一端，係經由 前述第1通孔導體（VH1 3a)而被連接於前述第1配線圖 案之另外一端，前述第3配線圖案之另外一端，係經由第 3通孔導體（VH34a)而被電性連接於前述第4配線圖案 之其中一端，前述第4配線圖案之另外一端，係經由前述 -18- 200835042 第2通孔導體（VH24a)而被電性連接於前述配線圖案之 另外一端（參考圖2)。 又，在由更爲合適之實施形態所致之電子裝置中，前 述第1配線圖案、前述第2配線圖案以及前述電感圖案之 從上層而平面視之時之各別的佔有區域（AA21〜AA24 ) ，係成爲使任一者之佔有區域包含有其他之佔有區域的關 係（參考圖4)。An inductance pattern (MS2 3 and MS24) formed as a single-numbered circuit or a plurality of loop-like lines from the third wiring layer to the lower layer, and the foregoing a first via-hole conductor (VH1 3a) electrically connected to one end of the inductance pattern at one end of the wiring pattern; and a second via-electrode connecting the other end of the second wiring pattern to the other end of the inductance pattern In the via-hole conductor (VH24a), the first wiring layer and the second wiring layer are mutually adjacent wiring layers (refer to FIG. 2). In the electronic device according to the more specific embodiment, the plurality of wiring layer substrates further include a fourth wiring layer (LY4) disposed under the third wiring layer (LY3). In the third φ wiring layer, a third wiring pattern (MS23) which is formed as a portion of the loop pattern and which is a part of the inductance pattern is provided, and the fourth wiring layer is provided in the fourth wiring layer. A fourth wiring pattern (MS24) which is formed slightly back into the meandering line and which is another part of the above-described inductance pattern. Here, one end of the third wiring pattern is connected to the other end of the first wiring pattern via the first via-hole conductor (VH1 3a), and the other end of the third wiring pattern is via the third The via-hole conductor (VH34a) is electrically connected to one end of the fourth wiring pattern, and the other end of the fourth wiring pattern is electrically connected via the -18-200835042 second via-hole conductor (VH24a). At the other end of the aforementioned wiring pattern (refer to FIG. 2). Further, in the electronic device according to the more preferable embodiment, the first wiring pattern, the second wiring pattern, and the respective occupied regions of the inductance pattern from the upper layer in plan view (AA21 to AA24) ) is a relationship in which any occupied area is included in another occupied area (refer to FIG. 4).

進而，在由其他之更爲合適之實施形態所致之電子裝 置中，前述第1配線圖案（MS21)以及前述第2配線圖 案（MS22 )的最大線寬幅，係成爲較前述電感圖案（ MS 23以及MS 24)之最大線寬幅爲更大者。 進而，在由其他之合適之實施形態所致之電子裝置中 ，前述複數配線基板之最下層或者是最上層，係成爲接地 電極（參考圖3 )。 進而，在由其他之合適之實施形態所致之電子裝置中 ，前述一般之電子裝置，係包含有帶域遮斷濾波器（LPF —HB、LPF 一 LB、ANT—FIL、RX—FIL)(參考圖 8)。 進而，在由其他之合適之實施形態所致之電子裝置中 ，前述一般之電子裝置，係包含有被形成在前述複數配線 層基板內之高頻波減衰用的帶域遮斷濾波器（LPF_ HB、 LPF 一 LB、ANT—FIL、RX—FIL)，在前述複數配線層基 板上’係被安裝有包含電力放大電路之第1半導體晶片（ PA 一 CP )與包含天線開關電路（ANT— SW)之第2半導 體晶片’前述帶域遮斷濾波器，係被連接於前述天線開關 19-Further, in the electronic device according to another embodiment, the maximum line width of the first wiring pattern (MS21) and the second wiring pattern (MS22) is higher than the inductance pattern (MS). 23 and MS 24) The maximum line width is larger. Further, in the electronic device according to another suitable embodiment, the lowermost layer or the uppermost layer of the plurality of wiring boards is a ground electrode (refer to Fig. 3). Furthermore, in an electronic device caused by other suitable embodiments, the above-mentioned general electronic device includes a band-blocking filter (LPF-HB, LPF-LB, ANT-FIL, RX-FIL) ( Refer to Figure 8). Further, in an electronic device according to another suitable embodiment, the general electronic device includes a band-stop filter (LPF_HB, which is used for high-frequency wave attenuation in the plurality of wiring layer substrates). LPF-LB, ANT-FIL, and RX-FIL) are mounted on the plurality of wiring layer substrates with a first semiconductor wafer (PA-CP) including a power amplifier circuit and an antenna switch circuit (ANT-SW). The second semiconductor wafer 'the aforementioned band-stop filter is connected to the antenna switch 19-

200835042 電路（參考圖1以及圖8)。 如上述一般，本發明之代表性的實施形態之 ，係使用複數配線基板，並將第1配線層的第1 ，和鄰接於此第1配線圖案之第2配線層的第2 ，形成爲至少具備有電感成分之形狀，並進而， 此第1以及第2配線層之層，形成電感圖案，而 而，此第1配線圖案之其中一端，係被作爲輸入 出節點，而另外一端，係經由通孔導體而被連接 電感圖案的其中一端。另一方面，第2配線圖案 端，係被作爲輸出又或是輸入節點，而另外一端 通孔導體而被連接於前述之電感圖案的另外一端 ，此電子裝置，係作爲並聯共振電路而起作用。 如此這般，藉由在相互鄰接之2個的配線層 方設置輸入又或是輸出節點，並在另外一方設置 是輸入節點，相較於設置在未鄰接之配線層的情 能夠增加輸入節點與輸出節點間之電容値。故而 夠以小面積而確保充分的電容値，因此能實現小 是低成本的並聯共振電路，而藉由將此適用於高 濾波電路等之中，成爲能夠實現該模組之小型化 成本化。另外，爲了更進而增大電容値，可將第 案與第2配線圖案之最大線寬幅設爲較電感圖案 寬幅爲更大。又，藉由將複數配線基板之最下層 上層作爲接地電極，成爲可因應於此接地電極與 案以及電感圖案間之距離關係，來適宜調整並聯 電子裝置 配線圖案 配線圖案 在相異於 被構成。 又或是輸 於前述之 之其中一 ，係經由 。亦即是 的其中一 輸出又或 況，成爲 ，由於能 型的又或 頻模組之 又或是低 1配線圖 之最大線 或者是最 各配線圖 共振電路 -20- 200835042 之電感値。 (2 )由其他觀點所致之實施形態中之電子裝置，係 藉由包含有第1配線層（LY1)、和被配置在前述第1配 線層之下層的第2配線層（LY2)、和被配置在前述第2 配線層之下層的第3配線層（LY3 )、和被配置於前述第 3配線層之下層的第4配線層（LY4)之複數配線層基板200835042 circuit (refer to Figure 1 and Figure 8). As described above, in a typical embodiment of the present invention, a plurality of wiring boards are used, and the first of the first wiring layer and the second wiring layer adjacent to the second wiring layer of the first wiring layer are formed at least. The shape of the inductor component is provided, and further, the layers of the first and second wiring layers form an inductance pattern, and one end of the first wiring pattern is used as an input/output node, and the other end is via The via hole conductor is connected to one end of the inductance pattern. On the other hand, the second wiring pattern end is connected as an output or an input node, and the other end via-hole conductor is connected to the other end of the above-described inductance pattern, and the electronic device functions as a parallel resonance circuit. . In this way, by providing an input or an output node on two adjacent wiring layers and setting an input node on the other side, the input node can be increased compared to the wiring layer disposed adjacent to the other. The capacitance between the output nodes is 値. Therefore, a sufficient capacitance 値 can be secured in a small area, so that a low-cost parallel resonant circuit can be realized, and by applying this to a high-filter circuit or the like, the cost of the module can be reduced. Further, in order to further increase the capacitance 値, the maximum line width of the first wiring pattern and the second wiring pattern can be made larger than the width of the inductance pattern. Further, by using the uppermost layer of the plurality of wiring boards as the ground electrode, it is possible to appropriately adjust the wiring pattern of the parallel electronic device in accordance with the distance relationship between the ground electrode and the inductance pattern. Or lose one of the above, through. That is, one of the outputs is either the maximum line of the energy mode or the frequency module or the low line 1 or the inductance of the most wiring pattern resonance circuit -20-200835042. (2) The electronic device according to the embodiment of the present invention includes the first wiring layer (LY1) and the second wiring layer (LY2) disposed under the first wiring layer, and a plurality of wiring layer substrates disposed on the third wiring layer (LY3) under the second wiring layer and the fourth wiring layer (LY4) disposed under the third wiring layer

而實現。而，該電子裝置，係具備有：在前述第配線層 中作爲略迴路（loop)狀之線路而被形成，且於一端具備 有第1節點（Nin)的第1配線圖案（MS31 ) •，和在前述 第2配線層中作爲略迴路（loop)狀之線路的方式而被形 成，且於一端具備有第2節點（Nout )的第2配線圖案（ MS32 ):和在前述第3配線層內，被形成爲平板狀之第3 配線圖案（MS33);和在前述第4配線層內，被形成爲 平板狀之第4配線圖案（MS34 );和將前述第1配線圖 案之另外一端與前述第2配線圖案之另外一端電性連接的 第1通孔導體（VH 12b);和第2通孔導體；以及第3通 孔導體。於此，前述第3配線圖案與前述第4配線圖案， 係包含有相互對向之面，前述第3配線圖案與前述第4配 線圖案之其中一方，係經由前述第2通孔導體（VH 13b又 或是VH24b )而被電性連接於前述第1節點，前述第3配 線圖案與前述第4配線圖案之另外一方，係經由前述第3 通孔導體（VH24b又或是VH13b)而被電性連接於前述第 2節點，前述第1配線層（LY1)與前述第2配線層（LY2 )，係成爲相互鄰接之配線層。 -21 - 200835042 於此，在由更具體之實施形態所致之電子裝置中，前 述第3配線圖案（M S 3 3 )，係經由前述第2通孔導體（ VH13b)而與前述第1節點（Nin)電性連接，前述第4 配線圖案（MS34 )，係經由前述第3通孔導體（VH24b ) ，而與前述第2節點（Nout )電性連接（參考圖5 )。And realized. In addition, the electronic device includes a first wiring pattern (MS31) including a first node (Nin) at one end of the wiring layer as a loop-like line. And a second wiring pattern (MS32) having a second node (Nout) at one end and a third wiring layer formed on the second wiring layer as a loop-like line a third wiring pattern (MS33) formed in a flat shape; and a fourth wiring pattern (MS34) formed in a flat shape in the fourth wiring layer; and the other end of the first wiring pattern a first via-hole conductor (VH 12b) electrically connected to the other end of the second wiring pattern; and a second via-hole conductor; and a third via-hole conductor. Here, the third wiring pattern and the fourth wiring pattern include mutually opposing surfaces, and one of the third wiring pattern and the fourth wiring pattern passes through the second via-hole conductor (VH 13b) Or VH24b) is electrically connected to the first node, and the other of the third wiring pattern and the fourth wiring pattern is electrically connected via the third via conductor (VH24b or VH13b) The first wiring layer (LY1) and the second wiring layer (LY2) are connected to each other in the second node, and the wiring layers are adjacent to each other. In the electronic device according to a more specific embodiment, the third wiring pattern (MS 3 3 ) is connected to the first node via the second via-hole conductor (VH13b). Nin) is electrically connected, and the fourth wiring pattern (MS34) is electrically connected to the second node (Nout) via the third via conductor (VH24b) (refer to FIG. 5).

又，在由更爲合適之實施形態所致之電子裝置中，前 述第1〜前述第4配線圖案之從上層而平面視之時之各別 的佔有區域（AA31〜AA34 )，係成爲使任一者之佔有區 域（AA31或是AA32 )包含有其他之佔有區域的關係（參 考圖7 )。 進而，在由其他之合適之實施形態所致之電子裝置中 ，前述複數配線基板之最下層，係成爲接地電極（參考圖 6 )。Further, in the electronic device according to the more preferable embodiment, the respective occupied regions (AA31 to AA34) of the first to fourth wiring patterns from the upper layer in plan view are used as The occupied area (AA31 or AA32) contains the relationship of other occupied areas (refer to Figure 7). Further, in the electronic device according to another suitable embodiment, the lowermost layer of the plurality of wiring boards is a ground electrode (see Fig. 6).

進而，在由其他之合適之實施形態所致之電子裝置中 前述一般之電子裝置，係包含有帶域遮斷濾波器（LPF —HB、LPF 一 LB、ANT—FIL、RX—FIL )(參考圖 8)。 進而，在由其他之合適之實施形態所致之電子裝置中 ’前述一般之電子裝置，係包含有被形成在前述複數配線 層基板內之高頻波減衰用的帶域遮斷濾波器（LPF_ HB、 LPF— LB、ANT— FIL、RX—FIL )，在前述複數配線層基 板上，係被安裝有包含電力放大電路之第1半導體晶片（ PA—CP)與包含天線開關電路（ANT— SW)之第2半導 體晶片，前述帶域遮斷濾波器，係被連接於前述天線開關 電路（參考圖1以及圖8)。 -22- 200835042Furthermore, in the electronic device caused by other suitable embodiments, the above-mentioned general electronic device includes a band-blocking filter (LPF-HB, LPF-LB, ANT-FIL, RX-FIL) (Reference) Figure 8). Further, in the electronic device according to another suitable embodiment, the above-described general electronic device includes a band-stop filter (LPF_HB, which is used for high-frequency wave attenuation in the plurality of wiring layer substrates). LPF - LB, ANT - FIL, RX - FIL ), on the plurality of wiring layer substrates, a first semiconductor wafer (PA-CP) including a power amplifier circuit and an antenna switch circuit (ANT-SW) are mounted The second semiconductor wafer, the band-stop filter, is connected to the antenna switch circuit (see FIGS. 1 and 8). -22- 200835042

如上述一般，在以其他觀點所致之實施形態之電子裝 置中，係使用複數配線基板，並將第1配線層的第1配線 圖案，和鄰接於此第1配線圖案之第2配線層的第2配線 圖案，形成爲具備有電感成分之形狀，並進而，在成爲更 下層之第3配線層與第4配線層，形成電容圖案，而被構 成。而，此第1配線圖案之其中一端，係被作爲輸入又或 是輸出節點，同時，被連接於前述之電容圖案的其中一端 ，而第2配線圖案之其中一端，係被作爲輸出又或是輸入 節點，同時，被連接於前述之電容圖案的另外一端。又， 第1配線圖案之另外一端，係被連接於第2配線圖案之另 外一端，又或是經由被形成在其他層之電感圖案而被連接 於第2配線圖案之另外一端。亦即是，此電子裝置，係作 爲並聯共振電路而起作用。 如此這般，藉由在相互鄰接之2個的配線層處形成輸 入節點以及輸出節點，與前述之內容相同的，成爲能夠增 φ 加此些之節點間的電容値。又，藉由將此輸入節點以及輸 出節點連接於在被形成於第3以及第4配線層處之電容圖 案，能夠更進而使電容値增大。藉由此，能實現小型的又 或是低成本的並聯共振電路，而藉由將此適用於高頻模組 之濾波電路等之中，成爲能夠實現該模組之小型化又或是 低成本化。另外，爲了追求更進一步的小型化，可將第1 配線圖案、第2配線圖案以及電容圖案之從上層而平面視 之時之各別的佔有區域，設爲使任一者之佔有區域包含有 其他之佔有區域的關係。又，藉由將複數配線基板之最下 -23- 200835042 層作爲接地電極，由於此接地電極與第1以及第2配線圖 案間之距離係變長，因此成爲可充分確保並聯共振電路之 電感値。As described above, in the electronic device according to the embodiment of the present invention, the plurality of wiring boards are used, and the first wiring pattern of the first wiring layer and the second wiring layer adjacent to the first wiring pattern are used. The second wiring pattern is formed to have a shape including an inductance component, and further, a capacitor pattern is formed in the third wiring layer and the fourth wiring layer which are lower layers. One end of the first wiring pattern is used as an input or an output node, and is connected to one end of the capacitor pattern, and one end of the second wiring pattern is used as an output or The input node is simultaneously connected to the other end of the aforementioned capacitive pattern. Further, the other end of the first wiring pattern is connected to the other end of the second wiring pattern, or is connected to the other end of the second wiring pattern via an inductance pattern formed in another layer. That is, the electronic device functions as a parallel resonant circuit. As described above, by forming the input node and the output node in the wiring layers adjacent to each other, the capacitance 値 between the nodes which can be increased by φ can be increased as described above. Further, by connecting the input node and the output node to the capacitance pattern formed at the third and fourth wiring layers, the capacitance 能够 can be further increased. As a result, a small-sized or low-cost parallel resonant circuit can be realized, and by applying this to a filter circuit of a high-frequency module or the like, it is possible to achieve downsizing or cost reduction of the module. In addition, in order to further reduce the size, the occupied area of each of the first wiring pattern, the second wiring pattern, and the capacitance pattern from the upper layer and the planar view may be included in any occupied area. Others occupy the relationship of the region. In addition, since the lowermost -23-200835042 layer of the plurality of wiring boards is used as the ground electrode, the distance between the ground electrode and the first and second wiring patterns is long, so that the inductance of the parallel resonant circuit can be sufficiently ensured. .

(3 )由另外之其他觀點所致的實施形態之電子裝置 ，係成爲具備有··包含有第1配線層及相異於前述第1配 線層之第2配線層的複數配線層基板；和被配置於前述複 數配線層基板之上，包含有電力放大電路（PA一 HB )之 半導體晶片；和被形成在前述第1配線層（LY2)內，並 與前述電力放大電路之輸出作電容性結合之接地電壓用的 第1配線（MS72);和被形成在前述第2配線層（LY3 ) 內，並與前述電力放大電路之輸入作電容性結合之接地電 壓用的第2配線（參考圖1 0 )。 於此，由更爲合適之實施形態所致之電子裝置，係在 位置於前述複數配線基板中之前述半導體晶片的下部之區 域中，具備有藉由將各別之配線層以通孔導體來作電性連 接而被視爲一體之接地電壓區域的導熱孔（Thermal via， TV )之形成區域，前述第1配線，係在前述第1配線層內 ，被連接於前述導熱孔之形成區域，前述第2配線，係在 前述第2配線層內，被連接於前述導熱孔之形成區域（參 考圖1 0 )。 又，在由其他之合適之實施形態所致之電子裝置中， 前述第1配線以及前述第2配線，係經由複數之通孔導體 (VHm)而被電性連接。 進而，在由其他之合適之實施形態所致之電子裝置中 -24- 200835042 ，前述第1配線層，係被配置於前述第2配線層之上層（ 參考圖10)。 進而，在由其他之合適之實施形態所致之電子裝置中 ，前述電力放大電路，係經由複數段之電晶體而被構成， 前述複數段之電晶體的所有之段數，係被形成在相同之半 導體晶片（PA_CP)中（參考圖17)。(3) The electronic device according to the embodiment of the present invention includes a plurality of wiring layer substrates including a first wiring layer and a second wiring layer different from the first wiring layer; a semiconductor wafer including a power amplifier circuit (PA-HB) disposed on the plurality of wiring layer substrates; and formed in the first wiring layer (LY2) and capacitively coupled to an output of the power amplifier circuit a first wiring (MS72) for ground voltage to be combined, and a second wiring for ground voltage that is formed in the second wiring layer (LY3) and capacitively coupled to an input of the power amplifier circuit (reference drawing) 1 0 ). Here, an electronic device according to a more suitable embodiment is provided in a region located in a lower portion of the semiconductor wafer in the plurality of wiring substrates by using a via conductor as a via conductor a region in which a thermal via (TV) is formed as an integral ground voltage region, and the first wiring is connected to a formation region of the heat conduction hole in the first wiring layer. The second wiring is connected to the formation region of the heat conduction hole in the second wiring layer (refer to FIG. 10). Further, in the electronic device according to another embodiment, the first wiring and the second wiring are electrically connected via a plurality of via-hole conductors (VHm). Further, in the electronic device according to another embodiment, the second wiring layer is disposed on the upper layer of the second wiring layer (see FIG. 10). Further, in an electronic device according to another embodiment, the power amplifier circuit is configured by a plurality of transistors, and all of the plurality of transistors of the plurality of segments are formed in the same In the semiconductor wafer (PA_CP) (refer to Figure 17).

如上述一般，由另外其他之觀點所致的電子裝置，其 構成，係成爲具備被安裝有包含了電力放大電路之半導體 晶片的複數配線基板，在其之第1配線層內，被形成有與 電力放大電路之輸出作電容性結合的接地電壓用之第1配 線，在其之第2配線層內，被形成有與電力放大電路之輸 入作電容性結合的接地電壓用之第2配線。藉由此，從電 力放大電路之輸出而回歸至輸入的回歸電流係被減低，而 成爲可實現電子裝置（高頻模組）之小型化。又，藉由此 回歸電流之減低，就算是在將電力放大電路內之各段的電 晶體形成於1個的半導體晶片的情況中，錯誤動作等的問 題亦被消除，而成爲可實現高頻模組之小型化。 (4 )本發明之代表性的實施形態所致之RF模組，係 包含有：RF電力放大器（ΗΡΑ )、和輸出整合電路（12c )、和方向性結合器（1 3 )、和高頻波除去濾波器（1 4 ) 。前述RF電力放大器之輸出放大訊號（P〇ut)係被供給 至前述輸出整合電路之輸入端子，前述輸出整合電路之輸 出端子的RF訊號，係經由前述方向性結合器之主線路， 而被供給至則述局頻波除去瀘波器之輸入端子。從前述方 -25·As described above, the electronic device according to another aspect is configured to include a plurality of wiring boards on which a semiconductor wafer including a power amplifier circuit is mounted, and the first wiring layer is formed in the first wiring layer. The output of the power amplifying circuit is a first wiring for grounding voltage that is capacitively coupled, and a second wiring for grounding voltage that is capacitively coupled to an input of the power amplifying circuit is formed in the second wiring layer. As a result, the return current that is returned from the output of the power amplifier circuit to the input is reduced, and the electronic device (high-frequency module) can be miniaturized. Further, in the case where the transistor of each stage in the power amplifier circuit is formed on one semiconductor wafer by the reduction of the return current, the problem of malfunction or the like is eliminated, and the high frequency module can be realized. Miniaturization. (4) An RF module according to a representative embodiment of the present invention includes: an RF power amplifier (ΗΡΑ), an output integration circuit (12c), a directional combiner (13), and a high-frequency wave removal Filter (1 4 ). An output amplification signal (P〇ut) of the RF power amplifier is supplied to an input terminal of the output integration circuit, and an RF signal of an output terminal of the output integration circuit is supplied via a main line of the directional connector. Until the local frequency wave removes the input terminal of the chopper. From the aforementioned side -25·

200835042 向性結合器之副線路而來的檢測訊號（Vcpl )，係被供 至前述RF電力放大器（HP A )之增益控制單元（1 7 ) 訊號輸入端子。前述高頻波除去濾波器之輸出端子的 訊號，係成爲可被傳達至天線（16)(參考圖19)。 若藉由前述之實施形態，則就算是RF電力放大器 輸出放大訊號（Pout )的高頻波成分，係成爲經由方向 結合器（1 3 )之副線路與增益控制單元（1 7 )之間的訊 配線、方向性結合器（1 3 )之副線路以及主線路而傳達 在方向性結合器（1 3 )之主線路與天線（1 6 )之間，亦 連接有高頻波除去濾波器（1 4 )。故而，能夠避免於？ 力放大器之輸出的高準位之高頻波成分，經由方向性結 器之副線路與增益控制單元之間的訊號配線、方向性結 器之副線路以及主線路，而傳達至天線。 以合適之實施形態所致之RF模組，係更進而包含 :天線開關（1 5 )，前述高調波除去濾波器之前述輸出 子的前述RF訊號，係被供給至天線開關之其中一方之 子，而另外一方之端子的RF訊號，係可被傳達至前述 線。 若藉由前述合適之實施形態，則成爲可提供高功 RF模組。 在合適之實施形態所致之RF模組中，前述高調密 去濾波器之前述輸出端子的前述RF訊號，係經由DC 斷電容器（Cd.c )，而被供給至前述天線開關之前述姜 一方的端子。 給 的 RF 之 性 Wi 係 電 合 合 有 端 端 天 之 除 截 中 -26- 200835042 若藉由則述合適之實施形悲’則Μ於由則述電力整合 電路與前述方向性結合器以及前述高頻波除去濾波器所成 的訊號路徑的相位回轉之調整係變爲容易，又，成爲可減 低在前述天線開關處的訊號歪曲。又，藉由前述高頻波除 去濾波器之前述輸出端子的前述DC截斷電容器，而成爲 能夠使方向性結合器之方向性結合度的調整亦變爲容易。200835042 The detection signal (Vcpl) from the secondary line of the sex combiner is supplied to the gain control unit (17) signal input terminal of the aforementioned RF power amplifier (HP A). The signal of the output terminal of the high-frequency wave removing filter is transmitted to the antenna (16) (refer to Fig. 19). According to the above-described embodiment, even if the high-frequency component of the RF power amplifier output amplification signal (Pout) is connected between the sub-line via the direction combiner (13) and the gain control unit (17), The sub-line of the directional coupler (13) and the main line are transmitted between the main line of the directional bonder (13) and the antenna (16), and a high-frequency wave removing filter (14) is also connected. So, can you avoid it? The high-frequency component of the high-level output of the power amplifier is transmitted to the antenna via the signal wiring between the sub-line of the directional amplifier and the gain control unit, the sub-line of the directional rectifier, and the main line. The RF module according to a suitable embodiment further includes an antenna switch (15), and the RF signal of the output of the high-frequency wave removing filter is supplied to one of the antenna switches. The RF signal of the other terminal can be transmitted to the aforementioned line. According to the above-described suitable embodiment, a high-power RF module can be provided. In an RF module according to a preferred embodiment, the RF signal of the output terminal of the high-density filter is supplied to the ginger of the antenna switch via a DC capacitor (Cd.c). One terminal. The RF integrated Wi-electricity is combined with the end-end of the -26-200835042. If the appropriate implementation is described, then the power integration circuit and the aforementioned directional combiner and the foregoing The adjustment of the phase rotation of the signal path formed by the high-frequency wave removing filter is facilitated, and the signal distortion at the antenna switch can be reduced. Further, by removing the DC cut capacitor of the output terminal of the filter by the high-frequency wave, it is easy to adjust the directivity coupling degree of the directional bond.

在由更合適之實施形態所致之RF模組中，前述RF 電力放大器，係包含有：多段放大器（10a、11a、12a) 、和藉由前述增益控制單元而被控制，並對前述多段放大 器之增益作控制的偏壓電路（l〇b、lib、12c)。 在以具體之實施形態所致之RF模組中，前述輸出整 合電路，係爲將由產生前述RF電力放大器之前述輸出放 大訊號（Pout )的輸出電感和前述天線（16 )之電感之間 的差所致的訊號反射減低者。 若藉由前述具體之實施形態，則成爲可減輕因電感不 整合所致之電力效率的降低。 在更爲具體之實施形態所致之RF模組中，前述多段 放大器、和前述偏壓電路、和前述增益控制單元，係被形 成在半導體積體電路晶片上。 在更爲具體之實施形態所致之RF模組中，前述方向 性結合器，係爲在主線路與副線路之間被連接有電容元件 之微親合器。 (5 )以其他觀點所致的實施形態之RF模組（1 00 ) ，係包含有：第1RF電力放大器（HPA1 )、和第1輸出 -27-In the RF module caused by a more suitable embodiment, the RF power amplifier includes: a multi-segment amplifier (10a, 11a, 12a), and is controlled by the gain control unit, and the foregoing multi-segment amplifier The gain is controlled by a bias circuit (l〇b, lib, 12c). In the RF module according to the specific implementation form, the output integration circuit is a difference between an output inductance of the output amplification signal (Pout) generating the RF power amplifier and an inductance of the antenna (16). The resulting signal reflection is reduced. According to the specific embodiment described above, it is possible to reduce the decrease in power efficiency due to inductance integration. In the RF module of a more specific embodiment, the multi-stage amplifier, the bias circuit, and the gain control unit are formed on a semiconductor integrated circuit wafer. In the RF module of a more specific embodiment, the directional coupler is a micro-coupler in which a capacitive element is connected between the main line and the sub-line. (5) The RF module (1 00) according to the embodiment of the present invention includes: a first RF power amplifier (HPA1), and a first output -27-

200835042 整合電路（22e)、和第1方向性結合器（23) 高頻波除去濾波器（24)、和第2RF電力放大] )、和第2輸出整合電路（12c)、和第2方向 (1 3 )、和第2高頻波除去濾波器（1 4 )。 前述第1RF電力放大器，係以將第1頻率帶 號（Rfin_LB)作放大的方式而被構成，前述第 放大器，係以將較前述第1頻率帶域RF訊號爲 率的第2頻率帶域RF訊號（Rfin_ HB )作放大 被構成。 前述第1RF電力放大器之第1輸出放大訊號 LB )係被供給至前述第1輸出整合電路之輸入端 第1輸出整合電路之輸出端子的第1RF訊號，係 第1方向性結合器之主線路，而被供給至前述第 除去濾波器之輸入端子。從前述第1方向性結合 路而來的第1檢測訊號（Vcpl_ LB )，係被供給 1RF電力放大器（ΗΡΑ)之第1增益控制單元（ 1訊號輸入端子。前述第1高頻波除去濾波器之 的第1RF訊號，係成爲可被傳達至天線（16)。 前述第2RF電力放大器之第2輸出放大訊號 ΗΒ)係被供給至前述第2輸出整合電路之輸入端 第2輸出整合電路之輸出端子的第2RF訊號，係 第2方向性結合器之主線路，而被供給至前述第 除去濾波器之輸入端子。從前述第2方向性結合 路而來的第2檢測訊號（Vcpl_HB)，係被供給 、和第1 I ( HPA2 性結合器 域RF訊 2RF電力 更高之頻 的方式而 (Pout — 子，前述 經由前述 1高頻波 器之副線 至前述第 27)的第 輸出端子 (Pout — 子，前述 經由前述 2高頻波 器之副線 至前述第 -28- 200835042 2RF電力放大器之第2增益控制單元（17)的第2訊號輸 入端子。前述第2高頻波除去濾波器之輸出端子的第2RF 訊號，係成爲可被傳達至前述天線（參考圖20)。 若藉由前述實施形態，則能夠避免對應於多帶域的 RF電力放大器之輸出的高準位之高頻波成分，經由方向 性結合器之副線路與增益控制單元之間的訊號配線、方向 性結合器之副線路以及主線路，而傳達至天線。200835042 integrated circuit (22e), and first directional coupler (23) high frequency wave removing filter (24), and second RF power amplification]), and second output integrating circuit (12c), and second direction (1 3 And the second high-frequency wave removing filter (1 4 ). The first RF power amplifier is configured to amplify a first frequency band number (Rfin_LB), and the first amplifier is a second frequency band RF having a rate higher than the first frequency band RF signal. The signal (Rfin_HB) is amplified. The first output amplification signal LB of the first RF power amplifier is supplied to the first RF signal of the output terminal of the first output integration circuit at the input end of the first output integration circuit, and is the main line of the first directional connector. And supplied to the input terminal of the aforementioned removal filter. The first detection signal (Vcpl_LB) from the first directional combining path is supplied to the first gain control unit (1 signal input terminal) of the 1RF power amplifier (the first high frequency removal filter) The first RF signal is transmitted to the antenna (16). The second output amplification signal of the second RF power amplifier is supplied to the output terminal of the second output integration circuit at the input end of the second output integration circuit. The second RF signal is a main line of the second directional combiner and is supplied to an input terminal of the aforementioned removal filter. The second detection signal (Vcpl_HB) from the second directional combining path is supplied and the first I (the HPA2-type combiner domain RF signal 2RF power is higher frequency (Pout-sub, the aforementioned Passing the sub-line of the first high-frequency wave device to the output terminal of the 27th) (Pout, the second gain control unit (17) via the sub-line of the second high-frequency wave device to the -28-200835042 2 RF power amplifier The second signal input terminal of the second high-frequency wave removing filter is transmitted to the antenna (refer to FIG. 20). The high-frequency component of the high-level output of the RF power amplifier of the domain is transmitted to the antenna via the signal wiring between the sub-line of the directional combiner and the gain control unit, the sub-line of the directional combiner, and the main line.

在合適的實施形態所致之RF模組中，前述第1高調 波除去濾波器之前述輸出端子的前述第1 RF訊號，係被供 給至天線開關（1 5 )之第1輸入端子，前述第2高調波除 去濾波器之前述輸出端子的前述第2RF訊號，係被供給至 前述天線開關之第2輸入端子。前述天線開關之輸出端子 的RF訊號，係成爲可被傳達至前述天線（1 6 )。 在合適之實施形態所致之RF模組中，前述第1高調 波除去濾波器之前述輸出端子的前述第1 RF訊號，係經由 第1DC截斷電容器（Cdc)，而被供給至前述天線開關之 前述第1輸入端子。前述第2高調波除去濾波器之前述輸 出端子的前述第2RF訊號，係經由第2DC截斷電容器（ Cdx )’而被供給至前述天線開關之前述第2輸入端子。 在合適之實施形態所致之RF模組中，前述第1 RF電 力放大器、和前述第2RF電力放大器、和前述第1增益控 制單元 '和前述第2增益控制單元，係被形成在半導體積 體電路晶片上。 前述半導體積體電路晶片，係實質上具備有4角形之 -29- 200835042 晶片的形狀。前述晶片’係具備有相互對向且略平行之第 !邊（Sdl)與第2邊（Sd2)。前述晶片，係更進而具備 有··被連接於前述第1邊與第2邊，且被配置爲和前述第 1邊與前述第2邊成略直角之第3邊（Sd3)，和對向於 前述第3邊，而與前述第3邊略平行之第4邊（Sd4)。In the RF module according to the preferred embodiment, the first RF signal of the output terminal of the first high-frequency wave removing filter is supplied to the first input terminal of the antenna switch (15), and the first The second RF signal of the output terminal of the high-frequency wave removing filter is supplied to the second input terminal of the antenna switch. The RF signal of the output terminal of the antenna switch is transmitted to the antenna (16). In the RF module according to the embodiment, the first RF signal of the output terminal of the first high-frequency wave removing filter is supplied to the antenna switch via a first DC cut capacitor (Cdc). The first input terminal. The second RF signal of the output terminal of the second high-frequency wave removing filter is supplied to the second input terminal of the antenna switch via the second DC cut capacitor (Cdx)'. In an RF module according to a preferred embodiment, the first RF power amplifier, the second RF power amplifier, the first gain control unit', and the second gain control unit are formed in a semiconductor integrated body. On the circuit chip. The semiconductor integrated circuit wafer is substantially in the shape of a square -29-200835042 wafer. The wafer ' is provided with a first side (Sd1) and a second side (Sd2) which are opposite to each other and are slightly parallel. The wafer further includes a third side (Sd3) that is connected to the first side and the second side, and is disposed at a right angle to the first side and the second side, and a direction On the third side, the fourth side (Sd4) is slightly parallel to the third side.

前述第1RF電力放大器之前述第1輸出放大訊號（ P〇ut_LB)係從前述晶片之前述第1邊而被導出，前述第 2RF電力放大器之前述第2輸出放大訊號（P〇ut_HB)， 係從前述晶片之前述第2邊而被導出。從前述第1方向性 結合器（2 3 )之前述副線路而來的前述第1檢測訊號（ Vcpl_ LB )，係從前述晶片之前述第3邊，而被導入至前 述第1RF電力放大器之前述第1增益控制單元（27)的前 述第1訊號輸入端子。從前述第2方向性結合器（13 )之 前述副線路而來的前述第2檢測訊號（Vcpl_ HB )，係從 前述晶片之前述第3邊，而被導入至前述第2RF電力放大 器之前述第2增益控制單元（17)的前述第2訊號輸入端 子（參考圖20、圖21)。 若藉由前述合適之實施形態，則能夠將前述第1輸出 放大訊號的前述晶片之前述第1邊的導出點、與前述第1 檢測訊號的前述晶片之前述第3邊的導入點，其兩者間之 距離變大。能夠將前述第2輸出放大訊號的前述晶片之前 述第2邊的導出點、與前述第2檢測訊號的前述晶片之前 述第3邊的導入點，其兩者間之距離變大。故而，能夠將 被傳達至增益控制單元之訊號輸入端子的輸出放大訊號之 •30- 200835042 高頻波成分的準位降低。The first output amplification signal (P〇ut_LB) of the first RF power amplifier is derived from the first side of the wafer, and the second output amplification signal (P〇ut_HB) of the second RF power amplifier is derived from The second side of the wafer is derived. The first detection signal (Vcpl_LB) from the sub-line of the first directional bonder (23) is introduced into the first RF power amplifier from the third side of the wafer The first signal input terminal of the first gain control unit (27). The second detection signal (Vcpl_Hb) from the sub-line of the second directional bonder (13) is introduced from the third side of the wafer to the second RF power amplifier 2 The second signal input terminal of the gain control unit (17) (refer to Figs. 20 and 21). According to the above-described preferred embodiment, the lead-out point of the first side of the wafer of the first output amplification signal and the lead-in point of the third side of the wafer of the first detection signal can be two The distance between the people becomes larger. The lead-out point of the second side of the wafer of the second output amplification signal and the lead-in point of the third side of the wafer corresponding to the second detection signal can be increased. Therefore, the level of the high-frequency wave component of the output amplification signal transmitted to the signal input terminal of the gain control unit can be lowered.

在更合適之實施形態所致的RF模組中，在前述第1 輸出放大訊號（Pout一 LB )之前述第1邊的導出點、與前 述第1檢測訊號（Vcpl_ LB )之前述第3邊的導入點之間 ，係被配置有前述第2檢測訊號（VcPi一 HB )之前述第3 邊的導入點。在前述第2輸出放大訊號（P〇ut 一 HB )之前 述第2邊的導出點、與前述第2檢測訊號（Vcpl 一 HB)之 前述第3邊的導入點之間，係被配置有前述第1檢測訊號 (Vcpl__ LB )之前述第3邊的導入點（參考圖20、圖21 若藉由前述更合適之實施形態’則能夠將被傳達至增 益控制單元之訊號輸入端子的輸出放大訊號之高頻波成分 的準位更進一步降低。 在其他之更合適之實施形態所致的RF模組中，在前 述第1輸出放大訊號（P〇ut_ LB )之前述第1邊的導出點 、與前述第1檢測訊號（VCpl_ LB )之前述第3邊的導入 點之間，被連接於接地電壓（GND )之第1接地配線（ 402 )，係被連接於前述第3邊。在前述第2輸出放大訊 號（Pout—HB)之前述第2邊的導出點、與前述第2檢測 訊號（Vcpl一HB)之前述第3邊的導入點之間，被連接於 接地電壓（GND )之第2接地配線（404 )，係被連接於 前述第3邊。（參考圖21) 在具體之實施形態所致的RF模組中，前述第1接地 配線（402 ) ’係前述第3邊之近旁，被配置在前述第2 -31 - 200835042 檢測訊號（Vcpl_ HB)之前述導入點與前述第1檢測訊號 (Vcpl_ LB )之前述導入點之間。前述第2接地配線（ 404 )，係前述第3邊之近旁，被配置在前述第1檢測訊 號（Vcpl_ LB)之前述導入點與前述第2檢測訊號（Vcpl _ HB )之前述導入點之間（參考圖2 1 )。In an RF module according to a more suitable embodiment, the first side of the first output amplification signal (Pout-LB) and the third side of the first detection signal (Vcpl_LB) The lead-in points of the third side of the second detection signal (VcPi-HB) are arranged between the lead-in points. The lead-out point of the second side of the second output amplification signal (P〇ut-HB) and the lead-in point of the third side of the second detection signal (Vcpl-HB) are arranged The introduction point of the third side of the first detection signal (Vcpl__ LB ) (refer to FIG. 20 and FIG. 21, if the above-described more appropriate embodiment is used), the output amplification signal transmitted to the signal input terminal of the gain control unit can be transmitted. The level of the high-frequency wave component is further reduced. In another RF module according to another embodiment, the derivation point of the first side of the first output amplification signal (P〇ut_LB) and the foregoing The first ground wiring (402) connected to the ground voltage (GND) between the lead-in points of the third detecting signal (VCpl_LB) is connected to the third side. The second output is The second ground of the grounding voltage (GND) is connected between the lead-out point of the second side of the amplification signal (Pout-HB) and the lead-in point of the third side of the second detection signal (Vcpl-HB) Wiring (404) is connected to the third side. In the RF module according to the specific embodiment, the first ground wiring (402)' is disposed adjacent to the third side, and is disposed in the second -31 - 200835042 detection signal (Vcpl_ HB). The introduction point is between the introduction point of the first detection signal (Vcpl_LB), and the second ground line (404) is disposed in the vicinity of the third side and is disposed in the first detection signal (Vcpl_LB). The introduction point is between the introduction point of the second detection signal (Vcpl _ HB ) (refer to FIG. 21).

在由更爲具體之實施形態的RF模組中，前述第1頻 率帶域RF訊號（RfinLB )，係爲GSΜ8 5 0與GSΜ900之 RF送訊訊號，前述第2頻率帶域RF訊號（RfinHB )，係 爲DCS 1 8 00與PCS 1 900之RF送訊訊號（參考圖23 )。 在最爲具體之實施形態所致之RF模組中，前述第1 方向性結合器與前述第2方向性結合器，係分別爲藉由在 主線路與副線路之間被連接有電容元件之微耦合器所構成 《實施形態之說明》 接下來，針對實施形態更進而作詳述。在以.下之實施 形態中，爲了方便，當有所必要時，係分割爲複數之段落 又或是實施形態而作說明，但是，除了有特別明示的情況 之外，該些之間，係並非爲相互無關者，而係爲其中一方 具備有另外一方之一部分又或是全部的變形例、詳細內容 、補充說明等的關係。又，在以下之實施形態中，當言及 要素之數等（包含個數、數値、範圍等）時，除了特別有 所明示以及從原理上而言係明顯的被限定爲特定之數的情 況之外，則並非爲被限定於該特定之數者，而亦可爲特定 -32- 200835042 之數以上又或是以下。In a more specific embodiment of the RF module, the first frequency band RF signal (RfinLB) is an RF transmission signal of the GS Μ 850 and GS Μ 900, and the second frequency band RF signal (RfinHB) It is the RF signal of DCS 1 8 00 and PCS 1 900 (refer to Figure 23). In the RF module of the most specific embodiment, the first directional coupler and the second directional coupler are respectively connected by a capacitive element between the main line and the sub line. Description of Embodiments of Micro Coupler Next, the embodiment will be further described in detail. In the embodiment below, for convenience, when necessary, it is divided into plural paragraphs or embodiments, but in addition to the case where it is specifically stated, It is not a relationship that is not related to each other, and one of them has a modification, a detailed description, a supplementary explanation, and the like of one or both of the other. In addition, in the following embodiments, when the number of elements (including the number, the number, the range, and the like) is expressed, unless otherwise specified, and in principle, it is obvious that the number is limited to a specific number. In addition, it is not limited to the specific number, but may be more than or equal to the number of -32-200835042.

進而，在以下之實施形態中，其構成要素（亦包含要 素步驟等），除了有特別明示以及在原理上而言明顯地係 爲必要的情況等之外，不用說，係並不一定爲絕對必要者 。同樣的，在以下之實施形態中，當言及構成要素等之形 狀位置關係等時，除了有特別明示以及在原理上而言係可 明顯地想見並非如此情況等之外，係亦包含有與該形狀等 相近似又或是類似者。此事，對於上述數値以及範圍亦爲 同理。 以下，根據圖面，對本發明之實施形態作詳細說明。 另外，在用以說明實施形態之全圖中，對於相同之構件， 原則上係附加同樣的符號，並省略其重複說明。又，在以 下’作爲本發明之實施形態所致的電子裝置之其中一例， 係針對共振電路或包含有該共振電路之高頻模組的構成以 及動作等進行說明。 (實施形態1 ) 圖1，係爲在本發明之實施形態1所致的高頻模組中 ’展示其構成的一例之圖。本實施形態1之高頻模組（高 頻電力放大模組），例如，係被使用在行動電話等之移動 體通訊機器中，並成爲對應於低帶域之頻率帶與高帶域之 頻率帶的兩者。例如，在低帶域中，GSM ( Global System for Mobile Communication) 850 又或是 GSM90〇 等係符合 此，在高帶域中，GSM1 800又或是GSM1 900係符合此。 -33 - 200835042 於此，所謂GSM，係指在數位行動電話中所被使用之無限 通訊方式的規格。在GSM中，所使用之電波的頻率帶係 有 4 個，並將 900MHz 帶（880 〜960MHz)稱爲 GSM900 又或是單純稱爲 GSM。又，將 1 800MHz帶（1710〜 1 880MHz)稱爲 GSM1800 又或是 DCS1 800 或者是 PCN， 將 1900 MHz 帶（1850 〜1990MHz)稱爲 GSM1900 又或是 DCS 1 900 或者是 P C S ( P er s 〇 nal C ommuni c at i on S er vi c e sFurther, in the following embodiments, the constituent elements (including the element steps and the like) are not necessarily absolute except for the case where they are specifically indicated and are obviously necessary in principle. Necessary. Similarly, in the following embodiments, when the shape and positional relationship of the constituent elements and the like are mentioned, unless otherwise specified and in principle, it is obvious that this is not the case, and the like is also included. The shape is similar or similar. This matter is also the same for the above numbers and scope. Hereinafter, embodiments of the present invention will be described in detail based on the drawings. In the entire description of the embodiments, the same components are denoted by the same reference numerals, and the description thereof will not be repeated. In addition, an example of an electronic device according to an embodiment of the present invention will be described below with respect to a resonance circuit or a configuration and operation of a high-frequency module including the resonance circuit. (Embodiment 1) FIG. 1 is a view showing an example of a configuration of a high-frequency module according to Embodiment 1 of the present invention. The high-frequency module (high-frequency power amplifying module) according to the first embodiment is used, for example, in a mobile communication device such as a mobile phone, and is a frequency band corresponding to a low band and a high band. Both. For example, in the low-band domain, GSM (Global System for Mobile Communication) 850 or GSM90〇 conforms to this. In the high-band domain, GSM1 800 or GSM1 900 is compatible. -33 - 200835042 Here, GSM refers to the specification of the unlimited communication method used in digital mobile phones. In GSM, there are four frequency bands used for radio waves, and the 900MHz band (880 to 960MHz) is called GSM900 or simply GSM. Also, the 1 800 MHz band (1710 to 1 880 MHz) is called GSM1800 or DCS1 800 or PCN, and the 1900 MHz band (1850 to 1990 MHz) is called GSM1900 or DCS 1 900 or PCS (P er s 〇 Nal C ommuni c at i on S er vi ces

)。另外，GSM 1 900係主要在北美被使用。又，在北美， 除了 GSM1 900之外，亦有使用8 5 0MHz帶（824〜894MHz )之GSM8 50的情況，). In addition, the GSM 1 900 series is mainly used in North America. Also, in North America, in addition to the GSM1 900, there are also cases where the GSM8 50 with the 850 MHz band (824 to 894 MHz) is used.

於圖1中所示之高頻模組RF_ MDL，係以1個的多 層配線基板而實現，在多層配線基板上，係被安裝有：被 形成有功率放大電路（電力放大電路、高頻電力放大電路 )等之半導體晶片PA — CP、和被形成有天線開關電路 ANT一 SW的半導體晶片等。又，在RF— MDL中，係使用 SMD ( Surface Mount Device )構件或是多層配線基板支 配線圖案，而被形成有輸出整合電路MN_ LB、MN_ JB 、耦合電路（方向性結合器）CPL_ LB、CPL_ HB、以及 各種濾波電路 LPF— LB、LPF_ HB、ANY FIL、ESD FIL、RX FIL1、RX FIL2。 半導體晶片PA— CP，係具備有功率放大電路PA_ LB 、PA— HB，和控制電路CTL。PA— LB，係經由未圖示之 調變電路等，而將從外部輸入端子Pin _ LB所輸入之 GSM850或GSM900之類的低帶域的訊號放大。此被放大 -34- 200835042The high-frequency module RF_MDL shown in FIG. 1 is realized by one multi-layer wiring substrate, and a multi-layer wiring substrate is mounted with a power amplifying circuit (power amplifying circuit, high-frequency power amplifying circuit) a semiconductor wafer PA-CP, and the like, and a semiconductor wafer in which the antenna switching circuits ANT-SW are formed. Further, in the RF-MDL, an SMD (Surface Mount Device) member or a multilayer wiring substrate wiring pattern is used, and an output integration circuit MN_LB, MN_JB, a coupling circuit (directionality combiner) CPL_LB, and the like are formed. CPL_ HB, and various filter circuits LPF-LB, LPF_ HB, ANY FIL, ESD FIL, RX FIL1, RX FIL2. The semiconductor wafer PA-CP is provided with power amplifier circuits PA_LB, PA-HB, and a control circuit CTL. The PA-LB is amplified from a low-band signal such as GSM850 or GSM900 input from the external input terminal Pin_LB by a modulation circuit or the like (not shown). This is a magnified -34- 200835042

之訊號，係依序經由輸出整合電路MN _ L B、耦合電路 CPL— LB以及低通濾波電路LPF— LB，而被傳送至天線開 關電路ANT_ SW之端子P1。MN— LB，例如係爲在特定 阻抗50Ω等中進行阻抗整合的電路，CPL_ LB，係爲檢測 出經由MN一 LB後之PA— LB的輸出電力値，並將該檢測 訊號DS—LB輸出至PA— CP內之控制電路CTL的電路。 低通濾波電路LPF— LB，係從經由CPL— LB後之PA— LB 的輸出訊號，來使高頻訊號（例如，2次高頻波（2HD ) 以及3次高頻波（3HD )等）減衰的電路。LPF— LB，係 亦可爲使特定之帶域通過的帶域濾波器（BPF )或是使特 定之帶域減衰的帶域除去濾波器（BEF)。 另一方面，P A 一 Η B，係經由未圖示之調變電路等， 而將從外部輸入端子Pin— ΗΒ所輸入之GSM1 800或 GSM 1 900之類的高帶域的訊號放大。此被放大之訊號，係 依序經由輸出整合電路MN—HB、耦合電路CPL_HB以 及低通濾波電路（又或是BPF或者是BEF ) LPF_ HB，而 被傳送至ANT一 SW之端子P2。MN一 HB，例如係爲在特 定阻抗50 Ω等中進行阻抗整合的電路，CPL— HB，係爲檢 測出經由MN一 HB後之PA一 HB的輸出電力値，並將該檢 測訊號DS_ HB輸出至PA— CP內之CTL的電路。LPF — HB，係從經由CPL—HB後之PA—HB的輸出訊號，來使 高頻訊號（例如’ 2次高頻波（2HD )以及3次高頻波（ 3HD)等）減衰的電路。 半導體晶片PC—CP內之控制電路CTL，係對於外部 -35- 200835042 控制輸入端子CS1，而接收從未圖示之基頻帶電路而來之 控制訊號、或是前述之檢測訊號DS_ LB、DS_ HB，並對 PA— LB、PA— HB或ANT— SW作控制。在從基頻帶電路The signals are transmitted to the terminal P1 of the antenna switch circuit ANT_SW via the output integration circuit MN_L B, the coupling circuit CPL_LB, and the low-pass filter circuit LPF-LB. MN-LB is, for example, a circuit for impedance integration in a specific impedance of 50 Ω or the like, and CPL_LB is for detecting the output power PA of the PA-LB via the MN-LB, and outputs the detection signal DS-LB to PA - The circuit of the control circuit CTL in the CP. The low-pass filter circuit LPF-LB is a circuit for reducing the high-frequency signal (for example, 2 high-frequency waves (2HD) and 3 high-frequency waves (3HD), etc.) from the output signal of the PA-LB via the CPL-LB. The LPF-LB can also be a band filter (BPF) that passes a specific band or a band removal filter (BEF) that degrades a specific band. On the other hand, P A Η B is amplified by a high-band signal such as GSM1 800 or GSM 1 900 input from the external input terminal Pin_ΗΒ via a modulation circuit or the like (not shown). The amplified signal is transmitted to the terminal P2 of the ANT-SW via the output integration circuit MN-HB, the coupling circuit CPL_HB, and the low-pass filter circuit (or BPF or BEF) LPF_Hb. The MN-HB is, for example, a circuit for impedance integration in a specific impedance of 50 Ω or the like, and the CPL-HB is for detecting the output power PA of the PA-HB after the MN-HB, and outputs the detection signal DS_ HB. Circuit to the CTL in the PA-CP. LPF — HB is a circuit that demodulates high-frequency signals (such as '2 high-frequency waves (2HD) and 3 high-frequency waves (3HD)) from the output signal of PA-HB after CPL-HB. The control circuit CTL in the semiconductor chip PC-CP is for receiving the control signal from the baseband circuit (not shown) or the aforementioned detection signals DS_LB, DS_B for the external-35-200835042 control input terminal CS1. And control PA-LB, PA-HB or ANT-SW. From the baseband circuit

而來之控制訊號中，例如係包含有：根據行動電話與基地 台間之距離而被產生之對於PA_ LB、PA_ HB的輸出電 力準位之指定訊號，或是因應於送收訊之處理內容所產生 的對於ANT_ SW之開關的切換訊號等。CTL，係根據此 輸出電力準位之指定訊號或檢測訊號DS_ LB、DS_ HB， 而控制PA_ LB、PA— HB之增益，並根據此開關之切換 訊號，而控制ANT_ SW。 ANT_ SW，係因應於前述之從CTL而來的控制訊號 ，並對於天線端子P0而連接端子P 1〜P4之任一者的電路 。天線端子P0，係經由天線濾波電路ANT— FIL以及ESD 濾波電路ESD_FIL，而連接於外部天線端子ANT，並於 此 ANT連接未圖示之天線。ANT_ FIL，主要係進行從 ANT— SW所產生之高頻波的減衰，或是被包含於從天線 而來之受訊訊號中的高頻波之減衰等。ESD_ FIL，主要係 進行對於從天線而來之受訊訊號而除去在ESD ( Electro Static Discharge)上會成爲問題的帶域（例如400MHz帶 或500MHz帶等）之除去。 又，ANT_ SW之端子P3，係經由受訊濾波電路RX — FIL1而被連接於外部輸出端子RX—LB，ANT— SW之端 子P4，係經由受訊濾波電路RX一 FIL2而被連接於外部輸 出端子RX_ HB。在RX_ LB中，係被傳送有從天線所受 -36- 200835042 訊之低帶域的訊號’在RX—HB中，係被傳送有從天線所 受訊之高帶域的訊號’此些之訊號，係被輸出至未圖示之 解調電路等。RX—FIL1 ’係對於從天線所受訊之低帶域的 訊號而進行高頻波之減衰，RX__ FIL2，係對於從天線所受 訊之高帶域的訊號而進行高頻波之減衰。The control signal, for example, includes: a designated signal for the output power level of PA_LB, PA_ HB generated according to the distance between the mobile phone and the base station, or the processing content corresponding to the receiving and receiving message. The generated switching signal for the switch of ANT_SW, and the like. The CTL controls the gain of PA_LB, PA-HB according to the specified signal of the output power level or the detection signals DS_LB, DS_Hb, and controls the ANT_SW according to the switching signal of the switch. ANT_SW is a circuit for connecting any of the terminals P1 to P4 to the antenna terminal P0 in response to the aforementioned control signal from the CTL. The antenna terminal P0 is connected to the external antenna terminal ANT via the antenna filter circuit ANT_FIL and the ESD filter circuit ESD_FIL, and an antenna (not shown) is connected to the ANT. ANT_FIL mainly performs the attenuation of high-frequency waves generated from ANT-SW, or the attenuation of high-frequency waves contained in the received signals from the antenna. ESD_FIL is mainly used to remove the received signal from the antenna to remove the band (e.g., 400 MHz band or 500 MHz band) which is a problem in ESD (Electrostatic Discharge). Further, the terminal P3 of the ANT_SW is connected to the external output terminal RX-LB via the signal filtering circuit RX_FIL1, and the terminal P4 of the ANT_SW is connected to the external output via the signal filtering circuit RX-FIL2. Terminal RX_ HB. In the RX_LB, the low-band signal transmitted from the antenna to the -36-200835042 is transmitted. In the RX-HB, the high-band signal transmitted from the antenna is transmitted. The signal is output to a demodulation circuit or the like not shown. RX-FIL1' is a high-frequency wave fading for the low-band signal from the antenna, and RX__FIL2 is the fading of the high-frequency wave for the high-band signal received from the antenna.

此種對應於複數之帶域的高頻模組，由於係成爲較對 應於1個的帶域之高頻模組而更爲大型，因此，除了半導 體晶片的尺寸之外，亦被要求能將各種濾波電路等以更小 之面積又或是更低之成本來形成。於此，爲了追求多層配 線基板之小型化（薄膜化）或低成本化，例如，係以使用 被廣泛使用之具備有4層或5層左右的層積構造之陶瓷基 板等爲理想。此時，在此4層或5層之內，能夠將圖1之Such a high-frequency module corresponding to a plurality of bands is larger because it is a higher-frequency module corresponding to one band. Therefore, in addition to the size of the semiconductor wafer, various filter circuits and the like are required. Formed with a smaller area or a lower cost. Here, in order to reduce the size (thinning) or cost reduction of the multilayer wiring board, for example, a ceramic substrate having a laminated structure of four or five layers which is widely used is preferably used. At this time, within this 4 or 5 layers, Figure 1 can be

各種濾波電路（LPF— LB、LPF HB、ANT FIL、ESD FIL、RX_ FIL1、RX— FIL2 )或輸出整合電路（MN— LB 、MN__ HB )以何種程度之小型化而形成一事，係爲重要 φ 。在圖1之各種濾波電路或輸出整合電路內，係多包含有 由電感與電容器所成之並聯共振電路，若是能夠將此種並 聯共振電路不使用SMD構件而形成爲小型，則對高頻模 組之小型化又或是低成本化係成爲有益。 此種並聯共振電路，例如，係藉由圖2所示一般之構 成，而成爲可實現。圖2，係爲在本發明之實施形態1的 共振電路中，展示其構成例者，（a)係爲立體圖，（b) 係爲展示（a)之各層的平面圖。於圖2(a) 、（b)所示 之共振電路，例如，係使用包含有第〗配線層1^¥1和於其 -37- 200835042 下層而依序被層積之第2配線層LY2〜第4配線層LY4的 4層之多層配線基板而被實現。另外’ LY4之背面，係成 爲接地電極。It is important that the various filter circuits (LPF-LB, LPF HB, ANT FIL, ESD FIL, RX_FIL1, RX-FIL2) or the output integration circuits (MN-LB, MN__ HB) are formed by miniaturization. φ. In the various filter circuits or output integration circuits of FIG. 1, a parallel resonant circuit composed of an inductor and a capacitor is included, and if the parallel resonant circuit can be formed into a small size without using an SMD member, the high frequency module is Miniaturization or low cost is beneficial. Such a parallel resonant circuit can be realized, for example, by the general configuration shown in Fig. 2. Fig. 2 is a perspective view showing a configuration of a resonance circuit according to a first embodiment of the present invention, wherein (a) is a perspective view, and (b) is a plan view showing each layer of (a). In the resonance circuit shown in FIGS. 2(a) and 2(b), for example, the second wiring layer LY2 including the first wiring layer 1^¥1 and the lower layer of -37-200835042 is sequentially used. It is realized by a multilayer wiring board of four layers of the fourth wiring layer LY4. In addition, the back of LY4 is a grounding electrode.

在LY1〜LY4中，係分別被形成有由將線路以略迴路 狀而圍繞約一圈之形狀所成的配線圖案MS21〜MS24。 MS21之其中一端係成爲訊號輸入節點Nin，另外一端係 經由被形成在自身之迴路的中心部之通孔導體VH13a，而 被連接於MS23&MS23，係其中一端經由被形成在自身之 迴路的中心部之通孔導體VH13a而被連接於前述之MS21 ，而另外一端經由被形成在自身之迴路的角隅部之通孔導 體VH34a而被連接於MS24。 MS24，係其中一端經由被形成在自身之迴路的角隅 部之通孔導體VH34a而被連接於前述之MS23，而另外一 端經由被形成在自身之迴路的側邊之通孔導體VH24a而被 連接於MS22。MS22，係其中一端經由被形成在自身之迴 路的側邊之通孔導體VH24a而被連接於前述之MS24，而 另外一端係成爲訊號輸出節點Nout。故而，當從Nin朝向 Nout而傳送了訊號的情況時，在各配線圖案MS21〜MS24 中，係以逆時針之迴路而傳送訊號，而MS21〜MS24係成 爲作爲電感而起作用。另外，亦可將Nin與Nout設爲相 反。又，在M S 2 3以及M S 2 4之各線路中，於一部份設置 有蛇行之形狀的原因，係爲了將線路長增長，而將電感値 增大之故。 於此’作爲圖2之構成全體，係等價地作爲由電感（ -38- 200835042In LY1 to LY4, wiring patterns MS21 to MS24 formed by a shape in which a line is wound in a substantially loop shape by about one turn are formed, respectively. One end of the MS 21 is a signal input node Nin, and the other end is connected to the MS23 & MS 23 via a via-hole conductor VH13a formed at the center of its own circuit, one end of which is formed at the center of the loop formed by itself. The via-hole conductor VH13a is connected to the MS21 described above, and the other end is connected to the MS 24 via the via-hole conductor VH34a formed in the corner portion of the loop of the circuit. The MS 24 is connected to the MS 23 described above via a via-hole conductor VH34a formed in a corner portion of its own loop, and the other end is connected via a via-hole conductor VH24a formed on the side of its own loop. On MS22. The MS 22 is connected to the aforementioned MS 24 via a via-hole conductor VH24a formed on the side of its own path, and the other end is a signal output node Nout. Therefore, when a signal is transmitted from Nin to Nout, signals are transmitted in the counterclockwise loops in the respective wiring patterns MS21 to MS24, and the MSs 21 to MS24 function as inductances. Alternatively, you can set Nin to be the opposite of Nout. Further, in the respective lines of M S 2 3 and M S 2 4, the reason why the shape of the meandering is provided in one part is to increase the inductance 値 in order to increase the length of the line. Here, as a whole of the configuration of Fig. 2, it is equivalently used as an inductance (-38-200835042)

線圈）Lml與電容器（capacitor、電容）Cml所成之並聯 共振電路LC1而起作用。而，此並聯共振電路LC1之主 要的特徵，例如係爲以下所述一般。首先，第1點，係爲 經由配線之引繞，而使訊號輸入節點N i η與訊號輸出節點 N out間的電容成分增加一事。圖3(a)，係爲圖2之並 聯共振電路LC1的簡易之等價電路圖，圖3 ( b )，係作 爲其之比較例，而爲在專利文獻1之圖8中所示的螺旋電 感Lcl之簡易的等價電路圖。 在圖3 ( a )所示之並聯共振電路LC 1中，第1配線 層LY1之訊號輸入節點Niii，係依序經由LY1之電感L1 、第3配線層LY3之電感L3、第4配線層LY4之電感L4 、以及第2配線層LY2之電感L2，而被連接於訊號輸出 節點Nout。L1〜L4，係爲分別對應於圖2之配線圖案 MS21〜MS24者。又，在Niri與Nout之間，係被連接有 成爲LY1與LY2間之層間電容的電容器C1，而在LY2與 LY3之間、LY3與LY4之間、LY4與背面之間，亦分別被 連接有成爲層間電容之電容器C2、C3、C4。 另一方面，在圖3 ( b )所示之螺旋電感Lc 1中，LY 1 之Nin，係依序經由LY1之電感LI 1、LY2之電感L12、 LY3之電感L13、以及LY4之電感L14，而被連接於Nout 。又，在LY1與LY2之間、LY3與LY4之間、LY4與背 面之間，亦分別被連接有成爲層間電容之電容器C 1 1、 C12、C13、C14。另外，在圖 3(a) 、（b)中，更嚴密 而言，例如係在圖3 ( a)之L3與L4的接點N1等，被插 -39- 200835042 入有伴隨著通孔導體之電感或電阻，又或是與此並聯地而 被插入有伴隨著LY3與LY4的層間電容之電容器，但是 ，於此，係簡易地以通孔導體而代表配線，並因應於此而 亦將電容器省略。此事，對於在圖3 ( a ) 、（ b )中之其 他的通孔導體的存在場所而言，亦爲相同。The coil) Lml acts in parallel with the capacitor (capacitor, capacitor) Cml and the resonant circuit LC1. The main features of the parallel resonant circuit LC1 are, for example, generally described below. First, the first point is to increase the capacitance component between the signal input node N i η and the signal output node N out by wiring. Fig. 3(a) is a simplified equivalent circuit diagram of the parallel resonant circuit LC1 of Fig. 2, and Fig. 3(b) is a comparative example thereof, and is a spiral inductor shown in Fig. 8 of Patent Document 1. A simple equivalent circuit diagram of Lcl. In the parallel resonant circuit LC1 shown in FIG. 3(a), the signal input node Niii of the first interconnect layer LY1 is sequentially passed through the inductor L1 of the LY1, the inductor L3 of the third interconnect layer LY3, and the fourth wiring layer LY4. The inductance L4 and the inductance L2 of the second wiring layer LY2 are connected to the signal output node Nout. L1 to L4 are those corresponding to the wiring patterns MS21 to MS24 of Fig. 2, respectively. Further, between Niri and Nout, a capacitor C1 which is an interlayer capacitance between LY1 and LY2 is connected, and between LY2 and LY3, between LY3 and LY4, and between LY4 and the back surface are also connected, respectively. Capacitors C2, C3, and C4 that become interlayer capacitances. On the other hand, in the spiral inductor Lc 1 shown in FIG. 3(b), Nin of LY1 is sequentially passed through the inductance LI1 of LY1, the inductance L12 of LY2, the inductance L13 of LY3, and the inductance L14 of LY4. And is connected to Nout. Further, capacitors C 1 1 , C12, C13, and C14 which are interlayer capacitances are also connected between LY1 and LY2, between LY3 and LY4, and between LY4 and the back surface. In addition, in FIGS. 3(a) and 3(b), more closely, for example, the contact N1 of L3 and L4 of FIG. 3(a), etc., is inserted into the -39-200835042 with the via conductor. The inductor or the resistor is inserted in parallel with the capacitor of the interlayer capacitance of LY3 and LY4. However, the wiring is simply represented by the via-hole conductor, and accordingly, The capacitor is omitted. This matter is also the same for the existence of other via-hole conductors in Figs. 3(a) and (b).

由此等價電路可以得知，在圖3 ( a )中，其構成，係 藉由將Nin與Nout形成在相互鄰接之.層中，而有效率地 進行此些間之電容結合（亦即是對應於電容器C1)，並 進而藉由將配線作引繞，而成爲使LY1〜LY4之所有的電 感成分作爲Nin與Nout間之電感成分而有所幫助。另一 方面，在圖3 (b)中，關於電感成分之有所幫助處，雖係 和圖3 ( a)爲相同，但是，由於Nin與Nout間之電容結 合，係經由複數之串聯連接的電容器（例如C 1 1與C 1 3 ) 而被進行，因此，Nin與Nout間之電容結合係變弱。故而 ，藉由使用如圖3 ( a ) —般之配線的引繞，相較於圖3 ( b )成爲能夠使Nin與Nout間之電容値增加，而成爲能夠 實現小型的又或是低成本的共振電路。 第2點，係在於：雖然MS21與MS22之線路寬幅係 幾乎爲相同，且MS23與MS24之線路寬幅係幾乎爲相同 ，但是MS21與MS22之最大線寬幅，係被形成爲較MS23 與MS24之最大線路寬幅爲更粗。藉由此’在能夠橫跨 MS21〜MS24而形成電感成分的同時，亦成爲能夠藉由以 相互挾持層而對向的方式所形成之MS21以及MS22’而 使Nin與Nout間之電容値更爲增大。 -40- 200835042It can be seen from the equivalent circuit that, in FIG. 3(a), the combination of Nin and Nout is formed in a layer adjacent to each other, and the capacitive coupling between the two is efficiently performed (ie, Corresponding to the capacitor C1), and by winding the wiring, all the inductance components of LY1 to LY4 are used as the inductance component between Nin and Nout. On the other hand, in Fig. 3 (b), the help of the inductance component is the same as that of Fig. 3 (a), but since the capacitance between Nin and Nout is combined, it is connected in series through a plurality of series. Capacitors (e.g., C 1 1 and C 1 3 ) are performed, and therefore, the capacitance bond between Nin and Nout becomes weak. Therefore, by using the wiring of the wiring as shown in FIG. 3(a), it is possible to increase the capacitance N between Nin and Nout as compared with FIG. 3(b), and it is possible to realize a small or low cost. Resonant circuit. The second point is that although the line widths of MS21 and MS22 are almost the same, and the line widths of MS23 and MS24 are almost the same, the maximum line width of MS21 and MS22 is formed to be compared with MS23. The MS24's maximum line width is thicker. Thus, the inductance component can be formed across MS21 to MS24, and the capacitance between Nin and Nout can be made even more so that MS21 and MS22' can be formed by opposing layers while holding each other. Increase. -40- 200835042

第3點，係在於：藉由將MS21與MS22設置在從 LY4之背面的接地電極而遠離之層（LY1、LY2 )處’相 較於形成在LY3或LY4等的情況，能夠實現大的電感値 。一般而言，由於被設置在接地面上之配線圖案的電感’ 係會由於藉由接地面所產生的影像電流之影響而變小，因 此，若是配線圖案能越遠離接地面，則能夠使電感變得越 大。故而，由於藉由此種構成，能夠使每單位面積之電感 値變爲最大化，因此，能夠將用以得到所期望之電感値的 必要之面積變爲最小，而能夠將共振電路小型化。另外， 由於依存於MS21〜MS24各部之電感値的平衡，亦有在將 MS23與MS24設置在從LY4之背面的接地電極遠離之層 (LY1、LY2)，而將MS23與MS24所致之電感値最大化 的情況時，能夠更有效果地將共振電路之共振頻率降低、 或是不使共振頻率降低而能夠使面積小型化的情形，因此 ，在該情形，亦可將MS21〜MS 24所被設置之層的順序設 爲與圖2相反。 而，第4點，係在於：圖2之各配線圖案MS21〜 MS24，係以使從表面視之時的投影面積變小的方式而被 形成。換言之，在將MS21〜MS24之各別的配線圖案之佔 有區域從表面側而作投影的情況時，任一者的配線圖案所 對應之佔有區域，係成爲包含有其他之配線圖案的佔有區 域之關係。圖4，係爲展示將圖2之主要部透視性地觀察 的情況時之構成例的立體圖。 如圖4所示一般，MMS21〜MS24之實質佔有區域， -41 - 200835042The third point is that a large inductance can be realized by providing MS21 and MS22 at a layer (LY1, LY2) away from the ground electrode on the back surface of LY4 as compared with the case of forming LY3 or LY4 or the like. value. In general, since the inductance of the wiring pattern provided on the ground plane is reduced by the influence of the image current generated by the ground plane, if the wiring pattern can be moved away from the ground plane, the inductance can be made. It gets bigger. Therefore, with such a configuration, the inductance 每 per unit area can be maximized. Therefore, the necessary area for obtaining the desired inductance 变为 can be minimized, and the resonance circuit can be miniaturized. In addition, depending on the balance of the inductances of the MS21 to the MS24, there are also layers (LY1, LY2) in which the MS23 and the MS24 are disposed away from the ground electrode on the back side of the LY4, and the inductance caused by the MS23 and the MS24. In the case of maximization, the resonance frequency of the resonance circuit can be more effectively reduced, or the area can be miniaturized without lowering the resonance frequency. Therefore, in this case, the MS 21 to the MS 24 can be The order of the layers set is set to be opposite to that of FIG. 2. On the other hand, the fourth point is that the wiring patterns MS21 to MS24 of Fig. 2 are formed such that the projected area when viewed from the surface is reduced. In other words, when the occupied area of each of the wiring patterns of the MSs 21 to MS 24 is projected from the front side, the occupied area corresponding to any of the wiring patterns is an occupied area including another wiring pattern. relationship. Fig. 4 is a perspective view showing a configuration example in a case where the main portion of Fig. 2 is seen in a perspective view. As shown in Figure 4, the Ms21 to MS24 essentially occupy the area, -41 - 200835042

係分別成爲AA21〜AA24。而’當將此AA21〜AA24從表 面側投影而視之的情況時，例如係成爲在AA2 1內包含有 AA22〜AA24的關係。另外，於此，AA21〜AA24之佔有 區域係成爲相等的關係而成爲在AA2 1之全部中，包含有 AA22〜AA24之全部。佔有區域之大小（亦即是投影面積 )(A2 1XA22)，雖並非爲被特別限定者，但是，例如係 爲1 mmx 1 mm左右。藉由此，例如，相較於如同專利文獻 3 (在圖7 ( b )處後述）中所示一般，將各配線圖案相錯 開而形成的情況，係能夠以小面積來實現並聯共振電路。 另外，於此，雖係展示如同前述一般之爲了減低多層 基板的成本而使用4層基板的構成例，但是，關於基板之 層數或是通孔導體所致之引繞方法，在不脫離該要旨的範 圍內，可作各種之變更。例如，亦可對圖2作變更，而以 第1配線層、第4配線層、第3配線層、第2配線層的順 序來將配線作引繞。又，例如，當使用3層基板的情況時 ，只要在第1配線層以及第2配線層中將MS 1等之類的 線路以粗的配線圖案來形成，並將此第3配線層之配線圖 案的其中一端連接於第i配線層，將另外一端連接於第2 配線層即可。 又，當使用5層基板的情況時，例如，只要在第1配 線層以及第2配線層中將MS 1等之類的線路以粗的配線 圖案來形成，並將在第3配線層〜第5配線層中而描繪螺 旋之MS3等的線路寬幅以細的配線圖案來形成，再將第3 配線層之線路圖案的其中一端連接於第1配線層，將第5 -42- 200835042 配線層之線路圖案的其中一端連接於第2配線層即可。進 而，若是在多層配線基板之成本上沒有問題，則對於6層 以上之多層配線基板，亦可同樣的適用。 以上，藉由本實施形態1，而成爲能夠實現共振電路 以及包含有其之高頻模組的小型化又或是低成本化。 (實施形態2 )The lines become AA21 to AA24, respectively. On the other hand, when the AA21 to AA24 are projected from the front side, for example, the relationship between AA22 and AA24 is included in AA2 1. Further, here, the occupied areas of AA21 to AA24 are in an equal relationship, and all of AA22 to AA24 are included in all of AA2. The size of the occupied area (that is, the projected area) (A2 1XA22) is not particularly limited, but is, for example, about 1 mm x 1 mm. By this, for example, in the case where the wiring patterns are formed to be shifted as shown in Patent Document 3 (described later in FIG. 7(b)), the parallel resonant circuit can be realized with a small area. In addition, although a configuration example in which a four-layer substrate is used in order to reduce the cost of the multilayer substrate as described above is used, the method of guiding the number of layers of the substrate or the via-hole conductor does not deviate from the configuration. Various changes can be made within the scope of the gist. For example, the wiring may be routed in the order of the first wiring layer, the fourth wiring layer, the third wiring layer, and the second wiring layer, as shown in Fig. 2 . In the case where a three-layer substrate is used, for example, a wiring such as MS 1 or the like is formed in a thick wiring pattern in the first wiring layer and the second wiring layer, and the wiring of the third wiring layer is formed. One end of the pattern is connected to the ith wiring layer, and the other end is connected to the second wiring layer. When a five-layer substrate is used, for example, a line such as MS 1 or the like is formed in a thick wiring pattern in the first wiring layer and the second wiring layer, and the third wiring layer is replaced by a third wiring layer. In the wiring layer, the line width of the MS3 such as the spiral is formed by a thin wiring pattern, and one end of the line pattern of the third wiring layer is connected to the first wiring layer, and the wiring layer of the fifth to 42-200835042 is connected. One end of the line pattern may be connected to the second wiring layer. Further, if there is no problem in the cost of the multilayer wiring board, the multilayer wiring board of six or more layers can be similarly applied. As described above, according to the first embodiment, it is possible to reduce the size and cost of the resonant circuit and the high-frequency module including the same. (Embodiment 2)

在本實施形態2中，針對與在圖1中之各種濾波電路 或輸出整合電路中所被使用之圖2相異的共振電路之構成 例作說明。圖5，係爲在本發明之實施形態2的共振電路 中，展示其構成例者，（a )係爲立體圖，（b )係爲展示 (a)之各層的平面圖。於圖5(a) 、（b)所示之共振電 路，與圖2同樣的，例如，係使用包含有第1配線層LY1 〜第4配線層LY4的4層之多層配線基板而被實現，而 LY4之背面，係成爲接地電極。 在LY1、LY2中，係分別被形成有由將線路以略迴路 狀而圍繞約一圈之形狀所成的配線圖案MS3 1、MS32。在 LY3、LY4中，係分別被形成有由平板狀之形狀所成的配 線圖案（電極圖案）MS33、MS34。MS31之其中一端係成 爲訊號輸入節點Niii，此訊號輸入節點Nin，係更進而經 由被形成在自身之迴路的中心部之通孔導體VH13b，而被 連接於MS33。另一方面，MS31之另外一端，係經由被形 成在自身之迴路的角隅部之通孔導體VH 12b，而被連接於 MS 3 2 〇 -43- 200835042In the second embodiment, a configuration of a resonance circuit different from that of Fig. 2 used in the various filter circuits or output integration circuits of Fig. 1 will be described. Fig. 5 is a perspective view showing a configuration of a resonance circuit according to a second embodiment of the present invention, wherein (a) is a perspective view, and (b) is a plan view showing each layer of (a). The resonance circuit shown in FIGS. 5(a) and 5(b) is realized by using, for example, a multilayer wiring board having four layers including the first to fourth wiring layers LY1 to LY4, as in the case of FIG. The back of LY4 is the grounding electrode. In LY1 and LY2, wiring patterns MS3 1 and MS32 formed by a shape in which the line is wound in a substantially loop shape by about one turn are formed, respectively. In LY3 and LY4, wiring patterns (electrode patterns) MS33 and MS34 each formed of a flat plate shape are formed. One end of the MS 31 is a signal input node Niii, and the signal input node Nin is further connected to the MS 33 via a via-hole conductor VH13b formed at the center of its own circuit. On the other hand, the other end of the MS 31 is connected to the MS 3 2 〇 -43- 200835042 via the via-hole conductor VH 12b formed in the corner portion of the loop of its own circuit.

MS32，係其中一端經由被形成在自身之迴路的角隅 部之通孔導體VH 12b而被連接於前述之MS3 1，而另外一 端，係在成爲訊號輸出節點Nout的同時，經由被形成在 自身之迴路的另外之角隅部的通孔導體VH24b而被連接 於MS 34。又’ MS3 3與MS 34，係以相互挾持層並對向的 方式而被形成。故而，當從Nin朝向Nout而傳送了訊號 的情況時，在MS31與MS32中，係成爲以逆時針之迴路 而傳送訊號，而MS3 1與MS32係成爲作爲電感而起作用 。又，除此之外，在Nin與Nout處，由於係經由 MS33 與MS 3 4而被形成有電容，因此，圖5之構成例，其全體 係作爲等價的由電感Lm2以及電容Cm2所成之並聯共振 電路LC2而起作用。另外，亦可將Nin與Nout設爲相反 圖6，係爲圖5之並聯共振電路LC2之簡易的等價電 路圖。在圖6中，LY1之Nin，係依序經由LY1之電感L5 φ 、L之電感L6，而連接於Nout。L5、L6，係爲分別對應 於圖5之配線圖案MS31、MS32者。又，在Nin與Nout 之間，係被連接有對應於圖5的LY3之MS33與LY4之 MS34的電容器C7，在LY1與LY2之間、LY2與LY3之 間、LY4與背面之間，亦分別被連接有成爲層間電容之電 容器C5、C6、C8。另外，與前述之圖3的等價電路同樣 的，關連於通孔導體之表示係被省略。 在此種構成中，本實施形態2之共振電路之主要的特 徵，例如係爲以下所述一般。首先，第1點，係在於：除 -44 - 200835042 了與實施形態1同樣的，將Nin與Nout形成在相互鄰接 之層中，並藉由此而使電容値（對應於圖6之C5)增大 之外，更經由MS33與MS34，而進一步使電容値（於圖6 中係對應於與C5並聯連接之C7)增大一事。又，第2點 和第3點，係如同在實施形態1中所說明一般，可列舉有 :將電感（MS31以及MS32)設置在從接地層而遠離之層 處一事，或是以使投影面積變小的方式來構成一事。The MS 32 is connected to the MS 3 1 via the via-hole conductor VH 12b formed in the corner portion of the loop of its own circuit, and the other end is formed at itself while being the signal output node Nout. The via hole conductor VH24b of the other corner of the loop is connected to the MS 34. Further, MS 3 3 and MS 34 are formed in such a manner as to hold each other and to face each other. Therefore, when a signal is transmitted from Nin toward Nout, in MS31 and MS32, signals are transmitted in a counterclockwise loop, and MS3 1 and MS32 function as inductances. In addition, in addition, in Nin and Nout, since capacitance is formed via MS33 and MS 3 4, the entire system of Fig. 5 is equivalently formed by inductance Lm2 and capacitance Cm2. The parallel resonant circuit LC2 functions. Alternatively, Nin and Nout may be reversed. Fig. 6 is a simplified equivalent circuit diagram of the parallel resonant circuit LC2 of Fig. 5. In FIG. 6, Nin of LY1 is connected to Nout via the inductance L5 φ of L1 and the inductance L6 of L. L5 and L6 are those corresponding to the wiring patterns MS31 and MS32 of Fig. 5, respectively. Further, between Nin and Nout, a capacitor C7 corresponding to MS33 of LY3 of FIG. 5 and MS34 of LY4 is connected, between LY1 and LY2, between LY2 and LY3, and between LY4 and the back, respectively. Capacitors C5, C6, and C8 which become interlayer capacitances are connected. Further, the same as the equivalent circuit of Fig. 3 described above, the description relating to the via conductor is omitted. In such a configuration, the main features of the resonant circuit of the second embodiment are as follows, for example. First, the first point is that, in addition to -44 - 200835042, in the same manner as in the first embodiment, Nin and Nout are formed in layers adjacent to each other, and thereby the capacitance 値 (corresponding to C5 of FIG. 6) In addition to the increase, the MS 与 and the MS 34 are further increased by the capacitance 値 (corresponding to C7 connected in parallel with C5 in FIG. 6). Further, the second point and the third point are as described in the first embodiment, and the inductance (MS31 and MS32) is set at a layer away from the ground layer, or the projected area is used. Smaller ways to make up.

關於此第3點之投影面積，使用圖7來作說明。圖7 (a )，係爲展示將圖5之主要部透視性地觀察的情況時 之構成例的立體圖，圖7(b)，係爲展示成爲其之比較例 的構成之立體圖。成爲圖7(b)中所示之比較例的共振電 路LCc2，係成爲反映前述之專利文獻3的構成例者。如 圖7(a)所示一般，在圖5中之MS31〜MS34之實質佔 有區域，係分別成爲AA3 1〜AA34。而，當將此AA31〜 AA34從表面側投影而視之的情況時，例如係成爲在ΑΑ3ι 內包含有AA32〜AA34的關係。佔有區域之大小（亦即是 投影面積）（A31XA32 )，雖並非爲被特別限定者，但是 ，例如係爲1 Hi m X 1 m m左右。 另一方面，在比較例中，如圖7(b)所示一般，電感 圖案之實質的佔有區域係成爲AA41、AA42，電容圖案之 實質的佔有區域係成爲 AA43、AA44。故而，當將此 AA4 1〜AA44從表面側投影而視之的情況時，例如係成爲 在AA41內並不包含有AA43的關係。在此情況，雖然投 影面積會增大，但是，藉由使用圖7(a)(圖5) —般之 -45- 200835042 構成，成爲能夠實現並聯共振電路之小型化。The projected area of this third point will be described using FIG. 7. Fig. 7 (a) is a perspective view showing a configuration example in which the main portion of Fig. 5 is seen in a perspective view, and Fig. 7 (b) is a perspective view showing a configuration of a comparative example thereof. The resonance circuit LCc2 of the comparative example shown in Fig. 7(b) is a configuration example of the above-mentioned Patent Document 3. As shown in Fig. 7(a), in general, the substantial occupied areas of MS31 to MS34 in Fig. 5 are AA3 1 to AA34, respectively. On the other hand, when the AA31 to AA34 are projected from the front side, for example, the relationship of AA32 to AA34 is included in ΑΑ3ι. The size of the occupied area (that is, the projected area) (A31XA32) is not particularly limited, but is, for example, about 1 Hi m X 1 m m. On the other hand, in the comparative example, as shown in Fig. 7(b), the substantial occupied area of the inductance pattern is AA41 and AA42, and the substantial occupied area of the capacitance pattern is AA43 and AA44. Therefore, when the AA4 1 to AA44 are projected from the front side, for example, the relationship of AA43 is not included in AA41. In this case, although the projection area is increased, the parallel resonance circuit can be miniaturized by using the configuration of Fig. 7 (a) (Fig. 5) -45-200835042.

然而，作爲圖2之構成例與圖5之構成例的比較，若 是將此兩者分別以相同之面積與相同之層數來形成，則圖 5之構成例，相較於圖2之構成例，由於係成爲藉由 MS3 1與MS32之2層份來實現電感成分，因此電感値係 變小。又，電容値，亦由於係使MS33與MS34在以AA33 與A A3 4所致之狹小投影面積內被形成，故係變小。故而 ，圖5之構成例所致之共振頻率，相較於圖2之構成例所 致之共振頻率，由於係變大，因此，圖之構成例，例如係 可使用在圖1之對應於高帶域的濾波電路等中。 另外，於圖5之構成例中，亦與圖2之構成例同樣的 ，關於基板之層數或是通孔導體所致之引繞方法，在不脫 離該要旨的範圍內，可作各種之變更。例如，當使用5層 基板的情況時，例如，係以第1配線層-第3配線層—第 2配線層的方式來描繪螺旋而形成MS3 1等之類的配線圖 案，並在第4配線層與第5配線層中形成MS33等之平板 狀的配線圖案。而後，只要將第1配線層之線路圖案的其 中一端連接於第4配線層，並將第2配線層之線路圖案的 其中一端連接於第5配線層即可。在圖5之構成例的情況 中，不論基板之層數係爲何種狀況，藉由將形成電感之配 線圖案相較於形成電容之平板狀的配線圖案而設置於從接 地電極更爲遠離之層中，能夠將每單位面積之電感値最大 化，並能夠將用以得到所期望之電感値所必要的面積最小 化，而能夠將共振電路小型化。 -46- 200835042 以上，藉由本實施形態2’而成爲能夠實現共振電路 以及包含有其之局頻模組的小型化又或是低成本化。 (實施形態3 )However, as a comparison between the configuration example of FIG. 2 and the configuration example of FIG. 5, if the two are formed by the same area and the same number of layers, the configuration example of FIG. 5 is compared with the configuration example of FIG. Since the inductance component is realized by two layers of MS3 1 and MS 32, the inductance 値 is small. Further, the capacitance 値 is also reduced because the MS 33 and the MS 34 are formed in a narrow projected area caused by AA33 and A A3 4 . Therefore, the resonance frequency due to the configuration example of FIG. 5 is larger than the resonance frequency due to the configuration example of FIG. 2, and therefore, the configuration example of the figure can be used, for example, in FIG. A filter circuit with a domain, etc. In addition, in the configuration example of FIG. 5, similarly to the configuration example of FIG. 2, the number of layers of the substrate or the winding method by the via-hole conductor can be variously selected without departing from the gist of the gist. change. For example, when a five-layer substrate is used, for example, a spiral pattern is formed so that the first wiring layer, the third wiring layer, and the second wiring layer are formed, and a wiring pattern such as MS3 1 or the like is formed, and the fourth wiring is formed. A flat wiring pattern of MS 33 or the like is formed in the layer and the fifth wiring layer. Then, one end of the line pattern of the first wiring layer is connected to the fourth wiring layer, and one end of the line pattern of the second wiring layer is connected to the fifth wiring layer. In the case of the configuration example of FIG. 5, the wiring pattern forming the inductance is provided on the layer farther from the ground electrode than the planar wiring pattern forming the capacitance regardless of the number of layers of the substrate. In this case, the inductance 値 per unit area can be maximized, and the area necessary for obtaining the desired inductance 値 can be minimized, and the resonance circuit can be miniaturized. In the second embodiment, the resonance circuit and the local frequency module including the same can be realized in a small size or at a reduced cost. (Embodiment 3)

在本實施形態3中，針對在圖1之高頻模組中適用有 圖2之並聯共振電路LC1或是圖5之並聯共振電路LC2 的情況之詳細構成例作說明。圖8，係爲在本發明之實施 形態3所致的高頻模組中，展示其構成例之電路圖。於圖 8所示之高頻模組中，如同在圖1中所述一般，低帶域用 之功率放大電路PA一 LB的輸出，係經由輸出整合電路 MN—LB、耦合電路CPL_LB、低通濾波電路LPF—LB以 及電容器Csl3而被傳送至天線開關電路ANT_ SW。於此 ，被形成於半導體晶片處之PA 一 LB的輸出，係經由焊接 導線等而被連接於形成在配線基板上之MN_ LB。又， Cs 1 3，係爲直流截除用之電容器，例如係經由sMD構件 而被形成。 PA一 LB ’例如係成爲將3個的功率電晶體從屬連接 後的3段構成之放大電路。MN 一 LB，例如，係成爲包含 有傳送線路LN1〜LN3、和被設置在LN1〜LN3之各別的 輸出與接地電壓HND之間的電容器Csl〜Cs3之3段構成 的低通濾波型之整合電路。Csl〜Cs3，例如係爲SMD構 件。LN1〜LN3，係從PA— LB之輸出起而依序被串聯連 接。Csl’其一端係被連接於LN1之輸出，另外一端係經 由電感Lil而被連接於GND。同樣的，Cs2、Cs3亦分別 -47- 200835042 地：其一端係被連接於LN2、LN3，另外一端係經由電感 Li2、Li3而被連接於GND。另外，Lil〜Li3，例如，係爲 相當於通孔導體等之寄生電感。In the third embodiment, a detailed configuration example in which the parallel resonant circuit LC1 of Fig. 2 or the parallel resonant circuit LC2 of Fig. 5 is applied to the high-frequency module of Fig. 1 will be described. Fig. 8 is a circuit diagram showing a configuration example of the high frequency module according to the third embodiment of the present invention. In the high frequency module shown in FIG. 8, as in the general description of FIG. 1, the output of the power amplifier circuit PA-LB for the low band is via the output integration circuit MN-LB, the coupling circuit CPL_LB, and the low pass filter circuit. The LPF_LB and the capacitor Csl3 are transmitted to the antenna switch circuit ANT_SW. Here, the output of the PA-LB formed at the semiconductor wafer is connected to the MN_LB formed on the wiring substrate via a solder wire or the like. Further, Cs 1 3 is a capacitor for DC cut, and is formed, for example, by an sMD member. The PA_LB' is, for example, an amplifying circuit composed of three stages in which three power transistors are connected in a slave state. The MN-LB is, for example, a low-pass filter type integration including three sections of the capacitors Cs1 to Cs3 including the transmission lines LN1 to LN3 and the respective outputs of the LN1 to LN3 and the ground voltage HND. Circuit. Cs1 to Cs3 are, for example, SMD components. LN1 to LN3 are sequentially connected in series from the output of the PA-LB. One end of Csl' is connected to the output of LN1, and the other end is connected to GND via the inductor Li1. Similarly, Cs2 and Cs3 are also -47-200835042: one end is connected to LN2 and LN3, and the other end is connected to GND via inductors Li2 and Li3. Further, Li1 to Li3 are, for example, parasitic inductances equivalent to via conductors.

CPL_ LB，係包含有以分別作電磁結合之方式而被形 成之主線路與副線路，主線路之其中一端係被連接於LN3 之輸出，另外一端係被連接於LPF—LB。副線路，係在其 中一端被連接有終端電阻（例如5 0 Ω )，在另外一端係經 由焊接導線等而被連接有與PA_ LB被形成在相同半導體 晶片上之電力檢測電路DET_ LB。 LPF— LB，係由被設置在前述之CPL— LB的主線路之 其中一端與電容器Csl3的其中一端之間的並聯共振電路 ，和分別被連接於此並聯共振電路之兩端與GND之間的2 個的串聯共振電路所構成。並聯共振電路，係由電感Li9 以及電容器Cs9所成。串聯共振電路之其中一方，係由從 前述之CPL_LB的主線路之其中一端起而依序被連接之 電容器Cs8與電感Li8所成，串聯共振電路之另外一方， 係由從前述之Cs 13的其中一端起而依序被連接之電容器 CslO與電感LilO所成。Cs8〜CslO，例如係由SMD構件 所成，Li 8〜LilO，係經由配線基板之內藏電路（通孔導 體或傳送線路）而被形成。此1^下_1^，對於從？八_1^ 所輸出之低帶域訊號.，例如係使其之2次高頻波（2HD ) 、3次高頻波（3HD)以及7次高頻波（7HD)減衰。 另一方面，與此低帶域側之構成同樣的，在高帶域側 ，高帶域用之功率放大電路PA_ HB的輸出，係經由輸出 -48 - 200835042 整合電路MN— HB、耦合電路CPL— HB、低通濾波電路 LPF_HB以及電容器Csl4而被傳送至天線開關電路ANT _ SW。於此，PA_ HB的輸出，係經由焊接導線等而被連 接於MN_HB。又，Csl4，係爲直流截除用之電容器，例 如係經由SMD構件而被形成。CPL_ LB includes a main line and a sub line formed by electromagnetic coupling, one end of which is connected to the output of LN3, and the other end is connected to LPF-LB. The sub-line is connected to a terminating resistor (e.g., 50 Ω) at one end thereof, and is connected to a power detecting circuit DET_LB formed on the same semiconductor wafer as PA_LB by a soldering wire or the like at the other end. LPF_LB is a parallel resonant circuit provided between one end of the main line of the aforementioned CPL-LB and one end of the capacitor Csl3, and is connected between the two ends of the parallel resonant circuit and GND, respectively. Two series resonant circuits are used. The parallel resonant circuit is formed by the inductor Li9 and the capacitor Cs9. One of the series resonant circuits is formed by a capacitor Cs8 and an inductor Li8 which are sequentially connected from one end of the main line of the aforementioned CPL_LB, and the other of the series resonant circuits is from the aforementioned Cs 13 The capacitor Cs10 and the inductor LilO are connected in sequence from one end. Cs8 to Cs10 are formed, for example, of SMD members, and Li 8 to LilO are formed via built-in circuits (via conductors or transmission lines) of the wiring board. This 1^下_1^, for from? The low-band signal output by the eight_1^ is, for example, such that it has two high-frequency waves (2HD), three high-frequency waves (3HD), and seven high-frequency waves (7HD). On the other hand, similarly to the configuration of the low band side, on the high band side, the output of the power amplifier circuit PA_ HB for the high band is output via the output -48 - 200835042 integrated circuit MN-HB, coupling circuit CPL - HB, low pass filter circuit LPF_HB and capacitor Cs14 are transmitted to antenna switch circuit ANT_SW. Here, the output of PA_HB is connected to MN_HB via a welding wire or the like. Further, Csl4 is a capacitor for DC cut, for example, formed by an SMD member.

PA— HB，亦和PA— LB同樣的，例如係成爲將3個 的功率電晶體從屬連接後的3段構成之放大電路。MN_ HB，例如，係成爲包含有傳送線路LN4〜LN7、和被設置 在LN4〜LN7之各別的輸出與接地電壓HND之間的電容 器Cs4〜Cs7之4段構成的低通濾波型之整合電路。Cs4〜 Cs7，例如係爲SMD構件。LN4〜LN7，係從PA— HB之 輸出起而依序被串聯連接。Cs4，其一端係被連接於LN4 之輸出，另外一端係經由電感Li4而被連接於GND。同樣 的，Cs5、Cs6、Cs7亦分SU地：其一端係被連接於LN5、 LN6、LN7，另外一端係經由電感Li5、Li6、Li7而被連接 於GND。Li4〜Li7，例如，係爲相當於通孔導體等之寄生 電感。 CPL_ HB，係包含有以分別作電磁結合之方式而被形 成之主線路與副線路，主線路之其中一端係被連接於LN7 之輸出，另外一端係被連接於LPF_HB。副線路，係在其 中一端被連接有終端電阻（例如50 Ω )，在另外一端係經 由焊接導線等而被連接有與PA_ HB (以及PA_ LB )被 形成在相同半導體晶片上之電力檢測電路DET_ HB。 LPF— HB，係由被設置在前述之CPL_ HB的主線路 -49- 200835042 之其中一端與電容器Cs 14的其中一端之間的並聯共振電 路，和被連接於此並聯共振電路之其中一端（CS14側） 與GND之間的串聯共振電路所構成。並聯共振電路，係 由電感Lil 1以及電容器Csl 1所成。串聯共振電路，係由 從前述之Csl4的其中一端起而依序連接之電容器Csl2與 電感U12所成。Csl 1、Csl2，例如係由SMD構件所成，The PA-HB is also an amplifying circuit composed of three stages in which three power transistors are connected in the same manner as the PA-LB. MN_HB is, for example, a low-pass filter type integrated circuit including four stages of capacitors Cs4 to Cs7 provided between the transmission lines LN4 to LN7 and the respective outputs of LN4 to LN7 and the ground voltage HND. . Cs4~Cs7 are, for example, SMD components. LN4 to LN7 are sequentially connected in series from the output of PA-HB. Cs4 has one end connected to the output of LN4 and the other end connected to GND via inductor Li4. Similarly, Cs5, Cs6, and Cs7 are also divided into SU grounds: one end is connected to LN5, LN6, and LN7, and the other end is connected to GND via inductors Li5, Li6, and Li7. Li4 to Li7 are, for example, parasitic inductances equivalent to via conductors. CPL_ HB includes a main line and a sub line formed by electromagnetic coupling, one end of which is connected to the output of LN7, and the other end is connected to LPF_HB. The sub-line is connected to a terminal resistance (for example, 50 Ω) at one end thereof, and is connected to a power detecting circuit DET_ which is formed on the same semiconductor wafer as PA_ HB (and PA_ LB ) via a soldering wire or the like at the other end. HB. LPF-HB is a parallel resonant circuit between one end of the main line -49-200835042 and the one end of the capacitor Cs 14 disposed at the aforementioned CPL_Hb, and is connected to one end of the parallel resonant circuit (CS14) Side) A series resonant circuit between GND and GND. The parallel resonant circuit is formed by the inductor Li1 1 and the capacitor Csl 1. The series resonant circuit is formed by a capacitor Cs12 and an inductor U12 which are sequentially connected from one end of the aforementioned Csl4. Csl 1, Csl2, for example, is made of SMD components,

Li 1 1、Li 1 2，係經由配線基板之內藏電路而被形成。此 LPF_ HB，對於從PA_ HB所輸出之高帶域訊號，例如係 使其之2次高頻波（2HD) 、3次高頻波（3HD)減衰。 天線開關電路ANT_ SW之天線端子P0，係依序經由 天線濾波電路ANT—FIL、EDS濾波電路ESD—FIL、電容 器Csl6，而被連接於外部天線端子ANT°Csl6(在此係 爲8.2pF)，係爲直流截除用之電容器，例如係經由SMD 構件而被形成。又，在ANT與GND之間，例如係被連接 有由SMD構件所成之阻抗調整用的電感Ls (於此係爲 15nH ) ° ANT— FIL，係具備有在Psl6之其中一端之間而被連 接的並聯共振電路，和在P0與GND之間而被連接的阻抗 調整用之電容器C s 1 5。C s 1 5 (在此係爲〇 . 5 pF )，例如係 經由SMD構件而被形成。另一方面，並聯共振電路，係 由電感Lil3與電容器Cil所成，於此，係使用有在實施 形態2中所示之圖5的並聯共振電路LC2。此並聯共振電 路，係以lmmxlmm之電路面積而被實現，Lil3之電感値 ，例如係爲3·5ηΗ，Cil之電容値，例如係爲〇.25PF。藉 -50- 200835042 由此，成爲高帶域訊號之3次高頻波（3 HD)的5.4 GHz 左右的訊號係被減衰。此ANT_ FIL，主要係進行由於經 由ΑΝΤ一 SW而產生的高帶域訊號之3HD的減衰，和對於 從天線所受訊之高帶域訊號的3HD之減衰。Li 1 1 and Li 1 2 are formed via a built-in circuit of the wiring board. The LPF_ HB, for the high band signal output from the PA_ HB, for example, causes the secondary high frequency wave (2HD) and the third time high frequency wave (3HD) to be degraded. The antenna terminal P0 of the antenna switch circuit ANT_SW is sequentially connected to the external antenna terminal ANT°Csl6 (here, 8.2pF) via the antenna filter circuit ANT-FIL, the EDS filter circuit ESD_FIL, and the capacitor Csl6. The capacitor for DC cut is formed, for example, via an SMD member. Further, between ANT and GND, for example, an inductance Ls for impedance adjustment by the SMD member (15nH in this case) ANT-FIL is connected, and is provided between one end of Psl6. A connected parallel resonant circuit and a capacitor C s 15 for impedance adjustment connected between P0 and GND. C s 1 5 (here, p 5 pF ) is formed, for example, via an SMD member. On the other hand, the parallel resonant circuit is formed by the inductance Lil3 and the capacitor Cil. Here, the parallel resonant circuit LC2 of Fig. 5 shown in the second embodiment is used. The parallel resonant circuit is realized with a circuit area of 1 mm x 1 mm, and the inductance L of Lil 3 is, for example, 3·5 η Η, and the capacitance C of Cil is, for example, 〇.25 PF. By -50- 200835042 As a result, the signal of about 5.4 GHz, which is the third-order high-frequency wave (3 HD) of the high-band signal, is degraded. This ANT_FIL mainly performs the attenuation of 3HD due to the high band signal generated by the SW, and the attenuation of the 3HD for the high band signal received from the antenna.

ESD—FIL，係具備有從前述之Csl6的其中一端起朝 向GND而依序連接之電容器CS15與電感Lil4。Csl5，例 如係由SMD構件所成，並具備有13pF之電容値。Lil4， 係經由配線基板之內藏電路所成，並具備有12nH之電感 値。ESD一 FIL，主要係對於從天線而來之受訊訊號，而將 在ESD對策上會成爲問題之4 0 0MHz左要的訊號減衰。 ANT— SW之天線端子P3，係依序經由直流截除用之 電容器Csl7與受訊濾波電路RX— FIL1，而被連接於外部 輸出端子RX— LB。Csl7 (在此係爲7.4pF )，例如係經 由SMD構件而被形成。 RX__ FIL1，係被連接於Csl7之其中一端與RX—LB 之間，並具備有由電感Lil5與電容器Ci2所成之並聯共 振電路。於此，在此並聯共振電路中，係使用有在實施形 態1中所示之圖2的並聯共振電路LC1。此並聯共振電路 ，係以lmmxlmm之電路面積而被實現，Lil5之電感値， 例如係爲5.6nH，Ci2之電容値，例如係爲〇.6pF。藉由此 ，成爲低帶域訊號之3次高頻波（3HD)的2.7GHz左右 的訊號係被減衰。亦即是，此RX— FIL 1，係對於從天線 所受訊之低帶域訊號，而進行3HD之減衰。 ANT_ SW之天線端子P4，係依序經由受訊濾波電路 -51 - 200835042The ESD-FIL is provided with a capacitor CS15 and an inductor Li14 which are sequentially connected from one end of the aforementioned Cs16 to the GND. Csl5, for example, is made of SMD components and has a capacitance of 13pF. Lil4 is formed by the built-in circuit of the wiring board and has an inductance of 12nH. ESD-FIL is mainly for the received signal from the antenna, and will be the problem of the 4D 0MHz signal that will become a problem in the ESD countermeasures. The antenna terminal P3 of the ANT-SW is connected to the external output terminal RX-LB via the DC cut-off capacitor Cs17 and the signal filter circuit RX-FIL1 in sequence. Csl7 (here, 7.4 pF) is formed, for example, by SMD members. RX__FIL1 is connected between one end of Csl7 and RX-LB, and has a parallel resonant circuit formed by inductor Lil5 and capacitor Ci2. Here, in this parallel resonance circuit, the parallel resonance circuit LC1 of Fig. 2 shown in Embodiment 1 is used. The parallel resonant circuit is realized with a circuit area of 1 mm x 1 mm, and the inductance L of Lil 5 is, for example, 5.6 nH, and the capacitance C of Ci2 is, for example, 〇.6 pF. As a result, the signal of about 2.7 GHz, which is the third-order high-frequency wave (3HD) of the low-band signal, is degraded. That is, the RX-FIL 1 is for the low-band signal received from the antenna, and the 3HD is reduced. Antenna terminal P4 of ANT_ SW is sequentially transmitted via the signal filtering circuit -51 - 200835042

RX_ FIL2與直流截除用之電容器Csl9，而被連接於外部 輸出端子RX_HB。Csl9 (在此係爲8pF )，例如係經由 SMD構件而被形成。RX— FIL2，係具備有從P4起朝向 GND而依序串聯連接之電容器Csl8與電感Lil6。Csl8, 例如係由SMD構件所成，並具備有10pF之電容値。Li 16 ，係經由配線基板之內藏電路所成，並具備有9nH之電感 値。RX— FIL2，於此由於係經由ANT— FIL而將高帶域訊 號之3HD減衰，因此，相異於RX—FIL1，而具備有ESD 對策用之濾波電路。此：RX— FIL2，係使在ESD對策上成 爲問題之400MHz左右的訊號減衰。 如上述一般，在圖8之高頻模組中，作爲用以對低帶 域訊號以及高帶域訊號而減衰3次高頻波（3 HD )，而使 用有如同圖2以及圖5所示一般，並不使用SMD構件且 能夠以小面積而實現的並聯共振電路LC1、LC2。藉由此 ，成爲能夠實現高頻模組之小型化又或是低成本化。另外 ，於此，對應於高帶域訊號，係使用圖5之構造，對應於 低帶域訊號，係使用可實現較圖5之構造而更低之共振頻 率的圖2之構造，但是，只要能夠實現所需要之電路定數 ，則並不特別限定於此組合。RX_FIL2 and DC cut-off capacitor Csl9 are connected to external output terminal RX_HB. Csl9 (here 8pF) is formed, for example, via SMD members. RX-FIL2 is provided with a capacitor Cs18 and an inductor Lil6 which are connected in series from P4 to GND in series. Csl8, for example, is made of SMD components and has a capacitance of 10 pF. Li 16 is formed by a built-in circuit of a wiring board and has an inductance of 9 nH. RX-FIL2, because the 3HD of the high-band signal is degraded by ANT-FIL, is different from RX-FIL1 and has a filter circuit for ESD countermeasures. This: RX-FIL2 is a signal that degrades around 400MHz, which is a problem in ESD countermeasures. As described above, in the high-frequency module of FIG. 8, as the low-band signal and the high-band signal, the high-frequency wave (3 HD) is reduced by 3 times, and the use is as shown in FIG. 2 and FIG. Parallel resonant circuits LC1, LC2 that can be implemented with a small area using SMD components. As a result, it is possible to achieve miniaturization or low cost of the high frequency module. In addition, here, corresponding to the high band signal, the configuration of FIG. 5 is used, corresponding to the low band signal, and the configuration of FIG. 2 that can achieve a lower resonance frequency than the configuration of FIG. 5 is used, but The combination of the required circuit constants is not particularly limited to this combination.

又，於此，雖係將圖2以及圖5之並聯共振電路L C1 、LC2，作爲3次高頻波（3HD )之減衰用而使用，但是 ’不用說’亦可作爲2次局頻波（2HD)之減衰用，或是 除此之外的n(n^4)次高頻波之減衰用而使用。亦即是 ，例如，圖8之電路例，係亦可適用在LPF—LB或是LPF -52- 200835042 _ HB等之中。在本實施形態中，僅將其適用在3次高頻 波（3 HD)之減衰用中的原因，是因爲3 HD減衰用之濾波 電路，相對於配線基板之製造誤差所伴隨之特性變動，係 具備有充分的餘裕（margin )之故。亦即是，實際上，當 產生有配線基板之製造誤差的情況時，雖然亦有經由SMD 構件之參數來對其影響作修正的情況，但是其必要性係爲 低之故。，In addition, although the parallel resonant circuits L C1 and LC2 of FIGS. 2 and 5 are used as the attenuation of the third-order high-frequency wave (3HD), the 'not necessary' can also be used as the secondary frequency wave (2HD). It is used for the fading of the fading, or for the reduction of the n (n^4) times of the high frequency wave. That is, for example, the circuit example of FIG. 8 can also be applied to LPF-LB or LPF-52-200835042 _ HB. In the present embodiment, the reason why it is applied to the attenuation of the third-order high-frequency wave (3 HD) is that the filter circuit for the 3 HD attenuation is provided with respect to the characteristic variation accompanying the manufacturing error of the wiring board. There is ample margin. That is, in actuality, when a manufacturing error of the wiring board occurs, there is a case where the influence is corrected by the parameters of the SMD member, but the necessity is low. ,

又，該當’於圖8中之電感Li 15以及電容器Ci2的圖2 之並聯共振電路LC1，係可如前述一般以圖3(a)之等價 電路來表示。在對此時之各電路元件的參數値作算出後， LI、L2、L3、L4，作爲槪算値，係分別具備有0.8nH、 0·8ηΗ、2·0ηΗ、2.0nH 左右。又，Cl、C2、C3、C4，作爲 槪算値，係分別具備有〇.4pF、O.lpF、O.lpF、O.lpF左右 。如同由此可得知一般，藉由圖2之MS21與MS22，係 可實現充分之電感成分（LI、L2)和充分的電容成分（C1 )° 另一方面，相當於圖8中之電感Li 13以及電容器Cil 的圖5之並聯共振電路LC2，係可如前述一般以圖6之等 價電路來表示。在對此時之各電路元件的參數値作算出後 ，L5、L6，作爲槪算値，係分別具備有1.7nH、1.7nH左 右。又，C5、C6、C7、C8，作爲槪算値，係分別具備有 0.05pF、0.05pF、0.15pF、〇.15pF 左右 〇 如此這般，圖5之並聯共振電路LC2，若是相較於圖 2之並聯共振電路LC 1，則雖然電感値以及電容値係變小 -53- 200835042 ，但是係能夠實現用以使高頻波減衰之充分的定數。又， 如同由前述之等價電路而可得知一般，圖5之LC2，相較 於圖之LC1，由於其之成爲構成要素的參數（電路元件） 之數量係爲較少’因此可以想見，其之對於前述配線基板 等的製造誤差所造成的影響係爲較少。 以上，藉由本實施形態3，而成爲能夠實現共振電路 以及包含有其之高頻模組的小型化又或是低成本化。Further, the parallel resonant circuit LC1 of Fig. 2, which is the inductor Li 15 and the capacitor Ci2 in Fig. 8, can be generally represented by the equivalent circuit of Fig. 3(a) as described above. After calculating the parameters of the circuit elements at this time, LI, L2, L3, and L4 are approximately 0.8nH, 0·8ηΗ, 2·0ηΗ, and 2.0nH, respectively. Further, Cl, C2, C3, and C4 are 槪.4pF, O.lpF, O.lpF, and O.lpF, respectively. As can be seen from the above, the MS21 and MS22 of Fig. 2 can realize sufficient inductance components (LI, L2) and sufficient capacitance components (C1). On the other hand, it is equivalent to the inductance Li in Fig. 8. 13 and the parallel resonant circuit LC2 of FIG. 5 of the capacitor Cil can be generally represented by the equivalent circuit of FIG. 6 as described above. After calculating the parameters of the circuit elements at this time, L5 and L6 are 1.7nH and 1.7nH, respectively. Further, C5, C6, C7, and C8 are provided as 槪 値, which are respectively 0.05pF, 0.05pF, 0.15pF, and 〇.15pF, and the parallel resonant circuit LC2 of Fig. 5 is compared with the figure. In the parallel resonant circuit LC1 of 2, although the inductance 値 and the capacitance 变 are reduced to -53-200835042, a sufficient constant for reducing the high-frequency wave can be realized. Further, as can be seen from the above-described equivalent circuit, LC2 of FIG. 5 is smaller than the number of parameters (circuit elements) which become constituent elements compared to LC1 of the figure. The influence on the manufacturing error of the wiring board or the like is small. As described above, according to the third embodiment, it is possible to reduce the size and cost of the resonant circuit and the high-frequency module including the same.

(實施形態4) 在本實施形態4中，係揭示對在將圖1之高頻模組小 型化時有可能會產生之回路（return path )的問題作解決 之方式。首先，針對回路之問題，使用圖9來作說明。圖 9，係爲在作爲本發明之前提而被檢討之高頻模組中，展 示其功率放大電路周圍之構成例的電路圖。 於圖9所示之高頻模組RF—MDLcl，係爲從在實施 形態3所示之圖8的電路例中，將高帶域訊號用之功率放 大電路P A_ HB與其輸出整合電路MN_ HB的部分作抽出 後所得者。以後，對關於與圖8重複之部分的說明，係省 略之。圖9之高頻模組MF—MDLcl，作爲其配線基板之 構造，通常，係在被形成有PA_HB之半導體晶片的正下 之各配線層（LY2〜LY4 )中形成接地電極圖案，並將此 各接地電極或背面之接地電極，分別以通孔導體來連接， 藉由此而形成最爲安定之接地電壓GND的區域。此區域 ，一般係被稱爲熱通孔TV之形成區域。 -54- 200835042(Embodiment 4) In the fourth embodiment, a method for solving a problem of a return path which may occur when the high-frequency module of Fig. 1 is downsized is disclosed. First, for the problem of the loop, use FIG. 9 for explanation. Fig. 9 is a circuit diagram showing a configuration example of the periphery of the power amplifying circuit in the high frequency module which has been reviewed before the present invention. The high frequency module RF-MDLcl shown in FIG. 9 is a portion of the power amplifying circuit P A_ HB for the high band signal and its output integrating circuit MN_ HB from the circuit example of FIG. 8 shown in the third embodiment. The person who obtained after the withdrawal. In the following, the explanation about the portion overlapping with Fig. 8 will be omitted. The high frequency module MF-MDLcl of FIG. 9 has a ground electrode pattern formed in each of the wiring layers (LY2 to LY4) directly under the semiconductor wafer in which the PA_HB is formed, and is grounded as a wiring substrate. The electrodes or the ground electrodes on the back side are respectively connected by via conductors, thereby forming a region of the most stable ground voltage GND. This area is generally referred to as a formation area of the thermal via TV. -54- 200835042

另一方面，例如，在被連接有PA— HB之輸出的輸出 整合電路MN—HBcl中，PA—HB之輸出電力，係經由電 容器Cs4〜Cs7 (特別是Cs4 )與電感Li4〜Li7 (特別是 Li4) ’而流入LY3之接地電極圖案中。另外，此接地電 極圖案係在LY3而被連接於熱通孔TV之形成區域，並進 而經由通孔導體而亦被連接於背面之接地電極。又，C s4 〜Cs7，例如係在第1配線層中作爲SMD構件而被安裝， Li4〜Li7，係該當於用以將此LY1與LY3作連接之通孔 導體。 然而，在圖8之電路例中雖並未圖示，但是在被包含 於PA— HB中且分別被作從屬連接之3段的功率電晶體之 各輸出節點處，例如係被連接有如圖9所示一般之偏壓電 路BC。在BC中，——般而言，係在將偏壓電壓Vcc經由被 稱爲抗流線圈（choke coil )等之高頻波遮斷用的電感而 供給至功率電晶體之各輸出（亦即是對下一段之輸出）的 φ 同時，在此Vcc與接地電壓GND之間，被設置有被稱爲 解耦合電容器等之高頻波性的接地用之電容器。於圖9中 ，此抗流線圈，係該當於傳送線路LN6 1〜LN65或是電感 Ls2，而解耦合電容器，係該當於電容器Cdl〜cd3。 於此，Cdl〜Cd3，例如係在LY1中作爲SMD構件而 被安裝，其一端係被連接於Vce，另外一端係經由被連接 在LY1和LY32之間的通孔導體（電感）VH1〜VH3而被 連接於LY3之接地電極圖案。故而，如圖9之箭頭所示一 般，PA一 HB之輸出電流，係被形成有：經由電容性結合 -55- 200835042 (Cs4〜Cs7 (特別是Cs4))而流入LY3之接地電極圖案 ，進而，從此接地電極圖案，經由電容性結合（Cdl〜Cd3 )而回歸至功率電晶體之輸入的路徑。此路徑，係被稱爲 回路（return pat h)RP。On the other hand, for example, in the output integration circuit MN-HBcl to which the output of the PA-HB is connected, the output power of the PA-HB is via the capacitors Cs4 to Cs7 (especially Cs4) and the inductances Li4 to Li7 (especially Li4) 'and flow into the ground electrode pattern of LY3. Further, the ground electrode pattern is connected to the formation region of the thermal via TV in LY3, and is also connected to the ground electrode on the back side via the via conductor. Further, C s4 to Cs7 are mounted as SMD members in the first wiring layer, for example, Li4 to Li7 are via-hole conductors for connecting the LY1 and LY3. However, although not shown in the circuit example of FIG. 8, at the output nodes of the power transistors included in the PA-HB and respectively connected as the slave segments, for example, as shown in FIG. A typical bias circuit BC is shown. In BC, in general, the bias voltage Vcc is supplied to the respective outputs of the power transistor via an inductance called high-frequency wave blocking such as a choke coil (that is, φ of the output of the next stage) At the same time, between this Vcc and the ground voltage GND, a capacitor for grounding called a decoupling capacitor or the like is provided. In Fig. 9, the choke coil is disposed on the transmission lines LN6 1 to LN65 or the inductor Ls2, and the decoupling capacitors are applied to the capacitors Cd1 to cd3. Here, Cdl to Cd3 are, for example, mounted as SMD members in LY1, one end of which is connected to Vce, and the other end of which is connected via via-hole conductors (inductors) VH1 to VH3 connected between LY1 and LY32. Connected to the ground electrode pattern of LY3. Therefore, as shown by the arrow in FIG. 9, the output current of the PA-HB is formed by a capacitive connection of -55-200835042 (Cs4~Cs7 (especially Cs4)) into the ground electrode pattern of LY3, and further From then on, the ground electrode pattern is returned to the path of the input of the power transistor via capacitive coupling (Cdl~Cd3). This path is called a return pat h RP.

另外’在圖9之電路例中，雖係展不有經由偏壓電路 BC之回路RP，但是，除此之外，雖並未圖示，但亦存在 著經由在功率電晶體之各段間所被插入的整合電路而形成 的回路。亦即是，例如，亦會有：將第1段之功率電晶體 的輸出暫時藉由焊接導線而拉出至配線基板上，並在配線 基板上進行阻抗整合，之後，再度經由焊接導線而回到第 2段之功率電晶體的輸入處一般之情況，在此種狀況下， 配線基板上之整合電路亦有可能會成爲回路。回路，係會 引起如前述一般之震盪現象，而成爲錯誤動作等之原因。 但是，在圖9中，例如，若是能夠在輸出整合電路MN_ HBxl與偏壓電路BC等之間保持充分的距離，貝IJ能夠減少 此種問題。然而，相反的，小型化係變爲困難。 於此，爲了在追求小型化的同時，亦解決回路之問題 ，例如，係可使用圖10 —般之構成。圖10，係爲在本發 明之實施形態4所致的高頻模組中，展示其功率放大電路 周邊的構成例之電路圖。於圖1 〇中所示之高頻模組RF_ MDLa，相較於圖9之構成例，其特徵係成爲：除了在 LY2處將電感（通孔導體）Li4、Li5與熱通孔TV之形成 區域作連接的配線圖案MS 72之外，更進而加上有將此 MS72與LY3之接地電極作連接的複數之通孔導體（電感 -56- 200835042 )VHm。另外，在MS 72中，係使用有線狀之配線圖案。In addition, in the circuit example of FIG. 9, although the circuit RP via the bias circuit BC is not shown, it is not shown, but it is also present in each section of the power transistor. A loop formed by the integrated circuit that is inserted. That is, for example, the output of the power transistor of the first stage is temporarily pulled out to the wiring substrate by soldering wires, and impedance integration is performed on the wiring substrate, and then returned again via the soldering wire. In the general case of the input of the power transistor of the second stage, in this case, the integrated circuit on the wiring substrate may also become a loop. The circuit causes a general oscillation as described above, and causes a malfunction or the like. However, in Fig. 9, for example, if a sufficient distance can be maintained between the output integration circuit MN_HBTx and the bias circuit BC or the like, the problem can be reduced. However, on the contrary, miniaturization becomes difficult. Here, in order to achieve miniaturization and solve the problem of the circuit, for example, it can be configured as shown in FIG. Fig. 10 is a circuit diagram showing a configuration example of the periphery of the power amplifying circuit in the high frequency module according to the fourth embodiment of the present invention. The high-frequency module RF_MDLa shown in FIG. 1 is characterized in comparison with the configuration example of FIG. 9 in that the formation regions of the inductors (via-hole conductors) Li4, Li5 and the thermal vias are made at LY2. In addition to the connected wiring pattern MS 72, a plurality of via-hole conductors (inductors - 56 - 200835042 ) VHm connecting the ground electrodes of the MS 72 and the LY 3 are further added. Further, in the MS 72, a wired wiring pattern is used.

若藉由此種構成，則以對應於TV之形成區域的GND 作爲基準，由於通孔導體Li4、Li 5與MS 72間之接點電位 VA，係成爲較Li4、Li5與LY3之接地電極圖案間的接點 電位VB爲更高，因此在LY2中，係成爲在從MS 72朝向 TV之方向上流動有較多的電流。此時，由於偏壓電路BC 係被連接於LY3之接地電極圖案，因此，並不會直接地流 入在此LY2中所流動之電流。又，經由通孔導體Li4、 Li5，在LY3之接地電極圖案中亦會流動有若千之電流， 但是，此電流，亦由於LY3之接地電極圖案係經由複數之 VHm而被與MS 72作連接，因此係成爲易於流向TV之形 成區域的方向。因此，在被連接於LY3之接地電極圖案的 偏壓電路BC側，電流係幾乎不會流入，而成爲能夠解決 回路之問題。進而，藉由將MS 72與LY3之接地電極以複 數之VHm來連接，亦成爲能夠減低MS72之電感成分的 影響，而可防止在輸出整合電路之特性中產生有誤差之類 的事態。 圖1 1，係爲在本發明之實施形態4所致的高頻模組中 ，展示其功率放大電路周邊之配線基板的構成例者‘，(a )係作爲比較對象，而爲對應於圖9之構成的佈線圖，（ b)係爲對應於圖10之構成的配線圖。圖12，係爲在本發 明之實施形態4所致的高頻模組中，展示對應於圖1 〇之 構成的配線基板之構成例者，（a )係爲將配線基板全體 作透視時的立體圖，（b )係爲將其之功率放大電路周邊 -57- 200835042According to this configuration, the contact potential VA between the via hole conductors Li4, Li5 and the MS 72 is made to be a ground electrode pattern of Li4, Li5, and LY3 with reference to the GND corresponding to the formation region of the TV. Since the contact potential VB is higher, in LY2, a large amount of current flows in the direction from the MS 72 toward the TV. At this time, since the bias circuit BC is connected to the ground electrode pattern of LY3, it does not directly flow into the current flowing in this LY2. Further, thousands of currents flow through the via-hole conductors Li4 and Li5 in the ground electrode pattern of LY3. However, this current is also connected to the MS 72 via the complex VHm through the ground electrode pattern of the LY3. Therefore, it is a direction that is easy to flow to the formation area of the TV. Therefore, in the bias circuit BC side connected to the ground electrode pattern of LY3, the current system hardly flows in, and the problem of the circuit can be solved. Further, by connecting the ground electrodes of the MS 72 and the LY3 with a plurality of VHm, it is possible to reduce the influence of the inductance component of the MS 72, and it is possible to prevent a situation in which an error occurs in the characteristics of the output integrated circuit. In the high-frequency module according to the fourth embodiment of the present invention, a configuration example of the wiring board around the power amplifier circuit is shown, and (a) is a comparison object, and corresponds to FIG. The wiring diagram of the configuration, (b) is a wiring diagram corresponding to the configuration of FIG. FIG. 12 is a perspective view showing a configuration of a wiring board corresponding to the configuration of FIG. 1 in the high-frequency module according to the fourth embodiment of the present invention, and (a) is a perspective view when the entire wiring board is seen through. (b) is to surround the power amplifier circuit -57- 200835042

作擴 後之 線層 圖案 偏壓 成（ 有從 LY3 連接 。另(b： 有從 ，此 LY3The expanded line layer pattern is biased into (there is a connection from LY3. Another (b: there is from , this LY3

之回 展示 成的 RF_ 回歸 之高 範圍 大的立體圖，（c)係爲從（b)而將第1配線層省略 立體圖。 在圖1 1 ( a )、（ b )中，係分別揭示有對應於第1配 LY1、第2配線層1^2以及第3配線層1^3之佈線 的一部份。如圖1 1 ( a )所示，輸出整合電路MN與 電路BC，係被配置在幾乎同樣的位置。在圖9之構 比較例）中，如圖1 1 ( a)所示，在L Y2處，係並沒 MN而連接至熱通孔TV之形成區域的配線圖案，在 之接地電極圖案處，係分別被連接有經由通孔導體所 之MN的GND、和經由通孔導體所連接之BC的GND 一方面，在圖10之構成（本實施形態）中，如圖11 以及圖12 ( a)〜（c)所示，在LY2處，係被設置 MN而連接至熱通孔TV之形成區域的配線圖案MS 72 MS72，係經由複數之通孔導體VHm，而亦被連接於 之接地電極圖案。 圖1 3，係爲對圖9之構成（比較例）與圖1 0之構成 歸增益（return gain )値作評價後之結果，（a )係爲 圖9之構成的結果之圖表，（b)係爲展示圖10之構 結果之圖表。如圖13所示一般，在圖9之高頻模組 MDLcl中，在1 .5GHz前後，係存在有15dB左右之 增益，藉由此，震盪現象係產生。另一方面，在圖1 〇 頻模組RD— MDLa中，橫跨寬廣的帶域（0〜4GHz ) ，均沒有超過OdB之回歸增益，而並不產生震盪現象 -58- 200835042 圖14〜圖16，係爲對圖9之構成（比較例）與圖l〇 之構成以電流密度而作解析後之結果，圖1 4，係爲展示在The high-dimensional view of the RF_regression is shown in the back, and (c) is a perspective view in which the first wiring layer is omitted from (b). In Figs. 1 1 (a) and (b), portions corresponding to the wirings of the first matching LY1, the second wiring layer 1^2, and the third wiring layer 1^3 are respectively disclosed. As shown in Fig. 11 (a), the output integration circuit MN and the circuit BC are arranged at almost the same position. In the comparative example of FIG. 9 , as shown in FIG. 11 ( a ), at L Y2 , the wiring pattern of the formation region of the thermal via TV is not connected to MN, and at the ground electrode pattern, The GND of the MN via the via conductor and the GND of the BC connected via the via conductor are respectively connected, and in the configuration of FIG. 10 (this embodiment), as shown in FIGS. 11 and 12 (a) As shown in (c), at LY2, the wiring pattern MS 72 MS72 which is connected to the formation region of the thermal via TV by MN is connected to the ground electrode pattern via the plurality of via-hole conductors VHm. . Fig. 13 is a result of evaluating the composition of Fig. 9 (comparative example) and the return gain of Fig. 10, and (a) is a graph showing the result of the configuration of Fig. 9, (b) ) is a chart showing the results of Figure 10. As shown in Fig. 13, in general, in the high-frequency module MDLcl of Fig. 9, there is a gain of about 15 dB before and after 1.5 GHz, whereby the oscillation phenomenon occurs. On the other hand, in the 〇-frequency module RD-MDLa of Figure 1, across the wide band (0~4GHz), there is no regression gain exceeding OdB, and no oscillation occurs. -58- 200835042 Figure 14~ 16. The result of analyzing the current density by the configuration of the FIG. 9 (comparative example) and the structure of FIG. 1 is shown in FIG.

第1配線層LY1處之解析結果，圖15，係爲展示在第2 配線層LY2處之解析結果，圖16，係爲展示在第3配線 層LY3處之解析結果。另外，在圖14〜圖16中，當從第 3段之功率放大電路PA而被輸出有電力時，係針對朝向 第1段（Ist)之功率電晶體（Tr)的輸入之回歸電流、和 朝向第2段（2nd )之Tr的輸入之回歸電流、和朝向第3 段（3^ )之Τι:的輸入之回歸電流，而分別作解析。 首先，在圖14所示之LY1的解析結果中，於左側， 係展示有成爲比較例之圖9的高頻模組RF_MDLcl之結 果，於右側，係展示有成爲本實施形態之圖1 0的高頻模 組RF _ MDLa之結果。如问由此圖而可以得知一'般，在圖 10之高頻模組RF—MDLa中，相較於圖9之高頻模組RF 一 MDLcl，特別是朝向lstTr之回歸電流與朝向3fdTr之回 歸電流，係大幅的被減低。接下來，在圖15所示之LY2 的解析結果中，在圖10之高頻模組RF_ MDLa中，可以 得知，經由前述之配線圖案MS 72，朝向TV之形成區域係 流動有多量的電流。另外，在圖 9之高頻模組 RF _ MDLcl中，由於係並不具備有此種配線圖案，因此在圖 15中係並不存在有該當之結果。 最後，在圖16所示之LY3的解析結果中，於左側， 係展示有成爲比較例之圖9的高頻模組RF_ MDLcl之結 果，於右側，係展示有成爲本實施形態之圖1 〇的高頻模 -59- 200835042 組RF_ MDLa之結果。如同由此圖而可以得知一般，在圖 10之高頻模組RF—MDLa中，相較於圖9之高頻模組RF — MDLcl，特別是朝向lstTr之回歸電流與朝向3fdTr之回 歸電流，係大幅的被減低。由上述，可以得知，藉由使用 圖10之高頻模組RF_ MDLa，能夠大幅的降低朝向輸入 端之回歸電流。The analysis results of the first wiring layer LY1, Fig. 15 shows the analysis results at the second wiring layer LY2, and Fig. 16 shows the analysis results at the third wiring layer LY3. In addition, in FIG. 14 to FIG. 16, when power is output from the power amplifier circuit PA of the third stage, the return current and the input current to the power transistor (Tr) of the first stage (Ist) are The regression current of the input to the Tr of the second stage (2nd) and the return current of the input of the :: of the third stage (3^) are respectively analyzed. First, in the analysis result of LY1 shown in FIG. 14, on the left side, the result of the high frequency module RF_MDLcl of FIG. 9 which is a comparative example is shown, and on the right side, the high frequency module which becomes the figure 10 of this embodiment is shown. The result of RF _ MDLa. As can be seen from this figure, in the high frequency module RF-MDLa of FIG. 10, compared with the high frequency module RF-MDLcl of FIG. 9, especially the regression current toward lstTr and the regression current toward 3fdTr, The system was greatly reduced. Next, in the analysis result of LY2 shown in Fig. 15, in the high-frequency module RF_MDLa of Fig. 10, it can be seen that a large amount of current flows in the formation region of the TV via the wiring pattern MS 72 described above. Further, in the high frequency module RF_MDLcl of Fig. 9, since such a wiring pattern is not provided, there is no such a result in Fig. 15. Finally, in the analysis result of LY3 shown in FIG. 16, on the left side, the result of the high frequency module RF_MDLcl of FIG. 9 which is a comparative example is shown, and on the right side, the high frequency mode which becomes the figure of FIG. -59- 200835042 The result of group RF_MDLa. As can be seen from this figure, in the high frequency module RF-MDLa of FIG. 10, compared with the high frequency module RF_MDLcl of FIG. 9, especially the regression current toward lstTr and the regression current toward 3fdTr are large. Being reduced. From the above, it can be seen that by using the high frequency module RF_MDLa of Fig. 10, the regression current toward the input terminal can be greatly reduced.

圖17，係爲用以針對圖10之構成例的合適之適用例 而作說明的槪略圖，（a) 、（b)係爲分別展示相異之構 成例者。例如，如同在圖17 ( b )之高頻模組RF_ MDLc2 中所示一般，對於構成功率放大電路之3段構成的功率電 晶體（Tr )，有在第3段（最終段）而以其他之半導體晶 片來作形成並安裝的情況。亦即是，將對應於低帶域以及 高帶域之第1·斷語第2段的Tr，藉由1個的半導體晶片 PC—CPcl來形成，並將對應於低帶域之第3段的Tp藉 由另外之半導體晶片PC 一 CPc2來形成，再將對應於高帶 域之第3段的Tr，更進而藉由其他之半導體晶片PA_ CPc3來形成的情況。 在此情況下，此3個的半導體晶片pA_CPel〜PA_ CPc3，係分別被安裝在RF— MDLc2上。如此一來，由於 從第3段之Tr的輸出起直到第1段又或是第2段的Tr之 輸入爲止的距離係變大，因此係成爲可容易的避免如前述 一般之回路的問題。然而，在此種構成中，會有：高頻模 組RF— MDLc2被大型化，且成本亦增大等之弊害。 於此’爲了追求小型化又或是低成本化，係以如同圖 -60- 200835042 17 ( a)之高頻模組RF—MDL —般，將3段的Tr藉由1 個的半導體晶片PA一 CP來形成爲理想。但是’如此一來 ，由於從第3段之Tr的輸出起直到第1段又或是第2段 的Tr之輸入爲止的距離係變短，因此回路的問題係成爲 更顯著。在此種情況，若是使用圖1 〇之構成例，則能夠 解決回路之問題，並成爲能夠實現高頻模組之小型化又或 是低成本化。Fig. 17 is a schematic diagram for explaining a suitable example of the configuration of Fig. 10, and (a) and (b) are diagrams showing different configurations. For example, as shown in the high frequency module RF_MDLc2 of FIG. 17(b), the power transistor (Tr) constituting the three stages of the power amplifying circuit has the third stage (final stage) and other semiconductors. The wafer is formed and installed. In other words, Tr corresponding to the second segment of the first band and the second segment of the low band and the high band is formed by one semiconductor wafer PC_CPcl, and corresponds to the third segment of the low band. The Tp is formed by another semiconductor wafer PC-CPc2, and the Tr corresponding to the third segment of the high band is further formed by the other semiconductor wafer PA_CPc3. In this case, the three semiconductor wafers pA_CPel to PA_CPc3 are respectively mounted on the RF-MDLc2. As a result, since the distance from the output of the third segment Tr to the input of the first segment or the second segment Tr becomes large, the problem of the above-described general circuit can be easily avoided. However, in such a configuration, there is a disadvantage that the high frequency module RF-MDLc2 is enlarged and the cost is increased. In order to pursue miniaturization or low cost, a three-segment Tr is used for a semiconductor wafer PA-CP as in the high-frequency module RF-MDL of Fig. 60-200835042 17 (a). To form an ideal. However, in this case, since the distance from the output of the third segment Tr to the input of the first segment or the second segment Tr is shortened, the problem of the circuit becomes more conspicuous. In this case, if the configuration example of Fig. 1 is used, the problem of the circuit can be solved, and the high-frequency module can be reduced in size or cost.

以上，藉由本實施形態4，回路之問題係被抑制，藉 由此，成爲能夠實現高頻模組的小型化又或是低成本化。 (實施形態5) 〈RF模組〉 圖1 9，係爲展示本發明之實施形態5所致的高頻模組 之電路構成的圖。圖19之RF模組，與圖18之RF模組 的基本之相異處，係在於輸出整合電路12c與方向性結合 φ 器（CPL ) 13以及高頻波除去濾波器（LPF ) 14之連接順 序。 故而，若藉由本發明之實施形態5的圖1 9之RF模組 ，則係具有下述一般之優點。亦即是，在圖19中，假定 RF電力放大器ΗΡΑ之輸出放大訊號P〇ut的高頻波成分， 係成爲經由方向性結合器1 3之副線路與增益控制單元1 7 之間的訊號配線、方向性結合器1 3之副線路以及主線路 ’而被傳達。就算是假定爲如此，在方向性結合器13之 主線路與天線1 6之間，亦係被連接有高頻波除去濾波器 -61 - 200835042 14。故而，能夠避免RF電力放大器ΗΡΑ之輸出的高準位 之高頻波成分，經由方向性結合器之副線路與增益控制單 元之間的訊號配線、方向性結合器之副線路以及主線路， 而傳達至天線1 6。As described above, according to the fourth embodiment, the problem of the circuit is suppressed, whereby the high-frequency module can be reduced in size or cost. (Embodiment 5) <RF Module> Fig. 1 is a view showing a circuit configuration of a high frequency module according to a fifth embodiment of the present invention. The RF module of Fig. 19 differs substantially from the RF module of Fig. 18 in the order in which the output integration circuit 12c is connected to the directional combining φ (CPL) 13 and the high frequency removing filter (LPF) 14. Therefore, the RF module of Fig. 19 according to the fifth embodiment of the present invention has the following general advantages. That is, in Fig. 19, it is assumed that the high-frequency wave component of the output amplification signal P〇ut of the RF power amplifier 成为 is the signal wiring and direction between the sub-line of the directional combiner 13 and the gain control unit 17. The sub-line of the sex combiner 13 and the main line 'are communicated. Even if it is assumed to be so, a high-frequency wave removing filter -61 - 200835042 14 is also connected between the main line of the directional combiner 13 and the antenna 16. Therefore, the high-frequency wave component of the high-level position capable of avoiding the output of the RF power amplifier is transmitted to the signal wiring between the sub-line of the directional combiner and the gain control unit, the sub-line of the directional combiner, and the main line. Antenna 16.

圖1 9之RF模組，係包含有：RF電力放大器ΗΡΑ、 和最終段之輸出整合電路12c、和方向性結合器（CPL ) 13、和高頻波除去濾波器（LPF ) 14、和天線開關（ANT 一 S W ) 1 5。天線開關1 5，係在RF模組之外部，被連接於 行動電話之天線（ANT ) 16。 〈RF模組內之單石半導體積體電路〉 RF電力放大器係被構成於單石（Monolithic)半導體 積體電路之晶片中，並包含有：初段放大器1 〇a、初段偏 壓電路10b、第1段間整合電路10c、次段放大器11a、次 段偏壓電路1 1 b、第2段間整合電路1 1 c、最終段放大器 1 2a、最終段偏壓電路1 2b、增益控制單元1 7。在初段放 大器l〇a之初段RF輸入端子中，係被供給有RF放大訊號 RFin，初段放大器l〇a之初段RF放大輸出訊號，係經由 第1段間整合電路1 〇e，而被供給至次段放大器1 1 a之次 段RF輸入端子中。次段放大器11a之次段RF放大輸出訊 號，係經由第2段間整合電路1 1 c，而被供給至最終段放 大器12a之最終段RF輸入端子處。 在單石半導體積體電路之矽晶片中，係被形成有構成 初段放大器10a、次段放大器11a、最終段放大器12a之 -62- 200835042The RF module of Fig. 19 includes: an RF power amplifier ΗΡΑ, and a final stage output integration circuit 12c, and a directional combiner (CPL) 13, and a high frequency removal filter (LPF) 14, and an antenna switch ( ANT a SW) 1 5. The antenna switch 15 is external to the RF module and is connected to an antenna (ANT) 16 of the mobile phone. <Single-semiconductor integrated circuit in RF module> The RF power amplifier is formed in a monolithic semiconductor integrated circuit, and includes an initial stage amplifier 1 〇a, an initial stage bias circuit 10b, and First inter-stage integration circuit 10c, sub-stage amplifier 11a, sub-stage bias circuit 1 1 b, second inter-stage integration circuit 1 1 c, final stage amplifier 1 2a, final stage bias circuit 1 2b, gain control Unit 1 7. In the initial stage RF input terminal of the initial stage amplifier l〇a, the RF amplification signal RFin is supplied, and the initial stage RF amplification output signal of the initial stage amplifier l〇a is supplied to the first stage integration circuit 1 〇e. The sub-stage amplifier 1 1 a is in the secondary RF input terminal. The sub-stage RF amplified output signal of the sub-stage amplifier 11a is supplied to the final stage RF input terminal of the final stage amplifier 12a via the second inter-stage integrating circuit 1 1 c. In the germanium wafer of the monolithic semiconductor integrated circuit, the first stage amplifier 10a, the second stage amplifier 11a, and the final stage amplifier 12a are formed -62-200835042

LD ( Lateral Diffused )構造 MOS 的功率 MO SFET。第 1 段間整合電路l〇c，係將因初段放大器10a之較高的輸出 阻抗與次段放大器1 1 a之較低的輸出阻抗間之差所致的訊 號反射減低。第2段間整合電路1 1 c，係將因次段放大器 11a之較低的輸出阻抗與最終段放大器12a之更低的輸出 阻抗間之差所致的訊號反射減低。第1段間整合電路1 0c 與第2段間整合電路11c，係藉由被形成在矽晶片上之螺 旋電感或MIM (金屬•絕緣膜•金屬）層積電容等之晶載 (on-chip)被動元件而構成。 〈RF模組內之分立（discrete)元件〉 RF電力放大器ΗΡΑ之最終段放大器12a的最終段RF 放大輸出訊號Pout，係經由單石半導體積體電路之晶片外 部的最終段之輸出整合電路1 2c，而被連接至方向性結合 器（CPL ) 13之主線路的其中一端。輸出整合電路12c， 係將因最終段放大器12a之極低的輸出阻抗（數Ω左右） 與方向性結合器1 3、天線1 6之較高的輸出阻抗（5 0 Ω左 右）間之差所致的訊號反射減低。輸出整合電路1 2c，係 藉由被形成在RF模組之多層配線基板處的微波傳送線 TRL1、TRL2、TRL3 ;電容 Cl、C2、C3 ;電感 LI、L2、 L3等的分立被動元件而被構成。方向性結合器（CPL) 13 之主線路與副線路，係藉由被形成在RF模組之多層配線 基板上的多層配縣所構成。LD ( Lateral Diffused) constructs the power of the MOS MO SFET. The integrated circuit l〇c between the first segments reduces the signal reflection due to the difference between the higher output impedance of the initial stage amplifier 10a and the lower output impedance of the secondary stage amplifier 1 1 a. The second stage integration circuit 1 1 c reduces the signal reflection due to the difference between the lower output impedance of the sub-stage amplifier 11a and the lower output impedance of the final stage amplifier 12a. The first-stage integrated circuit 10c and the second-stage integrated circuit 11c are on-chip by a spiral inductor or a MIM (metal/insulating film/metal) layered capacitor formed on a germanium wafer. ) consists of passive components. <Discrete Element in RF Module> The final stage RF amplified output signal Pout of the final stage amplifier 12a of the RF power amplifier is output integrated circuit 1 2c of the final stage outside the wafer of the monolithic semiconductor integrated circuit And is connected to one end of the main line of the directional bonder (CPL) 13. The output integration circuit 12c is different from the extremely low output impedance (about Ω) of the final stage amplifier 12a and the higher output impedance (about 50 Ω) of the directional combiner 13 and the antenna 16. The resulting signal reflection is reduced. The output integration circuit 12c is formed by the microwave transmission lines TRL1, TRL2, TRL3 formed at the multilayer wiring substrate of the RF module, the discrete components of the capacitors Cl, C2, C3, the inductors LI, L2, L3, etc. Composition. The main line and the sub line of the directional bonder (CPL) 13 are constituted by a multi-layered county formed on a multilayer wiring board of the RF module.

方向性結合器（CPL ) 1 3之主線路的另外一端之RF -63- 200835042Directional combiner (CPL) 1 3 The other end of the main line RF -63- 200835042

訊號，係被供給至高頻波除去濾波器（LPF) 14之RF訊 號輸入端子。高頻波除去濾波器（LPF ) 14，雖係將被供 給至RF訊號輸入端子之RF訊號的基本頻率成分以極小 之減衰率而傳達至RF訊號輸出端子，但是，2倍高頻波 、3倍高頻波、4倍高頻波等之高頻波成分，係以大的減 衰率而被減衰。故而，高頻波除去濾波器1 4，係作爲低通 濾波器（LPF)而動作。高頻波除去濾波器14之電感L5 與電容C2之並聯連接的並聯共振頻率f5，係被設定爲與 2倍高頻波略爲相等。藉由在並聯共振頻率f5處之電感 L5與電容C5的並聯連接之高阻抗，2倍高頻波係以大的 減衰率而被減衰。高頻波除去濾波器14之電感L4與電容 C4之串聯連接的串聯共振頻率f4，係被設定爲與3倍高 頻波略爲相等。藉由在並聯共振頻率f4處之電感L4與電 容C4的串聯連接之低阻抗，3倍高頻波係以大的減衰率 而被減衰。高頻波除去濾波器14之電感L6與電容C6之 串聯連接的串聯共振頻率f6，係被設定爲與4倍高頻波略 爲相等。藉由在並聯共振頻率f6處之電感L6與電容C6 的串聯連接之低阻抗，4倍高頻波係以大的減衰率而被減 衰。 高頻波除去濾波器1 4之RF訊號輸出端子的RF訊號 ，係被供給至天線開關1 5之其中一端，而天線開關1 5之 另外一端，係被連接於天線1 6之其中一端。高調波除去 濾波器14之輸出端子的RF訊號，係經由DC截斷電容器 Cdc，而被供給至天線開關15之其中一方的端子。RF電 -64- 200835042The signal is supplied to the RF signal input terminal of the high frequency removal filter (LPF) 14. The high frequency wave removing filter (LPF) 14 transmits the fundamental frequency component of the RF signal supplied to the RF signal input terminal to the RF signal output terminal with a minimum attenuation rate, but 2 times of high frequency wave, 3 times of high frequency wave, 4 High-frequency wave components such as high-frequency waves are degraded by a large attenuation rate. Therefore, the high-frequency wave removing filter 14 operates as a low-pass filter (LPF). The parallel resonance frequency f5 in which the inductance L5 of the high-frequency wave removing filter 14 and the capacitor C2 are connected in parallel is set to be slightly equal to the double-frequency high-frequency wave. By the high impedance of the parallel connection of the inductor L5 and the capacitor C5 at the parallel resonance frequency f5, the double-frequency wave system is degraded with a large attenuation rate. The series resonance frequency f4 of the series connection of the inductance L4 of the high-frequency wave removing filter 14 and the capacitor C4 is set to be slightly equal to the three-fold high frequency wave. By the low impedance of the series connection of the inductance L4 and the capacitance C4 at the parallel resonance frequency f4, the three-fold high-frequency wave is degraded with a large attenuation rate. The series resonance frequency f6 of the series connection of the inductance L6 of the high-frequency wave removing filter 14 and the capacitor C6 is set to be slightly equal to the four-fold high-frequency wave. The four-fold high-frequency wave is attenuated by a large attenuation rate by the low impedance of the series connection of the inductance L6 and the capacitance C6 at the parallel resonance frequency f6. The RF signal of the RF signal output terminal of the high-frequency wave removing filter 14 is supplied to one end of the antenna switch 15, and the other end of the antenna switch 15 is connected to one end of the antenna 16. The RF signal of the output terminal of the high-frequency wave removing filter 14 is supplied to one of the terminals of the antenna switch 15 via the DC cut capacitor Cdc. RF Power -64- 200835042

力放大器ΗΡΑ之最終段放大器12a的最終段RF放大輸出 訊號Pout，係伴隨著RF訊號成分而亦包含有DC電壓成 分。高頻波除去濾波器14之DC截斷電容器Cdx，係用以 避免將最終段RF放大輸出訊號Pout之DC電壓成分傳達 至天線開關15與天線16。經由本發明者之檢討，而明顯 得知了 ：藉由被配置於高頻波除去濾波器1 4之輸出端子 與天線開關15之間的DC截斷電容器Cdc，對於由輸出整 合電路12c與方向性結合器13與高頻波除去濾波器14所 成之訊號路徑的相位旋轉之調整係成爲容易，且在天線開 關15處之訊號歪曲亦被減低。 又，方向性結合器（CPL ) 1 3之副線路的其中一端與 另外一端，係分別被連接於終端電阻Rt與RF電力放大器 HPA之增益控制單元1 7的檢測電壓輸入端子。在增益控 制單元1 7中，係被供給有：經由RF類比訊號處理半導體 積體電路而從基頻帶訊號處理單元而來之增益控制訊號 Vramp，和從方向性結合器1 3而來之檢測電壓Vcpl。另 外，增益控制訊號Vramp之準位，係爲與基地台和行動電 話之距離成比例者，從RF電力放大器ΗΡΑ而被供給至天 線16之RF送訊訊號RFout的準位，係可藉由增益控制訊 號Vr amp之準位來作控制。增益控制單元17，係以使從 方向性結合器1 3而來之檢測電壓Vcpl準位追隨於增益控 制訊號Vramp之準位的方式，而對RF電力放大器ΗΡΑ之 增益作控制，藉由此，而進行APC動作。此APC，係藉 由以增益控制單元1 7所控制之初段偏壓電路1 Ob、次段偏 -65- 200835042 壓電力lib、最終段偏壓電路12b所致的初段放大器10s 、初段放大器l〇a、最終段放大器12a之增益控制而被實 行。 . (實施形態6 ) 〈成爲可進行多帶域之送訊的RF模組〉The final stage RF amplified output signal Pout of the final stage amplifier 12a of the power amplifier 亦 also includes a DC voltage component along with the RF signal component. The DC cut capacitor Cdx of the high frequency removal filter 14 is used to avoid transmitting the DC voltage component of the final stage RF amplified output signal Pout to the antenna switch 15 and the antenna 16. As a result of review by the inventors, it is apparent that the DC cut capacitor Cdc disposed between the output terminal of the high frequency removing filter 14 and the antenna switch 15 is used by the output integrating circuit 12c and the directional coupler. The adjustment of the phase rotation of the signal path formed by the high-frequency wave removing filter 14 is easy, and the signal distortion at the antenna switch 15 is also reduced. Further, one end and the other end of the sub-line of the directional coupler (CPL) 13 are respectively connected to the terminal voltage Rt and the detection voltage input terminal of the gain control unit 17 of the RF power amplifier HPA. The gain control unit 17 is supplied with a gain control signal Vramp from the baseband signal processing unit via the RF analog signal processing semiconductor integrated circuit, and a detection voltage from the directionality combiner 13 Vcpl. In addition, the level of the gain control signal Vramp is proportional to the distance between the base station and the mobile phone, and is supplied from the RF power amplifier to the RF transmit signal RFout of the antenna 16 by the gain. The level of the control signal Vr amp is used for control. The gain control unit 17 controls the gain of the RF power amplifier 方式 so that the detection voltage Vcpl from the directional combiner 13 follows the level of the gain control signal Vramp, thereby And perform APC action. The APC is an initial stage amplifier 10s, an initial stage amplifier, which is controlled by a gain control unit 17 and an initial stage amplifier circuit 10b, a second stage bias-65-200835042, and a final stage bias circuit 12b. l 〇 a, the gain control of the final stage amplifier 12a is carried out. (Embodiment 6) <Being an RF Module capable of transmitting in a multi-band domain>

圖20，係爲展示本發明之實施形態6所致的高頻模組 之電路構成的圖。此RF模組，係爲可進行GSM85〇、 GSM900、DCS 1880、PCS1900之多帶域的送訊者。因此’ 第1頻率帶域RF訊號RFin—LB係經由第1RF電力放大 器HPA1而被放大，第2頻率帶域RF訊號RFin 一 HB係經 由第2RF電力放大器HPA2而被放大。第1頻率帶域RF 訊號Rfin__ LB，係爲GSM85 0與GSM900之RF送訊訊號 ，第2頻率帶域RF訊號Rfin—HB，係爲DCS 1 800與 PCS 1 900之RF送訊訊號。 另外，GSM850之RF送訊訊號的頻率係爲824MHz〜 549MHz，GSM900之RF送訊訊號的頻率係爲880MHz〜 915MHz。另外，DCS 1 800之RF送訊訊號的頻率係爲 1710MHz〜1 7 8 0MHz，PCS 1 90 0之RF送訊訊號的頻率係 爲 1 850MHz〜1910MHz。 在圖20之RF模組100中，第1RF電力放大器HPA1 與第2RF電力放大器11?人2，係被形成在半導體積體電路 晶片IC—Chip之上。在晶片ic—Chip之周邊的RF模組 100之配線基板上，係被形成有第1輸出整合電路22c、 -66· 200835042 第1方向性結合器23、第1高頻波除去濾波器24、第2 輸出整合電路12c、第2方向性結合器13、第2高頻波除 去濾波器1 4、天線開關1 5。Fig. 20 is a view showing a circuit configuration of a high frequency module according to a sixth embodiment of the present invention. The RF module is a multi-band transmitter that can perform GSM85〇, GSM900, DCS 1880, and PCS1900. Therefore, the first frequency band RF signal RFin-LB is amplified by the first RF power amplifier HPA1, and the second frequency band RF signal RFin-H is amplified by the second RF power amplifier HPA2. The first frequency band RF signal Rfin__ LB is an RF transmission signal of GSM85 0 and GSM900, and the second frequency band RF signal Rfin-HB is an RF transmission signal of DCS 1 800 and PCS 1 900. In addition, the frequency of the RF transmission signal of the GSM850 is 824MHz~549MHz, and the frequency of the RF transmission signal of the GSM900 is 880MHz~915MHz. In addition, the frequency of the RF transmission signal of the DCS 1 800 is 1710 MHz to 178 MHz, and the frequency of the RF transmission signal of the PCS 1 90 0 is 1 850 MHz to 1910 MHz. In the RF module 100 of Fig. 20, the first RF power amplifier HPA1 and the second RF power amplifier 11A are formed on the semiconductor integrated circuit IC IC-Chip. The first output integrated circuit 22c, -66·200835042, the first directional coupler 23, the first high-frequency wave removing filter 24, and the second are formed on the wiring board of the RF module 100 around the chip ic-Chip. The output integration circuit 12c, the second directional coupler 13, the second high-frequency wave removal filter 14 and the antenna switch 15.

晶片IC— Chip，係實質上具備有4角形之晶片的形狀 。晶片IC— Chip，係具備有相互對向且略平行之第1邊 Sdl與第2邊Sd2。晶片IC—Chip，係更進而具備有：被 連接於第1邊Sdl與第2邊Sd2，且被配置爲和第1邊 Sdl與弟2邊Sd2成略直角之第3邊Sd3，和對向於第3 邊Sd3，而與第3邊略平行之第4邊Sd4。 第1RF電力放大器HPA1之第1輸出放大訊號pout — LB係從晶片IC— Chip之第1邊Sdl而被導出，第2RF電 力放大器HPA2之第2輸出放大訊號P〇ut—HB係從晶片 IC— Chip之第2邊Sd2而被導出。 從第1方向性結合器23之副線路而來的第1檢測訊 號Vcpl— LB，係從晶片IC—Chip之第3邊Sd3，而被導 入至第1RF電力放大器HP A1之第1增益控制單元27的 第1訊號輸入端子。從第2方向性結合器13之副線路而 來的第2檢測訊號Vcpl— HB，係從晶片IC— Chip之第3 邊Sd3 ’而被導入至第2RF電力放大器之第2增益控制單 元17的第2訊號輸入端子。 能夠將第1輸出放大訊號Pout—LB的晶片IC—Chip 之第1邊Sdl的導出點、與第1檢測訊號Vcpl—LB的晶 片IC—Chip之第3邊Sd3的導入點，其兩者間之距離變 大。能夠將第2輸出放大訊號Pout—HB的晶片IC—Chip -67- 200835042 之第2邊Sd2的導出點、與第2檢測訊號Vcpl— HB的晶 片IC—Chip之第3邊Sd3的導入點，其兩者間之距離變 大。故而，能夠將被傳達至增益控制單元2 7、1 7之訊號 輸入端子Vcpl—LB、Vcpl—HB的輸出放大訊號pout— LB 、Pout_ HB之高頻波成分的準位降低。The chip IC-Chip is substantially in the shape of a wafer having a quadrangular shape. The wafer IC-Chip is provided with a first side Sd1 and a second side Sd2 which are opposite to each other and are slightly parallel. The chip IC-Chip further includes a third side Sd3 that is connected to the first side Sd1 and the second side Sd2, and is disposed at a right angle to the first side Sd1 and the second side Sd2, and the opposite direction On the third side Sd3, the fourth side Sd4 is slightly parallel to the third side. The first output amplification signal pout of the first RF power amplifier HPA1 is derived from the first side Sdl of the chip IC-chip, and the second output amplification signal P〇ut-HB of the second RF power amplifier HPA2 is the slave IC. The second side of the chip, Sd2, is derived. The first detection signal Vcpl_LB from the sub-line of the first directional bonder 23 is introduced from the third side Sd3 of the chip IC-Chip to the first gain control unit of the first RF power amplifier HP A1. The first signal input terminal of 27 The second detection signal Vcpl-H from the sub-line of the second directional combiner 13 is introduced from the third side Sd3' of the chip IC-chip to the second gain control unit 17 of the second RF power amplifier. The second signal input terminal. The lead-out point of the first side Sd1 of the wafer IC-Chip of the first output amplification signal Pout-LB and the lead-in point of the third side Sd3 of the wafer IC-Chip of the first detection signal Vcpl-LB can be The distance becomes larger. The lead-out point of the second side Sd2 of the chip IC-Chip-67-200835042 of the second output amplification signal Pout-HB and the lead-in point of the third side Sd3 of the wafer IC-Chip of the second detection signal Vcpl-B can be The distance between the two becomes larger. Therefore, the levels of the high-frequency wave components of the output amplification signals pout_LB and Pout_H transmitted to the signal input terminals Vcpl-LB and Vcpl-HB of the gain control units 27 and 17 can be lowered.

進而，如圖20所示一般，在第1輸出放大訊號pout —LB之第1邊Sdl的導出點、與第1檢測訊號Vcp丨—LB 之第3邊Sd3的導入點之間，係被配置有第2檢測訊號 Vcpl—HB之第3邊Sd3的導入點。同樣的，在第2輸出 放大訊號Pout一 HB之第2邊Sd2的導出點、與第2檢測 訊號Vcpl — HB之弟3邊Sd3的導入點之間，係被配置有 第1檢測訊號Vcpl—LB之第3邊Sd3的導入點。故而， 能夠將被傳達至增益控制單元27、17之訊號輸入端子 Vcpl—LB、Vcpl_HB 的輸出放大訊號 Pout—LB、Pout — HB之高頻波成分的準位更進而降低。Further, as shown in FIG. 20, generally, the derivation point of the first side Sd1 of the first output amplification signal pout_LB and the introduction point of the third side Sd3 of the first detection signal Vcp丨-LB are arranged. There is an introduction point of the third side Sd3 of the second detection signal Vcpl_HB. Similarly, between the derivation point of the second side Sd2 of the second output amplification signal Pout-HB and the introduction point of the third side Sd3 of the second detection signal Vcpl-Hb, the first detection signal Vcpl is disposed. The introduction point of the third side Sd3 of LB. Therefore, the level of the high-frequency wave component of the output amplification signals Pout-LB, Pout-HB transmitted to the signal input terminals Vcpl-LB, Vcpl_HB of the gain control units 27, 17 can be further lowered.

〈晶片周邊之RF模組的配線〉 圖21，係爲展示圖20的高頻模組1〇〇之晶片〗c_ Chip的周邊之配線的模樣之圖。圖21 ( A)係爲展示其模 樣之平面圖，圖21 (B)係爲展示其模樣之立體圖。 如圖21 (A)所不一般’在第1輸出放大訊號Pout — LB之第1邊Sdl的導出點、與第1檢測訊號Vcpl_LB之 第3邊Sd3的導入點之間，被連接於接地電壓GND之第1 接地焊接導線402，係連接於第3邊Sd3。從第1邊Sdl -68- 200835042<Wiring of RF Module Around the Wafer> FIG. 21 is a view showing a pattern of wiring around the wafer c_Chip of the high-frequency module 1 of FIG. Fig. 21 (A) is a plan view showing a pattern thereof, and Fig. 21 (B) is a perspective view showing a pattern thereof. As shown in FIG. 21(A), the derivation point of the first side Sd1 of the first output amplification signal Pout_LB and the lead-in point of the third side Sd3 of the first detection signal Vcpl_LB are connected to the ground voltage. The first grounding bonding wire 402 of GND is connected to the third side Sd3. From the first side Sdl -68- 200835042

之第1輸出放大訊號P〇ut_ LB之導出點起，朝向被連接 於第1增益控制單元27之第1檢測訊號Vcpl_ LB之導入 點的焊接導線401，係存在有以虛線所表示之第1輸出放 大訊號Pont—LB之高頻波結合訊號路徑HD—LB— SP。 第1接地焊接導線402，係能夠將經由結合訊號路徑HD _LB_SP而從第1輸出放大訊號P〇ut_LB之導出點而朝 向第 1檢測訊號 Vcpl _ LB之導入點的訊號串音（ crosstalk)有效的降低。又，在第2輸出放大訊號Pout — HB之第2邊Sd2的導出點、與第2檢測訊號Vcpl— HB之 第3邊Sd3的導入點之間，被連接於接地電壓GND之第2 接地焊接導線404，係連接於第3邊Sd3。從第2邊Sd2 之第2輸出放大訊號P〇ut_ HB之導出點起，朝向被連接 於第2增益控制單元17之第2檢測訊號Vcpl— HB之導入 點的焊接導線405，係存在有以虛線所表示之第2輸出放 大訊號Pout—HB之高頻波結合訊號路徑HD—HB—SP。 第2接地焊接導線404，係能夠將經由結合訊號路徑HD —— sp而從第2輸出放大訊號Pout — HB之導出點而朝 向第 2檢測訊號 Vcpl _HB之導入點的訊號串音（ crosstalk)有效的降低。 另外，在圖21 (A)中，晶片IC—Chip之第3邊的 左側之6個的正方形，係代表被連接於焊接導線400…406 之晶片IC— Chip上的焊接墊片。又，在圖21(A)中， 晶片IC—Chip之第3邊的又側之6個的長方形，係代表 被連接於焊接導線400406之RF模組100之配線基板表面 -69- 200835042 的配線區域。At the lead-out point of the first output amplification signal P〇ut_ LB, the soldering wire 401 that is connected to the lead-in point of the first detection signal Vcpl_ LB connected to the first gain control unit 27 has the first one indicated by a broken line. The high frequency wave of the output amplification signal Pont-LB is combined with the signal path HD-LB-SP. The first ground bonding wire 402 is effective for crosstalk from the lead-out point of the first output amplification signal P〇ut_LB to the lead-in point of the first detection signal Vcpl_LB via the combined signal path HD_LB_SP. reduce. Further, the second ground welding is connected to the ground voltage GND between the derivation point of the second side Sd2 of the second output amplification signal Pout-H and the introduction point of the third side Sd3 of the second detection signal Vcpl-Hb. The wire 404 is connected to the third side Sd3. From the lead-out point of the second output amplification signal P〇ut_ HB of the second side Sd2, the soldering wire 405 is connected to the lead-in point of the second detection signal Vcpl-H connected to the second gain control unit 17 The high frequency wave of the second output amplification signal Pout_HB indicated by the broken line is combined with the signal path HD_HB_SP. The second ground bonding wire 404 is effective for crosstalk from the lead-out point of the second output amplifying signal Pout-HB to the lead-in point of the second detecting signal Vcpl_HB via the combined signal path HD-sp The reduction. Further, in Fig. 21(A), six squares on the left side of the third side of the wafer IC-Chip represent solder pads which are connected to the wafer IC-chip of the bonding wires 400...406. Further, in Fig. 21(A), the six rectangles on the other side of the third side of the wafer IC-Chip represent the wiring of the wiring substrate surface -69-200835042 of the RF module 100 connected to the bonding wire 400406. region.

圖21(B)之立體圖，係立體展示有：第2接地焊接 導線404，係能夠將經由結合訊號路徑HD— HB— SP而從 第2邊Sd2之第2輸出放大訊號pout— HB之導出點而朝 向第3邊Sd3之第2檢測訊號Vcpl— HB之導入點的訊號 串音（crosstalk)有效的降低一事。焊接導線4〇〇…4〇6， 係在晶片1C 一 Chip之4邊的周邊爲較高，而具有較長之 配線距離。被連接於第1增益控制單元27之第1檢測訊 號Vepl一LB的導入點之焊接導線401的左右之接地焊接 導線4 0 0、4 0 2 ’係將有害的訊號串音有效的減低。同樣的 ’被連接於第2增益控制單元1 7之第2檢測訊號Vcpl — HB的導入點之焊接導線405的左右之接地焊接導線404、 4〇6 ’亦係將有害的訊號串音有效的減低。 (實施形態7 ) 〈成爲可進行多帶域之送訊的具體之RF模組〉 圖22，係爲展示本發明之實施形態7所致的具體之 RF模組之電路構成的圖。於圖22中所示之具體的RF模 組，和圖20中所示之RF模組的基本相異之處，係爲天線 開關1 5。 在圖22所示之具體的RF模組中，天線開關1 5，係 實行將 GSM850、GSM900、DCS1800、PCS1900 之多帶域 的 TDMA ( Time Division Multiple Access，時間分割多重 存取）方式之送訊槽（slot )與受訊槽作切換之功能。亦 -70- 200835042 即是，天線開關15，在送訊槽處，係選擇第1RF送訊訊 號Tx—LB與第2RF送訊訊號Tx_HB之任一，並供給至 天線16。第1RF送訊訊號Tx— LB，係爲根據第1RF電力 放大器ΗΡΑ1之第1輸出RF訊號Pout—LB的GSM850、 GSM9 00之RF送訊訊號，第2RF送訊訊號Tx— LH，係爲 根據第2RF電力放大器HPA2之第2輸出RF訊號Pout_ HB 的 DCS1800、PCS1900 之 RF 送訊訊號，Fig. 21(B) is a perspective view showing a second grounding conductor 404 capable of deriving a second output amplification signal pout- HB from the second side Sd2 via the combined signal path HD-HB-SP. The crosstalk of the lead-in point of the second detection signal Vcpl-H toward the third side Sd3 is effectively reduced. The solder wires 4 〇〇 4 〇 6 are higher in the periphery of the four sides of the chip 1C - Chip, and have a longer wiring distance. The left and right ground soldering wires 4 0 0, 4 0 2 ' of the bonding wires 401 connected to the lead-in points of the first detecting signals Vepl-LB of the first gain control unit 27 effectively reduce the harmful signal crosstalk. Similarly, the left and right ground soldering wires 404, 4〇6' of the soldering wire 405 connected to the lead-in point of the second detecting signal Vcpl-Hb of the second gain control unit 17 are also effective for harmful signal crosstalk. reduce. (Embodiment 7) <Specific RF module that can perform multi-band transmission> FIG. 22 is a diagram showing a circuit configuration of a specific RF module according to Embodiment 7 of the present invention. The specific RF module shown in Fig. 22, which is substantially different from the RF module shown in Fig. 20, is the antenna switch 15. In the specific RF module shown in FIG. 22, the antenna switch 15 is configured to transmit a multi-band TDMA (Time Division Multiple Access) method of GSM850, GSM900, DCS1800, and PCS1900. The function of switching between the slot and the receiving slot. Also, the -70-200835042 is that the antenna switch 15 selects either the first RF transmission signal Tx_LB and the second RF transmission signal Tx_HB at the transmission slot and supplies it to the antenna 16. The first RF transmission signal Tx_LB is an RF transmission signal of the GSM850 and GSM9 00 according to the first output RF signal Pout-LB of the first RF power amplifier ΗΡΑ1, and the second RF transmission signal Tx_LH is based on the The RF signal of the DCS1800 and PCS1900 of the 2nd output RF signal Pout_ HB of the 2RF power amplifier HPA2,

又，天線開關1 5，在受訊槽處，係將在天線1 6所受 訊之RF受訊訊號，傳達至第1RF受訊訊號端子Rx_LB 與第2RF送訊訊號端子Rx_LH中之被選擇的訊號端子。 第1RF受訊訊號端子Rx_LB之RF受訊訊號，係爲 GSM85 0、GSM900之RF受訊訊號，第2RF受訊訊號端子 Rx—LH 之 RF 受訊訊號，係爲 DCS 1 800、PCS 1 900 之 RF 受訊訊號。 另外，在圖22所示之具體的RF模組中，於天線開關 15之共通輸入輸出端子處，係被連接有低通濾波器LPF_ ANT與陷波濾波器（trap filter) Trapl2與電容C13與電 感 L13。低通濾波器 LPF__ ANT，係以將 DCS 1 800、 PCS1 900之高帶域的3倍高頻波減衰的方式，而藉由電容 C10、C11、電感L11所構成。陷波濾波器TraP12，係以 將從RF訊號中之較低的頻率起直到直流附近爲止之外部 突波電壓（surge voltage)吸收的方式，而由電容C12、 電感L 1 2所構成。 在天線開關15與第1RF受訊訊號端子Rx_LB之間 -71 - 200835042 ，係被連接有低通濾波器LPF—Rx 一LB。低通濾波器LPF —Rx— LB，係以將GSM850、GSM900之低帶域的3倍高 頻波減衰的方式，而藉由電容。2 0、〇21、〇22、電感1^2 1 所構成。Moreover, the antenna switch 15 transmits the RF signal received by the antenna 16 to the selected one of the first RF signal terminal Rx_LB and the second RF signal terminal Rx_LH at the receiving slot. Signal terminal. The RF signal of the 1RF RF signal terminal Rx_LB is the RF signal of GSM85 0 and GSM900, and the RF signal of the 2RF RF signal terminal Rx-LH is DCS 1 800, PCS 1 900 RF received signal. In addition, in the specific RF module shown in FIG. 22, a low-pass filter LPF_ANT and a trap filter Trapl2 and a capacitor C13 are connected to the common input/output terminal of the antenna switch 15. Inductance L13. The low-pass filter LPF__ ANT is formed by attenuating three times of high-frequency waves of the high band of DCS 1 800 and PCS1 900, and by capacitors C10, C11 and L11. The notch filter TraP12 is composed of a capacitor C12 and an inductor L 1 2 in such a manner as to absorb an external surge voltage from a lower frequency in the RF signal up to the vicinity of the direct current. A low pass filter LPF_Rx_LB is connected between the antenna switch 15 and the first RF received signal terminal Rx_LB -71 - 200835042. The low-pass filter LPF - Rx - LB is a capacitor that reduces the attenuation of the 3 times high frequency of the low band of GSM850 and GSM900. 2 0, 〇21, 〇22, and inductance 1^2 1 are formed.

在天線開關15與第2RF受訊訊號端子Rx—HB之間 ，係被連接有陷波濾波器Trap31。陷波濾波器Trap31， 係以將從RF訊號中之較低的頻率起直到直流附近爲止之 外部突波電壓（surge voltage )吸收的方式，而由電容 C31、電感L31所構成。 〈行動電話〉 圖23，係爲展示搭載有於圖22中所示之RF模組（ 1〇〇)與高頻類比訊號處理半導體積體電路（RF_ 1C)與 基頻帶訊號處理LSI (BB_LSI)的行動電話之構成的區 塊圖。 於同圖所示之RF模組（RF— ML ) 100中，係包含有 :天線開關15、半導體晶片IC— Chip、第1輸出整合電 路22c、第1方向性結合器23、第1高頻波除去濾波器24 、第2輸出整合電路12c、第2方向性結合器13、第2高 頻波除去濾波器1 4。天線開關1 5係藉由類比開關微波單 石半導體積體電路（ANT—SW) 15而構成，半導體晶片 IC— Chip係包含有RF電力放大器HPA1、HPA2。 在行動電話之送收訊用天線ANT 1 6處，係被連接有 RF 模組（RF— ML) 100 之天線開關 MMIC ( ANT SW) -72- 200835042A notch filter Trap31 is connected between the antenna switch 15 and the second RF received signal terminal Rx_HB. The notch filter Trap31 is composed of a capacitor C31 and an inductor L31 in such a manner as to absorb an external surge voltage from a lower frequency of the RF signal to a near DC. <Mobile Phone> FIG. 23 shows an RF module (1〇〇) and a high-frequency analog signal processing semiconductor integrated circuit (RF_1C) and a baseband signal processing LSI (BB_LSI) mounted in FIG. Block diagram of the composition of the mobile phone. The RF module (RF-ML) 100 shown in the same figure includes an antenna switch 15, a semiconductor chip IC-Chip, a first output integration circuit 22c, a first directional coupler 23, and a first high-frequency wave removal. The filter 24, the second output integrating circuit 12c, the second directional coupler 13, and the second high-frequency wave removing filter 14 are provided. The antenna switch 15 is constituted by an analog switch microwave monolithic semiconductor integrated circuit (ANT-SW) 15, and the semiconductor chip IC-chip includes RF power amplifiers HPA1 and HPA2. Antenna switch with RF module (RF-ML) 100 is connected to the antenna ANT 1 6 of the mobile phone. MMIC (ANT SW) -72- 200835042

15的共通之輸入輸出端子I/O。從基頻帶訊號處理LSI (BB_ LSI )而來之控制訊號BB_ Cnt，係經由高頻類比 訊號處理半導體積體電路（RF_IC)(以下，稱爲RFIC )而被供給至RF模組（RF_ML) 100。從送收訊用天線 16而來之對於共通的輸入輸出端子I/O的高頻訊號之流 動，係成爲行動電話之受訊動作RX，從共通的輸入輸出 端子1/ 0對於送收訊用天線1 6的高頻訊號之流動，係成 爲行動電話之送訊動作TX。 RFIC ( RF_IC)，係進行對從基頻帶訊號處理LSI ( BB_LSI)而來之送訊基頻帶訊號Tx_BBS的高頻送訊訊 號之頻率增頻轉換（up conversion )。又，RFIC ( RF — 1C )，係相反地進行對在送收訊用天線ANT所收訊之高頻 受訊訊號的受訊基頻帶訊號Rx_BBS之頻率減頻轉換（ downconversion )。受訊基頻帶訊號Rx — BB，係被供給 至基頻帶訊號處理LSI ( BB_LSI)處。 RF模組（RF+ ML) 100之天線開關MMIC ( ANT — SW) 15，係在共通之輸入輸出端子I/O，與送訊端子 Txl、Tx2、受訊端子1^1、1^2之任一者的端子之間確立 訊號路徑，並進行受訊動作RX與送訊動作ΤΧ之任一者 。此天線開關MMIC ( ANT— SW) 15，係藉由將除了用以 進行受訊動作RX與送訊動作TX之任一者而確立的訊號 路徑以外之訊號路徑的阻抗設定爲極高之値，而得到必要 之隔離（Isolation)者。 另外，基頻帶訊號處理LSI(BB_LSI)，係被連接 -73- 200835042 於未圖示之外部不揮發性記憶體與未圖示之應用程式處理 器。應用程式處理器，係被連接於未圖示之液晶顯示裝置 與未圖示之按鍵輸入裝置，而能夠實行包含有汎用程式或 遊戲等之各種的應用程式。行動電話等之攜帶機器的啓動 程式（啓動起始程式）、作業系統程式（OS)、基頻帶訊 號處理LSI之內部的數位訊號處理器（DSP)所致的用以15 common input and output terminal I / O. The control signal BB_Cnt from the baseband signal processing LSI (BB_LSI) is supplied to the RF module (RF_ML) 100 via the high frequency analog signal processing semiconductor integrated circuit (RF_IC) (hereinafter referred to as RFIC). . The flow of the high-frequency signal from the transmitting and receiving antenna 16 to the common input/output terminal I/O is the receiving operation RX of the mobile phone, and the common input/output terminal 1/0 is used for the receiving and receiving. The flow of the high frequency signal of the antenna 16 is the transmission action TX of the mobile phone. The RFIC (RF_IC) is an up-conversion of the high-frequency transmission signal of the transmission baseband signal Tx_BBS from the baseband signal processing LSI (BB_LSI). Further, the RFIC (RF-1C) reversely performs frequency downconversion of the received baseband signal Rx_BBS of the high frequency received signal received by the transmitting and receiving antenna ANT. The received baseband signal Rx - BB is supplied to the baseband signal processing LSI (BB_LSI). RF module (RF+ ML) 100 antenna switch MMIC (ANT - SW) 15, is in the common input and output terminal I / O, and the communication terminals Txl, Tx2, the receiving terminal 1 ^ 1, 1 ^ 2 A signal path is established between the terminals of one of the terminals, and either the receiving operation RX and the transmitting operation are performed. The antenna switch MMIC (ANT-SW) 15 sets the impedance of the signal path other than the signal path established by either of the receiving operation RX and the transmitting operation TX to be extremely high. And get the necessary isolation (Isolation). Further, the baseband signal processing LSI (BB_LSI) is connected to an external non-volatile memory (not shown) and an application processor (not shown) from -73 to 200835042. The application processor is connected to a liquid crystal display device (not shown) and a key input device (not shown), and can execute various applications including a general-purpose program or a game. Used by the mobile device's boot program (startup program), operating system program (OS), and digital signal processor (DSP) inside the baseband signal processing LSI.

進行相關於GSM方式等之受訊基頻帶訊號的相位解調與 用以進行相關於送訊基頻帶訊號之相位調變的程式、各種 之應用程式，係可儲存在外部不揮發性記憶體中。 設想應將從基頻帶訊號處理L SI ( B B _ L SI )而來之 送訊基頻帶訊號Tx—BBS頻率增頻變換爲GSM85 0又或 是GSM800之送訊頻率帶的情況。另外，GSM850之RF 送訊訊號的頻率係爲824MHz〜849MHz，GSM900之RF 送訊訊號的頻率係爲 880MHz〜915MHz。在此情況中， RFIC之送訊訊號處理單元Tx_SPU係從送訊基頻帶訊號 Tx_ BBS而進行對此送訊頻率帶之頻率增頻變換，並產生 高頻送訊訊號RF_ Txl。此送訊頻率帶之高頻送訊訊號 RF— Txl，係藉由RF模組RF_ ML之1^高輸出電力放大 器HPA1而被電力放大，並經由低通濾波器12c而被供給 至天線開關MMIC ( ANT— SW) 15的送訊端子Txl。被供 給至送訊端子Txl之GSM850又或是GSM900的高頻送訊 訊號RF—Txl，係可經由共通之輸入輸出端子I/O，而從 送受訊天線（ANT) 16而被送訊。 藉由送受訊用天線（ANT) 16所受訊之GSM8 5 0又或 -74- 200835042Phase demodulation related to the received baseband signal of the GSM system and the like, and a program for performing phase modulation related to the transmission baseband signal, and various applications can be stored in the external non-volatile memory. . It is assumed that the transmission baseband signal Tx-BBS frequency is up-converted from the baseband signal processing L SI (B B _ L SI ) to the GSM 85 0 or the GSM 800 transmission frequency band. In addition, the frequency of the RF transmission signal of the GSM850 is 824MHz~849MHz, and the frequency of the RF transmission signal of the GSM900 is 880MHz~915MHz. In this case, the RFIC signal processing unit Tx_SPU performs frequency up-conversion on the transmission frequency band from the transmission baseband signal Tx_BBS, and generates a high frequency transmission signal RF_Txl. The high frequency transmission signal RF_Txl of the transmission frequency band is amplified by the RF module RF_ML 1^ high output power amplifier HPA1, and is supplied to the antenna switch MMIC via the low pass filter 12c. (ANT-SW) 15's transmission terminal Txl. The GSM850 supplied to the transmission terminal Txl or the GSM900 high-frequency transmission signal RF-Txl can be transmitted from the transmitting and receiving antenna (ANT) 16 via the common input/output terminal I/O. GSM8 5 0 or -74- 200835042 received by the transmitting and receiving antenna (ANT) 16

是GSM900的高頻受訊訊號RF—Rxl，係被供給至天線開 關MMIC ( ANT—SW) 15之共通的輸入輸出端子I/O。 另外，GSM850之RF受訊訊號的頻率係爲 869MHz〜 894MHz，GSM900之RF受訊訊號的頻率係爲925MHz〜 9 60MHz。從天線開關15之受訊端子Rxl所得到之此受訊 頻率帶之高頻受訊訊號RF_ Rxl，係經由表面彈性波濾波 器SAW1，而藉由RFIC之低雜音放大器LNA1而放大，而 後，被供給至受訊訊號處理單元Rx_SPU。在受訊訊號處 理單元RX_SPU中，係進行對從GSM之高頻受訊訊號 GSM_Rx所受訊之基頻帶訊號Rx_BBS的頻率減頻變換 在GSM8 5 0又或是GSM900之送受訊模式中，天線開 關1 5係對控制訊號BB_ Cut作回應，而將以共通之輸入 輸出端子I/ O與送訊端子Txl之連接所致的高頻送訊訊 號RF—Txl之送訊，與以共通之輸入輸出端子1/Ο與受 訊端子Rxl之連接所致的高頻受訊訊號RF—Rxl之受訊 ，以時間分割來進行。 設想應將從基頻帶訊號處理LSI ( BB— LSI )而來之 送訊基頻帶訊號Tx—BBS頻率增頻變換爲DCS 1 800又或 是PCS 1 900之送訊頻率帶的情況。另外，DCS 1 800之RF 送訊訊號的頻率係爲1710MHz〜1 7 80MHz，PCS 1 900之 RF送訊訊號的頻率係爲1 8 50MHz〜1910MHz。在此情況 中，RFIC之送訊訊號處理單元Tx— SPU係從送訊基頻帶 訊號Tx_ BBS而進行對此送訊頻率帶之頻率增頻變換， -75- 200835042 並產生此送訊頻率帶之高頻送訊訊號RF— Τχ2。此送訊頻 率帶之高頻送訊訊號RF— Τχ2，係藉由RF模組100之RF 高輸出電力放大器HP Α2而被電力放大，並經由低通濾波 器22c而被供給至天線開關15的送訊端子Tx2。被供給 至送訊端子Τχ2之DCS 1 800又或是PCS 1 900的高頻送訊 訊號RF— Τχ2，係可經由共通之輸入輸出端子〇，而從 送受訊天線（ANT) 16而被送訊。It is the GSM900 high-frequency receiving signal RF-Rxl, which is supplied to the common input/output terminal I/O of the antenna switch MMIC (ANT-SW) 15. In addition, the frequency of the RF signal of the GSM850 is 869MHz~894MHz, and the frequency of the RF signal of the GSM900 is 925MHz~960MHz. The high frequency received signal RF_Rxl of the received frequency band obtained from the received terminal Rx1 of the antenna switch 15 is amplified by the surface acoustic wave filter SAW1 and amplified by the low noise amplifier LNA1 of the RFIC, and then It is supplied to the received signal processing unit Rx_SPU. In the received signal processing unit RX_SPU, the frequency reduction signal of the baseband signal Rx_BBS received from the GSM high frequency received signal GSM_Rx is performed in the transmission mode of the GSM800 or GSM900, and the antenna switch The 1 5 series responds to the control signal BB_ Cut, and transmits the high frequency transmission signal RF-Tx1 caused by the connection of the common input/output terminal I/O and the transmission terminal Txl, and the common input and output. The high frequency received signal RF_Rxl caused by the connection of the terminal 1/Ο to the received terminal Rx1 is subjected to time division. It is assumed that the transmission baseband signal Tx-BBS frequency is up-converted from the baseband signal processing LSI (BB-LSI) to the DCS 1 800 or the transmission frequency band of the PCS 1 900. In addition, the frequency of the RF transmission signal of the DCS 1 800 is 1710 MHz to 1 7 80 MHz, and the frequency of the RF transmission signal of the PCS 1 900 is 1 8 50 MHz to 1910 MHz. In this case, the RFIC signal processing unit Tx_SPU performs frequency up-conversion on the transmission frequency band from the transmission baseband signal Tx_BBS, and generates the transmission frequency band. High frequency transmission signal RF - Τχ 2. The high frequency transmission signal RF_Τχ2 of the transmission frequency band is electrically amplified by the RF high output power amplifier HP Α2 of the RF module 100, and is supplied to the antenna switch 15 via the low pass filter 22c. Sending terminal Tx2. The DCS 1 800 supplied to the transmitting terminal Τχ2 or the high-frequency transmitting signal RF-Τχ2 of the PCS 1 900 can be transmitted from the transmitting and receiving antenna (ANT) 16 via the common input/output terminal 〇. .

藉由送受訊用天線（ANT) 16所受訊之DCS1 80 0又 或是PCS 1 900的高頻受訊訊號RF— Rx2，係被供給至天線 開關15之共通的輸入輸出端子I/O。另外，DCS1 800之 RF受訊訊號的頻率係爲1805MHz〜180MHz，PCS1900之 RF受訊訊號的頻率係爲1 93 0MHz〜1 990MHz。從天線開 關15之受訊端子Rx2所得到之DCS1800又或是PCS1900 之高頻受訊訊號RF _ Rx2，係經由表面彈性波濾波器 SAW2，而藉由RFIC之低雜音放大器LNA2而放大，而後 ，被供給至受訊訊號處理單元Rx_ SPU。在受訊訊號處理 單元Rx— SPU中，係進行對從DCS 1 800又或是PCS1900 之高頻受訊訊號RF—Rx2所受訊之基頻帶訊號Rx—BBS 的頻率減頻變換。 在DC S 1800又或是PCS 1900之送受訊模式中，天線 開關1 5係對控制訊號BB一 Cut作回應’而將以共通之輸 入輸出端子1/ Ο與送訊端子Tx2之連接所致的局頻迭訊 訊號RF— Τχ2之送訊，與以共通之輸入輸出端子1/〇與 受訊端子Rx2之連接所致的高頻受訊訊號RF—Rx2之受 -76- 200835042 訊，以時間分割來進行。 〈天線開關MMIC &gt; 圖24，係爲展示構成圖22中所示之RF模組的天線 開關15之天線開關微波單石半導體積體電路（MMIC ) 3 00之電路圖。The DCS1 80 0 received by the transmitting antenna (ANT) 16 or the high frequency received signal RF_Rx2 of the PCS 1 900 is supplied to the common input/output terminal I/O of the antenna switch 15. In addition, the frequency of the RF signal of the DCS1 800 is 1805MHz~180MHz, and the frequency of the RF signal of the PCS1900 is 1930-1MHz~1 990MHz. The DCS1800 obtained from the receiving terminal Rx2 of the antenna switch 15 or the high frequency receiving signal RF_Rx2 of the PCS1900 is amplified by the surface acoustic wave filter SAW2 and by the low noise amplifier LNA2 of the RFIC, and then It is supplied to the received signal processing unit Rx_SPU. In the received signal processing unit Rx_SPU, frequency down conversion of the baseband signal Rx_BBS received from the high frequency received signal RF_Rx2 of the DCS 1 800 or the PCS1900 is performed. In the DC S 1800 or PCS 1900 transmission and reception mode, the antenna switch 15 responds to the control signal BB_Cut, and the common input/output terminal 1/Ο is connected with the transmission terminal Tx2. The transmission of the local frequency superimposed signal RF-Τχ2, and the high-frequency receiving signal RF-Rx2 caused by the connection of the common input/output terminal 1/〇 and the receiving terminal Rx2 are received by -76-200835042 Split to proceed. <Antenna Switch MMIC> Fig. 24 is a circuit diagram showing an antenna switch microwave single crystal semiconductor integrated circuit (MMIC) 300 which constitutes the antenna switch 15 of the RF module shown in Fig. 22.

於圖24中所示之天線開關MMIC ( 300 )，係在共通 之輸入輸出端子1/0(301)，與送訊端子Txl (306)、 Tx2 ( 307 )、受訊端子 Rxl ( 308 ) 、Rx2 ( 309 ) 、Rx3 ( 3 08’）、Rx4 ( 309，）之任一者的端子之間確立訊號路徑 ，並進行受訊動作RX與送訊動作TX之任一者。此天線 開關MMIC ( 3 00 )，係藉由將除了用以進行受訊動作RX 與送訊動作TX之任一者而確立的訊號路徑以外之訊號路 徑的阻抗設定爲極高之値，而得到必要之隔離（Isolation )者。在天線開關之領域中，共通之輸入輸出端子1/ 〇 (301)，係被稱爲單極（single pole)。又，送訊端子 Txl ( 3 06 ) &gt; Tx2 ( 3 07 )、受訊端子 Rxl ( 3 08 ) 、Rx2 ( 3 09 ) 、Rx3 ( 3 08,）、Rx4 ( 3 09’）之合計 6 個的端子， 係被稱爲6攤（6'throw )。故而’圖23之天線開關 MMIC ( 300 )，係爲單極 6 擲（SP6T ; Single Pole 6 throw )型之開關。 天線開關MMIC (300)，係包含有6個的高頻開關 302 、 303 、 304 、 305 、 304， 、 305 第1送訊開關302，係藉由被連接在共通之輸入輸出 -77- 200835042 端子1/ 〇 ( 301 )與第1送訊端子Txl ( 306 )之間，而確 立從第1送訊端子Txl (3 06 )起至共通之輸入輸出端子I /0( 301)的第1送訊訊號之路徑。第2送訊開關303, 係藉由被連接在共通之輸入輸出端子1/0(301)與第2 送訊端子Tx2 ( 307 )之間，而確立從第2送訊端子Tx2 ( 307 )起至共通之輸入輸出端子1/0(301)的第2送訊 訊號之路徑。The antenna switch MMIC (300) shown in FIG. 24 is connected to the common input/output terminal 1/0 (301), and the transmission terminals Tx1 (306), Tx2 (307), and the received terminal Rxl (308). A signal path is established between the terminals of any of Rx2 (309), Rx3 (3 08'), and Rx4 (309,), and either the received operation RX and the transmission operation TX are performed. The antenna switch MMIC (300) is obtained by setting the impedance of the signal path other than the signal path established by either of the receiving operation RX and the transmitting operation TX to be extremely high. Necessary isolation (Isolation). In the field of antenna switches, the common input/output terminal 1/〇 (301) is called a single pole. In addition, the total of 6 transmission terminals Txl ( 3 06 ) &gt; Tx2 ( 3 07 ), the received terminals Rxl ( 3 08 ) , Rx2 ( 3 09 ) , Rx3 ( 3 08 , ) and Rx4 ( 3 09 ') The terminal is called 6 stall (6'throw). Therefore, the antenna switch MMIC (300) of Figure 23 is a single-pole 6-throw (SP6T; Single Pole 6 throw) type switch. The antenna switch MMIC (300) includes six high frequency switches 302, 303, 304, 305, 304, and 305. The first transmission switch 302 is connected to the common input and output -77-200835042 terminal. 1/ 〇 ( 301 ) and the first transmission terminal Txl ( 306 ), and the first transmission from the first transmission terminal Txl (3 06 ) to the common input/output terminal I / 0 ( 301 ) is established. The path of the signal. The second transmission switch 303 is established from the second transmission terminal Tx2 ( 307 ) by being connected between the common input/output terminal 1/0 (301) and the second transmission terminal Tx2 ( 307 ). The path of the second transmission signal to the common input/output terminal 1/0 (301).

第1受訊開關304，係藉由被連接在共通之輸入輸出 端子1/ Ο ( 301 )與第1受訊端子Rxl ( 308 )之間，而確 立從共通之輸入輸出端子1/0(301)起至第1受訊端子 Rxl ( 3 08 )的第1受訊訊號之路徑。第2受訊開關305， 係藉由被連接在共通之輸入輸出端子1/0(301)與第2 受訊端子Rx2 ( 309 )之間，而確立從共通之輸入輸出端 子I/O ( 301)起至第2受訊端子Rx2 ( 3 09 )的第2受訊 訊號之路徑。第3受訊開關304’，係藉由被連接在共通之 輸入輸出端子1/0(301)與第3受訊端子Rxl (308’） 之間，而確立從共通之輸入輸出端子I/O (301)起至第 3受訊端子Rxl ( 3 08’）的第3受訊訊號之路徑。第4受 訊開關305’，係藉由被連接在共通之輸入輸出端子1/ Ο (301 )與第4受訊端子Rx2 ( 3 09’）之間，而確立從共通 之輸入輸出端子1/ 〇 ( 301 )起至第4受訊端子Rx2 ( 3 09’）的第4受訊訊號之路徑。 又，在圖24中，身爲SP6T型開關之天線開關，由於 係並聯連接有第1受訊開關3 04與第3受訊開關3 04’，且 -78- 200835042 並聯連接有第2受訊開關305與第4受訊開關305’，因此 ，SP6T型開關，實質上係成爲SP4T開關。藉由開關之並 聯連接，成爲能夠減輕在受訊模式下之訊號損失。 另外，作爲構成6個的高頻開關302、303、3 04、305 、304，、305’之高頻開關 Qtxl、Qtx2、Qrxl、Qrx2、Qrx3 、Qrx4，係被使用有具備低導通電阻之異質接合構造的 HEMT ( High Electron Mobility Transistor)The first receiving switch 304 is connected between the common input/output terminal 1/Ο (301) and the first receiving terminal Rx1 (308) to establish a common input/output terminal 1/0 (301). The path from the first received signal to the first received terminal Rxl (3 08). The second receiving switch 305 establishes a common input/output terminal I/O by being connected between the common input/output terminal 1/0 (301) and the second receiving terminal Rx2 (309) (301). ) The path from the second received signal to the second received terminal Rx2 ( 3 09 ). The third receiving switch 304' establishes a common input/output terminal I/O by being connected between the common input/output terminal 1/0 (301) and the third receiving terminal Rx1 (308'). (301) The path of the third received signal from the third received terminal Rxl (3 08'). The fourth receiving switch 305' is established between the common input/output terminal 1/Ο (301) and the fourth receiving terminal Rx2 (3 09') to establish a common input/output terminal 1/1. The path of the fourth received signal from 〇 ( 301 ) to the fourth received terminal Rx2 ( 3 09 '). Further, in Fig. 24, the antenna switch of the SP6T type switch has the first receiving switch 3 04 and the third receiving switch 3 04' connected in parallel, and the -78-200835042 is connected in parallel with the second receiving signal. Since the switch 305 and the fourth receiving switch 305', the SP6T type switch is substantially an SP4T switch. By the parallel connection of the switches, it is possible to reduce the signal loss in the received mode. In addition, as the high-frequency switches Qtxl, Qtx2, Qrxl, Qrx2, Qrx3, and Qrx4 constituting the six high-frequency switches 302, 303, 3, 04, 305, 304, and 305', heterogeneity with low on-resistance is used. HEMT (High Electron Mobility Transistor)

進而，第1送訊開關3 02，係包含有第1DC升壓（ boost )電路DC— BC1，第2送訊開關3 03係包含有第 2DC 升壓（boost)電路 DC—BC1。 第1送訊開關302之第1DC升壓電路DC—BC1，係 對從第1RF電力放大器HPA1而供給至送訊端子Txl ( 306)之高準位的第1RF送訊訊號作回應，而將被供給至 第1送訊控制端子3 1 0之約3伏特的DC控制電壓升壓。 藉由升壓，從第1DC升壓電路DC_BC1所產生之約5伏 特的高準位之升壓輸出電壓，係被供給至第1送訊開關 302之FETQtxl之閘極。 其結果，能夠顯著地將第1送訊開關302之FETQtxl 的導通電阻Ron減低，而成爲能夠減低在送訊動作時之 RF送訊訊號的訊號損失。又，經由約5伏特之高準位的 升壓輸出電壓，共通之輸入輸出端子1/0(301)的電壓 ，亦成爲約4伏特之高準位。其他之開關3 03、3 04、305 、3 04，、3 05 ’ 之 FETQtx2、Qrx 1、Qrx2、Qrx3、Qrx4 之閘 極，係成爲約0伏特之低電壓。此些之FETQtx2、Qrxl、 -79- 200835042Further, the first transmission switch 312 includes a first DC boosting circuit DC-BC1, and the second transmitting switch 303 includes a second DC boosting circuit DC_BC1. The first DC boosting circuit DC_BC1 of the first transmitting switch 302 responds to the first RF transmitting signal supplied from the first RF power amplifier HPA1 to the high level of the transmitting terminal Tx1 (306), and will be The DC control voltage supplied to the first transmission control terminal 3 10 is boosted by about 3 volts. By boosting, the boost output voltage of the high level of about 5 volts generated from the first DC boost circuit DC_BC1 is supplied to the gate of the FET Qtx1 of the first transfer switch 302. As a result, the on-resistance Ron of the FET Qtx1 of the first transmission switch 302 can be remarkably reduced, and the signal loss of the RF transmission signal at the time of the transmission operation can be reduced. Further, the voltage of the input/output terminal 1/0 (301) which is common through the boost output voltage of the high level of about 5 volts also becomes a high level of about 4 volts. The gates of FETs Qtx2, Qrx 1, Qrx2, Qrx3, and Qrx4 of the other switches 3 03, 3 04, 305, 3 04, and 3 05 ' are low voltages of about 0 volts. FETQtx2, Qrxl, -79- 200835042

Qrx2、QrX3、Qrx4之閘極*源極間電容，係成爲極小之 値，而成爲能夠顯著的減低天線開關MMIC ( 3 00 )之高頻 波歪曲。The gate-to-source capacitance of Qrx2, QrX3, and Qrx4 is extremely small, and it can significantly reduce the high-frequency distortion of the antenna switch MMIC (300).

第2送訊開關303之第2DC升壓電路DC— BC2，係 對從第2RF電力放大器HPA2而供給至送訊端子Tx2( 3〇7)之高準位的第2RF送訊訊號作回應，而將被供給至 第2送訊控制端子311之約3伏特的DC控制電壓升壓。 藉由升壓，從第2D C升壓電路DC— BC2所產生之約5伏 特的高準位之升壓輸出電壓，係被供給至第2送訊開關 303之FETQtx2之閘極。 其結果，能夠顯著地將第2送訊開關3 03之FETQtx2 的導通電阻Ron減低，而成爲能夠減低在送訊動作時之 RF送訊訊號的訊號損失。又，經由約5伏特之高準位的 升壓輸出電壓，共通之輸入輸出端子1/0(301)的電壓 ，亦成爲約4伏特之高準位。其他之開關302、304、305 、304，、305,之 FETQtxl、Qrxl、Qrx2、Qrx3、Qrx4 之閘 極，係成爲約〇伏特之低電壓。此些之FETQtxl、Qrxl、 Qrx2、Qrx3、Qrx4之閘極•源極間電容，係成爲極小之 値，而成爲能夠顯著的減低天線開關MMIC ( 3 00 )之高頻 波歪曲。 以上，雖係將藉由本發明者所進行之發明，根據實施 形態而作了具體說明，但是，本發明係並不被此所限定者 ，不用說，在不脫離其要旨的範圍內，可作各種之變更。 例如，構成第1、第2RF電力放大器HPA1、HPA2之 -80- 200835042 初段放大器l〇a、20a ;次段放大器1 la、21a ;最終段放 大器12a、22a的功率電晶體，係並非被限定爲LD構造之 矽功率MOSFET者。亦可將此功率電晶體，置換爲GaAs 或InP等之化合物半導體的MESFETHEMT之N通道的場 效電晶體，進而，亦可將其置換爲使用有GaAs、InGaAs 或是矽•鍺的NPN型HBT (異質雙極電晶體）。The second DC boosting circuit DC_BC2 of the second transmission switch 303 responds to the second RF transmission signal supplied from the second RF power amplifier HPA2 to the high level of the transmission terminal Tx2 (3〇7). The DC control voltage of about 3 volts supplied to the second transmission control terminal 311 is boosted. The boost output voltage of the high level of about 5 volts generated from the second DC boost circuit DC-BC2 is supplied to the gate of the FET Qtx2 of the second transfer switch 303 by boosting. As a result, the on-resistance Ron of the FET Qtx2 of the second transmission switch 303 can be remarkably reduced, and the signal loss of the RF transmission signal during the transmission operation can be reduced. Further, the voltage of the input/output terminal 1/0 (301) which is common through the boost output voltage of the high level of about 5 volts also becomes a high level of about 4 volts. The gates of the other switches 302, 304, 305, 304, and 305, FETQtxl, Qrxl, Qrx2, Qrx3, and Qrx4 are low voltages of about volts. The gate-source capacitance of these FETQtxl, Qrxl, Qrx2, Qrx3, and Qrx4 is extremely small, and the high-frequency distortion of the antenna switch MMIC (300) can be significantly reduced. The present invention has been described in detail with reference to the embodiments of the present invention. However, the present invention is not limited thereto, and it is needless to say that it can be made without departing from the gist of the invention. Various changes. For example, the -80-200835042 primary amplifiers l〇a, 20a constituting the first and second RF power amplifiers HPA1, HPA2; the secondary amplifiers 1a, 21a; and the power transistors of the final stage amplifiers 12a, 22a are not limited to LD Power MOSFET for LD construction. Alternatively, the power transistor may be replaced by a N-channel field effect transistor of MESFETHEMT of a compound semiconductor such as GaAs or InP, or may be replaced by an NPN type HBT using GaAs, InGaAs or 矽•锗. (Heteromorphic bipolar transistor).

又，輸出整合電路12c、22c之微波傳送線TRL1、 TRL2、TRL3 ;電容 Cl、C2、C3 ;電感 LI、L2、L3 等， 係並非被限定爲R F模組內之分立被動元件。此些之構件 ，係可積體在GaAs半導體基板、玻璃絕緣基板、低溫燒 成陶瓷絕緣基板、環氧絕緣基板等之上。亦即是，係可利 用將電容或電感積體在絕緣基板等上後之積體被動元件（Further, the microwave transfer lines TRL1, TRL2, and TRL3 of the output integration circuits 12c and 22c; the capacitors Cl, C2, and C3; and the inductances LI, L2, and L3 are not limited to the discrete passive elements in the R F module. Such members are based on a GaAs semiconductor substrate, a glass insulating substrate, a low-temperature fired ceramic insulating substrate, an epoxy insulating substrate, or the like. In other words, it is possible to use an integrated passive component in which a capacitor or an inductor is integrated on an insulating substrate or the like (

Integrated Passive Device ) ° 又，在圖24之天線開關MMIC ( 3 00 )的高頻開關處 ，係可將 FETQtxl、Qtx2、Qrxl、Qrx2、Qrx3、Qrx4，從 HEMT電晶體而置換爲N通道之降壓（depression)型的 絕緣閘極MOS電晶體。另外，此時，在共通之輸入輸出 端子1/ 〇處’係被供給有約4伏特之偏壓電壓。當行動 電話之系統係使用有約3伏特之單一電源電壓的情況時， 在圖24之天線開關MMIC ( 300 )之內部，係包含有將3 伏特之單一電源電壓升壓爲約4伏特之偏壓電壓的電荷泵 電路等之升壓電路。 進而，在圖20或圖22之RF模組100中，可將第1 方向性結合器23與第2方向性結合器13分別置換爲微耦 -81 - 200835042 合器。所謂微耦合器，係爲在主線路與副線路之間被連接 有電容元件者。在微耦合器中，由於在通常之電磁結合中 ’係被附加有經由電容元件而得的主線路與副線路之間之 電容結合’因此，成爲能夠將主線路與副線路之配線距離 設爲較通常之1/4波長（λ/4)爲更短。其結果，藉由 將將第1方向性結合器23與第2方向性結合器13置換爲 微耦合器。可將圖20或圖22之RF模組100小型化。Integrated Passive Device ) ° Also, at the high frequency switch of the antenna switch MMIC (300) of Figure 24, FETQtxl, Qtx2, Qrxl, Qrx2, Qrx3, Qrx4 can be replaced from the HEMT transistor to the N channel. Depression type insulated gate MOS transistor. Further, at this time, a bias voltage of about 4 volts is supplied to the common input/output terminal 1/〇. When the mobile phone system uses a single supply voltage of approximately 3 volts, the antenna switch MMIC (300) of Figure 24 contains a bias of boosting a single supply voltage of 3 volts to approximately 4 volts. A booster circuit such as a voltage-charged charge pump circuit. Further, in the RF module 100 of Fig. 20 or Fig. 22, the first directional coupler 23 and the second directional coupler 13 can be replaced with the microcoupler -81 - 200835042. The micro coupler is a capacitor element that is connected between the main line and the sub line. In the micro-coupler, since the capacitance is coupled between the main line and the sub-line via the capacitive element in the normal electromagnetic coupling, the wiring distance between the main line and the sub-line can be set to It is shorter than the usual 1/4 wavelength (λ/4). As a result, the first directional coupler 23 and the second directional coupler 13 are replaced with a micro coupler. The RF module 100 of FIG. 20 or FIG. 22 can be miniaturized.

[產業上之利用可能性] 本發明之其中一實施形態所致的電子裝置以及高頻模 組，係特別是適用在被使用於行動電話等之中的對應於多 帶域之高頻電力放大器，而爲有益之技術，且，不僅於此 ，例如亦可廣泛適用在包括各種共振器或是包含有其之無 線通訊機器等之各種的機器中。 【圖式簡單說明】 [圖1]在本發明之實施形態1所致的高頻模組中，展 示其構成的一例之區瑰圖。 [圖2]在本發明之實施形態1的共振電路中，展示其 構成例者，（a )係爲立體圖，（b )係爲展示（a )之各 層的平面圖。 [圖3]對本發明之實施形態1的共振電路作說明者， (a)係爲圖2之簡易的等價電路圖，（b)係爲成爲其之 比較例的一般螺旋電感之簡易的等價電路圖。 -82- 200835042 [圖4]展示將圖2之主要部透視性地觀察的情況時之 構成例的立體圖。 [圖5]在本發明之實施形態2的共振電路中，展示其 構成例者，（a )係爲立體圖，（b )係爲展示（a )之各 層的平面圖。 [圖6]圖5之並聯共振電路之簡易的等價電路圖。[Industrial Applicability] The electronic device and the high-frequency module according to one embodiment of the present invention are particularly applicable to a high-frequency power amplifier corresponding to a multi-band domain used in a mobile phone or the like. In addition, for example, it can be widely applied to various types of machines including various resonators or wireless communication devices including the same. [Brief Description of the Drawings] [Fig. 1] A high-frequency module according to the first embodiment of the present invention is shown as an example of a configuration of the configuration. [Fig. 2] In the resonant circuit according to the first embodiment of the present invention, (a) is a perspective view, and (b) is a plan view showing each layer of (a). [Fig. 3] A resonant circuit of the first embodiment of the present invention is described. (a) is a simple equivalent circuit diagram of Fig. 2, and (b) is a simple equivalent of a general spiral inductor which is a comparative example thereof. Circuit diagram. -82- 200835042 [Fig. 4] A perspective view showing a configuration example in a case where the main portion of Fig. 2 is seen in a perspective view. In the resonance circuit according to the second embodiment of the present invention, (a) is a perspective view, and (b) is a plan view showing each layer of (a). Fig. 6 is a simplified equivalent circuit diagram of the parallel resonant circuit of Fig. 5.

[圖7]對本發明之實施形態2的共振電路作說明者， 圖7 ( a )，係爲展示將圖5之主要部透視性地觀察的情況 時之構成例的立體圖，圖7(b)，係爲展示成爲其之比較 例的構成之立體圖。 [圖8 ]在本發明之實施形態3所致的高頻模組中，展 示其構成例之電路圖。 [圖9]在作爲本發明之前提而被檢討之高頻模組中， 展示其功率放大電路周圍之構成例的電路圖。 [圖10]在本發明之實施形態4所致的高頻模組中，展 示其功率放大電路周邊的構成例之電路圖。 [圖1 1 ]在本發明之實施形態4所致的高頻模組中，展 示其功率放大電路周邊之配線基板的構成例者，（a )係 作爲比較對象，而爲對應於圖9之構成的佈線圖，（b ) 係爲對應於圖1 0之構成的配線圖。 [圖12]在本發明之實施形態4所致的高頻模組中，展 示對應於圖10之構成的配線基板之構成例者’ （a)係爲 將配線基板全體作透視時的立體圖，（b )係爲將其之功 率放大電路周邊作擴大的立體圖，（c )係爲從（b )而將 -83- 200835042 第1配線層省略後之立體圖。 [圖13]對圖9之構成（比較例）與圖10之構成之回 歸增益（return gain )値作評價後之結果，（a )係爲展示 圖9之構成的結果之圖表，（b)係爲展示圖10之構成的 結果之圖表。 [圖14]對圖9之構成（比較例）與圖10之構成進行 了電流密度之解析後的結果。Fig. 7 is a perspective view showing a configuration of a resonance circuit according to a second embodiment of the present invention, and Fig. 7(a) is a perspective view showing a configuration example in which the main portion of Fig. 5 is seen in a perspective view, and Fig. 7(b) It is a perspective view showing the constitution of a comparative example. [Fig. 8] A circuit diagram showing a configuration example of the high frequency module according to the third embodiment of the present invention. [Fig. 9] A circuit diagram showing a configuration example around a power amplifying circuit in a high frequency module which has been reviewed before the present invention. [Fig. 10] A circuit diagram showing a configuration example of the periphery of the power amplifying circuit in the high frequency module according to the fourth embodiment of the present invention. [Fig. 1] In the high-frequency module according to the fourth embodiment of the present invention, a configuration example of the wiring board around the power amplifying circuit is shown, and (a) is a comparison object, and corresponds to the configuration of FIG. The wiring pattern, (b) is a wiring diagram corresponding to the configuration of Fig. 10. In the high-frequency module according to the fourth embodiment of the present invention, a configuration example of the wiring board corresponding to the configuration of FIG. 10 is shown. (a) is a perspective view when the entire wiring board is seen through, (b) The system is an enlarged perspective view of the periphery of the power amplifier circuit, and (c) is a perspective view in which the first wiring layer of -83-200835042 is omitted from (b). [Fig. 13] The result of evaluating the regression gain of the configuration of Fig. 9 (comparative example) and the configuration of Fig. 10, (a) is a graph showing the result of the configuration of Fig. 9, (b) It is a graph showing the results of the composition of FIG. Fig. 14 shows the results of analyzing the current density of the configuration (comparative example) of Fig. 9 and the configuration of Fig. 10.

[圖15]對圖9之構成（比較例）與圖10之構成進行 了電流密度之解析後的結果。 [圖16]對圖9之構成（比較例）與圖10之構成進行 了電流密度之解析後的結果。 [圖17]用以針對圖10之構成例的合適之適用例而作 說明的槪略圖，（a )、（ b )係爲分別展示相異之構成例 者。 [圖18]展示在本發明之前之開發期間中’經由本發明 者們所檢討之RF模組的電路構成之圖。 [圖19]展示本發明之實施形態5所致的高頻模組之電 路構成的圖。 [圖20]展示本發明之實施形態6所致的高頻模組之電 路構成的圖。 [圖2 1]展示圖20的高頻模組之晶片的周邊之配線的 模樣之圖。 [圖22]展示本發明之實施形態7所致的具體之RF模 組之電路構成的圖。 -84- 200835042 [圖23]展示搭載有於圖22中所示之RF模組與高頻類 比訊號處理半導體積體電路與基頻帶訊號處理LSI的行動 電話之構成的區塊圖。 [圖24]展示構成圖22中所示之RF模組的天線開關之 天線開關微波單石半導體積體電路之電路圖。 【主要元件符號說明】Fig. 15 shows the results of analyzing the current density of the configuration (comparative example) of Fig. 9 and the configuration of Fig. 10. Fig. 16 shows the results of analyzing the current density of the configuration (comparative example) of Fig. 9 and the configuration of Fig. 10. [Fig. 17] A schematic diagram for explaining a suitable application example of the configuration example of Fig. 10, and (a) and (b) are examples in which different configurations are respectively shown. Fig. 18 is a view showing the circuit configuration of an RF module reviewed by the present inventors during the development period before the present invention. Fig. 19 is a view showing a circuit configuration of a high frequency module according to a fifth embodiment of the present invention. Fig. 20 is a view showing the circuit configuration of the high frequency module according to the sixth embodiment of the present invention. [Fig. 21] A view showing a pattern of wiring around the periphery of the wafer of the high frequency module of Fig. 20. Fig. 22 is a diagram showing the circuit configuration of a specific RF module according to the seventh embodiment of the present invention. -84-200835042 [Fig. 23] A block diagram showing the configuration of a mobile phone equipped with the RF module shown in Fig. 22, the high-frequency analog signal processing semiconductor integrated circuit, and the baseband signal processing LSI. Fig. 24 is a circuit diagram showing an antenna switch microwave single crystal semiconductor integrated circuit constituting an antenna switch of the RF module shown in Fig. 22. [Main component symbol description]

RF—MDL :高頻模組 PA—CP :半導體晶片 PA :功率放大電路 CTL :控制電路 MN :輸出整合電路 CPL :耦合電路 LPF :低通濾波電路 P0 :天線端子RF-MDL: High-frequency module PA-CP: Semiconductor wafer PA: Power amplifier circuit CTL: Control circuit MN: Output integration circuit CPL: Coupling circuit LPF: Low-pass filter circuit P0: Antenna terminal

ANT_ SW :天線開關電路 RX— FIL :受訊濾波電路 ANT—FIL :天線濾波電路 ESD_ FIL ： ESD濾波電路 Pin :外部輸入端子 RX :外部輸出端子 CS1 :外部控制輸入端子 ANT :外部天線端子 -85- 200835042 LY :配線層 MS :配線圖案ANT_ SW : Antenna switch circuit RX — FIL : Receiver filter circuit ANT—FIL : Antenna filter circuit ESD_ FIL : ESD filter circuit Pin : External input terminal RX : External output terminal CS1 : External control input terminal ANT : External antenna terminal -85 - 200835042 LY : Wiring layer MS: Wiring pattern

Nin :訊號輸入節點Nin: signal input node

Noiit :訊號輸出節點 LC :並聯共振電路 L :電感 C :電容器Noiit : Signal output node LC : Parallel resonance circuit L : Inductance C : Capacitor

VH :通孔導體 DET :檢測電路 LN :傳送線路 TV :熱通孔 B C :偏壓電路 AA :佔有區域 HPA : RF電力放大器 l〇a :初段放大器 l〇b :初段偏壓電路 l〇c :第1段間整合電路 1 1 a :次段放大器 1 1 b :次段偏壓電路 1 1 c :次段間整合電路 1 2 a :最終段放大器 12b:最終段偏壓電路 12 c :輸出整合電路 1 3 :方向性結合器 -86- 200835042 14:高頻波除去濾波器 1 5 :天線開關 1 6 :天線 17 :增益控制單元 HPA1 :第1RF電力放大器 22c :第1輸出整合電路 23:第1方向性結合器VH: via conductor DET: detection circuit LN: transmission line TV: thermal via BC: bias circuit AA: occupied area HPA: RF power amplifier l〇a: initial stage amplifier l〇b: initial stage bias circuit l〇 c: the first stage integration circuit 1 1 a : the sub-stage amplifier 1 1 b : the sub-stage bias circuit 1 1 c : the inter-segment integration circuit 1 2 a : the final stage amplifier 12b: the final stage bias circuit 12 c : Output integration circuit 1 3 : Directional coupler - 86 - 200835042 14 : High frequency wave removal filter 1 5 : Antenna switch 1 6 : Antenna 17 : Gain control unit HPA1 : 1st RF power amplifier 22c : 1st output integration circuit 23 : 1st directional bonder

24 :第1高頻波除去濾波器 27 :第1增益控制單元 HPA2 :第2RF電力放大器 12c:第2輸出整合電路 13:第2方向性結合器 1 4 :第2高頻波除去濾波器 1 7 :第2增益控制單元 100 : RF模組 1C — Chip :晶片24: First high-frequency wave removing filter 27: First gain control unit HPA2: Second RF power amplifier 12c: Second output integrating circuit 13: Second directional coupler 1 4: Second high-frequency wave removing filter 1 7: 2nd Gain Control Unit 100: RF Module 1C - Chip: Chip

Sdl :第1邊Sdl: the first side

Sd2 ：第2邊Sd2: 2nd side

Sd3 :第3邊Sd3: 3rd side

Sd4 :第4邊 300 :天線開關MMICSd4: 4th side 300: Antenna switch MMIC

Claims (1)

200835042 十、申請專利範圍 1· 一種電子裝置’其特徵爲，具備有以下構成： 在包含有第1配線層、和被配置在前述第i配線層之 下層的第2配線層、和被配置在前述第2配線層之下層的 第3配線層之複數配線層基板上，係被形成有：2008. The invention is characterized in that the electronic device includes a first wiring layer, a second wiring layer disposed under the ith wiring layer, and a second wiring layer. The plurality of wiring layer substrates on the third wiring layer below the second wiring layer are formed with: 第1配線圖案，係以在前述第1配線層中包含有一定 寬幅以上之線幅的略迴路（loop )狀之線路的方式而被形 成’且於一端具備有將訊號輸入又或是輸出之第1節點； 和 第2配線圖案，係以在前述第2配線層中包含有前述 一定寬幅以上之線幅的略迴路（loop )狀之線路的方式而 被形成，且於一端具備有將訊號輸入又或是輸出之第2節 點；和 第3配線圖案，係以在前述第3配線層中包含有較前 述一定寬幅爲更狹窄之線幅的略迴路（loop)狀之線路的 方式而被形成，或是以橫跨前述第3配線層與較第3配線 層更爲下層之配線層而包含有較前述一定寬幅爲更狹窄之 線幅的複數之略迴路（l〇〇P )狀之線路的方式而被形成； 和 第1通孔導體，係將前述第1配線圖案之另外一端與 前述第3配線圖案之其中一端電性連接；和 第2通孔導體，係將前述第2配線圖案之另外一端與 前述第3配線圖案之另外一端電性連接， 前述第1配線圖案、前述第2配線圖案、以及前述第 -88- 200835042 3配線圖案，係以相互重疊的方式而被形成，前述第1配 線圖案與前述第2配線圖案間之重疊面積，係較前述第2 配線圖案與前述第3圖案間之重疊面積爲更大。 2.如申請專利範圍第1項所記載之電子裝置，其中， 前述第1配線圖案之前述一端、前述第2配線圖案之 前述一端、以及前述第3配線圖案之前述另外一端，係分 別被設置在配線圖案之外周部，The first wiring pattern is formed so as to include a loop-like line having a width of a certain width or more in the first wiring layer, and is provided with a signal input or output at one end. The first node and the second wiring pattern are formed so as to include a loop-like line having a width of a predetermined width or more in the second wiring layer, and are provided at one end. The second node for inputting or outputting the signal; and the third wiring pattern is a loop-like line including a line having a narrower width than the predetermined width in the third wiring layer. In a method, or a wiring layer that is lower than the third wiring layer and the third wiring layer, a plurality of loops having a narrower width than the predetermined width are included (l〇〇 a P-shaped line is formed; and the first via-hole conductor electrically connects the other end of the first wiring pattern to one end of the third wiring pattern; and the second via-hole conductor The other end of the second wiring pattern is The other end of the third wiring pattern is electrically connected, and the first wiring pattern, the second wiring pattern, and the first-88-200835042 3 wiring pattern are formed so as to overlap each other, and the first wiring pattern is formed. The area of overlap with the second wiring pattern is larger than the area of overlap between the second wiring pattern and the third pattern. 2. The electronic device according to claim 1, wherein the one end of the first wiring pattern, the one end of the second wiring pattern, and the other end of the third wiring pattern are respectively provided. Outside the wiring pattern, 前述第1配線圖案之前述另外一端、以及前述第3配 線圖案之前述一端，係分別被設置在配線圖案之迴路內部 3.如申請專利範圍第1項所記載之電子裝置，其中， 前述複數配線層基板，係在前述第3配線圖案下，具 備有下層配線層，或是在前述第1配線層上，具備有上層 配線層， 前述下層配線層或是前述上層配線層，係成爲被連接 於接地電位之接地電極。 4.如申請專利範圍第1項所記載之電子裝置，其中， 前述複數配線層基板’係更進而包含有被配置在前述 第3配線層之下層的第4配線層’ 前述第3配線圖案，係包含有被形成在前述第3配線 層之略迴路狀的第1線路、和被形成在前述第4配線層之 略迴路狀的第2線路， 前述第1線路之一端，係爲前述第3配線圖案之一端 -89 - 200835042 前述第2線路之另外一端，係爲前述第3配線圖案之 另外一端， 前述第1線路之另外一端，係經由第3通孔導體而被 電性連接於前述第2線路之一端。 5 ·如申請專利範圍第1〜4項中之任一項所記載之電 子裝置，其中，The other end of the first wiring pattern and the one end of the third wiring pattern are respectively provided in the circuit of the wiring pattern. The electronic device according to the first aspect of the invention, wherein the plurality of wirings The layer substrate includes a lower wiring layer under the third wiring pattern, or an upper wiring layer on the first wiring layer, and the lower wiring layer or the upper wiring layer is connected to Ground electrode for ground potential. 4. The electronic device according to the first aspect of the invention, wherein the plurality of wiring layer substrates ′ further include a fourth wiring layer ′ disposed in a lower layer of the third wiring layer, and the third wiring pattern. A first line formed in a slightly looped shape of the third wiring layer and a second line formed in a slightly looped shape of the fourth wiring layer, and one end of the first line is the third line One end of the wiring pattern -89 - 200835042 The other end of the second line is the other end of the third wiring pattern, and the other end of the first line is electrically connected to the first via the third via conductor One of the 2 lines. 5. The electronic device according to any one of claims 1 to 4, wherein 前述電子裝置，係構成共振電路，並包含由前述第1 配線圖案與前述第2配線圖案所構成之電容元件，且包含 以前述第3配線圖案所構成之電感。 6.—種RF模組，其特徵爲，具備有電子裝置、和第1 半導體晶片、和第2半導體晶片， 該電子裝置，係具備有以下構成： 在包含有第1配線層、和被配置在前述第1配線層之 下層的第2配線層、和被配置在前述第2配線層之下層的 第3配線層之複數配線層基板上，係被形成有： 第1配線圖案，係以在前述第1配線層中包含有一定 寬幅以上之線幅的略迴路（loop)狀之線路的方式而被形 成，且於一端具備有將訊號輸入又或是輸出之第1節點； 和 第2配線圖案，係以在前述第2配線層中包含有前述 一定寬幅以上之線幅的略迴路（loop )狀之線路的方式而 被形成，且於一端具備有將訊號輸入又或是輸出之第2節 點；和 第3配線圖案，係以在前述第3配線層中包含有較前 -90 - 200835042 述一定寬幅爲更狹窄之線幅的略迴路（i〇〇p)狀之線路的 方式而被形成，或是以橫跨前述第3配線層與較第3配線 層更爲下層之配線層而包含有較前述一定寬幅爲更狹窄之 線幅的複數之略迴路（loop )狀之線路的方式而被形成； 和 第1通孔導體，係將前述第1配線圖案之另外一端與 前述第3配線圖案之其中一端電性連接；和The electronic device includes a resonant circuit and includes a capacitive element including the first wiring pattern and the second wiring pattern, and includes an inductance formed by the third wiring pattern. 6. An RF module comprising: an electronic device; a first semiconductor wafer; and a second semiconductor wafer, wherein the electronic device includes a first wiring layer and is disposed The second wiring layer under the first wiring layer and the plurality of wiring layer substrates disposed on the third wiring layer below the second wiring layer are formed with a first wiring pattern. The first wiring layer is formed by including a loop-like line having a width of a certain width or more, and has a first node for inputting or outputting a signal at one end; and 2nd The wiring pattern is formed such that a loop-like line including the above-described width of a predetermined width or more is included in the second wiring layer, and a signal is input or outputted at one end. The second node and the third wiring pattern include a circuit of a slightly looped (i〇〇p) shape in which the third wiring layer includes a narrower width than the first-90-200835042. Formed or crossed The third wiring layer and the lower wiring layer of the third wiring layer are formed to include a plurality of loop-like lines having a narrower width than the predetermined width; and a via-hole conductor electrically connecting the other end of the first wiring pattern to one end of the third wiring pattern; and 第2通孔導體，係將前述第2配線圖案之另外一端與 前述第3配線圖案之另外一端電性連接， 前述第1配線圖案、前述第2配線圖案、以及前述第 3配線圖案，係以相互重疊的方式而被形成，前述第1配 線圖案與前述第2配線圖案間之重疊面積，係較前述第2 配線圖案與前述第3圖案間之重疊面積爲更大， 該桌1半導體晶片，係包含有將所輸入之訊號放大並 輸出之電力放大電路，並被安裝在前述複數配線層基板上 該第2半導體晶片，係包含有接收前述電力放大電路 之輸出的天線開關電路，並被安裝在前述複數配線層基板 上，且被連接於前述電子裝置之前述第1節點或者是前述 第2節點之任一方。 7·—種電子裝置，其特徵爲，具備有以下構成： 在包含有第1配線層、和被配置在前述第丨配線層之 下層的第2配線層、和被配置在前述第2配線層之下層的 第3配線層、和被配置在前述第3配線層之下層的第4配 -91 - 200835042 線層之複數配線層基板上，係被形成有： 第1配線圖案，係以在前述第1配線層中包含有略^ 路（loop )狀之線路的方式而被形成，且於一端具備有將 訊號輸入又或是輸出之第1節點；和 第2配線圖案，係以在前述第2配線層中包含有略迴 路（loop )狀之線路的方式而被形成，且於一端具備有將 訊號輸入又或是輸出之第2節點；和The second via-hole conductor electrically connects the other end of the second wiring pattern to the other end of the third wiring pattern, and the first wiring pattern, the second wiring pattern, and the third wiring pattern are Formed to overlap each other, the overlapping area between the first wiring pattern and the second wiring pattern is larger than the overlapping area between the second wiring pattern and the third pattern, and the semiconductor wafer of the table 1 is And a power amplifier circuit for amplifying and outputting the input signal, and mounting the second semiconductor wafer on the plurality of wiring layer substrates, and including an antenna switch circuit for receiving an output of the power amplifier circuit, and mounting The plurality of wiring layer substrates are connected to one of the first node of the electronic device or the second node. In the electronic device, the first wiring layer includes a first wiring layer, a second wiring layer disposed under the second wiring layer, and the second wiring layer. The third wiring layer of the lower layer and the plurality of wiring layer substrates of the fourth-91-200835042 line layer disposed under the third wiring layer are formed with the first wiring pattern. The first wiring layer is formed by including a loop-like line, and has a first node for inputting or outputting a signal at one end; and a second wiring pattern is provided in the first 2 The wiring layer is formed by including a loop-like line, and has a second node for inputting or outputting a signal at one end; and 第3配線圖案，係以板狀而被形成在前述第3配線層 中；和 第4配線圖案，係以板狀而被形成在前述第4配線層 中， 前述第1配線圖案之另外一端與前述第2配線圖案之 另外一端，係經由第1通孔導體而被電性連接， 前述第3配線圖案與前述第4配線圖案，係以相互對 向之方式而被配置， 前述第3配線圖案與前述第4配線圖案之一方的圖案 ，係經由第2通孔導體，而與前述第1節點電性連接， 前述第3配線圖案與前述第4配線圖案之另外一方的 圖案，係經由第3通孔導體，而與前述第2節點電性連接 前述第1配線圖案、前述第2配線圖案、前述第3配 線圖案、以及前述第4配線圖案，係以相互重疊的方式而 被形成，前述第3配線圖案與前述第4配線圖案間之重疊 面積，係較前述第2配線圖案與前述第3圖案間之重疊面 -92-The third wiring pattern is formed in the third wiring layer in a plate shape, and the fourth wiring pattern is formed in the fourth wiring layer in a plate shape, and the other end of the first wiring pattern is The other end of the second wiring pattern is electrically connected via the first via-hole conductor, and the third wiring pattern and the fourth wiring pattern are disposed to face each other, and the third wiring pattern is disposed. The pattern of one of the fourth wiring patterns is electrically connected to the first node via the second via-hole conductor, and the other pattern of the third wiring pattern and the fourth wiring pattern is via the third a via-hole conductor electrically connected to the second node, the first wiring pattern, the second wiring pattern, the third wiring pattern, and the fourth wiring pattern are formed so as to overlap each other The overlapping area between the wiring pattern and the fourth wiring pattern is compared with the overlapping surface of the second wiring pattern and the third pattern - 92- 200835042 積爲更大。 8 ·如申請專利範圍第7項所記載之電子裝置，其中 前述第3配線圖案以及前述第4配線圖案，係被配 在較前述第1配線圖案或者是前述第2配線圖案之外周 更內側。 9.如申請專利範圍第7項所記載之電子裝置，其中 前述複數配線層基板，係在前述第4配線圖案下， 備有第5配線層，或是在第1配線層上，具備有第6配 層， 前述第5配線層或是前述第6配線層，係成爲被連 於接地電位之接地電極。 10·如申請專利範圍第7項所記載之電子裝置，其 前述第3配線圖案，係經由前述第2通孔導體而與 述第1節點電性連接， 述弟4配線圖案’係經由前述第3通孔導體，而 前述第2節點電性連接。 11·如申請專利範圍第10項所記載之電子裝置，其 前述第1配線圖案之前述一端以及前述另外一端， 前述第2配線圖案之前述一端以及前述另外一端，和前 第1通孔導體，和前述第3通孔導體，係被配置在較前 第3配線圖案之外周爲更外側。 12·如申請專利範圍第7〜11項中之任一項所記載 置 爲 具 線 接 中 、八 刖 與 中 和 述 述 之 -93- 200835042 電子裝置，其中， 前述電子裝置，係構成共振電路，並包含由前述第1 配線圖案與前述第2配線圖案所構成之電感，且包含以前 述第3配線圖案與前述第4配線圖案所構成之電容元件。 13·—種RF模組，其特徵爲，具備有電子裝置、和第 1半導體晶片、和第2半導體晶片， 該電子裝置，係具備有以下構成：200835042 The product is bigger. The electronic device according to the seventh aspect of the invention, wherein the third wiring pattern and the fourth wiring pattern are disposed on the inner side of the outer circumference of the first wiring pattern or the second wiring pattern. 9. The electronic device according to claim 7, wherein the plurality of wiring layer substrates are provided with a fifth wiring layer under the fourth wiring pattern or a first wiring layer In the sixth layer, the fifth wiring layer or the sixth wiring layer is a ground electrode connected to the ground potential. The electronic device according to claim 7, wherein the third wiring pattern is electrically connected to the first node via the second via-hole conductor, and the second wiring pattern is described above. 3 through-hole conductors, and the second node is electrically connected. The electronic device according to claim 10, wherein the one end and the other end of the first wiring pattern, the one end of the second wiring pattern, the other end, and the front first via conductor are The third via-hole conductor is disposed on the outer side of the outer circumference of the third wiring pattern. 12. The electronic device as described in any one of claims 7 to 11 of the present application, which is described in the above-mentioned item, wherein the electronic device constitutes a resonant circuit. And including an inductance including the first wiring pattern and the second wiring pattern, and including a capacitance element including the third wiring pattern and the fourth wiring pattern. An RF module comprising: an electronic device; a first semiconductor wafer; and a second semiconductor wafer, wherein the electronic device has the following configuration: 在包含有第1配線層、和被配置在前述第1配線層之 下層的第2配線層、和被配置在前述第2配線層之下層的 第3配線層、和被配置在前述第3配線層之下層的第4配 線層之複數配線層基板上，係被形成有： 第1配線圖案，係以在前述第1配線層中包含有略迴 路（loop)狀之線路的方式而被形成，且於一端具備有將 訊號輸入又或是輸出之第1節點；和 第2配線圖案，係以在前述第2配線層中包含有略迴 路（loop )狀之線路的方式而被形成，且於一端具備有將 訊號輸入又或是輸出之第2節點；和 第3配線圖案，係以板狀而被形成在前述第3配線層 中；和 第4配線圖案，係以板狀而被形成在前述第4配線層 中， 前述第1配線圖案之另外一端與前述第2配線圖案之 另外一端，係經由第1通孔導體而被電性連接， 前述第3配線圖案與前述第4配線圖案，係以相互對 -94- 200835042 向之方式而被配置， 前述第3配線圖案與前述第4配線圖案之一方的圖案 ’係經由第2通孔導體’而與則述第1節點電性連接， 前述第3配線圖案與前述第4配線圖案之另外一方的 圖案，係經由第3通孔導體，而與前述第2節點電性連接a first wiring layer, a second wiring layer disposed under the first wiring layer, and a third wiring layer disposed under the second wiring layer, and the third wiring layer In the plurality of wiring layer substrates on the fourth wiring layer of the lower layer of the layer, the first wiring pattern is formed so that the first wiring layer includes a loop-like line. And a first node having a signal input or output at one end; and a second wiring pattern formed by including a loop-like line in the second wiring layer, and One end is provided with a second node for inputting or outputting a signal; and a third wiring pattern is formed in the third wiring layer in a plate shape; and the fourth wiring pattern is formed in a plate shape In the fourth wiring layer, the other end of the first wiring pattern and the other end of the second wiring pattern are electrically connected via a first via conductor, and the third wiring pattern and the fourth wiring pattern are electrically connected to each other. To each other -94- 200835042 In the arrangement, the pattern of the third wiring pattern and the fourth wiring pattern is electrically connected to the first node via the second via-hole conductor, and the third wiring pattern and the first The other pattern of the wiring pattern is electrically connected to the second node via the third via-hole conductor. 刖述弟1配線圖案、前述第2配線圖案、前述第3配 線圖案、以及前述第4配線圖案，係以相互重疊的方式而 被形成，前述第3配線圖案與前述第4配線圖案間之重疊 面積，係較前述第2配線圖案與前述第3配線圖案間之重 疊面積爲更大， 該第1半導體晶片，係包含有將所輸入之訊號放大並 輸出之電力放大電路，並被安裝在前述複數配線層基板上 該第2半導體晶片，係包含有接收前述電力放大電路 之輸出的天線開關電路，並被安裝在前述複數配線層基板 上，且被連接於前述電子裝置之前述第1節點或者是前述 第2節點之任一方。 14. 一種RF模組，其特徵爲，係被形成在包含有第1 配線層、和被配置在前述第1配線層之下層的第2配線層 、和被配置在前述第2配線層之下層的第3配線層、和被 配置在前述第3配線層之下層的第4配線層之複數配線層 基板上，具備有： 第1共振電路，其係包含有： -95- 200835042 入又 第2 2節 橫跨 案3The wiring pattern, the second wiring pattern, the third wiring pattern, and the fourth wiring pattern are formed so as to overlap each other, and the third wiring pattern overlaps with the fourth wiring pattern. The area is larger than the overlapping area between the second wiring pattern and the third wiring pattern, and the first semiconductor wafer includes a power amplifying circuit that amplifies and outputs the input signal, and is mounted on the foregoing The second semiconductor wafer on the plurality of wiring layer substrates includes an antenna switch circuit that receives an output of the power amplifier circuit, is mounted on the plurality of wiring layer substrates, and is connected to the first node of the electronic device or It is either one of the aforementioned second nodes. An RF module, comprising: a first wiring layer; a second wiring layer disposed under the first wiring layer; and a second wiring layer disposed under the second wiring layer The third wiring layer and the plurality of wiring layer substrates disposed on the fourth wiring layer below the third wiring layer include: a first resonant circuit including: -95-200835042 2 sections across the case 3 入又 第2 4節 圖案 出之 和Into the 2nd 4th pattern 輸出 ，且 述第 節點 案2 前述 爲更 被形成在前述第1配線層，且於一端具備有將訊號輸 或是輸出之第1節點的配線圖案1、和被形成在前述 配線層，且於一端具備有將訊號輸入又或是輸出之第 點的配線圖案2、和被形成在前述第3配線層 '或是 前述第3配線層與更下層之配線層而被形成的配線圖 :和 第2共振電路，其係包含有= 被形成在前述第1配線層，且於一端具備有將訊號輸 或是輸出之第3節點的配線圖案4、和被形成在前述 配線層，且於一端具備有將訊號輸入又或是輸出之第 點的配線圖案5、和被形成於前述第3配線層之配線 6、和被形成在前述第4配線層之配線圖案7 ;和 第1半導體晶片，係包含有將所輸入之訊號放大並輸 電力放大電路，並被安裝在前述複數配線層基板上； 第2半導體晶片，係包含有接收前述電力放大電路之 的天線開關電路，並被安裝在前述複數配線層基板上 被連接於前述第1共振電路之前述第1節點或者是前 2節點之任一方、以及前述第2共振電路之前述第3 或者是前述第4節點之任一方， 以前述第1共振電路之前述配線圖案1與前述配線圖 所形成之電容的電容値，係較以前述第2共振電路之 配線圖案6與前述配線圖案7所形成之電容的電容値 大， - 96- 200835042 在前述第1共振電路，係被輸入有第1頻率之訊號， 在前述第2共振電路，係被輸入有較前述第1頻率爲更高 之頻率的第2頻率之訊號。 15. 如申請專利範圍第14項所記載之RF模組，其中 ，前述配線圖案1以及前述配線圖案2,與前述配線圖案 6以及前述配線圖案7，係以相互重疊的方式而被形成，Output, and the second node 2 is a wiring pattern 1 formed on the first wiring layer and having a first node for transmitting or outputting a signal at one end, and is formed on the wiring layer. One end of the wiring pattern 2 having a signal input or output, and a wiring pattern formed on the third wiring layer ' or the third wiring layer and the lower wiring layer: The resonance circuit includes a wiring pattern 4 formed on the first wiring layer and having a third node for transmitting or outputting a signal at one end, and is formed on the wiring layer, and is provided at one end a wiring pattern 5 for inputting or outputting a signal, and a wiring 6 formed on the third wiring layer, a wiring pattern 7 formed on the fourth wiring layer, and a first semiconductor wafer. The method includes: amplifying the input signal and transmitting the power amplifying circuit, and mounting the circuit on the plurality of wiring layer substrates; and the second semiconductor chip includes an antenna switching circuit for receiving the power amplifying circuit, and is mounted The plurality of wiring layer substrates are connected to one of the first node or the first two nodes of the first resonant circuit, and the third or the fourth node of the second resonant circuit, The capacitance 电容 of the capacitance formed by the wiring pattern 1 of the first resonance circuit and the wiring pattern is larger than the capacitance of the capacitance formed by the wiring pattern 6 of the second resonance circuit and the wiring pattern 7, - 96- 200835042 In the first resonant circuit, a signal having a first frequency is input, and in the second resonant circuit, a signal having a second frequency higher than the first frequency is input. 15. The RF module according to claim 14, wherein the wiring pattern 1 and the wiring pattern 2 are formed so as to overlap the wiring pattern 6 and the wiring pattern 7 so as to overlap each other. 前述第1共振電路之前述配線圖案1與前述配線圖案 2間的重疊面積，係較前述第2共振電路之前述配線圖案 6與前述配線圖案7間的重疊面積爲更大。 16. —種RF模組，其特徵爲，係被形成在包含有第1 配線層、和被配置在前述第1配線層之下層的第2配線層 、和被配置在前述第2配線層之下層的第3配線層、和被 配置在前述第3配線層之下層的第4配線層之複數配線層 基板上，具備有： 第1共振電路，其係包含有： 被形成在前述第1配線層，且於一端具備有將訊號輸 入又或是輸出之第1節點的配線圖案1、和被形成在前述 第2配線層，且於一端具備有將訊號輸入又或是輸出之第 2節點的配線圖案2、和被形成在前述第3配線層、或是 橫跨前述第3配線層與更下層之配線層而被形成的配線圖 案3， 前述配線圖案1之另外一端，係被電性連接於前述配 線圖案3之一端， 前述配線圖案3之另外一端，係被電性連接於前述配 -97- 200835042 線圖案2之另外一端；和 第2共振電路，其係包含有： 被形成在前述第1配線層，且於一端具備有將訊號輸 入又或是輸出之第3節點的配線圖案4、和被形成在前述 第2配線層，且於一端具備有將訊號輸入又或是輸出之第 4節點的配線圖案5、和以板狀而被形成於前述第3配線 層之配線圖案6、和以板狀而被形成在前述第4配線層之The overlapping area between the wiring pattern 1 and the wiring pattern 2 in the first resonant circuit is larger than the overlapping area between the wiring pattern 6 and the wiring pattern 7 in the second resonant circuit. 16. An RF module, comprising: a first wiring layer; a second wiring layer disposed under the first wiring layer; and a second wiring layer disposed on the second wiring layer The third wiring layer of the lower layer and the plurality of wiring layer substrates disposed on the fourth wiring layer below the third wiring layer include: a first resonant circuit including: formed in the first wiring And a wiring pattern 1 having a first node for inputting or outputting a signal at one end, and a second wiring layer formed at the one end, and having a second node for inputting a signal or outputting at one end The wiring pattern 2 and the wiring pattern 3 formed on the third wiring layer or the wiring layer that straddles the third wiring layer and the lower layer, and the other end of the wiring pattern 1 is electrically connected One end of the wiring pattern 3 is electrically connected to the other end of the line pattern of the -97-200835042 line 2; and the second resonance circuit includes: First wiring layer, and A wiring pattern 4 having a third node for inputting or outputting a signal at one end, and a wiring pattern 5 formed at the second wiring layer and having a fourth node for inputting or outputting a signal at one end And a wiring pattern 6 formed in the third wiring layer in a plate shape, and a wiring pattern 6 formed in a plate shape in the fourth wiring layer 配線圖案7， 前述配線圖案4之另外一端，係被電性連接於前述配 線圖案5之另外一端， 前述配線圖案6，係被電性連接於前述配線圖案4之 一端的前述第3節點， 前述配線圖案7，係被電性連接於前述配線圖案5之 一端的前述第4節點；和 第1半導體晶片，係包含有將所輸入之訊號放大並輸 出之電力放大電路，並被安裝在前述複數配線層基板上； 和 第2半導體晶片，係包含有接收前述電力放大電路之 輸出的天線開關電路，並被安裝在前述複數配線層基板上 ’且被連接於前述第1共振電路之前述第1節點或者是前 述第2節點之任一方、以及前述第2共振電路之前述第3 自口點或者是前述第4節點之任一方， 以前述第1共振電路之前述配線圖案1與前述配線圖 案2所形成之電容的電容値，係較以前述第2共振電路之 -98- 200835042 前述配線圖案6與前述配線圖案7所形成之電容的電容値 爲更大’ 在前述第1共振電路，係被輸入有第1頻率之訊號， 在則述第2共振電路，係被輸入有較前述第1頻率爲更高 之頻率的第2頰率之訊號。 1 7 ·如申請專利範圍第1 6項所記載之RF模組，其中In the wiring pattern 7, the other end of the wiring pattern 4 is electrically connected to the other end of the wiring pattern 5, and the wiring pattern 6 is electrically connected to the third node at one end of the wiring pattern 4, The wiring pattern 7 is electrically connected to the fourth node at one end of the wiring pattern 5; and the first semiconductor wafer includes a power amplifying circuit that amplifies and outputs the input signal, and is mounted on the plural And the second semiconductor wafer includes an antenna switch circuit that receives an output of the power amplifier circuit and is mounted on the plurality of wiring layer substrates ′ and is connected to the first one of the first resonant circuits The node is either the second node or the third self-porting of the second resonant circuit or one of the fourth nodes, and the wiring pattern 1 and the wiring pattern 2 of the first resonant circuit are The capacitance 値 of the formed capacitor is compared with the wiring pattern 6 and the wiring pattern 7 of -98-200835042 of the second resonant circuit. The capacitance of the capacitor becomes larger. In the first resonant circuit, a signal having a first frequency is input, and in the second resonant circuit, a frequency higher than the first frequency is input. The signal of the second cheek rate. 1 7 · The RF module as described in item 16 of the patent application, wherein 刖述配線圖案1以及前述配線圖案2，與前述配線圖 案ό以及前述配線圖案7，係以相互重疊的方式而被形成 前述第1共振電路之前述配線圖案1與前述配線圖案 2間的重疊面積，係較前述第2共振電路之前述配線圖案 6與前述配線圖案7間的重疊面積爲更大。 18·—種電子裝置，其特徵爲： 在被形成於包含有第1配線層之複數配線層基板處的 共振電路中，係包含有以使配線層包含有略迴路狀之線路 的方式而被形成之配線圖案， 前述配線圖案，係以蛇行的方式而被形成。 19.一種RF模組，其特徵爲，係包含有： RF電力放大器、輸出整合電路、和方向性結合器、 和高調波除去濾波器， 前述RF電力放大器之輸出放大訊號，係被供給至前 述輸出整合電路之輸入端子， 前述輸出整合電路之輸出端子的RF訊號，係經由前 -99- 200835042 述方向性結合器之主線路，而被供給至前述高調波除去濾 波器的輸入端子， 從前述方向性結合器之副線路而來的檢測訊號，係被 供給至前述RF電力放大器增益控制單元的訊號輸入端子 前述高調波除去濾波器之輸出端子的RF訊號，係成 爲可傳達至天線處。The wiring pattern 1 and the wiring pattern 2 are overlapped with the wiring pattern ό and the wiring pattern 7 so as to overlap each other with the overlapping area between the wiring pattern 1 and the wiring pattern 2 of the first resonant circuit. The overlapping area between the wiring pattern 6 and the wiring pattern 7 of the second resonant circuit is larger. An electronic device comprising: a resonant circuit formed on a plurality of wiring layer substrates including a first wiring layer, wherein the wiring layer includes a circuit having a slightly looped shape In the formed wiring pattern, the wiring pattern is formed in a serpentine manner. 19. An RF module, comprising: an RF power amplifier, an output integration circuit, and a directional combiner, and a high-modulation removal filter, wherein an output amplification signal of the RF power amplifier is supplied to the foregoing An input terminal of the output integration circuit, and an RF signal of an output terminal of the output integration circuit is supplied to an input terminal of the high-frequency wave removal filter via a main line of the directional connector described in the preceding paragraph-99-200835042, from the foregoing The detection signal from the sub-line of the directional combiner is supplied to the signal input terminal of the RF power amplifier gain control unit, and the RF signal of the output terminal of the high-modulation removal filter is transmitted to the antenna. 2 0.如申請專利範圍第19項所記載之RF模組，其中 ，係更進而包含有： 天線開關，前述高調波除去濾波器之前述輸出端子的 前述RF訊號，係被供給至天線開關之其中一方之端子， 而天線開關另外一方之端子的RF訊號，係可被傳達至前 述天線。 21.如申請專利範圍第20項所記載之RF模組，其中 前述高調波除去濾波器之前述輸出端子的前述RF訊 號，係經由DC截斷電容器，而被供給至前述天線開關之 前述其中一方的端子。 22.如申請專利範圍第19項所記載之RF模組，其中 前述RF電力放大器，係包含有：多段放大器、和藉 由前述增益控制單元而被控制，並對前述多段放大器之增 益作控制的偏壓電路。 2 3.如申請專利範圍第19項所記載之RF模組，其中 -100- 200835042 前述輸出整合電路，係爲將由產生前述RF電力放大 器之前述輸出放大訊號的輸出阻抗和前述天線之阻抗之間 的差所致的訊號反射減低者。 24.如申請專利範圍第22項所記載之RF模組，其中The RF module according to claim 19, further comprising: an antenna switch, wherein the RF signal of the output terminal of the high-frequency wave removing filter is supplied to an antenna switch The RF signal of one of the terminals and the other terminal of the antenna switch can be transmitted to the antenna. The RF module according to claim 20, wherein the RF signal of the output terminal of the high-frequency wave removing filter is supplied to one of the antenna switches via a DC cut capacitor. Terminal. 22. The RF module of claim 19, wherein the RF power amplifier comprises: a multi-segment amplifier, and is controlled by the gain control unit, and controls gain of the multi-segment amplifier. Bias circuit. 2. The RF module as recited in claim 19, wherein the output integrated circuit of -100-200835042 is between an output impedance of the output amplified signal of the RF power amplifier and an impedance of the antenna. The signal reflection caused by the difference is reduced. 24. The RF module as recited in claim 22, wherein 前述多段放大器、和前述偏壓電路、和前述增益控制 單元，係被形成在半導體積體電路晶片上。 2 5.如申請專利範圍第19項所記載之RF模組，其中 前述方向性結合器，係爲在主線路與副線路之間，被 連接有電容元件的微耦合器。 2 6.—種RF模組，其特徵爲，包含有： 第1RF電力放大器、和第1輸出整合電路、和第1方 向性結合器、和第1高調波除去濾波器、和第2RF電力放 大器、和第2輸出整合電路、和第2方向性結合器、和第 2高調波除去濾波器， 前述第1RF電力放大器，係以將第1頻率帶域rf訊 號放大的方式而被構成，前述第2 RF電力放大器，係以將 較前述第1頻率帶域RF訊號更高之頻率的第2頻率帶域 RF訊號放大的方式而被構成， 前述第1RF電力放大器之第1輸出放大訊號，係被供 給至前述第1輸出整合電路的輸入端子，前述第1輸出整 合電路之輸出端子的第1RF訊號，係經由前述第1方向性 -101 - 200835042 結合器的主線路，而被供給至前述第1高調波除去濾波器 之輸入端子，從前述第1方向性結合器之副線路而來的第 1檢測訊號，係被供給至用於前述第1 RF電力放大器的第 1增益控制單元之第1訊號輸入端子，前述第1高調波除 去濾波器之輸出端子的第1RF訊號，係成爲可傳達至天線The multi-stage amplifier, the bias circuit, and the gain control unit are formed on a semiconductor integrated circuit wafer. The RF module according to claim 19, wherein the directional coupler is a microcoupler to which a capacitive element is connected between the main line and the sub line. 2. A RF module, comprising: a first RF power amplifier, a first output integration circuit, a first directional coupler, a first high-order wave removal filter, and a second RF power amplifier; And a second output integration circuit, a second directional coupler, and a second high-modulation removal filter, wherein the first RF power amplifier is configured to amplify the first frequency band rf signal, and the first The RF power amplifier is configured to amplify a second frequency band RF signal having a higher frequency than the first frequency band RF signal, and the first output amplification signal of the first RF power amplifier is The first RF signal supplied to the input terminal of the first output integration circuit, the first RF signal of the output terminal of the first output integration circuit is supplied to the first via the main line of the first directionality -101 - 200835042 combiner The input terminal of the high-frequency wave removing filter, the first detection signal from the sub-line of the first directional coupler is supplied to the first gain control unit for the first RF power amplifier A signal input terminal, the first output terminal of the harmonics are removed by the first filter 1RF signals, can be communicated to the antenna system 前述第2RF電力放大器之第2輸出放大訊號，係被供 給至前述第2輸出整合電路之輸入端子，前述第2輸出整 合電路的輸出端子之第2RF訊號，係經由前述第2方向性 結合器的主線路，而被供給至前述第2高調波除去濾波器 之輸入端子，從前述第2方向性結合器之副線路而來的第 2檢測訊號，係被供給至用於前述第2RF電力放大器之第 2增益控制單元的第2訊號輸入端子，前述第2高調波除 去濾波器之輸出端子的第2RF訊號，係成爲可傳達至前述 天線。 27.如申請專利範圍第26項所記載之RF模組，其中 前述第1高調波除去濾波器之前述輸出端子的前述第 1RF訊號，係被供給至天線開關之第1輸入端子，前述第 2高調波除去濾波器之前述輸出端子的前述第2RF訊號， 係被供給至前述天線開關之第2輸入端子，而前述天線開 關之輸出端子的RF訊號，係可被傳達至前述天線。 28·如申請專利範圍第27項所記載之RF模組，其中 -102-The second output amplification signal of the second RF power amplifier is supplied to an input terminal of the second output integration circuit, and the second RF signal of the output terminal of the second output integration circuit is transmitted via the second directional coupler The main line is supplied to the input terminal of the second high-frequency wave removing filter, and the second detection signal from the sub-line of the second directional coupler is supplied to the second RF power amplifier. The second signal input terminal of the second gain control unit and the second RF signal of the output terminal of the second high-modulation removal filter are transmitted to the antenna. The RF module according to claim 26, wherein the first RF signal of the output terminal of the first high-frequency wave removing filter is supplied to a first input terminal of the antenna switch, and the second The second RF signal of the output terminal of the high-frequency wave removing filter is supplied to the second input terminal of the antenna switch, and the RF signal of the output terminal of the antenna switch can be transmitted to the antenna. 28·If the RF module described in the 27th patent application area, -102- 200835042 前述第1高調波除去濾波器之前述輸 1RF訊號，係經由第1DC截斷電容器而被 開關之前述第1輸入端子，前述第2高調 前述輸出端子的前述第2RF訊號，係經技 容器而被供給至前述天線開關之前述第2 29.如申請專利範圍第26項所記載之 前述第1RF電力放大器、和前述第 、和前述第1增益控制單元、和前述第2 係被形成在半導體積體電路晶片上， 前述半導體積體電路晶片，係具備有 之晶片形狀’ 前述晶片，係爲具備有相互對向而略 第2邊、和被連接於前述第1邊與前述第 爲和前述第1邊與前述第2邊成略直角之 於前述第3邊，且與前述第3邊成略平行 前述第1RF電力放大器之前述第1輸 從前述晶片之前述第1邊而被導出’前述 器之前述第2輸出放大訊號，係從前述晶 而被導出， 從前述第1方向性結合器之前述副 1檢測訊號，係由前述晶片之前述第3 於前述第1RF電力放大器之前述第1增 第1訊號輸入端子，從前述第2方向性 出端子的前述第 供給至前述天線 波除去濾波器之 3第2DC截斷電 輸入端子。 RF模組，其中 2RF電力放大器 增益控制單元， 實質上爲4角形 平行之第1邊與 2邊，且被配置 第3邊、和對向 之第4邊者， 出放大訊號，係 第2RF電力放大 片之前述第2邊 路而來的前述第 :’而被導入至用 :控制單元的前述 :合器之前述副線 -103- 200835042 路而來的前述第2檢測訊號，係由前述晶片之前述第3邊 ，而被導入至用於前述第2RF電力放大器之前述第2增益 控制單元的前述第2訊號輸入端子。 3 0·如申請專利範圍第29項所記載之RF模組，其中200835042 The first input RF signal of the first high-order wave removing filter is the first input terminal that is switched by the first DC cut capacitor, and the second RF signal of the second high-profile output terminal is used by the technical container. The second RF power amplifier according to claim 26, wherein the first RF power amplifier and the first gain control unit and the second system are formed in a semiconductor integrated body. In the circuit wafer, the semiconductor integrated circuit wafer includes a wafer shape, wherein the wafer has a second side that is opposite to each other, and is connected to the first side, the first and the first The first input of the first RF power amplifier is slightly parallel to the third side and is parallel to the third side, and the first input of the first RF power amplifier is derived from the first side of the wafer. The second output amplification signal is derived from the crystal, and the sub 1 detection signal from the first directional connector is the third RF of the wafer. Of the first power amplifier by a first signal input terminal, the first terminal of the supply from the second directional antenna to the first 2DC wave filter 3 to remove the power input terminal truncation. The RF module, wherein the 2RF power amplifier gain control unit is substantially the first side and the two sides of the quadrilateral parallel, and the third side and the fourth side of the opposite side are arranged, and the amplified signal is the second RF power. The second detection signal from the second side of the enlarged slice is introduced into the second detection signal of the above-mentioned sub-line -103-200835042 of the combiner of the control unit by the aforementioned wafer The third side is introduced to the second signal input terminal of the second gain control unit for the second RF power amplifier. 3 0. The RF module as recited in claim 29, wherein 前述第1輸出放大訊號之前述第1邊的導出點，與前 述第1檢測訊號之前述第3邊的導入點之間，係被配置有 前述第2檢測訊號之前述第3邊的導入點，前述第2輸出 放大訊號之前述第2邊的導出點，與前述第2檢測訊號之 前述第3邊的導入點之間，係被配置有前述第1檢測訊號 之前述第3邊的導入點。 3 1.如申請專利範圍第29項所記載之RF模組，其中 前述第1輸出放大訊號之前述第1邊的導出點，與前 述第1檢測訊號之前述第3邊的導入點之間，被連接於接 地電壓之第1接地配線，係被連接於前述第3邊，前述第 2輸出放大訊號之前述第2邊的導出點，與前述第2檢測 訊號之前述第3邊的導入點之間，被連接於前述接地電壓 之第2接地配線，係被連接於前述第3邊。 32.如申請專利範圍第30項所記載之RF模組，其中 前述第1輸出放大訊號之前述第1邊的導出點，與前 述第1檢測訊號之前述第3邊的導入點之間，被連接於接 地電壓之第1接地配線，係被連接於前述第3邊，前述第 -104- 200835042 2輸出放大訊號之前述第2邊的導出點，與前述第2檢測 訊號之前述第3邊的導入點之間，被連接於前述接地電壓 之第2接地配線，係被連接於前述第3邊。 3 3 ·如申請專利範圍第32項所記載之RF模組，其中The lead-out point of the first side of the first output amplification signal and the lead-in point of the third side of the first detection signal are arranged with the lead-in point of the third side of the second detection signal. The lead-out point of the second side of the second output amplification signal and the lead-in point of the third side of the second detection signal are arranged with the lead-in point of the third side of the first detection signal. 3. The RF module according to claim 29, wherein a derivation point of the first side of the first output amplification signal and an introduction point of the third side of the first detection signal are The first ground wiring connected to the ground voltage is connected to the third side, the derivation point of the second side of the second output amplification signal, and the introduction point of the third side of the second detection signal The second ground wiring connected to the ground voltage is connected to the third side. The RF module according to claim 30, wherein the derivation point of the first side of the first output amplification signal is between the lead point of the third side of the first detection signal and the introduction point of the third side of the first detection signal The first ground wiring connected to the ground voltage is connected to the third side, and the derivation point of the second side of the amplification signal is outputted from the -104-200835042 2 and the third side of the second detection signal The second ground wiring connected to the ground voltage between the lead-in points is connected to the third side. 3 3 · The RF module as described in item 32 of the patent application, wherein 前述第1接地配線，係在前述第3邊之近旁，而被配 置於前述第2檢測訊號之前述導入點，與前述第1檢測訊 號之前述導入點之間，前述第2接地配線，係在前述第3 邊之近旁，而被配置於前述第1檢測訊號之前述導入點， 與前述第2檢測訊號之前述導入點之間。 34.如申請專利範圍第28項所記載之RF模組，其中 前述第 1頻率帶域 RF訊號，係爲 GSM85 0與 GSM90 0之RF送訊訊號，前述第2頻率帶域RF訊號，係 爲DCS1 800與PCS1900之RF送訊訊號。 3 5.如申請專利範圍第28項所記載之RF模組，其中 ，前述第1方向性結合器與前述第2方向性結合器，係分 別爲藉由在主線路與副線路之間，被連接有電容元件的微 耦合器所構成。 -105-The first ground wiring is disposed adjacent to the third side, and is disposed between the lead-in point of the second detection signal and the lead-in point of the first detection signal, and the second ground line is The vicinity of the third side is disposed between the lead-in point of the first detection signal and the lead-in point of the second detection signal. 34. The RF module as claimed in claim 28, wherein the first frequency band RF signal is an RF transmission signal of GSM85 0 and GSM90 0, and the second frequency band RF signal is RF signal transmission of DCS1 800 and PCS1900. The RF module according to claim 28, wherein the first directional coupler and the second directional coupler are respectively disposed between the main line and the sub line. It is composed of a microcoupler to which a capacitive element is connected. -105-
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