200834692 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種晶圓加工方法，特別是一種可使晶圓 達到更溥效果之加工方法。 【先前技術】 隨著半導體製程之進步，以及使用者對電子產品輕薄短小特色 之要求與日俱增，使得降低晶片封裝體之尺寸變成各家廠商競爭之要 點，由既往之單片晶片封裝轉向多片晶片封裝，如堆疊式晶片封裝， 以縮小晶片封裝體在應用印刷電路板上之面積。然而，為了兼顧縮 J曰曰片封裝體體積以及增加晶片封裝體功能雙重目的，最直 接的方法就是於封裝體内堆疊更多小尺寸晶粒，而晶片研磨 之製程能力則直接影響晶片封裝體内晶粒堆疊的層數。 習知之晶圓加工方法流程，如第丨圖所示，一般晶圓經過電性 功月&測试之後，隨即進入後段加工的階段：首先於晶圓的主動面（即 包含複數個晶粒之一表面）上貼附一保護膠帶（步驟sl〇)，用以保 護曰曰圓主動面上之晶粒；將晶圓翻轉180度並放置於一研磨機台上， 使得晶圓之背面朝向-研磨具（步驟S12);然後對晶圓之背面進行 研磨步驟，將晶圓的厚度研磨至預定厚度（步驟S14);接著於晶圓 背面貼附-切婦帶，並將晶圓峡於—框架之一環狀開口中（步驟 S16);接著將晶圓再度翻轉18〇度使主動面朝上（步驟)，然後 去除主動面上之保護膠帶，並將晶圓放置於—切韻台上（步驟 S20);最後利用一切割具將晶圓切割為複數個晶粒（步驟s22)，以 供後段封裝製程使用。 然而/傳統晶圓加工方法中所使用之保護膠帶已經無法因應晶 圓越來越薄的趨勢，隨著晶圓的薄度減低，晶圓在研磨後容易產生勉 5 200834692 _ 曲（Warpage)的現象，而導致晶圓在後續製程加工困難。另外，由 於保護膠帶(grindingtape)之材質與製程特性，無法提供薄晶圓支撐， 容易產生研磨後晶圓邊緣破損的情形。再者，傳統晶圓加=方法^ 去除保護膠帶（De-taping)時，容易因撕開的動作對薄曰圓產生靡力 而損壞晶圓，造成晶圓破片、崩裂，㈣致日後晶片封裝體㈤:） 不良的電性連接、或晶圓上的殘夥導致晶粒污染等不_ 口出現生、 報廢品增加，無形之中增加不必要之成本費用。又，在义後續二$ 製程中’因晶圓本身的材質問題，易導致晶圓之多層測試塾（把⑽） 因切割刀的作用而部份娜，而祕之測試塾碎片容練著切彻具 之轉動而被帶至晶圓主動面上，造成晶粒污染、刮傷亦或晶粒與晶粒 間不正常之連接或者其他如赠 '異物殘留或銲麵㈣問題。 【發明内容】 為了解決上述問題，本發明目的之—係在提供—種晶圓加 工方法’利用保護層取代傳統之保護膠帶，可省略晶圓貼附保護膠 及去除膠帶之步驟，可有效簡化晶圓製程。 / 本發明之另一目的係在提供一種晶圓加工方法，於晶圓之主 動面塗佈-層保護層，可避免傳統貼附保護膠帶所產生之殘膠污半， 且改善既有晶圓貼附保護膠帶及錄膠帶對晶圓所產生 而、 成破片等問題。 〜 ^本I月之又一目的係在提供一種晶圓加工方法，利用塗佈保 護層取代傳統貼_帶及去除膠帶之步驟，可保護晶圓之完整性，且 晶圓切割後，仍能保持晶粒之完整性，進而提升晶粒之良率，增加產 品競爭力。 曰 本U之又目的係、在提供一種晶圓加工方法，藉由保声 的4寸性支撐曰曰圓，可避免晶圓因研磨後厚度降低而產生晶圓纽曲的& 6 200834692 v 題’同時’於不產生晶圓趣曲的前提下， 的傳送運輸更加容易。 對極度薄化的晶圓在後製程 本4月之又目的係在提供一種晶圓加工方法，藉由塗姊保 護層於晶圓主動面上，可於晶圓切割時提供研磨後之晶圓主動面一保 護與支樓，可避免晶圓之多層測試塾因切割而㈣，同時可有效避免 造成晶粒汙染及不必要的電性連接和其減物前或腐钱。200834692 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a wafer processing method, and more particularly to a processing method which can achieve a more flawed effect on a wafer. [Prior Art] With the advancement of semiconductor manufacturing technology and the increasing demand for thin and light electronic products, the reduction of the size of the chip package has become the main point of competition among manufacturers, from the previous monolithic chip package to multiple wafers. Packages, such as stacked wafer packages, reduce the area of the chip package on the printed circuit board. However, in order to balance the volume of the J-chip package and increase the function of the chip package, the most direct method is to stack more small-sized grains in the package, and the process capability of the wafer polishing directly affects the chip package. The number of layers of inner die stacking. The conventional wafer processing method flow, as shown in the figure, after the general wafer is subjected to the electrical power month & test, then enters the post-processing stage: first on the active side of the wafer (ie, including a plurality of grains) Attaching a protective tape (step sl〇) to one of the surfaces to protect the die on the active side of the circle; flipping the wafer 180 degrees and placing it on a grinding machine, so that the back side of the wafer faces - a grinding tool (step S12); then grinding the back side of the wafer to grind the thickness of the wafer to a predetermined thickness (step S14); then attaching a strip to the back side of the wafer - one of the frames in the annular opening (step S16); then flip the wafer again by 18 degrees to bring the active side up (step), then remove the protective tape on the active surface and place the wafer on the -cut rhyme Upper (step S20); finally, the wafer is diced into a plurality of dies by a cutting tool (step s22) for use in the post-packaging process. However, the protective tape used in the traditional wafer processing method has been unable to cope with the trend of thinner and thinner wafers. As the thinness of the wafer is reduced, the wafer is prone to be generated after grinding. 200834692 _ 曲 (Warpage) The phenomenon causes the wafer to be difficult to process in subsequent processes. In addition, due to the material and process characteristics of the protective tape, it is impossible to provide thin wafer support, and it is easy to cause damage to the edge of the wafer after polishing. In addition, when the conventional wafer is added with the method of removing the protective tape (De-taping), it is easy to damage the wafer due to the tearing action, which causes the wafer to be fragmented and cracked, and (4) the chip package is replaced in the future. Body (5):) Poor electrical connection, or debris on the wafer leads to grain contamination, etc., and the increase in scrap is added, and unnecessary costs are added invisibly. In addition, in the follow-up two-process, 'due to the material problem of the wafer itself, it is easy to cause the multi-layer test of the wafer (the (10)) is partially due to the action of the cutter, and the test of the secret is smashed and cut. It is brought to the active surface of the wafer by the rotation, causing grain contamination, scratching or abnormal connection between the grain and the grain or other problems such as 'foreign matter residue or soldering surface (4). SUMMARY OF THE INVENTION In order to solve the above problems, the object of the present invention is to provide a wafer processing method that replaces a conventional protective tape with a protective layer, and can omit the steps of attaching a protective adhesive to a wafer and removing the tape, which can be simplified. Wafer process. Another object of the present invention is to provide a wafer processing method for coating a protective layer on an active surface of a wafer, thereby avoiding the residual glue generated by the conventional attached protective tape and improving the existing wafer. Attaching protective tape and recording tape to the wafer, resulting in fragmentation. ~ ^ Another goal of this month is to provide a wafer processing method that uses the protective layer to replace the traditional tape and tape removal steps to protect wafer integrity and after wafer dicing Maintain the integrity of the die, thereby increasing the yield of the die and increasing product competitiveness.曰本U's purpose is to provide a wafer processing method, which can avoid the wafer due to the thickness reduction after polishing by the 4-inch support of the sound preservation. 6 200834692 v The problem of 'simultaneous' is easier to transport and transport without the production of wafer fun. For the extremely thinned wafers in the post-process, this April is aimed at providing a wafer processing method that provides a polished wafer during wafer dicing by applying a protective layer on the active side of the wafer. Active surface protection and branch building can avoid multi-layer testing of wafers due to cutting (4), while effectively avoiding grain contamination and unnecessary electrical connections and pre-consumption or corruption.
晶圓於一框架之一環狀開口内 為了達到上述目的’本發明之—實施例提供—種晶圓加 工方法，塗佈-保護層於-晶圓之—主動面上；固化保護層； 研磨晶圓之-背面；黏貼—切割膠帶於晶圓之背面，以固定 切割晶圓；及清洗晶圓。 以下藉由具體實施例酉己合所p付的圖式詳加說明，當更容易瞭解 本發明之目的、技躺容、特點及其職成之功效。 【實施方式】 明參閱第2圖’所示為依據本發明所實施一實施例之晶圓加工 方法々IL程示思圖。晶圓在完成晶圓階段之電性功能測試（wafer probing)以確保晶圓中每一晶粒（die)的品質與良率之後，隨即進 入後段加工的階段：首先將晶圓放置於一旋轉平台上，然後於晶圓之 主動面上噴灑一保護層材料，例如由特殊壓克力（aerylic)所構成， 接著叙轉此旋轉平台，使保護層材料均勻旋轉塗佈於主動面上以形成 一保護層，待保護層形成之後，加熱固化保護層使之具有一硬度（步 驟S100);接著將晶圓翻轉180度並放置於一研磨機台上，使得晶圓 之背面朝向一研磨具（步驟S102 );然後對晶圓之背面進行研磨步驟， 將晶圓的厚度研磨至預定厚度（步驟S104);接著黏貼一切割膠帶 (Dicing Tape)於晶圓之背面，以固定晶圓於一框架（frame)之 壞狀開口中（步驟S106)，以完成晶圓黏片（Wafer Mount) 7 200834692 的動作，其中，框架係用以避免切割膠帶皺摺；接續，將完 成晶圓黏片動作之晶圓再度翻轉180度，並放置已翻轉之晶 圓於一切割機台上（步驟S108)，使晶圓之主動面朝向一切 砉ij具’以俾利進彳亍切割動作（Wafer Die Saw )，將整片晶圓切 割為複數個晶粒（步驟S110)，其中，切割好之晶粒係黏著於切割膠 V上且固疋於環狀開口内；晶圓切割完畢後，進行清洗晶圓之動作， 將塗佈於晶圓主動面之保護層移除（步驟S112)，其係利用異丙醇 (IPA)專洗劑將保護層移除，待保護層移除完畢後，晶圓加工即完 成，可進入下一階段之封裝製程··將切割後之晶粒逐一吸起放至承載 件（如基板）上（Die Bond)、打線接合(Wire Bond )、封模（Molding)、 植球（Ball Mount)、單顆化（Singulation )、及包裝且運送（packing ancjThe wafer is in an annular opening of a frame for the above purpose. The present invention provides an embodiment of a wafer processing method, a coating-protective layer on a wafer-active surface, a cured protective layer, and a polishing process. Wafer-back; pasting—cutting tape on the back side of the wafer to securely cut the wafer; and cleaning the wafer. In the following, the detailed description of the specific embodiments of the present invention will be explained in detail, and the purpose of the present invention, the technical features, the features, and the functions of the functions will be more easily understood. [Embodiment] Referring to Fig. 2, there is shown a wafer processing method according to an embodiment of the present invention. After the wafer has completed the wafer probing to ensure the quality and yield of each die in the wafer, it then enters the post-processing stage: first place the wafer in a rotation On the platform, a protective layer material is sprayed on the active surface of the wafer, for example, by a special acilic, and then the rotating platform is rotated to uniformly apply the protective layer material on the active surface to form a protective layer, after the protective layer is formed, heat-curing the protective layer to have a hardness (step S100); then flipping the wafer 180 degrees and placing it on a polishing machine such that the back side of the wafer faces a polishing tool ( Step S102); then performing a grinding step on the back side of the wafer to grind the thickness of the wafer to a predetermined thickness (step S104); and then pasting a Dicing Tape on the back side of the wafer to fix the wafer in a frame In the bad opening of the (frame) (step S106), to complete the action of the wafer adhesive (Wafer Mount) 7 200834692, wherein the frame is used to avoid wrinkling of the cutting tape; The wafer of action is flipped again by 180 degrees, and the flipped wafer is placed on a cutting machine (step S108), so that the active surface of the wafer faces all the 砉 具 俾 俾 俾 ( ( ( ( ( ( ( ( ( ( ( ( ( Saw), cutting the entire wafer into a plurality of crystal grains (step S110), wherein the cut crystal grains are adhered to the cutting adhesive V and fixed in the annular opening; after the wafer is cut, the cleaning is performed. The operation of the wafer removes the protective layer applied to the active surface of the wafer (step S112), which removes the protective layer by using an isopropyl alcohol (IPA) specific lotion, and after the protective layer is removed, the crystal The round processing is completed, and the packaging process of the next stage can be entered. · The cut die is sucked up one by one onto the carrier (such as the substrate) (Die Bond), wire bonding (wire bonding), and Molding (Molding). , Ball Mount, Singulation, and packaging and shipping (packing ancj
Delivery)至使用者端。 表丁、合上述，本發明之晶圓加工方法係利用於晶圓主動面上塗佈 一保護層取代習知技術所使用之保護膠帶，保護層的設置可保護晶圓 主動面之複數個晶粒，戦在去除倾料義應力的影響而造成破 片、或於切割時污染晶粒、刮傷損壞銲墊（B〇nd pad)，造成晶圓良 率下降，可於曰曰圓切割時提供研磨後之晶圓主動面一保護與支撐，可 避免晶圓之多制試_蝴_落，而導致造成晶粒汙染及不必要 的電性連接和其他異物殘留或腐餘。藉由保護層的特性支撐曰曰曰圓，可 避免晶81目研磨後厚度降低而產生晶圓翹觸問題;因不產生晶圓想 曲的現象，晶圓可被研磨的更薄，而所切割出的晶粒厚度也更薄，可 以理解的，於後段晶片封裝製程中，同—封裝體中堆疊之晶粒數目也 將更多。本發明具有增加封裝體的魏及縮顿裝體的體積之優勢， 以創造更高之產品競爭力。 以上所述之實施例僅係為說明本發明之技術思想及特 點，其目的在使熟習此項技藝之人士能夠瞭解本發明之内容 並據以戶、靶，虽不月色以之限定本發明之專利範圍，即大凡依 8 200834692 ~ 本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本 V 發明之專利範圍内。 【圖式簡單說明】 第1圖所示為習知之晶圓加工方法流程示意圖。 第2圖所示為依據本發明所實施一實施例之晶圓加工方法流程示意 圖0Delivery) to the user side. In the above, the wafer processing method of the present invention utilizes a protective layer on the active surface of the wafer to replace the protective tape used in the prior art, and the protective layer is disposed to protect a plurality of crystals of the active surface of the wafer. Granules, strontium removes the influence of the tilting stress, causing fragmentation, or contaminating the grain during cutting, scratching the damaged pad (B〇nd pad), resulting in a decrease in wafer yield, which can be provided during the round cut After the grinding, the active surface of the wafer is protected and supported, which can avoid the excessive test of the wafer, which leads to grain contamination and unnecessary electrical connection and other foreign matter residue or corrosion. By supporting the roundness of the protective layer, it is possible to avoid wafer scratching caused by the thickness reduction of the crystal 81 after polishing; the wafer can be polished thinner without causing the wafer to be bent. The thickness of the cut grains is also thinner. It can be understood that in the latter stage of the chip packaging process, the number of crystal grains stacked in the same package will be more. The present invention has the advantage of increasing the volume of the package and the shrinkage of the package to create a higher product competitiveness. The embodiments described above are merely illustrative of the technical idea and features of the present invention, and the purpose of the present invention is to enable those skilled in the art to understand the contents of the present invention and to define the present invention. The scope of the patent, i.e., the equivalent variation or modification of the spirit of the present invention, which is disclosed in the present invention, should still be covered by the scope of the patent of the present invention. [Simple description of the drawing] Fig. 1 is a schematic flow chart of a conventional wafer processing method. 2 is a flow chart showing a wafer processing method according to an embodiment of the present invention.
【主要元件符號說明】 S10、S12、S14、S16、S18、S20、步驟 S22 S100、S102、S104、S106、S108、步驟 S110、S112[Description of main component symbols] S10, S12, S14, S16, S18, S20, steps S22 S100, S102, S104, S106, S108, steps S110, S112