200826232 93053 21740twf.doc/n 九、發明說明： 【發明所屬之技術領域】 3本發明是有關於-種金屬内連線的製作方法，且特別 是有關於-種接觸窗開π與金屬插塞的製作方法。 【先前技術】 在半導體的製程中，元件的尺寸不斷地微縮，因此， 姓，選擇性與均勻度將變得更為重要。隨著元件尺寸的愈 來愈小，造成内連線之接觸窗深寬比不斷地增加，使得微 心‘私的困難度也持續提高，造成元件尺寸的控制益形困 難。 為了解決此問題，目前的半導體製程大都是使用多晶 石夕的材料來取代製作接觸窗之光阻，以做為硬罩幕。與光 阻相比夕曰曰矽硬罩幕具有較強的抗蝕刻能力，因此能夠 在钱刻製程中更精確地完成各階段的随化製程。 圖1Α至圖1Β為習知一種接觸窗開口的製作流程剖面 圖。 、凊簽照圖1Α，首先，提供基底1〇〇。基底1〇〇上已形 成有閘極結構102。然後，於基底1〇〇上依序形成介電層 1〇4、多晶石夕硬罩幕層1〇6。繼之以多晶石夕硬罩幕層则 為姓刻罩幕，去除部份介電層104以形成開π 108，並暴 露基底100。 ★再來，請參照圖1Β，於開口 108表面以及多晶矽硬 ，幕層106上形成阻障層11〇。阻障層11〇通常是由欽金 屬層112與氮化鈦層114構成。 5 200826232 93053 21740twf.doc/n 然而’欽金屬層112會與多晶梦硬罩幕層106相互反 應而於其界面處形成砍化欽。由於多晶砍硬罩幕層的 晶粒尺寸粗大的物理特性，因此，存在於多晶矽硬罩幕層 106表面的石夕化鈦並不均勻（N〇n-Uniform)。此不均勻的梦 化鈦在後續的平坦化製程中不易被完全移除。而殘留的石夕 化鈦可能會使導線與導線間連通而導致漏電情況發生。 【發明内容】 f200826232 93053 21740twf.doc/n IX. Description of the invention: [Technical field to which the invention pertains] 3 The present invention relates to a method for fabricating a metal interconnect, and particularly relates to a contact window opening π and a metal plug Production method. [Prior Art] In the process of semiconductors, the size of components is constantly reduced, so the surname, selectivity and uniformity will become more important. As the size of the component becomes smaller and smaller, the aspect ratio of the contact line of the interconnect is continuously increased, so that the degree of difficulty of the core is continuously increased, and the control of the component size is difficult. In order to solve this problem, most of the current semiconductor processes use polycrystalline materials to replace the photoresist of the contact window as a hard mask. Compared with the photoresist, the hard mask has strong etching resistance, so it can complete the process of the stages more accurately in the process of engraving. 1A to 1B are cross-sectional views showing a manufacturing process of a contact window opening.凊 凊 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图 图A gate structure 102 has been formed on the substrate 1A. Then, a dielectric layer 1〇4 and a polycrystalline hard mask layer 1〇6 are sequentially formed on the substrate 1〇〇. A polycrystalline stone hard mask layer is followed by a mask for the surname, and a portion of the dielectric layer 104 is removed to form an opening π 108, and the substrate 100 is exposed. ★ Again, please refer to FIG. 1A, and a barrier layer 11〇 is formed on the surface of the opening 108 and the polycrystalline crucible and the curtain layer 106. The barrier layer 11 is usually composed of a chelating layer 112 and a titanium nitride layer 114. 5 200826232 93053 21740twf.doc/n However, the 'metal layer 112' will react with the polycrystalline dream hard mask layer 106 to form a chopping at its interface. Due to the coarse physical properties of the polycrystalline hard mask layer, the titanium oxide present on the surface of the polysilicon hard mask layer 106 is not uniform (N〇n-Uniform). This uneven dreaming titanium is not easily removed completely in the subsequent planarization process. The residual titanium oxide may cause the wire to communicate with the wire to cause leakage. SUMMARY OF THE INVENTION f
有鑑於此，本發明的目的就是在提供一種接觸窗開口 的製造方法，此方法能完全移除矽化鈦，以避免因矽化鈦 殘留所造成之漏電現象。 本發明的另一目的就是在提供一種金屬插塞的製造 方法，此方法能完全移除矽化鈦，以避免因矽化鈦殘留所 造成之漏電現象。 本叙明的目的就是在提供一種接觸窗開口的製作方 法，此方法包括T解驟。首先，提供基底，此基底上已 形成有介電層。織，於介電層上形成非糾硬罩幕層， 2露出介電層。接著’財晶㈣罩幕層職刻罩幕， =暴^之介電層’以形賴口。繼之， 盍開口表面。 方轉日㈣難實施朗叙制㈣口的製造 介，〗，成ί電層的步驟包括先於基底上形成第〆 後’於第一介電層上形成第二介電層。 U本發明實施例所述之接觸窗開口的製造 ' 处之弟一介電層的材質包括硼磷矽玻璃 6 200826232 93053 21740twf.doc/n (Borophosphosilicate Glass，BPSG)。 依照本發明的較佳實施例所述之接觸窗開口的製造 方法’上述之形成第一介電層的方法包括化學氣相沉積法。 依照本發明的較佳實施例所述之接觸窗開口的製造 方法，上述之第二介電層的材質包括以四乙基矽烷 (Tetraeth〇xysilane，TEOS)為反應氣體源所形成之氧化物。 依照本發明的較佳實施例所述之接觸窗開口的製造In view of the above, it is an object of the present invention to provide a method of manufacturing a contact opening which completely removes titanium telluride to avoid leakage due to titanium halide residue. Another object of the present invention is to provide a method of manufacturing a metal plug which can completely remove titanium telluride to avoid leakage due to residual titanium halide. The purpose of this description is to provide a method of making a contact opening that includes a T-solution. First, a substrate is provided on which a dielectric layer has been formed. Weaving, forming a non-hardened mask layer on the dielectric layer, 2 exposing the dielectric layer. Then the 'Caijing (4) mask layer engraved the mask, = the dielectric layer of the violent ^'s shape. Then, lick the opening surface. It is difficult to implement the production of the syllabary (4). The step of forming the electrical layer includes forming a second dielectric layer on the first dielectric layer before forming a second layer on the substrate. U. The fabrication of the contact opening described in the embodiment of the invention is based on the material of the dielectric layer comprising borophosphophosphorus glass 6 200826232 93053 21740 twf.doc/n (Borophosphosilicate Glass, BPSG). A method of fabricating a contact opening according to a preferred embodiment of the present invention. The method of forming the first dielectric layer described above includes chemical vapor deposition. According to a method of fabricating a contact opening according to a preferred embodiment of the present invention, the material of the second dielectric layer comprises an oxide formed by using Tetraeth(R) xysilane (TEOS) as a reactive gas source. Manufacture of contact window openings in accordance with a preferred embodiment of the present invention
方法’上述之形成第二介電層的方法包括化學氣相沉積法。 依照本發明的較佳實施例所述之接觸窗開口的製造方 法，上述之形成非晶矽硬罩幕層的方法包括化學氣相沉積 法。 依照本發明的較佳實施例所述之接觸窗開口的製造 方法上述之形成阻障層的步驟包括先於非晶石夕硬罩幕層 與開口表面形成鈦金屬層。然後，於鈦金屬層上形成氮^匕 本發明的再一目的是提供一種金屬插塞的製作方 ΐΐϋ法包括下列步驟。首先，提絲底，此基底上已 形成^介電層。然後，於介電層上形成非轉硬罩幕層， 以暴露出介電層。縣，以非晶⑪硬罩幕層㈣刻罩^， 去除暴露出之介電層，以形成開口。接著， 蓋開口表面和非晶轉罩幕層。錢’於基底 層並填滿開口。接著，對金屬層進行第—抑化^至屬 去除開Π以外的金屬層。最後，進行第二平 ^ ’以 去除部份阻障層與非結晶硬罩幕層。 衣私’以 7 200826232 93053 21740twf.doc/n 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之形成介電層的步驟包括先於基底上形成第一介 電層。然後，於第一介電層上形成第二介電層。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之第一介電層的材質包括硼磷矽玻璃。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之形成第一介電層的方法包括化學氣相沉積法。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之第二介電層的材質包括以四乙基矽烷為反應氣 體源所形成之氧化物。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之形成第二介電層的方法包括化學氣相沉積法。 依照本發明的較佳實施例所述之金屬插塞的製造方 上述之形成非結晶硬罩幕層的方法包括化學氣相沉積 法。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之形成阻障層的步驟包括先於非晶矽硬罩幕層與 開口表面形成鈦金屬層。然後，於鈦金屬層上形成氮化鈦 層。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之金屬層的材質包括鎢。 依照本發明的較佳實施例所述之金屬插塞的製造方 法’上述之第一平坦化製程包括化學機械研磨法。 依照本發明的較佳實施例所述之金屬插塞的製造方 8 200826232 93053 21740twf.doc/n 法，上述之第二平坦化製程包括化學機械研磨法。 本發明之金屬插塞的製造方法，是以非晶矽層作為硬 罩幕層。與多晶矽層相比，由於非晶矽層的晶粒尺寸相對 較小’因此，於鈦金屬層與非晶矽硬罩幕層界面間將形成 均勻（Uniform)的矽化鈦層。於後續的平坦化製程中，此矽 化鈦層將可被完全移除，因而避免了漏電現象的發生。 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 圖2A至圖2G為依照本發明較佳實施例所繪示之金屬 插塞製造的流程剖面示意圖。 首先，請參照圖2A，提供基底200，此基底200例如 是矽基底。在基底200上已形成多數個閘極結構202，其 由閘極介電層204、閘極導體層206以及頂蓋層208所構 成。閘極介電層204的材質例如是氧化矽，其形成方法例 如是熱氧化法。閘極導體層206例如是由多晶矽層與金屬 矽化物層所組成，其形成方法例如是化學氣相沉積法。頂 盖層208的材質例如是氮化發。 接著’清參照圖2B，在基底200上形成一層第一介 電層210。第一介電層210的材質例如是硼磷矽玻璃，其 形成方法例如是化學氣相沉積法。然後，經化學機械研磨 法平坦化後之第一介電層210上形成一層第二介電層 212。第一介電層212的材質例如是以四乙基矽烷為反應氣 9 200826232 ^3053 21740twf.doc/n 體源所形成之氧化物，其形成方法例如是化學氣相沉積法。 之後，請參照圖2C，在第二介電層212上形成一層 非曰a石夕硬罩幕層214’其形成方法例如是化學氣相沉積法。 再來，請參照圖2D，於非晶矽硬罩幕層214上形成 圖案化光阻層（未繪示）。以圖案化光阻層為罩幕，移除部 份非晶矽硬罩幕層214,直到暴露出第二介電層212，而形 成非晶砍硬罩幕層214a。 ( 繼之，請繼續參照圖2D，以非晶矽硬罩幕層214a為 罩幕，移除部分第二介電層212以及部分第一介電層21〇, 直到曝露基底200，而形成圖案化之第二介電層2i2a以及 弟’丨層210a並形成開口 216。 然後，請參照圖2E，於開口 216表面以及非晶石夕硬罩 幕層214a表面形成一層阻障層218。阻障層218的形成方 法例如是先於開口 216表面以及圖案化之非晶石夕硬罩幕層 214a表面形成一層鈦金屬層22〇，接著，形成一層氮化鈦 層222共形覆蓋鈦金屬層22〇。而形成鈦金屬層22〇與氮 C 化鈦層222的方法大多係利用氮化反應法或是反應性濺鍍 法。鈦金屬層220會與非晶石夕硬罩幕層214a反應形成均勻 的矽化鈦層。在後續的平坦化製程中，此矽化鈦層可被完 全移除’因此避免了可能產生之導線與導線間導通的問題。 接著，請參照圖2F，於基底200上形成一層金屬層 224並填滿開口 216。其中，金屬層224之材質可為鋁或鎢， 較佳者為鎢。而形成金屬層224之方法例如是化學氣相沉 積法。 200826232 93053 21740twf.doc/n 然後、’請繼續參照圖2F，進行第一平坦化製程，移除 ^ s 216以外的部份金屬層。平坦化金屬層似的方法例 如疋化學機械研磨法。 繼之，請參照圖2G，進行第二平坦化製程，移 份阻障層218以及非晶石夕硬罩幕層214a。第二平坦化製程 例如是化學機械研磨法。 ^ fMethod The method of forming the second dielectric layer described above includes chemical vapor deposition. In accordance with a method of fabricating a contact opening according to a preferred embodiment of the present invention, the method of forming an amorphous germanium hard mask layer comprises a chemical vapor deposition method. The method of fabricating a contact opening according to a preferred embodiment of the present invention comprises the step of forming a barrier layer comprising forming a titanium metal layer prior to the amorphous hard mask layer and the open surface. Then, formation of nitrogen on the titanium metal layer. A further object of the present invention is to provide a method for fabricating a metal plug comprising the following steps. First, a silicon substrate has a dielectric layer formed on the substrate. A non-rotating hard mask layer is then formed over the dielectric layer to expose the dielectric layer. In the county, the amorphous 11 hard mask layer (four) is masked to remove the exposed dielectric layer to form an opening. Next, cover the open surface and the amorphous turn mask layer. Money' is on the base layer and fills the opening. Next, the metal layer is first-inhibited to a metal layer other than the opening. Finally, a second flattening is performed to remove portions of the barrier layer and the amorphous hard mask layer. The method of forming a metal plug according to a preferred embodiment of the present invention is as follows. The step of forming a dielectric layer includes forming a first dielectric layer on a substrate. Then, a second dielectric layer is formed on the first dielectric layer. A method of manufacturing a metal plug according to a preferred embodiment of the present invention. The material of the first dielectric layer includes borophosphon glass. A method of fabricating a metal plug according to a preferred embodiment of the present invention. The method of forming the first dielectric layer described above includes chemical vapor deposition. A method of fabricating a metal plug according to a preferred embodiment of the present invention The material of the second dielectric layer described above comprises an oxide formed by using tetraethyl decane as a source of a reactive gas. A method of fabricating a metal plug according to a preferred embodiment of the present invention. The method of forming the second dielectric layer described above includes chemical vapor deposition. Manufacture of a Metal Plug According to a Preferred Embodiment of the Invention The above method of forming an amorphous hard mask layer includes a chemical vapor deposition method. The method of fabricating a metal plug according to a preferred embodiment of the present invention comprises the step of forming a barrier layer comprising forming a titanium metal layer adjacent to the surface of the opening of the amorphous hard mask layer. Then, a titanium nitride layer is formed on the titanium metal layer. A method of manufacturing a metal plug according to a preferred embodiment of the present invention. The material of the metal layer described above includes tungsten. A method of manufacturing a metal plug according to a preferred embodiment of the present invention' The first planarization process described above includes a chemical mechanical polishing process. According to a method of manufacturing a metal plug according to a preferred embodiment of the present invention, the second flattening process described above includes a chemical mechanical polishing method. The metal plug of the present invention is produced by using an amorphous germanium layer as a hard mask layer. Since the grain size of the amorphous germanium layer is relatively small compared to the poly germanium layer, a uniform (former) titanium telluride layer is formed between the titanium metal layer and the amorphous germanium hard mask layer interface. In the subsequent planarization process, the titanium-titanium layer will be completely removed, thus avoiding leakage. The above and other objects, features and advantages of the present invention will become more <RTIgt; 2A to 2G are schematic cross-sectional views showing the manufacture of a metal plug according to a preferred embodiment of the present invention. First, referring to Fig. 2A, a substrate 200 is provided, such as a substrate. A plurality of gate structures 202 have been formed on the substrate 200, which are comprised of a gate dielectric layer 204, a gate conductor layer 206, and a cap layer 208. The material of the gate dielectric layer 204 is, for example, ruthenium oxide, and the formation method is, for example, a thermal oxidation method. The gate conductor layer 206 is composed of, for example, a polysilicon layer and a metal halide layer, and is formed by, for example, a chemical vapor deposition method. The material of the cap layer 208 is, for example, a nitrided hair. Next, referring to FIG. 2B, a first dielectric layer 210 is formed on the substrate 200. The material of the first dielectric layer 210 is, for example, borophosphon glass, and the formation method thereof is, for example, chemical vapor deposition. Then, a second dielectric layer 212 is formed on the first dielectric layer 210 which is planarized by chemical mechanical polishing. The material of the first dielectric layer 212 is, for example, an oxide formed by tetraethyl decane as a reaction gas, which is formed by a chemical vapor deposition method, for example. Thereafter, referring to FIG. 2C, a non-曰a stone mask layer 214' is formed on the second dielectric layer 212, and the formation method thereof is, for example, a chemical vapor deposition method. Referring to FIG. 2D, a patterned photoresist layer (not shown) is formed on the amorphous hard mask layer 214. With the patterned photoresist layer as a mask, a portion of the amorphous hard mask layer 214 is removed until the second dielectric layer 212 is exposed to form an amorphous hard mask layer 214a. (Continuously, referring to FIG. 2D, a portion of the second dielectric layer 212 and a portion of the first dielectric layer 21 are removed by using the amorphous hard mask layer 214a as a mask until the substrate 200 is exposed to form a pattern. The second dielectric layer 2i2a and the second layer 210a are formed and an opening 216 is formed. Then, referring to FIG. 2E, a barrier layer 218 is formed on the surface of the opening 216 and the surface of the amorphous hard mask layer 214a. The layer 218 is formed by, for example, forming a titanium metal layer 22 先 on the surface of the opening 216 and the surface of the patterned amorphous hard mask layer 214a, and then forming a titanium nitride layer 222 conformally covering the titanium metal layer 22 The method of forming the titanium metal layer 22 and the titanium C titanium oxide layer 222 is mostly by a nitridation reaction method or a reactive sputtering method. The titanium metal layer 220 is formed by reacting with the amorphous stone hard mask layer 214a. Uniform titanium oxide layer. In the subsequent planarization process, the titanium telluride layer can be completely removed' thus avoiding the problem of possible conduction between the wires and the wires. Next, please refer to FIG. 2F to form on the substrate 200. A layer of metal 224 fills the opening 216. The material of the metal layer 224 may be aluminum or tungsten, preferably tungsten. The method of forming the metal layer 224 is, for example, chemical vapor deposition. 200826232 93053 21740twf.doc/n Then, 'Please continue to refer to FIG. 2F, Performing a first planarization process to remove portions of the metal layer other than ^ s 216. A method of planarizing the metal layer is performed, for example, a chemical mechanical polishing method. Next, referring to FIG. 2G, performing a second planarization process, shifting The barrier layer 218 and the amorphous hard mask layer 214a. The second planarization process is, for example, a chemical mechanical polishing method.
综上所述，本發明之金屬插塞的製造方法，是以非晶 石夕層作為硬罩幕層。與多轉層相比，由於非轉層的晶 粒尺寸相對較*，因此，於鈦金屬層與非砂硬罩幕層界 面上將形成均勻的魏鈦層。於後續的平坦化製程中，此 石夕化鈦層將可被完全歸，因而避免了漏電現象的產生。 〜雖然本發明已讀佳實闕揭露如上，然其並非用以 限)本發明，任何熟習此技藝者，在不麟本發明之精神 ^範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1A至圖1B為習知一種接觸窗開口的製作流程剖面 圖。 圖2A至圖2G為依照本發明較佳實施例所緣示之金屬 插塞的製造流程剖面示意圖。 【主要元件符號說明】 100、200 :基底 102、202 :閘極結構 104 :介電層 π 200826232 93053 21740twf.doc/n 106 :多晶矽硬罩幕層 108、216 :開口 110、218 :阻障層 112、220 :鈦金屬層 114、222 ·•氮化鈦層 204 ··閘極介電層 206 :閘極導體層 208 :頂蓋層 210 :第一介電層 210a :圖案化之第一介電層 212 :第二介電層 212a ··圖案化之第二介電層 214、214a :非晶矽硬罩幕層 224 :金屬層In summary, the method for manufacturing the metal plug of the present invention is to use an amorphous layer as a hard mask layer. Since the non-transformed crystal grain size is relatively * compared to the multi-transformed layer, a uniform Wei-Ti layer is formed on the interface between the titanium metal layer and the non-sand hard mask layer. In the subsequent planarization process, the Titanization Titanium layer can be completely returned, thus avoiding the occurrence of leakage. Although the present invention has been described above, it is not intended to limit the invention, and anyone skilled in the art can make some modifications and refinements within the scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to Fig. 1B are cross-sectional views showing a manufacturing process of a contact window opening. 2A through 2G are schematic cross-sectional views showing a manufacturing process of a metal plug according to a preferred embodiment of the present invention. [Main component symbol description] 100, 200: substrate 102, 202: gate structure 104: dielectric layer π 200826232 93053 21740twf.doc/n 106: polysilicon hard mask layer 108, 216: opening 110, 218: barrier layer 112, 220: titanium metal layer 114, 222 · titanium nitride layer 204 · gate dielectric layer 206: gate conductor layer 208: cap layer 210: first dielectric layer 210a: patterned first Electrical layer 212: second dielectric layer 212a · patterned second dielectric layer 214, 214a: amorphous hard mask layer 224: metal layer