KR20000061705A - Manufacturing Method of Semiconductor Device - Google Patents
Manufacturing Method of Semiconductor Device Download PDFInfo
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- KR20000061705A KR20000061705A KR1019990010958A KR19990010958A KR20000061705A KR 20000061705 A KR20000061705 A KR 20000061705A KR 1019990010958 A KR1019990010958 A KR 1019990010958A KR 19990010958 A KR19990010958 A KR 19990010958A KR 20000061705 A KR20000061705 A KR 20000061705A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
본 발명은 반도체장치의 제조방법에 관한 것으로서, 특히, 추가 열처리 공정이 필요 없는 메탈 실리사이드(Metal Silicide) 콘택을 형성할 수 있는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of forming a metal silicide contact without requiring an additional heat treatment process.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art.
도 1a를 참조하면, 반도체기판(11)내에 STI(Shallow Trench Isolation)방법으로 형성된 소자격리막(15)과 이온주입방법으로 불순믈이 도핑된 액티브 영역(18)이 형성된다. 이어서 층간 절연층으로 두꺼운 두께의 CVD 실리콘산화막(SiO2)(21)이 증착 형성된다.Referring to FIG. 1A, a device isolation film 15 formed by a shallow trench isolation (STI) method and an active region 18 doped with impurities by an ion implantation method are formed in a semiconductor substrate 11. Subsequently, a thick CVD silicon oxide film (SiO 2 ) 21 is deposited by an interlayer insulating layer.
도 1b를 참조하면, 실리콘산화막(SiO2)(21)상에 리소그래피 방법으로 레지스트 막(101)을 패터닝한다Referring to FIG. 1B, a resist film 101 is patterned on a silicon oxide film (SiO 2 ) 21 by a lithography method.
도 1c를 참조하면, 패터닝된 레지스트 막(101)을 마스크로 하여 실리콘산화막(SiO2)(21)을 플라즈마 RIE(Reactive Ion Etching)방법으로 제거하여 불순물이 도핑된 반도체 기판의 실리콘(Silicon)을 노출시킨다. 그 후 레지스트 막(101)을 제거한다.Referring to FIG. 1C, a silicon oxide film (SiO 2 ) 21 is removed by a plasma reactive ion etching (RIE) method using a patterned resist film 101 as a mask to remove silicon of a semiconductor substrate doped with impurities. Expose Thereafter, the resist film 101 is removed.
도 1d를 참조하면, 반도체 기판을 세정한 후 반도체기판(11)의 전체 표면에 스퍼터(Sputter)방법으로 얇은 Ti(Titanium)(23) / TiN (Titanium Nitride)막(25)을 증착한다.Referring to FIG. 1D, a thin Ti (Titanium) 23 / TiN (Titanium Nitride) film 25 is deposited on the entire surface of the semiconductor substrate 11 by the sputtering method.
상기에서 Ti(Titanium)(23)은 스퍼터링(Sputtering)장비에서 타겟 물질(Target Material)로 순도 99.999%의 Ti를 챔버 온도 200 ~300℃에서 아르곤(Argon)가스로 스퍼터링하여 두께 100Å 정도의 티타니윰(Titanium)을 불순믈이 도핑된 액티브 영역(18) 및 실리콘산화막(SiO2)(21a)상에 증착한다. 이어서 같은 쳄버에서 타겟 물질(Target Material)로 순도 99.999%의 Ti를 챔버 온도 200 ~300℃에서 질소(N2)가스로 스퍼터링하여 두께 400Å 정도의 질화 티타니윰(Titanium Nitride)(25)을 Ti(Titanium)(23)상에 증착한다.In the above, Ti (Titanium) (23) is sputtered (Tiger) in the sputtering equipment (Target Material) of 99.999% of the purity of the Ti to the thickness of 100 곤 by sputtering with Argon gas at 200 ~ 300 ℃ Titanium is deposited on the impurity doped active region 18 and silicon oxide film (SiO 2 ) 21a. Subsequently, a titanium nitride (25) having a thickness of about 400 mm was sputtered by sputtering 99.999% of Ti as a target material with nitrogen (N 2 ) gas at a chamber temperature of 200 to 300 ° C. in the same chamber. (Titanium) (23) is deposited.
도 1e를 참조하면, 반도체 기판을 600℃ 이상의 고온 RTP(Rapid Thermal Processing) 또는 통상의 열처리 공정으로 Ti(Titanium)(23)을 기판(11)인 실리콘(Silicon)과의 열적반응으로 저저항의 티타늄 실리사이드(Titanium Silicide, TiSix)(27)를 형성한다.Referring to FIG. 1E, the semiconductor substrate is subjected to a low resistance by thermal reaction with Ti (Titanium) 23 with silicon, which is the substrate 11, by a high temperature rapid thermal processing (RTP) or a general heat treatment process of 600 ° C. or higher. Titanium Silicide (TiSi x ) 27 is formed.
상기에서 실리콘(Silicon)과의 열적반응으로 변환된(Transformed) 티타늄 실리사이드(Titanium Silicide)(27)는 두께 250Å 정도의 TiSix로 실리콘(Silicon)과의 계면(Interface)보다 낮은 곳에서 형성된다. TiSix의 형성공정시 실리콘(Silicon) 기판내의 실리콘 원자(Atoms)들의 공핍(Depletion)을 가져오며, Ti(Titanium)(23)의 TiSix으로의 상변태시 체적 축소(Volume Shrinkage)를 가져온다.Titanium Silicide 27, which is transformed by thermal reaction with silicon, is formed at a lower thickness than the interface with silicon with TiSi x having a thickness of about 250 microns. In the formation process of TiSi x , depletion of silicon atoms (Atoms) in a silicon substrate is brought about, and volume shrinkage is caused in the phase transformation of Ti (Titanium) 23 to TiSi x .
도 1f를 참조하면, 반도체 기판상에 두꺼운 두께의 CVD 텅스텐(Tungsten)(30)을 증착 형성한다. 이후 CMP(Chemical Mechanical Polishing)방법으로 실리콘산화막(SiO2)(21a)상의 텅스텐 (Tungsten)(30) 및 TiN(Titanium Nitride)막(25) 및 Ti(Titanium)(23)을 제거하여 플러그(Plug)(도시 안 함)를 형성하고, 이후 공정(Subsequent Processing)에서 메탈라인(Metal Line)을 패터닝힌다(도시 안 함). 상기 플러그로 불순물이 도핑된 액티브 영역(18)과 메탈라인을 전기적으로 연결한다.Referring to FIG. 1F, a thick CVD tungsten 30 is deposited on a semiconductor substrate. Thereafter, the plug is removed by removing the tungsten 30, the titanium nitride (25), and the titanium (23) from the silicon oxide film (SiO 2 ) 21a by the chemical mechanical polishing (CMP) method. (Not shown), and then metal lines (metal lines) in the subsequent processing (Subsequent Processing) (not shown). The plug electrically connects the active region 18 doped with impurities to the metal line.
상술한 종래 기술은 티타늄 실리사이드(Titanium Silicide)(27)의 상변태시 도펀트(Dopant)들의 외부 확산(Out Diffusion)이 발생되어 액티브 콘택 저항의 증가를 가져오며 또한 체적 축소(Volume Shrinkage)로 인한 액티브 영역의 정션(Junction)에서 누설 전류(Leakage Current)의 증가를 가져오는 등의 문제점이 있었다.In the above-described conventional technique, out diffusion of dopants occurs during phase transformation of titanium silicide 27, resulting in an increase in active contact resistance, and also an active region due to volume shrinkage. There was a problem such as an increase in leakage current at the junction of the junction.
따라서, 본 발명의 목적은 추가 열처리 공정이 필요 없는 저저항의 메탈 실리사이드(Metal Silicide) 콘택을 형성할 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of forming a low resistance metal silicide contact without the need for an additional heat treatment process.
상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 소자격리층이 형성된 반도체 기판내에 불순물이 도핑된 확산층을 형성하는 공정과, 상기 반도체 기판상에 절연층을 형성하는 공정과, 상기 절연층내에 콘택홀을 형성하여 상기 확산층을 노출시키는 공정과, PVD 방법으로 메탈 실리사이드(Metal Silicide)층을 상기 확산층 및 상기 절연층상에 형성하는 공정과, 상기 메탈 실리사이드(Metal Silicide)층상에 메탈 나이트라이드(Metal Nitride)층을 형성하는 공정과, 상기 반도체 기판상에 금속층으로 상기 콘택홀을 충진(Gap Filling)하는 공정을 구비한다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a diffusion layer doped with an impurity in a semiconductor substrate having a device isolation layer, forming an insulating layer on the semiconductor substrate, and the insulation Forming a contact hole in the layer to expose the diffusion layer, forming a metal silicide layer on the diffusion layer and the insulating layer by PVD, and metal nitride on the metal silicide layer Forming a (metal nitride) layer; and filling the contact hole with a metal layer on the semiconductor substrate.
도 1a 내지 도 1f는 종래 기술에 따른 반도체장치의 제조공정도이다.1A to 1F are manufacturing process diagrams of a semiconductor device according to the prior art.
도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조공정도이다.2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f는 본 발명에 따른 반도체장치의 제조공정도이다.2A to 2F are manufacturing process diagrams of a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체기판(111)내에 STI(Shallow Trench Isolation)방법으로 형성된 소자격리막(115)과 이온주입방법으로 불순믈이 도핑된 액티브 영역(118)이 형성된다. 이어서 층간 절연층으로 두꺼운 두께의 CVD 실리콘산화막(SiO2)(121)이 증착 형성된다.Referring to FIG. 2A, an isolation layer 115 formed by a shallow trench isolation (STI) method and an active region 118 doped with impurities by an ion implantation method are formed in the semiconductor substrate 111. Subsequently, a thick CVD silicon oxide film (SiO 2 ) 121 is deposited as an interlayer insulating layer.
도 2b를 참조하면, 실리콘산화막(SiO2)(121)상에 리소그래피 방법으로 레지스트 막(201)을 패터닝한다Referring to FIG. 2B, a resist film 201 is patterned on a silicon oxide film (SiO 2 ) 121 by a lithography method.
도 2c를 참조하면, 패터닝된 레지스트 막(201)을 마스크로 하여 실리콘산화막(SiO2)(121)을 플라즈마 RIE(Reactive Ion Etching)방법으로 제거하여 불순물이 도핑된 반도체 기판의 실리콘(Silicon)을 노출시킨다. 그 후 레지스트 막(201)을 제거한다.Referring to FIG. 2C, a silicon oxide film (SiO 2 ) 121 is removed by a plasma reactive ion etching (RIE) method using a patterned resist film 201 as a mask to remove silicon of a semiconductor substrate doped with impurities. Expose Thereafter, the resist film 201 is removed.
도 2d를 참조하면, 반도체 기판을 세정한 후 반도체기판(111)의 전체 표면에 스퍼터(Sputter)방법으로 얇은 TiSi2(Titanium Silicide)(123) 을 증착한다.Referring to FIG. 2D, a thin TiSi 2 (Titanium Silicide) 123 is deposited on the entire surface of the semiconductor substrate 111 by the sputtering method after cleaning the semiconductor substrate.
상기에서 TiSi2(Titanium Silicide)(123)은 PVD(Physical Vapor Deposition) 장비에서 TiSi2(Titanium Silicide)조성의 타겟 물질(Target Material)로 고온 기판 가열 방법으로 기판 온도 500 ~800℃ 에서 아르곤(Argon)가스로 스퍼터링하여 두께 250Å 정도의 TiSi2(Titanium Silicide)(123)을 불순믈이 도핑된 액티브 영역(118) 및 실리콘산화막(SiO2)(121a)상에 증착한다. TiSi2(Titanium Silicide)조성의 타겟 물질(Target Material)대신에 텅스텐 실리사이드 (WSi), 탄탈리움 실리사이드(TaSi2), 코발트 실리사이드(CoSi2)의 타겟 물질들에서 선택하여 증착 형성할 수 있다.In the above, TiSi 2 (Titanium Silicide) 123 is a target material of TiSi 2 (Titanium Silicide) composition in PVD (Physical Vapor Deposition) equipment, and is heated at a substrate temperature of 500 to 800 ° C. by argon at a substrate temperature of 500 to 800 ° C. Sputtering with a gas to deposit TiSi 2 (Titanium Silicide) 123 having a thickness of about 250 Å on the impurity doped active region 118 and the silicon oxide film (SiO 2 ) 121a. Instead of a target material of TiSi 2 (Titanium Silicide) composition, a target material of tungsten silicide (WSi), tantalum silicide (TaSi 2 ), and cobalt silicide (CoSi 2 ) may be selected for deposition.
도 2e를 참조하면, TiSi2(Titanium Silicide)(123)상에 스퍼터(Sputter)방법으로 얇은 질화 티타니윰(Titanium Nitride)(125)을증착한다.Referring to FIG. 2E, a thin titanium nitride 125 is deposited on a TiSi 2 (Titanium Silicide) 123 by a sputtering method.
상기에서 질화 티타니윰(Titanium Nitride)(125)은 도 2d에서 언급된 같은 장비에서 타겟 물질(Target Material)로 순도 99.999%의 Ti를 챔버 온도 200 ~300℃에서Titanium Nitride (125) in the above is a target material in the same equipment mentioned in Figure 2d (Ti) with a purity of 99.999% Ti at the chamber temperature of 200 ~ 300 ℃
질소(N2)가스로 스퍼터링하여 두께 400Å 정도의 질화 티타니윰(Titanium Nitride)(125)을 TiSi2(Titanium Silicide)(123)상에 증착한다.By sputtering with nitrogen (N 2 ) gas, titanium nitride (Titanium Nitride) 125 having a thickness of about 400 mm is deposited on TiSi 2 (Titanium Silicide) 123.
질화 티타니윰(Titanium Nitride)(125) 대신에 텅스텐 나이트라이드 (WN), 탄탈리움 나이트라이드(TaN), 코발트 나이트라이드(CoN)들 중에서 선택할 수 있다.Instead of titanium nitride 125, tungsten nitride (WN), tantalum nitride (TaN), and cobalt nitride (CoN) may be selected.
도 2f를 참조하면, 반도체 기판상에 두꺼운 두께의 CVD 텅스텐(Tungsten)(130)을 증착 형성한다.Referring to FIG. 2F, a thick CVD tungsten 130 is deposited on a semiconductor substrate.
상기에서 텅스텐(Tungsten)(130) 대신에 알루미늄(Aluminum, Aluminium Alloy), 구리 (Copper)들 중에서 선택할 수 있다.Instead of tungsten 130, it may be selected from aluminum (Aluminum, Aluminum Alloy) and copper (Copper).
이후 CMP(Chemical Mechanical Polishing)방법으로 실리콘산화막(SiO2)(121a)상의 텅스텐 (Tungsten)(130) 및 TiN(Titanium Nitride)막(125) 및 TiSi2(Titanium Silicide)(123)을 제거하여 플러그(Plug)(도시 안 함)를 형성하고, 이후 공정(Subsequent Processing)에서 메탈라인(Metal Line)을 패터닝힌다(도시 안 함). 상기 플러그로 불순물이 도핑된 액티브 영역(118)과 메탈라인을 전기적으로 연결한다.After CMP (Chemical Mechanical Polishing) method of a silicon oxide film (SiO 2), (121a), tungsten (Tungsten) (130) and TiN (Titanium Nitride) plug to remove the film 125 and the TiSi 2 (Titanium Silicide) (123) on the (Plug) (not shown) is formed, and then Metal Line is patterned (not shown) in Subsequent Processing. The plug electrically connects the active region 118 doped with impurities to the metal line.
상술한 바와 같이 본 발명에 따른 반도체 장치의 제조방법은 소자격리층이 형성된 반도체 기판내에 불순물이 도핑된 확산층을 형성하며, 상기 반도체 기판상에 절연층을 형성하며, 상기 절연층내에 콘택홀을 형성하여 상기 확산층을 노출시키며, PVD 방법으로 메탈 실리사이드(Metal Silicide)층을 상기 확산층 및 상기 절연층상에 형성하며, 상기 메탈 실리사이드(Metal Silicide)층상에 메탈 나이트라이드(Metal Nitride)층을 형성하며, 상기 반도체 기판상에 금속층으로 상기 콘택홀을 충진(Gap Filling)한다.As described above, the method of manufacturing a semiconductor device according to the present invention forms a diffusion layer doped with impurities in a semiconductor substrate on which an element isolation layer is formed, an insulating layer is formed on the semiconductor substrate, and contact holes are formed in the insulating layer. Exposing the diffusion layer, forming a metal silicide layer on the diffusion layer and the insulating layer by PVD, and forming a metal nitride layer on the metal silicide layer, The contact hole is filled with a metal layer on a semiconductor substrate.
따라서, 본 발명은 액티브 영역에 메탈 실리사이드(Metal Silicide)를 PVD(Physical Vapor Deposition)방법으로 직접 실리콘(Silicon)에 형성함으로 종전의 실리사이드 (Silicide) 상 변태시의 문제점들인 도펀트들의 외부 확산을 방지하여 콘택저항의 증가를 억제할 수 있으며 또한 체적축소를 최소화됨으로 누설전류의 증대로 인한 소자특성이 저하되는 것을 방지할 수 있는 잇점이 있다.Accordingly, the present invention forms metal silicide in the active region directly on silicon by PVD (Physical Vapor Deposition) method, thereby preventing external diffusion of dopants, which is a problem in the conventional silicide phase transformation. The increase in contact resistance can be suppressed and the volume reduction can be minimized, thereby preventing the deterioration of device characteristics due to an increase in leakage current.
Claims (5)
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400769B1 (en) * | 2000-12-29 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming barrier layer of semiconductor device |
| US7189641B2 (en) | 2003-08-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers |
| KR100715761B1 (en) * | 2005-04-01 | 2007-05-08 | 영남대학교 산학협력단 | The trobleshooting of electroless plating on Al pad of SiO2 wafer doped boron |
| US7521357B2 (en) | 2004-02-24 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming metal wiring in semiconductor devices using etch stop layers |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5279990A (en) * | 1990-03-02 | 1994-01-18 | Motorola, Inc. | Method of making a small geometry contact using sidewall spacers |
| JP3018383B2 (en) * | 1990-04-03 | 2000-03-13 | ソニー株式会社 | Wiring formation method |
| JP3369716B2 (en) * | 1994-04-27 | 2003-01-20 | 川崎製鉄株式会社 | Method of forming connection structure |
| KR960042961A (en) * | 1995-05-25 | 1996-12-21 | 김주용 | Method of forming diffusion barrier of semiconductor device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100400769B1 (en) * | 2000-12-29 | 2003-10-08 | 주식회사 하이닉스반도체 | Method for forming barrier layer of semiconductor device |
| US7189641B2 (en) | 2003-08-19 | 2007-03-13 | Samsung Electronics Co., Ltd. | Methods of fabricating tungsten contacts with tungsten nitride barrier layers in semiconductor devices, tungsten contacts with tungsten nitride barrier layers |
| US7521357B2 (en) | 2004-02-24 | 2009-04-21 | Samsung Electronics Co., Ltd. | Methods of forming metal wiring in semiconductor devices using etch stop layers |
| KR100715761B1 (en) * | 2005-04-01 | 2007-05-08 | 영남대학교 산학협력단 | The trobleshooting of electroless plating on Al pad of SiO2 wafer doped boron |
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