200820432 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種金氧半導體 (metal-oxide-semiconductor; MOS)電晶體的製作方法，尤 指一種具有應變矽（strained silicon)之金氧半導體電晶體的 製作方法。本發明的特徵在於先去除金氧半導體電晶體之 側壁子，再於金氧半導體電晶體上形成一應力覆蓋層（cap stressed layer)來產生結構上應變，使金氧半導體電晶體可 以具有較高的驅動電流(drive current)，藉此提升半導體電 晶體的知作效能。 【先前技術】 隨著半導體製造技術愈來愈精密，積體電路也發生重大 的變革’使得電腦的運算性能和存儲容量突飛猛進，並帶 動周邊産業迅速發展。而半導體產業也如同摩爾定律所預 測的，以每18個月在積體電路上增加一倍電晶體數目的速 度發展著，同時半導體製程也已經從1999年的0.18微米、 2〇〇1年的〇·13微米、2003年的90奈米，進入到2005年 65奈米。而隨著半導體製程進入深次微米時代，在半導體 製程中如何提升金氧半導體電晶體的驅動電流已逐漸成為 一熱門課題。 6 200820432 目前提升金氧半導體電晶體之驅動電流的方法有很多 種，例如美國專利公開號第2005/0059228號專利即教導一 種提升金氧半導體電晶體的驅動電流之方法，其係利用一 氮化物乳化物混合覆蓋層之退火(anneal)製程來改變基底 的推貝为佈’以提升通道中的電子遷移率（electron mobility)。上述方法請參考第1圖至第6圖，第1圖至第6 圖為習知提升金氧半導體電晶體的驅動電流之方法示意 圖。如第1圖所示，首先提供一半導體裝置3〇〇。於基底 309中佈植N型摻質310,使其達到一預定之深度與濃度而 形成一主動區域302與一主動區域303，並於基底309中 佈植P型摻質而形成二硼摻質區315。主動區域302與主 動區域303之間則定義出一 P型之通道區域301。半導體 裝置300包含有一閘極氧化層（gate oxide layer)304、一多 晶石夕氧化物(poly oxide)305、一多晶石夕閘極(polysilicon gate)306、以及一偏移側壁子（offset spacer)311。 如第2圖所示，接著形成側壁子412、側壁子413、側 壁子414,毗鄰於閘極氧化層304與多晶矽閘極306周圍。 然後以此多晶矽閘極306及側壁子412、側壁子413、側壁 子414做為遮罩進行離子佈植(i〇n implantation)，把坤或鱗 等N型摻質植入於基底309中，以形成源極區域407與汲 極區域408。 7 200820432 如第3圖所示，接著進行一化學氣相沈積製程（chemical vapor deposition ; CVD)，以形成一混合覆蓋層（c〇mp〇site cap)516。混合覆蓋層516包含有一襯墊層（未圖示）與一氮 化物層位於襯墊層之上，其中襯墊層通常由氧化物或氮氧 化物所構成。襯墊層之厚度約介於5〇至1〇〇埃（angstr〇m)， 而氮化物層之厚度約大於等於3〇〇埃。尤其注意的是，混 合覆蓋層516可以被選擇性地移除，而暴露出p型金氧半 導體電晶體。 如第4圖所示，然後進行一快速升溫退火(rapidthermal annealing ; RTA)製程，用以活化（active)源極區域4〇7與汲 極區域408内的摻質，並同時修補在離子佈植製程中受損 之基底309表面的晶格結構。混合覆蓋層516之氮化物層 包含有多量之氫，部分氫617會於快速升溫退火製程中進 入氧化物或襯墊層中，使得氧化物之氩濃度上升，進而導 致通道區域301中部分之p型摻質輕易進入側壁子412或 疋混合覆蓋層516之襯墊層中。由於通道區域3〇1中鄰近 閘極部分之P型摻質的數量減少，因此提升了 N型金氧半 ‘體電晶體的通道區域301之電子遷移率。 如第5圖所示，隨後去除混合覆蓋層516。如第6圖所 不’接著進行一自對準金屬矽化物（salicide)製程，於基底 8 200820432 309表面形成-金屬層（未示於圖中），例如一錄金屬層，使 金屬層與主動區域302、主動區域3〇3、多晶矽閘極3〇6等 、石夕化物相接觸的部分發生反應，形成金屬石夕化物818，最 後再去除未反應成金屬石夕化物818之金屬層。 習知技術利用通道區域3〇1之p型摻質濃度下降來提升 通道區域301之電子遷移率，然而此方法受限於偏移側壁 子311、側壁子412、側壁子413、側壁子414與混合覆蓋 層516之結構，僅能改變通道區域3〇1與多晶矽閘極 父界處的摻貝/辰度，因此習知技術之提升效果相當有限。 另一方面，習知技術雖可提升N型金氧半導體電晶體 的通道區域301之電子遷移率，然而，由於習知技術係利 用混合覆蓋層516而使基底309之P型摻質的濃度下降， 因此混合覆蓋層516也會減少P型金氧半導體電晶體之p 型輕摻雜汲極(p-type lightly-doped-drain，PLDD)的 P 型摻 質濃度，進而破壞所製作之p型金氧半導體電晶體的運 作。有鑑於此，習知技術的混合覆蓋層516完全不適用於 P型金氧半導體電晶體。因此如何有效提升通道區域之電 子遷移率仍為該領域一重要議題。 【發明内容】 200820432 因此，本發明之主要目的在提供一種製作金氧半導體 電晶體之方法，其先去除金氧半導體電晶體之側壁子，再 於金氧半導體電晶體表面形成一應力覆蓋層來改變通道區 域的應力，使金氧半導體電晶體具有較佳的操作效能。 根據本發明之較佳實施例，本發明提供一種製作金氧 半導體電晶體的方法。首先，提供一半導體基底，半導體 基底上包含有一閘極結構。然後於閘極結構相對二側之半 導體基底中形成一淺接面源極延伸以及一淺接面没極延 伸，再於閘極結構之相對二側壁上形成一概塾層與一側壁 子，利用閘極結構以及側壁子作為佈植遮罩，對半導體基 底進行一離子佈植製程，藉此於閘極結構相對二側之半導 體基底中形成一源極區域與一汲極區域。去除側壁子之 後，於半導體基底上形成一應力覆蓋層，覆蓋於閘極結構、 襯墊層、源極區域與汲極區域上。接著，進行一活化製程， 再對應力覆蓋層進行一蝕刻製程，使應力覆蓋層成為一自 對準金屬石夕化物阻檔層（salicide block，SAB)。然後，進行 一自對準金屬矽化物製程，以於未覆蓋有應力覆蓋層之閘 極結構、源極區域與汲極區域上形成一金屬矽化物層。 根據本發明之另一較佳實施例，本發明另提供一種製 作金氧半導體電晶體的方法。首先，提供一半導體基底， 半導體基底上定義有一第一主動區域、一第二主動區域與 200820432 一第三主動區域，第一、第二與第三主動區域上分別包含 有至少一閘極結構，閘極結構相對二側壁上包含有一襯墊 層，各閘極結構相對二側之半導體基底中則具有一源極區 域與一没極區域。之後，於第一、第二與第三主動區域中 之半導體基底上形成一應力覆蓋層，覆蓋於閘極結構、襯 墊層、源極區域與汲極區域。接著，對應力覆蓋層進行一 第一蝕刻製程，以暴露出第二主動區域中之閘極結構、源 極區域與没極區域，爾後對源極區域、没極區域與應力覆 蓋層進行一活化製程，再對應力覆蓋層進行一第二蝕刻製 程，以暴露出第一主動區域中之閘極結構、源極區域與汲 極區域。然後，進行一自對準金屬矽化物製程，以於第一 與第二主動區域中未覆蓋有應力覆蓋層之閘極結構、源極 區域與汲極區域上形成一金屬矽化物層。 由於本發明係先去除金氧半導體電晶體之側壁子，再 於金氧半導體電晶體上形成一應力覆蓋層來產生結構上應 變，因此可使金氧半導體電晶體可以具有較向的驅動電 流，藉此提升金氧半導體電晶體的操作效能。 為了使貴審查委員能更進一步了解本發明之特徵及 技術内容，請參閱以下有關本發明之詳細說明與附圖。然 而所附圖式僅供參考與輔助說明用，並非用來對本發明加 以限制者。 11 200820432 【實施方式】 凊參照第7圖至第13圖，其繪示的是本發明之第一較 佳實施例製作金氧半導體電晶體的方法的剖面示意圖，其 中相同的元件或部位仍沿用相同的符號來表示。需注音的 是圖式僅以說明為目的，並未依照原尺寸作圖。2外:在 第7圖至第13圖中對於與本發明有關之部分的微影及姓刻 製程由於為該項技藝者以及通常知識者所熟知的，因此並 未明示於圖中。 本發明係關於一種製作積體電路中的金氧半導體電晶 體的方法，可適用於N型金氧半導體電晶體與p型金氧半 導體電晶體，為了進行詳細說明，第7圖至第13圖中特別 以位於不同區域之金氧半導體電晶體製程作為說明。如第 7圖所示，首先提供一半導體基底1〇，例如一矽基底或者 是石夕覆絕緣(silicon_on_insulator; SOI)基底。半導體基底1〇 上定義有一第一主動區域1、一第二主動區域2與一第三 主動區域3,例如第一主動區域1、第二主動區域2與第三 主動區域3可分別為一核心電路(core circuit)區域、一輪入 或輸出（input/output ; I/O)元件區域與一靜電放電 (electrostatic discharge ; ESD)保護元件區域。而本發明於 第一主動區域1、一第二主動區域2與一第三主動區域3 12 200820432 内所製作之金氧半導體電晶體110、金氧半導體電晶體120 ' 與金氧半導體電晶體130可以為N型金氧半導體電晶體或 - P型金氧半導體電晶體。 首先分別在第一主動區域1、第二主動區域2與第三 主動區域3之半導體基底10上形成一閘極介電層14以及 一閘極12，構成一閘極結構，其中閘極12通常包含有摻 雜多晶石夕（dopedpolysilicon)等之導電材料，閘極介電層14 則可為二氧化石夕（silicon dioxide ; Si02)或氮化石夕（siHc〇n nitride)等之絕緣材料。接著，在各閘極12二側之半導體基 底10中分別形成一淺接面源極延伸17以及一淺接面沒極 延伸19，而淺接面源極延伸17以及淺接面沒極延伸19之 間即為金氧半導體電晶體110、120、130之通道區域22。 之後，進行化學氣相沉積製程，以形成二遮蔽層（未 不於圖中）覆蓋於各閘極12和半導體基底1〇上方。然後， 對一遮敝層進行一非等向性餘刻製程（anis〇tr〇pic etch)，以 使一遮敵層形成一概塾層30與一側壁子（spacer)32，概墊 層30位於各閘極12的相對二側壁上，而側壁子32則位於 各襯墊層30上。其中，襯墊層3〇可以為一偏移側壁子， 材料可包含有氧化矽等，且通常為L型，而側壁子32則可 包含有氮矽化合物或氧矽化合物。 13 200820432 如第8圖所示，於形成側壁子32之後，接著進行一離 • 子佈植製程，將摻質植入半導體基底10中，藉此於第一主 - 動區域1、第二主動區域2與第三主動區域3内各形成一 源極區域18以及一汲極區域20。如習知該項技藝者以及 通常知識者所熟知，針對N型金氧半導體電晶體，摻質可 以為砷、銻或磷等N型摻質物種；針對P型金氧半導體電 晶體，摻質則可為硼、鋁等P型摻質物種。 此外，在完成源極區域18與汲極區域20的摻雜後， 半導體基底10可以選擇性地進行一活化製程，例如一快速 升溫退火或一退火製程，用以活化淺接面源極延伸17、淺 接面汲極延伸19、源極區域18以及汲極區域20内的摻質， 並同時修補半導體基底10表面的晶格結構。由於後續製程 中仍會包含有其他的高溫製程，因此此處亦可先不進行活 化製程，而改於應力覆蓋層形成之後再進行此活化製程， 以活化源極區域18以及汲極區域20内的摻雜質。 如第9圖所示，隨後去除側壁子32，留下閘極12側 壁上的襯墊層30。根據本發明之較佳實施例，去除側壁子 32之後，則在閘極12側壁上留下約略呈L型的襯墊層30。 然而，習知該項技藝者以及通常知識者應理解襯墊層30不 一定呈L型，而其亦可以進行一較溫和的蝕刻製程，略微 蝕刻襯墊層30，以縮減其厚度。而在其它實施例中，襯墊 14 200820432 層30甚至可被完全去除。 - 如第10圖所示，接著半導體基底10上形成一應力覆蓋 層46，並覆蓋於襯墊層3〇、閘極、源極區域18與汲極 區域20表面。於此較佳實施例中，應力覆蓋層46為一單 層結構’由氧化秒或氮化石夕所組成，其厚度可介於1 〇埃至 3000埃之間。以一層氧化矽之應力覆蓋層46為例，其形 成方式可利用一高溫氧化製程於半導體基底1〇表面全面 形成一高溫氧化物(high temperature oxide，HTO)作為應力 覆蓋層46 ;其亦可利用一次常壓化學氣相沉積 (sub-atmospheric pressure chemical vapor deposition 5 SACVD)製程於半導體基底1〇表面全面沉積一層氧化矽作 為應力覆蓋層46。 針對P型金氧半導體電晶體，習知該項技藝者以及通常 知識者應理解亦可以於形成應力覆蓋層46後，再選擇性地 進行一道半導體製程來改變應力覆蓋層46的應力狀態，減 少應力覆蓋層46的伸張應力，或增加壓縮應力。例如進行 一離子佈植製程’利用鍺離子佈植來改變應力覆蓋層46的 應力狀悲。或者’於形成應力覆蓋層46後，再選擇性地進 打一微影暨蚀刻製程，以去除p型金氧半導體電晶體上方 .的應力覆蓋層46。此種可於-覆蓋層中結合壓縮應力與伸 ' 張應力之技術稱之為選擇性應力系統(selective strain 15 200820432 scheme，SSS) 〇 如第11圖所示，於本較佳實施例巾，由於第二主動區 域2内的金氧半導體電晶體u〇無需進行應力改變，因此 可利用微景多暨姓刻製程去除位於第二主動區支或2内的應力 覆蓋層46，保留位於第—主動區域第三主動區域3内 的應力覆蓋層46，以暴露出第二主動區域2中之閘極ι2、 源極區域18與汲極區域2〇。 然後對應力覆蓋層46進行一現場(jn-situ)或非現場(n〇n in-situ)的活化製程，例如進行一紫外線硬化(UVcuring)製 程、一退火製程、一高溫峰值退火(thermalspikeanneal)製 程或一電子束(e-beam)處理。藉著活化製程把應力記憶入金 氧半導體電晶體110與金氧半導體電晶體13〇之中，拉大 通道區域22之半導體基底1G的晶格排列，進而提升位於 第-主動區域1及第二主動區域3之通道區域22的電子遷 移率以及金A半導體電晶體1H)與金氧半導體電晶體咖 之驅動電流。 實驗結果顯示，當本發明之應力覆蓋屬46為氧化矽之 單層結構時’由次常壓化學氣相沉積製程所形成的應力覆 蓋層46約可增加N型金氧半導體電晶體之開啟電流增益<百 分比（Ion gain percentage)達5.3%左右，而僅使p型金氧半 16 200820432 導體電晶體之開啟電流增益百分比減少了 0·7% ;由高溫氧 化製程所形成應力覆蓋層46約可增加Ν型金氧半導體電曰曰 體之開啟電流增益百分比至4.4%左右，而可使ρ型金氧半 導體電晶體之開啟電流增益百分比增加〇·4% 。 根據本發明之一實施例，應力覆蓋層46於沈積時係為 伸張應變(tensile-stressed)狀態。且由於側壁子32已被去 除，因此應力覆蓋層46可與閘極12側壁上的襯墊層3〇直 接接壤。在沒有側壁子32阻隔的情況下，應力覆蓋層46 之應力便可更直接地作用於金氧半導體電晶體11〇與金氧 半導體電晶體130上。如此，使得金氧半導體電晶體11〇 與金氧半導體電晶體130之通道區域22在通道方向上受到 與概墊層30直接接壤的氮化石夕蓋層46之伸張應力作用， 改變通道區域22的電子遷移率及金氧半導體電晶體之驅 動電流。 如弟12圖所示，為了於第一主動區域1與第二主動區 域2形成自對準金屬矽化物，因此可進行一微影暨蝕刻製 程去除位於第一主動區域！内的應力覆蓋層46，以暴露出 預疋要死/成自對準金屬石夕化物之區域，例如第一主動區域 1中之閘極12、源極區域18與汲極區域2〇，未被去除之 應力覆蓋層46則作為後續之自對準金屬矽化物阻擋層。 17 200820432 隨後進行一自對準金屬矽化物製程，於半導體基底1Q 表面濺鍍一金屬層（未示於圖中），例如一鎳金屬層，並覆 盍在第主動£域1、第一主動區域2與第三主動區域3 之閘極12、源極區域18、汲極區域20、以及半導體基底 10表面。接著進行一快速升溫退火製程，使金屬層與第一 主動區域1與第二主動區域2之閘極12、源極區域18與 汲極區域20接觸的部分反應成自對準金屬矽化物層42。 最後再利用一選擇性濕式蝕刻，例如以氨水與過氧化氫混 合物(NH4OH/H2O2/H2O，ammonia hydrogen peroxide mixture，APM)或硫酸與過氧化氫混合物(h2s〇4/H2〇2， sulfuric acid-hydrogen peroxide mixture，SPM)來去除未反 應成金屬矽化物之金屬層。 如第13圖所示，接著再進行一蝕刻製程，去除應力覆 蓋層46。接著，於半導體基底1〇上沈積一介電層牦，前 述之介電層48可以為氧化矽、摻雜氧化矽或者低介電常數 材料等等。接著進行習知的微影暨㈣製程，於介電層# 中形成接觸洞52,通達金氧半導體電晶體11〇、金氧半導 體電晶體120與金氧半導體電晶體130的閘極12、源極區 域18與汲極區域20。此夕卜，該領域具通常知識者應知曉 本發明亦可結合接觸洞韻刻停止層（contact etch stop " layer’ CESL ’未圖示）之技術，亦即在完成前述之製程後， 著再开y成〃適g應力之接觸洞蚀刻停止層覆蓋於各相姆 18 200820432 應金氧半導體電晶體110、金氧半導體電晶體120或金氧 • 半導體電晶體130，並使接觸洞蝕刻停止層具有不同的應 力狀態，例如P型金氧半導體電晶體上方的接觸洞蝕刻停 止層係在壓縮應變狀態，而N型金氧半導體電晶體上方内 的接觸洞蝕刻停止層係在伸張應變狀態。 此外，於本發明之另一較佳實施例中，應力覆蓋層46 亦可為一雙層結構。請參考第14圖，第14圖為本發明之 第二較佳實施例具有應力覆蓋層之金氧半導體電晶體的剖 面示意圖，其中相同的元件或部位仍沿用相同的符號來表 示。於此較佳實施例中，應力覆蓋層46同時包含有一氧化 矽層462與一氮化矽層464位於氧化矽層462之上。氧化 矽層462可以由一高溫氧化製程或一次常壓化學氣相沉積 製程所形成，其厚度約介於50埃至2000埃之間。氮化矽 層464可以由一化學氣相沉積製程所形成，尤其注意的 是，氮化矽層464之厚度較佳在100埃至200埃之間。需 特別留意的是，本發明之實施例中所述的厚度範圍皆是針 對65奈米製程而定，習知該項技藝者應理解本發明各尺寸 範圍可視實際需求而調整。換句話說，當電晶體的尺寸愈 來愈小時，應力覆蓋層力46的厚度可隨之薄化，以提供適 當之應力值。 . 當本發明之應力覆蓋層46為雙層結構時，由次常壓化 19 200820432 學氣相沉積製程所形成的氧化矽層與厚度3〇〇埃左右的氮 化矽層共同構成的應力覆蓋層46可增加n型金氧半導體電 晶體之開啟電流增益百分比達114%左右，而使p型金氧 半導體電晶體之開啟電流增益百分比減少約25 5% ;由次 常壓化學氣相沉積製程所形成的氧化矽層與厚度約1卯埃 的氮化矽層共同構成的應力覆蓋層46約可增金氧半 導體電晶體之開啟電流增益百分比至1G8%，而僅使？型 金氧半導體電晶體之開啟電流增益百分比減少9篇。 本發明可以大幅增加N型金氧半導體電晶體之開啟電 流增益效果，且對於P型金氧半導體電晶體之負面影響較 小’甚至可增加P型金氧半導體電晶體之開啟電流增益效 果。前述製程亦可再搭配其他半導體製程，藉此達到大幅 增加N型金氧半導體電晶體之開啟電流增益的目的，並且 ^會減低P型金氧半導體電晶體之開啟電流增益。舉例 \兄，本發明可先於—金氧半導體電晶體上形成一雙層社 構的應力覆蓋層46,包含有氧化石夕層與厚度約19〇埃㈣ :::方:Γ影暨蘭製程去除位於p型金氧半導體電 :體美二/蓋層46 ’之後再利用活化製程來活化半 底Π)，使應力狀態記憶人金氧半導體電晶體之中。200820432 IX. Description of the Invention: [Technical Field] The present invention relates to a method for fabricating a metal-oxide-semiconductor (MOS) transistor, and more particularly to a metal oxide semiconductor having strained silicon. A method of making a transistor. The invention is characterized in that the sidewall of the MOS transistor is removed first, and then a cap stressed layer is formed on the MOS transistor to generate structural strain, so that the MOS transistor can have a higher The drive current, thereby improving the known performance of the semiconductor transistor. [Prior Art] With the increasingly sophisticated semiconductor manufacturing technology, major changes have taken place in the integrated circuit, which has made the computer's computing performance and storage capacity soar and drove the rapid development of the surrounding industries. The semiconductor industry, as predicted by Moore's Law, is growing at a rate that doubles the number of transistors on integrated circuits every 18 months, and the semiconductor process has also been 0.18 micron, 1.9 years from 1999. 〇·13 micron, 90 nm in 2003, entered 65 nm in 2005. As the semiconductor process enters the deep submicron era, how to improve the driving current of the MOS transistor in the semiconductor process has gradually become a hot topic. 6 200820432 There are a number of methods for increasing the driving current of a MOS transistor, for example, US Patent Publication No. 2005/0059228 teaches a method for improving the driving current of a MOS transistor, which utilizes a nitride. The anneal process of the emulsion mixed cover layer changes the push of the substrate into a cloth to enhance the electron mobility in the channel. For the above method, please refer to Fig. 1 to Fig. 6. Fig. 1 to Fig. 6 are schematic diagrams showing the method of raising the driving current of the MOS transistor. As shown in Fig. 1, a semiconductor device 3 is first provided. The N-type dopant 310 is implanted in the substrate 309 to a predetermined depth and concentration to form an active region 302 and an active region 303, and a P-type dopant is implanted in the substrate 309 to form a boron-doped dopant. Area 315. A P-type channel region 301 is defined between the active region 302 and the active region 303. The semiconductor device 300 includes a gate oxide layer 304, a polycrystalline oxide 305, a polysilicon gate 306, and an offset sidewall (offset). Spacer) 311. As shown in Fig. 2, a sidewall spacer 412, a sidewall spacer 413, and a side wall 414 are formed adjacent to the gate oxide layer 304 and the periphery of the polysilicon gate 306. Then, the polysilicon gate 306 and the sidewall spacers 412, the sidewall spacers 413, and the sidewall spacers 414 are used as masks for ion implantation, and N-type dopants such as Kun or scales are implanted in the substrate 309. The source region 407 and the drain region 408 are formed. 7 200820432 As shown in FIG. 3, a chemical vapor deposition (CVD) process is then performed to form a c〇mp〇site cap 516. The hybrid cover layer 516 includes a liner layer (not shown) and a nitride layer overlying the liner layer, wherein the liner layer is typically comprised of an oxide or oxynitride. The thickness of the liner layer is between about 5 Å and 1 angstrom, and the thickness of the nitride layer is about 3 angstroms or more. It is particularly noted that the hybrid cap layer 516 can be selectively removed to expose the p-type MOS transistor. As shown in Fig. 4, a rapid thermal annealing (RTA) process is then performed to activate the dopants in the source region 4〇7 and the drain region 408, and simultaneously repair the ion implantation. The lattice structure of the surface of the damaged substrate 309 in the process. The nitride layer of the mixed cap layer 516 contains a large amount of hydrogen, and a portion of the hydrogen 617 enters the oxide or liner layer during the rapid temperature annealing process, so that the argon concentration of the oxide rises, thereby causing a portion of the channel region 301. The type of dopant readily enters the liner layer of sidewall spacer 412 or tantalum hybrid overlay layer 516. Since the number of P-type dopants adjacent to the gate portion in the channel region 3〇1 is reduced, the electron mobility of the channel region 301 of the N-type gold oxide semiconductor transistor is improved. As shown in Figure 5, the hybrid cover layer 516 is subsequently removed. If a self-aligned metal salicide process is performed as shown in FIG. 6, a metal layer (not shown) is formed on the surface of the substrate 8 200820432 309, for example, a metal layer is formed to make the metal layer active. The region 302, the active region 3〇3, the polysilicon gate 3〇6, and the like, the portion in contact with the lithium compound reacts to form the metal lithium 818, and finally the metal layer which is not reacted into the metal lithium 818 is removed. The prior art utilizes a decrease in the p-type dopant concentration of the channel region 3.1 to increase the electron mobility of the channel region 301. However, this method is limited to the offset sidewall sub-311, the sidewall spacer 412, the sidewall sub-413, and the sidewall sub-414. The structure of the mixed cover layer 516 can only change the doping/length of the channel region 3〇1 and the polysilicon gate parent boundary, so the improvement effect of the prior art is rather limited. On the other hand, the conventional technique can improve the electron mobility of the channel region 301 of the N-type MOS transistor, however, since the prior art utilizes the mixed cap layer 516 to lower the concentration of the P-type dopant of the substrate 309. Therefore, the mixed cap layer 516 also reduces the P-type dopant concentration of the p-type lightly-doped-drain (PLDD) of the P-type MOS transistor, thereby destroying the p-type produced. The operation of MOS transistors. In view of this, the conventional hybrid cover layer 516 is completely unsuitable for P-type MOS transistors. Therefore, how to effectively improve the electron mobility of the channel region is still an important issue in this field. SUMMARY OF THE INVENTION Accordingly, the main object of the present invention is to provide a method of fabricating a MOS transistor, which first removes sidewalls of a MOS transistor and then forms a stress coating on the surface of the MOS transistor. The stress in the channel region is changed to make the MOS transistor have better operational efficiency. In accordance with a preferred embodiment of the present invention, the present invention provides a method of fabricating a MOS transistor. First, a semiconductor substrate is provided having a gate structure on the semiconductor substrate. Then forming a shallow junction source extension and a shallow junction extension in the semiconductor substrate on the opposite sides of the gate structure, and forming a general layer and a sidewall on the opposite sidewalls of the gate structure, using the gate The pole structure and the sidewalls serve as an implant mask, and an ion implantation process is performed on the semiconductor substrate, thereby forming a source region and a drain region in the semiconductor substrate opposite to the two sides of the gate structure. After removing the sidewalls, a stress coating is formed over the semiconductor substrate overlying the gate structure, the liner layer, the source region and the drain region. Then, an activation process is performed, and an etching process is performed on the stress coating layer to make the stress coating layer a self-aligned metallization block (SAB). Then, a self-aligned metal telluride process is performed to form a metal germanide layer on the gate structure, the source region and the drain region which are not covered with the stress cladding layer. According to another preferred embodiment of the present invention, the present invention further provides a method of fabricating a gold oxide semiconductor transistor. First, a semiconductor substrate is provided. The semiconductor substrate defines a first active region, a second active region, and a 200820432-third active region. The first, second, and third active regions respectively include at least one gate structure. The gate structure includes a liner layer on opposite sidewalls, and each of the gate structures has a source region and a gate region in opposite semiconductor substrates. Thereafter, a stress coating layer is formed on the semiconductor substrate in the first, second, and third active regions to cover the gate structure, the pad layer, the source region, and the drain region. Then, a first etching process is performed on the stress coating layer to expose the gate structure, the source region and the gate region in the second active region, and then activate the source region, the gate region and the stress coating layer. The process further performs a second etching process on the stress cap layer to expose the gate structure, the source region and the drain region in the first active region. Then, a self-aligned metal telluride process is performed to form a metal germanide layer on the gate structure, the source region and the drain region of the first and second active regions not covered with the stress cladding layer. Since the present invention first removes the sidewall of the MOS transistor and then forms a stress coating layer on the MOS transistor to generate structural strain, the MOS transistor can have a relatively large driving current. Thereby improving the operational efficiency of the MOS transistor. In order to provide a more detailed understanding of the features and technical aspects of the present invention, the following detailed description of the invention and the accompanying drawings. The drawings are for illustrative purposes only and are not intended to limit the invention. 11 200820432 [Embodiment] Referring to Figures 7 to 13, there is shown a cross-sectional view showing a method of fabricating a MOS transistor according to a first preferred embodiment of the present invention, in which the same components or parts are still used. The same symbol is used to indicate. It is necessary to note that the drawings are for illustrative purposes only and are not plotted in the original size. 2External: The lithography and surname processes in the drawings relating to the present invention in Figures 7 through 13 are well known to those skilled in the art and are generally not shown in the drawings. The present invention relates to a method for fabricating a MOS transistor in an integrated circuit, which is applicable to an N-type MOS transistor and a p-type MOS transistor. For detailed explanation, FIGS. 7 to 13 In particular, the oxynitride transistor process in different regions is used as an illustration. As shown in Fig. 7, first, a semiconductor substrate 1 is provided, such as a germanium substrate or a silicon_on_insulator (SOI) substrate. A first active region 1, a second active region 2 and a third active region 3 are defined on the semiconductor substrate 1 , for example, the first active region 1 , the second active region 2 and the third active region 3 are respectively a core A core circuit area, an input/output (I/O) component area, and an electrostatic discharge (ESD) protection element area. The MOS transistor 110, the MOS transistor 120' and the MOS transistor 130 fabricated in the first active region 1, the second active region 2, and the third active region 3 12 200820432. It may be an N-type MOS transistor or a -P-type MOS transistor. First, a gate dielectric layer 14 and a gate 12 are formed on the semiconductor substrate 10 of the first active region 1, the second active region 2 and the third active region 3, respectively, to form a gate structure, wherein the gate 12 is usually The conductive material comprising doped polysilicon or the like may be an insulating material such as silicon dioxide (SiO 2 ) or SiO 2 (siHc〇n nitride). Next, a shallow junction source extension 17 and a shallow junction no-pole extension 19 are formed in the semiconductor substrate 10 on each of the two sides of the gate 12, and the shallow junction source extension 17 and the shallow junction non-polar extension 19 There is a channel region 22 between the MOS transistors 110, 120, 130. Thereafter, a chemical vapor deposition process is performed to form a second mask layer (not shown) overlying each of the gates 12 and the semiconductor substrate 1A. Then, an anisotropic process (anis〇tr〇pic etch) is performed on a concealing layer, so that an enveloping layer forms a general layer 30 and a spacer 32, and the cushion layer 30 is located. The opposite side walls of each of the gates 12 are located on the respective liner layers 30. Wherein, the liner layer 3〇 may be an offset sidewall, the material may comprise yttrium oxide or the like, and is generally L-shaped, and the sidewall spacer 32 may comprise a nitrogen ruthenium compound or an oxonium compound. 13 200820432 As shown in FIG. 8, after the sidewall spacers 32 are formed, an ion implantation process is then performed to implant dopants into the semiconductor substrate 10, thereby enabling the first active-active region 1 and the second active region. A source region 18 and a drain region 20 are formed in each of the region 2 and the third active region 3. As is well known to those skilled in the art and those of ordinary skill in the art, for N-type MOS transistors, the dopant may be an N-type dopant species such as arsenic, antimony or phosphorus; for P-type MOS transistors, dopants It can be a P-type dopant species such as boron or aluminum. In addition, after doping the source region 18 and the drain region 20, the semiconductor substrate 10 can be selectively subjected to an activation process, such as a rapid thermal annealing or an annealing process to activate the shallow junction source extension 17 The shallow junction drain extension 19, the source region 18, and the dopant in the drain region 20, and simultaneously repair the lattice structure of the surface of the semiconductor substrate 10. Since other high-temperature processes are still included in the subsequent process, the activation process may not be performed here, and the activation process may be performed after the stress coating layer is formed to activate the source region 18 and the drain region 20. Doping quality. As shown in Fig. 9, the sidewall spacers 32 are subsequently removed leaving the liner layer 30 on the side walls of the gate 12. In accordance with a preferred embodiment of the present invention, after removal of the sidewall spacers 32, an approximately L-shaped liner layer 30 is left on the sidewalls of the gate 12. However, it is understood by those skilled in the art and those of ordinary skill that the pad layer 30 is not necessarily L-shaped, but it can also be subjected to a milder etching process to slightly etch the pad layer 30 to reduce its thickness. In other embodiments, the liner 14 200820432 layer 30 can even be completely removed. - As shown in Fig. 10, a stress covering layer 46 is formed on the semiconductor substrate 10 and covers the surface of the pad layer 3, the gate, the source region 18 and the drain region 20. In the preferred embodiment, the stressor layer 46 is a single layer structure 'consisting of oxidized seconds or nitrite, and may have a thickness between 1 Å and 3,000 Å. Taking a layer of yttrium oxide stress coating 46 as an example, a high temperature oxidation process can be used to form a high temperature oxide (HTO) as a stress coating layer 46 on the surface of the semiconductor substrate 1; A sub-atmospheric pressure chemical vapor deposition (SACVD) process deposits a layer of tantalum oxide as a stress coating layer 46 on the surface of the semiconductor substrate. For P-type MOS transistors, it is understood by those skilled in the art and those of ordinary skill that it is also possible to selectively perform a semiconductor process to change the stress state of the stressor layer 46 after forming the stress cap layer 46. The tensile stress of the stress covering layer 46, or the compressive stress is increased. For example, an ion implantation process is performed to change the stress of the stress coating layer 46 by using cesium ion implantation. Alternatively, after the stress cladding layer 46 is formed, a lithography and etching process is selectively performed to remove the stress coating layer 46 over the p-type MOS transistor. Such a technique for combining compressive stress and tensile stress in a cover layer is referred to as a selective strain system (selective strain 15 200820432 scheme, SSS). As shown in FIG. 11, in the preferred embodiment, Since the MOS transistor u〇 in the second active region 2 does not need to undergo stress change, the stress coverage layer 46 located in the second active region branch or 2 can be removed by using the micro-view multi-element process, and the reservation is located at the first The stress coverage layer 46 in the third active region 3 of the active region exposes the gate ι2, the source region 18 and the drain region 2 中 in the second active region 2. A stress-on-site (n-n) or off-site (n〇n in-situ) activation process is then performed, such as a UV curing process, an annealing process, and a thermal spike Anneal. Process or an electron beam (e-beam) process. The stress is memorized into the MOS transistor 110 and the MOS transistor 13 by the activation process, and the lattice arrangement of the semiconductor substrate 1G of the channel region 22 is pulled, thereby enhancing the position of the first active region 1 and the second active region. The electron mobility of the channel region 22 of the region 3 and the driving current of the gold A semiconductor transistor 1H) and the MOS transistor. The experimental results show that when the stress covering genus 46 of the present invention is a single layer structure of yttrium oxide, the stress covering layer 46 formed by the sub-atmospheric pressure chemical vapor deposition process can increase the opening current of the N-type MOS transistor. The gain <% (Ion gain percentage) is about 5.3%, and only the percentage of the on-current gain of the p-type gold oxide half 16200820432 conductor transistor is reduced by 0.7%; the stress cover layer 46 formed by the high temperature oxidation process is about The percentage of the turn-on current gain of the germanium-type MOS semiconductor body can be increased to about 4.4%, and the percentage of the turn-on current gain of the p-type MOS transistor can be increased by 〇·4%. In accordance with an embodiment of the present invention, the stressor layer 46 is deposited in a tensile-stressed state. And because the sidewall spacers 32 have been removed, the stress coverage layer 46 can be directly bordered by the liner layer 3 on the sidewalls of the gate 12. Without the barrier of the sidewall spacers 32, the stress of the stress cladding layer 46 acts more directly on the MOS transistor 11 and the MOS transistor 130. Thus, the channel region 22 of the MOS transistor 11 and the MOS transistor 130 is subjected to the tensile stress of the nitride cap layer 46 directly bordering the blanket layer 30 in the channel direction, and the channel region 22 is changed. Electron mobility and drive current of MOS transistors. As shown in Figure 12, in order to form a self-aligned metal germanide in the first active region 1 and the second active region 2, a lithography and etching process can be performed to remove the first active region! The inner stressor layer 46 is exposed to expose the area of the pre-existing/destructive metallurgical compound, such as the gate 12, the source region 18 and the drain region 2 in the first active region 1, not The removed stressor layer 46 acts as a subsequent self-aligned metal telluride barrier. 17 200820432 Subsequently, a self-aligned metal telluride process is performed, and a metal layer (not shown), such as a nickel metal layer, is sputtered on the surface of the semiconductor substrate 1Q, and is covered by the first active region. The gate 12, the source region 18, the drain region 20, and the surface of the semiconductor substrate 10 of the region 2 and the third active region 3. Then, a rapid thermal annealing process is performed to react the metal layer with the first active region 1 and the gate 12 of the second active region 2, and the portion of the source region 18 in contact with the drain region 20 to form a self-aligned metal telluride layer 42. . Finally, a selective wet etching is used, for example, a mixture of ammonia water and hydrogen peroxide (NH4OH/H2O2/H2O, ammonia hydrogen peroxide mixture, APM) or a mixture of sulfuric acid and hydrogen peroxide (h2s〇4/H2〇2, sulfuric acid) -hydrogen peroxide mixture, SPM) to remove metal layers that are not reacted into metal halides. As shown in Fig. 13, an etching process is then performed to remove the stress cladding layer 46. Next, a dielectric layer 沉积 is deposited on the semiconductor substrate 1 , and the dielectric layer 48 may be yttrium oxide, doped yttrium oxide or a low dielectric constant material or the like. Then, the conventional lithography and (4) process is performed, and a contact hole 52 is formed in the dielectric layer #, and the gate electrode 12 of the MOS transistor 11, the MOS transistor 120, and the MOS transistor 130 is obtained. Polar region 18 and drain region 20. Furthermore, those of ordinary skill in the art should be aware that the present invention may also incorporate a technique of contact etch stop " layer 'CESL 'not shown, that is, after completing the aforementioned process, The contact hole etch stop layer of the y 〃 g g stress is overlaid on each phase 18 200820432 MOS transistor 110, MOS transistor 120 or MOS semiconductor transistor 130, and the contact hole etching is stopped. The layers have different stress states. For example, the contact hole etch stop layer above the P-type MOS transistor is in a compressive strain state, and the contact hole etch stop layer in the upper portion of the N-type MOS transistor is in a tensile strain state. In addition, in another preferred embodiment of the present invention, the stress covering layer 46 may also be a two-layer structure. Referring to FIG. 14, FIG. 14 is a cross-sectional view showing a metal oxide semiconductor transistor having a stress coating layer according to a second preferred embodiment of the present invention, wherein the same elements or portions are denoted by the same reference numerals. In the preferred embodiment, the stressor layer 46 includes a tantalum oxide layer 462 and a tantalum nitride layer 464 over the tantalum oxide layer 462. The ruthenium oxide layer 462 can be formed by a high temperature oxidation process or a one-time atmospheric pressure chemical vapor deposition process having a thickness of between about 50 angstroms and about 2,000 angstroms. The tantalum nitride layer 464 can be formed by a chemical vapor deposition process, with particular attention to the fact that the tantalum nitride layer 464 preferably has a thickness between 100 angstroms and 200 angstroms. It is to be noted that the thickness ranges described in the embodiments of the present invention are determined by the 65 nm process, and those skilled in the art will appreciate that the various size ranges of the present invention can be adjusted to meet actual needs. In other words, as the size of the transistor becomes smaller, the thickness of the stress overburden 46 can be thinned to provide a suitable stress value. When the stress coating layer 46 of the present invention has a two-layer structure, the stress coverage of the yttrium oxide layer formed by the sub-atmospheric pressure 19 200820432 vapor deposition process and the tantalum nitride layer having a thickness of about 3 angstroms The layer 46 can increase the on-current gain percentage of the n-type MOS transistor by about 114%, and reduce the on-current gain percentage of the p-type MOS transistor by about 255%; by the sub-atmospheric chemical vapor deposition process. The stress absorbing layer 46 formed by the formed yttrium oxide layer and the tantalum nitride layer having a thickness of about 1 卯 can increase the opening current gain percentage of the MOS transistor to 1 G 8%, and only? The percentage of turn-on current gain of the MOS transistor was reduced by nine. The present invention can greatly increase the on-current gain effect of the N-type MOS transistor, and has a relatively small negative effect on the P-type MOS transistor, and can even increase the on-current gain effect of the P-type MOS transistor. The foregoing process can also be combined with other semiconductor processes, thereby achieving the purpose of greatly increasing the turn-on current gain of the N-type MOS transistor, and reducing the turn-on current gain of the P-type MOS transistor. For example, the present invention can form a two-layered structural stress covering layer 46 on the oxynitride transistor, comprising a layer of oxidized stone and a thickness of about 19 angstroms (four) ::: square: Γ影暨兰The process removes the p-type MOS semiconductor: the body II / cap layer 46 ' and then uses the activation process to activate the semi-bottom enamel), so that the stress state is stored in the MOS transistor.
It於it氧半導體電晶體上形成-雙層結構的應 m ^石夕層與厚度約190埃的氮化石夕 θ進灯一離子佈植製程，利用錯離子佈植來減少P型 20 200820432 金氧半導體電晶體上方的應力覆蓋層46的伸張應力，之後 再利用活化製程將應力記憶入N型金氧半導體 型金氧半導體電晶體中。 、 根據本發明之第三較佳實施例，金氧半導體電晶體旁亦 可保留部分之應力覆蓋層46,作為應力側壁子54。請來考 =15圖與第丨6圖，第15圖至第16圖繪示的是本‘二之 第三較佳實施例製作金氧半導體電晶體的方法的剖面示意 圖。於此實施例中，先利用第7圖至第u圖所示各步驟於 半導體基底1G上形成金氧半導體電晶體UG、金氧半導體 ，晶體120、金氧半導體電晶體13〇與應力覆蓋層46，接 者如第15圖所示’進行—微影暨朗製程去除第一主動區 域1中位於半導體基底10、閘極12、源極區域18與汲極 區域20上部分之應力覆蓋層46，並保留位於襯塾層川上 之應力覆蓋層46來作為—應力側壁子％。如此一來，應 力覆蓋層46可暴露出需形成自對準金屬石夕化物之區域，^ 應力側壁子54可用以保護金氧半導體電晶體⑽。It forms on the oxygen semiconductor transistor - a two-layer structure of the m ^ 夕 layer and a thickness of about 190 angstroms of nitrite θ into the lamp-ion implantation process, using the wrong ion implantation to reduce the P-type 20 200820432 gold The stress above the oxygen semiconductor transistor covers the tensile stress of the layer 46, and then the activation process is used to memorize the stress into the N-type MOS type MOS transistor. According to a third preferred embodiment of the present invention, a portion of the stress cladding layer 46 may remain as a stress sidewall 54 adjacent to the MOS transistor. Please refer to Fig. 15 and Fig. 6, and Fig. 15 to Fig. 16 are cross-sectional views showing a method of fabricating a MOS transistor according to the third preferred embodiment of the present invention. In this embodiment, a gold oxide semiconductor transistor UG, a gold oxide semiconductor, a crystal 120, a gold oxide semiconductor transistor 13 and a stress coating layer are formed on the semiconductor substrate 1G by using the steps shown in FIGS. 7 to u. 46, the receiver as shown in Fig. 15 'Processing - lithography and sizing process to remove the first active region 1 in the semiconductor substrate 10, the gate 12, the source region 18 and the portion of the drain region 20 of the stress coating 46 And retaining the stress covering layer 46 on the lining layer as the stress sidewall %. As such, the stressor layer 46 can expose areas where self-aligned metallurgy is to be formed, and the stress sidewalls 54 can be used to protect the MOS transistor (10).
Ik後進订-自對準金屬⑪化物製程，並利用未被去除之 應力覆蓋層46作為自對準金屬魏物阻，於基底1〇 表面雜—金屬層（未示於圖中），並覆蓋在第-主動區域！ ”第-主動區域2之閘極12、源極區域18、汲極區域2〇、 以及半導體基底U)表面。接著進行—快速升溫退火製程， 200820432 使金屬層與第一主動區域1、第二主動區域2與第三主動 • 區域3之閘極12、源極區域18與汲極區域20接觸的部分 - 反應成自對準金屬矽化物層42。之後再利用SPM或APM 去除未反應成金屬石夕化物之金屬層。 如第16圖所示，接著再進行一蝕刻製程，去除第三主 動區域3内，位於半導體基底10、閘極12、源極區域18 與汲極區域20上之應力覆蓋層46，而保留位於金氧半導 體電晶體110與金氧半導體電晶體130之襯墊層30上之應 力覆蓋層46來作為一應力側壁子54。接著，於半導體基 底10上沈積一介電層48,前述之介電層48可以為氧化矽、 摻雜氧化矽或者低介電常數材料等等。接著進行一微影暨 蝕刻製程，於介電層48中形成接觸洞52，通達金氧半導 體電晶體110、金氧半導體電晶體120與金氧半導體電晶 體130的閘極12、源極區域18與汲極區域20。 此外，於本發明之另一較佳實施例中，此處之應力側壁 子54亦可為一雙層結構。請參考第17圖，第17圖為本發 明之第四較佳實施例具有應力側壁子之金氧半導體電晶體 的剖面示意圖，其中相同的元件或部位仍沿用相同的符號 來表示。於此較佳實施例中，應力側壁子54同時包含有一 ， 氧化矽層542與一氮化矽層544位於氧化矽層542之上。 „ 氧化矽層542可以由一高溫氧化製程或一次常壓化學氣相 22 200820432 沉積製程所形成，其厚度約介於5 氮化矽層544之厚度較佳在1〇〇 2〇〇〇埃之間，而 *至2〇〇埃之間。 需特別留意的是，應力側壁子5 切齊(如第17圖之第—主動區域丨所示、襯塾層3。之邊緣 層30之邊緣外（如第17圖之第三主不。），亦可覆蓋於襯墊 裸露出襯墊層30之邊緣部分(如第丨=域:所示)，更可 所示）。 圖之第—主動區域1 本發明的特徵在於先去除金氧 子，再於金氧半導體電晶體上形成體之側壁 構上應變。由於側壁子已被去除，因此來產生結 極側壁上的襯墊層直接接壌。如此，:力覆蓋層可與閘 方向上受到與襯墊層直接接壤的氮化矽道區域在通道 在沒有側壁子阻隔的情況下，應力覆蓋>二應力作用。 接地作用於金氧半導體電晶體上，改變通道區 ^ ’使金氧半導體電晶體可以具有較高的驅動電流曰，曰藉此 提升半導體電晶體的操作效能。此外，應力覆蓋層亦可同 時作為後續製程之自對準金屬矽化物阻擋層，使金氧半導 體電晶體之製程簡化。 而且根據上述各實施例之製程，本發明更可針對一半 導體基底之不同區域而同時形成多種不同結構的金氧半導 23 200820432 體電晶體’例如可同時形成-具有應變矽通道與自對準全 金氧半導體電晶體、-具有物通道= 對準r矽化物之金氧半導體電晶體與一不具應變矽通 、且不具自對準金屬矽化物之金氧半導體電晶體。因此， 本發明不但可㈣製作多個金氧半導體電晶體，亦可針對 不同需求㈣成多财同結構之金氧半導體電晶體。 以上所述僅為本發明之較佳實施例，凡依本發明申，專 利範圍所做之均㈣化與修飾，皆應屬本發日狀涵蓋範圍。 圖式簡單說明】 第1圖至第6圖為習知提升金氧半導體電晶體的驅動電流 之方法示意圖。 第7圖至第13圖繪示的是本發明之第一較佳實施例製作金 氧半導體電晶體的方法的剖面示意圖。 第14圖為本發明之第二較佳實施例具有應力覆蓋層之金 氧半導體電晶體的刮面示意圖。 第15圖至第16圖繪示的是本發明之第三較佳實施例製作 金氧半導體電晶體的方法的剖面示意圖。 第17圖為本發明之第四較佳實施例具有應力覆蓋層之金 氧半導體電晶體的剖面示意圖。 24 200820432 【主要元件符號說明】 1 第一主動區域 2 第二主動區域 3 第三主動區域 10 半導體基底 12 閘極 14 閘極介電層 17 淺接面源極延伸 18 源極區域 19 淺接面没極延伸 20 汲極區域 22 通道區域 30 襯墊層 32 側壁子 42 自對準金屬秒化物層 46 應力覆蓋層 48 介電層 52 接觸洞 54 應力側壁子 110 金氧半導體電晶體 120 金氧半導體電晶體 130 金氧半導體電晶體 300 半導體裝置 301 通道區域 302 主動區域 303 主動區域 304 閘極氧化層 305 多晶矽氧化物 306 多晶石夕閘極 309 基底 310 N型摻質 311 偏移側壁子 315 石朋推質區 407 源極區 408 没極區 412 側壁子 413 側壁子 414 側壁子 462 氧化矽層 464 氮化矽層 516 混合覆蓋層 818 金屬石夕化物 542 氧化矽層 25 200820432 544 氮化矽層 26Ik post-precision-self-aligned metal 11 compound process, and using the uncovered stress coating layer 46 as a self-aligned metal object resistance, on the substrate 1 〇 surface impurity-metal layer (not shown), and covered in - Active area! The surface of the gate 12, the source region 18, the drain region 2〇, and the semiconductor substrate U) of the first active region 2. Then, a rapid temperature annealing process is performed, and the metal layer and the first active region 1 and 2 The active region 2 and the third active/region 3 gate 12, the source region 18 and the drain region 20 are in contact with each other - reacting into a self-aligned metal telluride layer 42. The SPM or APM is then used to remove unreacted metal. The metal layer of the Si Xi compound. As shown in Fig. 16, an etching process is further performed to remove the stress in the third active region 3 on the semiconductor substrate 10, the gate 12, the source region 18 and the drain region 20. The layer 46 is covered while the stress capping layer 46 on the pad layer 30 of the MOS transistor 110 and the MOS transistor 130 is retained as a stress sidewall 54. Next, a dielectric is deposited on the semiconductor substrate 10. The layer 48, the dielectric layer 48 may be yttrium oxide, doped yttrium oxide or low dielectric constant material, etc. Then a lithography and etching process is performed to form a contact hole 52 in the dielectric layer 48 to access the gold oxide. Semiconductor transistor 11 0. The MOS transistor 120 and the gate 12, the source region 18 and the drain region 20 of the MOS transistor 130. Further, in another preferred embodiment of the invention, the stress sidewalls herein 54 may also be a two-layer structure. Referring to FIG. 17, FIG. 17 is a cross-sectional view showing a metal oxide semiconductor transistor having a stress sidewall according to a fourth preferred embodiment of the present invention, wherein the same component or portion is still used. The same reference numerals are used. In the preferred embodiment, the stress sidewalls 54 include a tantalum oxide layer 542 and a tantalum nitride layer 544 on the tantalum oxide layer 542. „ The hafnium oxide layer 542 can be heated by a high temperature. The oxidation process or the one-time atmospheric pressure chemical vapor phase 22 200820432 is formed by a deposition process having a thickness of about 5, and the thickness of the tantalum nitride layer 544 is preferably between 1 and 2 angstroms, and * to 2 angstroms. between. It is important to note that the stress sidewalls 5 are aligned (as shown in Figure 17 - active area 、, lining layer 3. The edges of the edge layer 30 are outside (as in the third master of Figure 17). Alternatively, the pad may be exposed to the edge portion of the pad layer 30 (as shown in Fig. 域 = field: more). The first embodiment of the present invention - active region 1 is characterized in that the gold oxide is removed first, and then the sidewall of the formed body on the MOS transistor is strained. Since the sidewalls have been removed, the underlying layer on the sidewalls of the anodes is directly connected. Thus, the force cover layer can be subjected to a stress in the gate direction by the tantalum nitride region directly bordering the liner layer in the absence of sidewall spacers, stress coverage > The grounding acts on the MOS transistor, and changing the channel region ^' allows the MOS transistor to have a higher driving current 曰, thereby improving the operational efficiency of the semiconductor transistor. In addition, the stress coating layer can also be used as a self-aligned metal telluride barrier layer for subsequent processes, which simplifies the process of the gold-oxygen semiconductor transistor. Moreover, according to the processes of the above embodiments, the present invention can simultaneously form a plurality of different structures of gold-oxygen semiconductors 23 for different regions of a semiconductor substrate. 200820432 bulk transistors can be formed simultaneously, for example, with strained channels and self-aligned. A full MOS transistor, a MOS transistor having an object channel = aligned with a ruthenium compound, and a MOS transistor having no strain 矽 pass and no self-aligned metal telluride. Therefore, the present invention can not only (4) fabricate a plurality of MOS transistors, but also can form a MOS transistor having a multi-conformity structure for different needs (4). The above is only the preferred embodiment of the present invention, and all of the (four)izations and modifications of the patent range should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 to Fig. 6 are schematic views showing a method of raising the driving current of a MOS transistor. Fig. 7 through Fig. 13 are schematic cross-sectional views showing a method of fabricating a MOS transistor according to a first preferred embodiment of the present invention. Figure 14 is a schematic view showing the scraping surface of a MOS transistor having a stress coating layer in accordance with a second preferred embodiment of the present invention. 15 to 16 are schematic cross-sectional views showing a method of fabricating a MOS transistor according to a third preferred embodiment of the present invention. Figure 17 is a cross-sectional view showing a metal oxide semiconductor transistor having a stress coating layer in accordance with a fourth preferred embodiment of the present invention. 24 200820432 [Description of main component symbols] 1 First active region 2 Second active region 3 Third active region 10 Semiconductor substrate 12 Gate 14 Gate dielectric layer 17 Shallow junction source extension 18 Source region 19 Shallow junction Pole extension 20 Bungee region 22 Channel region 30 Liner layer 32 Sidewall sub 42 Self-aligned metal secondary layer 46 Stress overlay 48 Dielectric layer 52 Contact hole 54 Stress sidewall 110 Gold oxide transistor 120 Gold oxide semiconductor Transistor 130 MOS transistor 300 semiconductor device 301 channel region 302 active region 303 active region 304 gate oxide layer 305 polycrystalline germanium oxide 306 polycrystalline silicon gate 309 substrate 310 N-type dopant 311 offset sidewall 315 stone朋 Push region 407 Source region 408 Nom region 412 Side wall 413 Side wall 414 Side wall 462 Cerium oxide layer 464 Tantalum nitride layer 516 Mixed cover layer 818 Metal lithium 542 Cerium oxide layer 25 200820432 544 Tantalum nitride layer 26