TW200820257A - Bistable resistance random access memory structures with multiple memory layers and multilevel memory states - Google Patents

Abstract

A bistable resistance random access memory comprises a plurality of memory cells where each memory cell having multiple memory layer stack. Each memory layer stack includes a conductive layer overlying a programmable resistance random access memory layer. A first memory layer stack overlies a second memory layer stack, and the second memory layer stack overlies a third memory layer stack. The first memory layer stack has a first conductive layer overlies a first programmable resistance random access memory layer. The second memory layer stack has a second conductive layer overlies a second programmable resistance random access memory layer. The second programmable resistance random access memory layer has a memory area that is larger than a memory area of the first programmable resistance random access memory layer.

Description

TW2957PA 200820257 IX. Description of the invention: [Technology of the 4th member of the invention] Highly poorly based on the programmable resistive memory material, the method of making and manufacturing these devices Memory materials include "transoxidation (four) secret materials like other materials; / [previous technology]

Phase change.丨 丨 丨 广泛 广泛 广泛 广泛 广泛 广泛 di di di di di di di di di di di di di di di di di di The material has at least two solid phase "^ PhaSe" 'for example, an amorphous solid phase (amorphous s〇lid = CryStalline solid phase). The pulse system is applied to the pre-write optical disc. Converting the phase and reading the optical properties of the material after phase change. Phase change memory materials, such as chaleogenide materials and materials, can achieve phase changes by appropriate currents in the integrated circuit. The crystalline form (4) is characterized by a high resistivity compared to the state of the crystal form, which can be quickly sensed to the specified data. These characteristics cause the use of the Shouwang type resistive § Recall material to make a random access non-volatile Attention to the memory circuit. Generally, the amorphous state is changed to the crystalline state by the operation of low current. Here, the change from the crystalline state to the amorphous state is classified as a reset. , which includes a brief high-density current pulse to melt or collapse the crystal structure, and 'suppress the phase change process after the phase change material is rapidly cooled, so that at least one Part of the phase change 200820257 can be stabilized in an amorphous state. This part needs to minimize the magnitude of the reset current. The reset current is used to change the phase of the material from the crystalline state to the amorphous state. By reducing the phase change The cell size of the material component, and the reduction of the contact area between the electrode and the phase change material, can reduce the magnitude of the reset current during resetting to achieve a small absolute value of current through the phase change material in the high current density. The fabrication of small pores in the integrated circuit structure and the application of a small amount of programmable resistive material to fill the small pore system is a development direction. The patents for the development of small pores 10 include Ovshinsky's release on November 11, 1997. nMultibit Single Cell Memory Element Having Tapered

Contact11 (US Patent No. 5687112); "Method of Making Chalogenide [sic] Memory Device" by Zahorik et al., August 4, 1989; US Patent No. 5789277; Doan et al., November 2000 "Controllable Ovonilc" released on the 21st

Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same" (US Patent No. 6150253). 10 The manufacture of such devices with very small dimensions is problematic, and the process variations of large-sized memory devices are subject to more stringent specifications. In order to find a larger memory space, the phase change memory that can store multiple bits will be hot. SUMMARY OF THE INVENTION A bistable programmable resistive random access memory includes a plurality of programmable resistive random access memory cells. Programmable resistive random access

TW2957PA 200820257 Memory cells have multiple memory layer stacks. Each memory layer stack includes a conductive layer </ RTI> disposed on a programmable resistive random access memory layer. Each of the programmable resistive random access memory layers has a plurality of drawers, for example, a first bit system for storing a first state and a first bit system for storing a second state. The first memory layer stack is in series with the second-hex layer stack, and the second memory layer stack is coupled to the third memory layer &amp; A memory cell with three memory layer stacks can provide eight logics, or two logic states. k indicates that the number of layers of the memory layer or the memory layer stack can be increased or decreased according to the design of the memory sister. For example, if the cell has two memory layer stacks, the memory layer stack is reduced, and another two memory cells have a reading (four) shirt, and the counting stack is increased. A suitable material for a programmable resistive random access m-type random access memory layer or a third sigma-programmable resistor includes metal: two-electric: random access memory layer megnet〇resistance, CMR) Flat material 'a giant magnetoresistance (c〇l〇sSal element 0xide), phase change, diterpene oxide (three - the above mentioned materials are not used to define = poly; ^ material as a base material, material. The choice of the random access memory currency 2 is used for the first routable material and for the second programmable memory 4 (deleted: the material system can be (4) or Μ. = ί random access memory layer _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The RRAM material of the memory layer can be the same or different for each private-resistance sewing machine. Each is used for the first,

TW2957PA 200820257 The first and first various types of resistive random access systems have a range of, for example, the thickness of the material of the force, and the thickness of the material, from the large, and from the 1 to 200 nm. A wide range of devices includes a resistive random access memory configuration. The younger brother can be a program. The first conductive member and the first surface of the resistor-resistance have a plurality of sides. ϋ = formula random access memory component random access _ on the piece. The second-programmable resistance component is located on the second conductive member, and the first resistive random access memory memory member is coupled to the first-programmable resistive random access. The second programmable electrical random access memory component is the area of the string two resistor values. The second member has - indicates - the largest. Self-resistance self-remembering the area of the building - the kind used to make _ and the ancient eve 泰 泰 々 々 — — 丫 有 有 有 有 有 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆 记忆Herein, the memory of the material is located on the first programmable resistance random access ttir (four) heap (four) placed in a second memory layer stacking program; V: Hidden® includes - the second conductive layer , is located in the second - _ _ two; on the '; J hood by dry #刻 or wet fish first 丨 knife brother on a conductive layer. The left side and the right side of the first conductive layer of the random access memory layer are electrically connected to the first type: the conductive member and the first flexible member. A dielectric sidewall sub-system is deposited in the first

TW2957PA 200820257 Conductive member and the left and right sides of the first programmable resistive random access memory device. The thickness of the dielectric sidewall affects the size of the second conductive member and the second programmable resistive random access memory member. For example, if the critical dimension of the mask is about 0·15 # m, the thickness of the dielectric sidewall can be chosen to be 31 nm. That is, the area of the second programmable resistive random access memory component is approximately twice the area of the first programmable resistive random access brother. The area is inversely proportional to the resistance value, as shown by the mathematical relationship R=p(l/A), where 1 represents the length of the programmable resistive random access memory component, and symbol A represents the programmable resistive random access memory component. The area. In this example, the resistance of the second programmable resistive random access memory component is about half that of the first programmable resistive random access memory component. The resistance difference required by the first and second programmable resistive random access memory components is based on the resistance window of the programmable resistive random access memory component setting/reset (SET/RESET) (resis1: ance wind〇w The decision is made that the band-stop window is defined as the resistance ratio of the -state to the other state. Etching the second: the left layer of the electrical layer and the second programmable resistive random access memory layer (10) into a second conductive member and - the second programmable resistor type with the ^_/remembering member. - The dielectric side material is placed on the left side of the first conductive member and the resistive random access memory member. Side-down-layer, or _ to access the left and right sides of the memory layer through the 0 machine to the next layer. ~Floor. A Via plug is disclosed. According to the second aspect of the present invention, a programmable resistive random access memory having a memory layer stack of two serials 200820257-arranged is disclosed. The first memory layer stack includes a first conductive layer on a first programmable resistive random access memory layer. And the second memory layer stack includes a second conductive layer </ RTI> disposed on a second programmable resistive random access memory layer. a first turtle pressure Vbl is connected to one of the top surfaces of the first conductive layer and a second voltage

The Vb2 is connected to one of the bottoms of the second programmable resistive random access memory layer. A first programmable resistive random access memory voltage V1RRAM 1313 has a first end point connected to the first conductive member. A second programmable resistor _-type random access memory voltage VmAM1314 has a first endpoint and a second endpoint. The first endpoint is typically coupled to the first programmable resistive random access memory component and the second endpoint is coupled to the second programmable resistive random access memory component. &quot; Two important variables affect how a bistable programmable resistive random access memory transitions from one logic state to another. The first variable is not /] and represents the characteristics of a selected memory material. The second variable, _, is 彳, representing the thickness or width of the dielectric sidewall. The choice/variation of the variables/conforms to the change in resistance such that an operating window (〇perati〇n wind〇w) is sufficient to execute a multi-bit RRAM. A bistable programmable resistive random access memory has two memory layers stacked in each memory cell, and the bistable programmable resistive random access memory operates in four logic states, including a logic state. 〇〇" (or logic state "〇"), logic state "01" (or logic state "1"), logic state "10" (or logic state "2"), and logic state "11" (or logic state " 3"). The four different logic states can be represented by two variables /3 and / and a resistor i?. The logical state "〇" 11 200820257TW2957Pa is expressed in mathematical expression (1 + /). The logical state "1" is expressed in mathematical expression. The logical state Γ 2" is expressed in mathematical expression (l+/3/)i?. The logical state "3" represents the system /7(1 + /)犮 in mathematical expression. The present invention utilizes a plurality of memory layer stacks in each memory cell to increase the total density of the bistable programmable resistive random access memory. The present invention also provides a three-dimensional solution for designing and fabricating a bistable programmable electronic random access memory. The present invention further reduces the resistance variation of the bistable programmable resist random access memory. The structure and method of the present invention will be disclosed in the detailed description below. This abstract is not intended to define the invention. The invention is defined by the patent application. These and other embodiments, features, aspects and advantages of the present technology are disclosed by the following description, the scope of the appended claims and the accompanying claims. [Embodiment] Xin now provides a description of the embodiments and methods of the present invention, and with reference to the drawings shown in Figures 1 through 17. It is to be understood that the disclosed embodiments are not intended to limit the invention, but the invention may be applied to other features, elements, methods and embodiments. The same elements are generally given the same reference numerals in the same embodiment. Figure 1 illustrates an illustration of a memory array 100, the manner in which it is implemented will be described herein. The illustration shown in FIG. 1 'co-on source line 128, one word line (w〇ni Hne) 123, and word line 124 are substantially parallel to each other. In the γ direction. One yuan only 12

TW2957PA 200820257 The bit line 141 and the bit line 142 are substantially parallel to each other in the X direction. Therefore, a γ-decoder (γ-dec der) and a word line driVer located in a block i45 are coupled to the word lines 123, 124. The X-Decoder (x-dec〇der) and the - sense amplifier of one of the blocks 146 are coupled to the bit lines mi, 142. The common source line 128 is coupled to the source terminals of the transistors 150, 151, 152, and 153. The gate of the transistor 15 is lightly connected to the word line 123. The gate of the transistor 151 is consuming with the word line 124. The gate of the transistor 152 and the word line 123 are coupled to each other. The gate of transistor 153 is connected to word line 124. The drain of the transistor ι5 is coupled to the lower electrode member 132 as a sidewaU pin memory cel 1 135. The sidewall pin memory cell has an upper electrode member 134 and a lower electrode member 132. The upper electrode member 134 is coupled to the bit line 141. It can be seen here that the common source line 128 is shared by the memory cells of the two columns. As shown in the figure, one of the columns is arranged in the Y direction. In other embodiments, the transistor can be replaced by a diode. Others The structure that controls the current in the array to select the device for reading and writing data in the array can also be used to replace the transistor. 2 is a simplified block diagram of the integrated circuit 200 of the RRAM structure in accordance with an embodiment of the present invention. The integrated circuit 275 includes a memory array constructed using a sidewall active pin bistable resistance random access memory cell on the semiconductor substrate. - column 13

The 200820257 TW2957PA decoder 261 is coupled to a plurality of word lines 262 and is arranged in a memory array 260 along a column. A pin decoder 263 is connected to the plurality of bit lines 264. The bit lines 264 are arranged along the pins of the memory array 260 to capture and program the data of the sidewall pins in the memory array 260. Bus 265 provides an address to pin decoder 263 and column decoder 261. The sense amplifier and data-in structure located in block 266 are connected to pin 263 via data sink drain 267. The data is supplied from the input/output port located on the integrated circuit 275 or from other sources located inside or outside the integrated circuit 275 via the physical input line 271 to the block 2 6 6 data input structure. In the illustrated embodiment, other circuits are also included in the integrated circuit, such as a general-purpose processor, a specialiated application circuitry, or a thin film bistable resistive random access. The memory cell array provides a modular system-on-a-chip module combination. The data is provided from the inductive amplifier located at block 266, via the data output line 272, to the input/output port located on the integrated circuit 275 or to other data destinations located inside or outside the integrated circuit 275. (data destination). In this example, the controller uses a bias arrangement state machine 269 to control the application of the bias arrangement supply voltage 268, such as read-and-fetch, program, wipe, and erase verification. And stylize verification voltage. The controller is implemented by a conventional special-purpose logic circuit system (special-purpose 200820257 TW2957pa hie circuitry). In another alternative embodiment, the control

General purpose processor, its application can be on the same-integrated circuit. The I £ body circuit uses a subtraction computer program to control the operation of the device. Further, in one embodiment, the special logic circuit system and the general (10) processor are used to implement the controller.夕 = Program Resistive Random Access Memory, a simplified flow chart of the reference steps 'Bistable Resistive Random Memory

The memory system has two programmable resistive memory layers fabricated by deposition and lithography. The bistable RRAM 300 includes a first programmable resistive access memory layer 310 in series with a second programmable resistive random access k layer 320. Both the first programmable resistive random access memory layer 31 and the second programmable resistive random access memory layer 320 provide the ability to store two data states. The first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320 provide a total of four logic states in the bistable Snapdragon 300, including the first logic state "00" ( or

"0"), the second logic state "01" (or "1"), the third logic state "!〇" (or "2"), and the fourth logic state "11" (or "3"). In one embodiment, the first programmable resistive random access memory layer and the second programmable resistive random access memory layer 320 are the same material. In another embodiment, the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320 are different materials. The thickness of the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320 may be the same or different. The first programmable resistive random access memory layer 310 or the second

200820257TW2957PA Program resistive random access memory layer thickness range, for example, from i nm to 2〇〇nm ° Each programmable resistive random access memory layer 31〇 and 32〇 consists of at least two stable resistance levels (resistance) The material of ievei) is shaped as "resistance random access memory material". The following statements describe several materials that can be used to fabricate RRAM. The term "bistable RRAM" means controlling the resistance level by a voltage amplitude, an electric current amplitude or an electrical polarity. The state control of the phase change memory is handled by voltage amplitude, current amplitude or pulse time. The polarity of the bistable RRAM 300 does not affect the stylization of the bistable RRAM 300. The following statements are presented to describe a short summary of the four resistive material forms that are suitable for RRAM implementation. The first form of memory material used in the examples is a colossal magnetoresistance (CMR) material such as 镨-about-manganese oxide (PrxCayMn〇3), x:y=0.5:0.5 or scent x:0 ~l;y: other components of 0~1. The manganese oxides included in the CMR materials can be selectively used. An exemplary method for forming a CMR is to use argon (Ar) at a gas pressure of 1 m to 100 m Torr using a physical vapor deposition (PVD) ore-magnetron-sputtering method. A gas source such as nitrogen (N2), oxygen (〇2), and/or helium (He). The temperature of the sputtering is determined by the post-spray treatment and the temperature ranges from room temperature to 600 °C. Collimator with an aspect ratio of 1 to 5 16

200820257TW2957PA (collimator) can be used to improve the effectiveness of the fill. In order to improve the filling effect, a DC bias of several tens to several hundreds of volts can also be used. On the other hand, a combination of DC bias and collimator can also be used simultaneously. Dozens of Gauss w to at most one Tesla (Tesla = 10000 Gauss) can be applied to improve the magnetic crystallized phase. In a vacuum, N2 environment or 〇2/N2 mixed environment, post-deposition annealing treatment is selective to improve the crystallized state of the CMR material. Typical annealing temperatures range from 4 〇 to less than 2 hours (TC to 600 ° C. The thickness of the CMR material is determined by the design of the wafer structure. CMR from 1 〇 nm to 2 〇〇 nm The thickness can be used as a core material. YBaCu〇3 is a form of high temperature superconductor material as a buffer layer to improve The crystallized state of the CMR material. The YBC0 is deposited before the deposition of the CMR material. The thickness of the YBC0 has a range from 30 nm to 200 nm. 10 苐 Two kinds of memory materials are binary compounds such as nickel oxide (NixOy), Titanium oxide (Tix〇y), alumina (Alx〇y), tungsten oxide (wx〇y), zinc oxide (Znx〇y), oxidized hammer (Zrx〇y) or copper oxide (cUx〇y), etc. x : y = 0 · 5: 0 · 5, or x: 〇 ~ 1 ; y: other composition of Q ~ 1. The exemplary method of formation is to use metal oxide as a target, such as Nix〇y, Tix〇y, Alx 〇y, W)y, Znx〇y, Zrx〇y or Cux〇y, etc., under the pressure of 1111~1〇〇111, benefit - using Ar, N2, 〇 A reaction gas such as 2 and/or He is formed by PVD sputtering or magnetron sputtering. Deposition is usually performed at room temperature. With a aspect ratio 17 200820257XW2957pa A collimator of 1 to 5 can be used to improve the effectiveness of the filling. In order to improve the effect of filling, a DC bias of several tens of volts to several hundreds of volts can also be used. The combination of DC bias and collimator can also be used at the same time if needed. - Post-deposition annealing in a vacuum, N2 environment or 〇2/沁 mixed environment is selectively used to improve the distribution of oxygen in the metal oxide. Annealing temperature in the case of annealing time less than 2 hours, the range is from 400 °C to 600 °C ° An alternative manufacturing method using PVD sputtering or magnetron sputtering _ method, at a pressure of 1 m~1 〇〇m, using Ar/〇2, Ar/N2/〇2, pure, He/〇2 or He/N2/〇2 reaction gases such as nickel (Ni), titanium (Ti), aluminum (A1) Metal oxides such as crane (W), zinc (Zn), knot (Zr) or copper (Cu) are used as targets. Deposition is usually performed at room temperature. A collimator with an aspect ratio of 1 to 5 can be used to improve the effectiveness of the filling. In order to improve the filling, a DC bias of several tens of volts to several hundreds of volts can also be used. The combination of DC bias and collimator can also be used at the same time if required. The post-deposition annealing treatment is carried out in a vacuum, N2 environment or 〇2/N2 mixed environment to selectively use to improve the distribution of oxygen in the metal oxide. Annealing temperature in the case of annealing time less than 2 hours, the range is from 400 °C to 6 ° ° C - Another manufacturing method is by oxidation by high temperature oxidation system, such as heating, furnace or rapid heat treatment (rapid Thermal pulse, RTP) system. In a pure helium 2 or krypton/niobium 2 mixed gas atmosphere, the temperature range is from 200 Ϊ to 700, and the pressure is from a few millitorr to 1 atm. The time range can range from a few minutes to a few hours. Another oxidation method is plasma oxidation (plasma 18

200820257XW2957PA oxidation). In the RF source plasma or DC source plasma with pure (7) or red / (1) mixed gas or red / 仏 / ^ mixed gas, in the pneumatic system 1 m ~ 1 〇〇 mTorr For oxygen, the surface of the metal, such as Ti, Al, W, Zn, Zr or Cu. The oxygenation time ranges from a few seconds to a few minutes. The oxidation temperature is determined by the degree of ion oxidation. From room temperature to 300. (3. The third form of memory material is a polymer material, such as cyano-tetracyquinodimethane (TCNQ) added with Cu, • C6°, hydrazine, etc. or phenyl C61 Phenyi C61-butyric acid methyl ester (PCBM)-cyano-p-dioxane complex (TCNq) mixed hydrate. One method of manufacture is to use hotmai evaporation, electron beam evaporation. A vaporization method such as an e-beam evaporation or a molecular beam epitaxy (MBE) system. The solid phase TCNQ and the doped particles are co-evaporated in a single cavity. The TCNQ and doped particles are placed on a tungsten boat (W-boat) and a group boat (W-boat:) Or in a ceramic boat, the material source is melted by a current or an electron beam supply to mix and deposit the material on the wafer. There is no reaction chemical or gas. The deposition is performed at a pressure of 1 (Γ4~Torr. The wafer temperature ranges from room temperature to 200 °C: in a vacuum or N2 environment, post-deposition annealing is selective to improve the compositional distribution of the polymer material. The annealing temperature is in the range of room temperature to 3 Torr when the annealing time is less than 1 hour. Another technique for manufacturing a memory material layer of a polymer as a binder 19

200820257TW2957PA is a spin coater. The spin coater has a TCNQ doped solution&apos; and is rotated at less than 1 rpm. After spin coating, the wafer is placed for a period of time sufficient to form a solid phase. The temperature of the placement is typically room temperature or less than 2 〇 (rc. The time of placement is determined by temperature and manufacturing conditions, ranging from minutes to days.

The fourth form is a chalcogenide material, such as GexSbyTez 'xWz=2:2:5, or other x:0~5; y:0~5; z:〇~1{) Combination ingredients. GeSbTe can selectively use dopants such as N-, Si-, Ti~ or other elements. An exemplary method for the material of the L-based gas compound may be a gas plating method or a magnetically controlled sputtering method using a gas source of a gas source of Ar, N2 or/and He. The temperature range is usually room temperature. A collimator with a deep width of 1 to 5 can be used to improve the effectiveness of the filling. A DC bias of several tens of volts to several hundreds of volts can also be used in order to improve the filling. The combination of direct bias and collimator on the other side can also be used simultaneously. In a vacuum or N2 environment, post-deposition annealing is selectively used to modify the crystalline state of the material. The typical annealing temperature ranges from iq〇〇c to 4〇〇°c in the annealing limit and in the case of 3 姜 姜 姜. The thickness of the p+ composite material is determined by the design of the wafer structure. Generally, the chalcogenide material having a thickness of more than 8 mm has a phase change so that the material can exhibit at least two stable resistance states. The memory cell located in the bistable RRAM 300 may include: a memory material comprising a chalcogen compound; and an inch and other materials for forming a first-programmable resistive random ear 20 200820257 The blue memory layer 310 and the second programmable resistive random access memory layer 320. The chalcogen compound includes any one of the four elements oxygen (0), sulfur (S), selenium (Se), and tellurium (Te) constituting the sixth group of the periodic table. Chalcogenides include compounds having &apos;chalcogen having a plurality of electropositive elements or radicals. Chalcogenide alloys include combinations of chalcogenides with other materials, such as transition metals. The chalcogenide alloy usually includes one or more elements of the sixth row of the periodic table, such as germanium (Ge) and tin (Sn). The chalcogenide alloys mostly comprise one or more combinations of antimony (Sb), gallium (Ga), indium (In) and silver (Ag). Many phase change memory materials are described in the technical literature as having the following alloys Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/ Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te, and Te/Ge/Sb/S.

In the Ge/Sb/Te alloy family, a wide range of alloy compositions are feasible. The characteristics of the constituents can be classified as TeaGebSbioo-uHo. One investigator described that most useful alloys have an average concentration of less than 70% Te in the deposited material. The concentration of Te is less than 60%, and the concentration range is about 23% to 58%. Most of the preferred concentrations of Te are about 48% to 58%. The concentration of Ge is greater than 5% and the average range in the material is approximately 8% to 30%. Most prefer a concentration of about 8% to 40% Ge. The main constituent element remaining in this component is Sb. These percentages are atomic percentages of all atoms constituting the element (lines 1-11 of Ovshinsky's Patent 112). Another study - the specific alloys evaluated include Ge2Sb2Te5, GeSb2Te4 and

GeSb4Te7 (Noboru Yamada, !| Potential of Ge-Sb-Te 21

200820257rw2957PA

Phase-Change Optical Disks f0r High-Data-Rate

Recording," vSPJT f. Magic (4), pp. 28~37 (1997)). More broadly, transition metals such as Cr, Fe, Ni, Nb, Pd, Pt and mixtures or 'alloys can be combined with Ge/Sb /Te combines to form a phase change alloy with programmable resistance characteristics. Lines 13 to 0 of Ovshinsky's patent H2 provide specific examples of useful memory materials. These examples are included in the references. The alloy system can be converted in the first structural state and the second structural state. The first structural state of the material is a generally amorphous solid phase, and the second structural state of the material is in the active channel region of the cell body. The regional order (l〇cai order) is a general crystalline solid phase. These alloys are at least bistable. The amorphous term means a relatively less ordered structure, that is, a single crystal is not in order. The characteristic of the crystal structure, such as the resistance with a higher crystal phase. The crystal structure refers to a more ordered structure, that is to say, the order of the amorphous structure is more orderly. More The crystal phase has a low electrical resistance. In general, the phase change material can be electrically converted between different regions of the detectable state and the spectrum. The spectrum is in a fully crystalline state and a completely amorphous state. Material properties affected by changes in the crystalline phase and the amorphous phase include atomic order, free electron density, and activation energy. This material can be transferred to a different solid phase or a mixture of two or more solids to provide an Gray state* (gray SCale) of the state of the fully crystalline phase and the incompletely crystalline phase. The electrical state of the material changes correspondingly. The phase change alloy is transformed from a phase state by applying an electrical pulse 22

TW2957PA 200820257 To make the pulse of phase short and high amplitude easy to pulse, it is easy to change the phase change material to - generally the pulse energy of ^ = can make the crystal structure 嶋 ^ 匕 匕 H avoid atom realignment into crystal form status. It is not necessary to over-test to determine the curve suitable for a particular phase change. In the section disclosed below, 'phase change material means 锗-锑-碲 (GST),

It can be seen here that other forms of phase change materials can also be used. Here, the material used to implement the phase chage random access memeory (PCRAM) is described. Ge2Sb2Te5. Other programmable resistive memory materials may be used in other embodiments of the invention to determine resistance, including 1 doped GST, GexSby, or other materials that use different crystal phase variations. PrxCayMn〇3, PrSrMn〇3, Zr〇χ,

Ti〇x, AlOx or other materials use electrical pulses to change the resistance state. 7, 7, 8, 8-TCNQ, PCBM, TCNQ-PCBM, Cu-TCNQ, Ag-TC_., —-TCNQ, TCNQ doped with other metals or any bistable or multi-stable resistors controlled by electrical pulses State of the polymer material. The first conductive layer 312 is located on the first programmable resistive random access memory layer 310 and functions as a conductive element. The second conductive layer 322 is deposited between the first programmable resistive random access memory layer 310 and the second programmable resistive random access memory layer 320. The first conductive layer 312 is connected as a conductive element ′ to the first programmable resistive random access memory layer 310. The second conductive trace 322 serves as a conductive element for connection to the second programmable resistive random access memory layer 320. First conductive layer 312 23

Suitable materials for 200820257TW2957PA and second conductive layer 322 include Ti, titanium nitride (TiN), TiN/W/nN'TiN/n/Al/TiN'^ polycrystalline yttrium (n+polysillc〇n), Ti(10), Ta, TaN, TaON and other materials. In one embodiment, the first conductive layer 312 has the same material as the second conductive layer 322'. In another embodiment, the first conductive layer 312 has a different material than the second conductive layer 322. The first conductive layer 312 and the second ^&quot; electrical layer 322 may have the same or different thicknesses. The first conductive layer M2 or the second conductive layer 322 has a thickness ranging from, for example, about 1 to 200 nm. A mask 330 is formed on the first conductive layer 312. The mask 330 includes a photoresist or a hard mask such as yttrium oxide (Si〇x), tantalum nitride (SiNx), and gas oxidized (Si〇xNy). The critical dimensions of the mask 330 can be tailored to fit the desired technique in the form of a mask. If the mask 330 is a photoresist, an active ion engraver with a chemical system based on C12 or HBr can be used to remove the photoresist. If the mask 330 is a hard mask, wet dimming with a suitable solvent can be used to remove the hard mask. In certain cases, hydrofluoric acid (dilute HF) can be used to remove the hard mask produced by Si〇x. Hot phosphoric acid can be used to remove the hard mask made of Sil. 4 is a flow diagram of a step of fabricating a bistable RRAM 300, which performs an etching process to a second conductive layer 322 having dielectric sidewalls deposited thereon, a dielectric sidewall sub-system and a first conductive layer. The member 412 and the first programmable resistive random access memory member 410 are adjacent. As shown in FIG. 3, the first conductive layer 312 and the first programmable resistive random access memory layer are etched 24

rW2957PA 200820257 310 to the top surface of the second conductive layer 322, to produce the first programmable resistance type, the conductive member 412 can be a pair of the first conductive layer 310 can be: &amp; type resistive random access memory engraving, brother-etching system with the first - eclipse ~ eclipse through a # 纠 etch etch etch etched first conductive layer - relationship to the second _ chemical tips 312, The machine accesses the memory layer 31〇. The 耘-type resistance type is determined by the material. For example, if: ^^ selects a single-material or a plurality of materials, which is used as the material of the first-programmable resistor m412 member 410, then the access memory is CL-etched as the first ribbon s The Qi 〇 etch step is based on the muscle as the second; the layer to the chemical 'second money 31'. The suspicion of learning:; =; resistive random access memory layer ^ to the younger brother a dielectric sidewall 430 is deposited in the first programmable resistance random access ink, die m, 丨Μ = component 41G and - The left and right (four) H electric side walls (10) of the electrically conductive member 412 are located on a portion of the top surface of the reed. Suitable materials for the flute 9 ^ _ and _, _ electric sidewall 430 include

The Sl〇x and Si lion readings have a predetermined thickness (four) of the thickness of the second conductive member 512 (such as the area map of the second and second programmable resistive random access memory members 51). </ RTI> If the mask 330 is - the critical dimension is about 0.15 / zm, the predetermined thickness can be about 31 nm, so that the area of the second programmable resistive random access memory member 51 is about the first programmable The area of the resistive random access memory component 410 is twice as large. In other words, in the same logic state, such as the set or reset state, the second programmable resistor 25

The resistance of the W2957PA 200820257 type random access memory unit 51 is approximately half of the resistance of the first programmable resistive random access memory unit 410. The % difference of the first programmable resistive random access memory component 410 and the second programmable resistive random access memory component 510 is determined by the setting/resetting power limit window of the pen resistance type. If the setting/resetting window is about 10 times (an order of magnitude 〇f magnitude), the first programmable resistive random access memory unit 41 is coupled to the first programmable resistive random access memory unit 51. The difference in resistance is about 2 times more appropriate. Figure 5 depicts the non-bistable programmable resistive random access memory 500, which is etched through a second programmable resistive random access memory layer. The last name of the second conductive layer 322 and the second programmable resistive random access memory layer 32G (as shown in FIG. 3) to the top surface of the bottom layer, or from the active side = the edge of the machine to the bottom layer (such as Figure 6) to generate I. The ^' 512 and the second programmable resistive random access memory device can be a single non-isotropic etch of 2 layers! 20 for the second conductive, 3 2 2 and second programmable resistors. Etching process or conductive ί 3 2: 'II-one etching: etching the second type of electricity with the first etching chemistry: random storage: etching the second etchable material with the second etching chemistry or: Material 2 layer etching chemical random random access memory structure: 2 used as the second programmable resistance type of money engraving step to C1 your material, then perform the two-step money engraving, the first thing, the second money engraving step ^ For the second step of the second conductive member 512, SF8 is used as the second programmable resistance type 26

200820257TW2957PA The surname of the random access memory component 510 is a chemical. Figure 6 is a simplified flow chart of a programmable resistive memory cell structure that does not have a bistable and sturdy private resistive random access memory. The programmable resistive memory cell structure exemplifies that the underlying layer 610 is passed by the surname, as described above in the section of FIG. The programmable resistive memory cell structure of the bistable programmable resistive random access memory layer includes a bottom layer 610 and is located under the second programmable resistive random access 5 MIMO component 510. The bottom layer 61 刻 刻 刻 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 到达 。 。 。 。 。 。 。 。 。 。 The bottom layer 610 is connected to a via plug 620. Contact holes 620 are deposited under the bottom layer 610 with an intermediate dielectric layer 630 surrounding it. The contact hole 620 includes a tungsten germanium contact hole (w-plUg) or a poly-Si plug in the embodiment. The polycrystalline germanium contact hole may be composed of a polycrystalline spine or a NP diode. FIG. 7 is a diagram showing an example current-voltage curve 700 of a bistable programmable resistive random access memory having a programmable resistive random access memory layer, wherein the X-axis represents voltage 710 and the y-axis represents current. 720. In Reset ® Status 730, the programmable resistive random access memory layer is low resistance. In the set state 740, the programmable resistive random access memory layer is in a high resistance state. In this example, the set/reset window of the programmable resistive random access memory layer is approximately one order of magnitude read voltage 750. The read voltage 75, indicated by dashed line 752, is used to show a significant distance between the high current state (or high logic state) and the low current state (or low logic state). After a voltage stress, the current is raised from the reset state 730 to the high current state, falling from the set state 740. 27

2〇〇820257: The rise and fall of the W2957PA flow from a low state to a high state or from a high state to a low state makes it difficult for the voltage controller to distinguish different logic and multi-layer states. The programmable resistive random access memory layer can be used to achieve different logic states in the bistable programmable resistive random access memory. Each programmable resistive random access memory layer has its own area or resistance. Figure 8A depicts a simplified flow of a bistable programmable resistive random access memory without two programmable resistive random access memory components. These programmable resistive random access memory components are Reset status. = the first programmable resistive random access memory component 41 and the second programmable = resistive random access memory component 51 are all in a reset state, the bistable programmable resistive random access memory 600 In the logical state of "〇〇" = operation. The second programmable resistive random access memory unit 51 has an I-resistance i? 810' and the first-programmable resistive random access memory member 41 is: - resistance / i? 82G. Variable / greater than! Because the area of the first-programmable resistor _$ random access memory member 410 is smaller than the second programmable resistance type, the area of the machine access memory member 510. The total resistance of the bistable programmable resistance random memory is approximately (10)) j?. For example, if the number of texts/system is 2 ’, the total amount of electricity can be calculated and the mathematical equation is (1+2) shame 3i?. The eight-figure 8B picture shows two programmable resistive random access memory structures. The simplification of the bistable programmable resistive random access memory of the pottery is two programmable resistive random access memory components. It is in the set state and 4 set state. When the first-stage program resistive random access memory member 41〇 28

TW2957PA 200820257 is a set state and the second programmable resistive random access memory device 5l is reset. The bistable 4 programmable resistive random access memory 600 is in a logic state, "〇1" Mode operation. The second programmable resistive random access memory component 510 is held in a reset state or has not changed state. The second programmable resistive random access memory device 51 has a resistor i? 810, and the first programmable resistive random access memory member 41 has a resistor 830. The variable ϋ can be greater than 2. The total resistance of the bistable programmable resist random access memory 600 is approximately (1+/2/) 犮. For example, _, if the variable ί is 2 and the variable £/ is 1〇, then the total resistance is 21i?, where the mathematical expression is (1+2〇) shame 21i?. FIG. 8C is a simplified flowchart of a bistable programmable resistive random access memory 600 having two programmable resistive random access memory components consistent with the present invention, such programmable resistive random access The memory component is set to a state and a reset state. When the first programmable resistive random access memory component 410 is in a reset state and the second programmable resistive random access memory 510 is in a set state, the bistable programmable resistive random access memory The 600 Series operates in a logical state of "1". The first programmable resistive random access memory component 410 is in a state of being reset or not changing. The second programmable resistive random access memory device 51 has a resistor 850, and the first programmable resistive random access memory member 410 has a resistor 860. The variable 15 can be greater than one. The total resistance of the bistable programmable resist random access memory 600 is approximately (n + f)i?. For example, if the variable f is 2 and the variable η is 1〇, then the total resistance is 12i?, where the mathematical expression is 29

200820257rW2957PA (10+2) iM2i? 〇 8D shows a simplified flow of a bistable programmable resistive random access memory 600 with two programmable resistive random access memory components - such a programmable Resistive random access memory components are in a set state. When the first programmable resistive random access memory component 410 and the second programmable resistive random access device and the component 510 are in a set state, the bistable programmable resistive random access memory 600 is Operate in the logical state rn". The second programmable resistive random access memory device 51 has a _ resistor 870, and the first programmable resistive random access memory member 41 has an electrical supply 880. The total resistance of the bistable programmable resistive random access memory 600 is approximately η(1 + /) and . For example, if the variable 歹 is 2 and the variable /3 is 10, then the total resistance is calculated as , where the mathematical expression is 10 (1 + 2) shame 30i?. FIG. 9 is a schematic diagram showing the mathematical relationship between the bistable programmable resistive random access memory 600 having two programmable resistive random access memory components connected in series, which are identical to the present invention. The program resistive random access memory component provides four logic states and each memory cell provides rain bits. Three variables are used in the resistance relation, η and ^:. The variable i? represents the reset resistance of the memory component. The variable η is related to the characteristics of the resistive memory material. The variable / is related to the thickness of a dielectric sidewall. In other words, the variable η is determined by the characteristics of the material selected. The variable f can be controlled by the thickness of the dielectric sidewalls. In the logic state "〇" 91〇, the total resistance of the bistable programmable resist random access memory 600 is approximately (l + i)i?. In the logic state "〗" 92, bistable programmable resistance random 30

TW2957PA 200820257 The total resistance of the access memory 600 is about (the 930, bistable programmable resistance random surgery fans). The total resistance of each memory access memory 600 is (10) m. "3" _ type resistive random access memory coffee _ Ί if μ if Miao effect, ^ people &lt; ~ flying resistance system is about n (l + i) i?. Variables are adjusted to match the king, resistance changes 'Let the operation 电阻 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ And the variable pays, the 2-bit operation window can be calculated as 3i?, l〇2i?, 20ii? to 300 and. Figure 10 Green does not have multiple memory components bistable programmable resistance random access As shown in the figure, a plurality of programmable resistive random access memory components are connected in series to provide a plurality of bits in each memory cell. The bistable programmable resistive random access memory includes a plurality of a programmable resistive random access memory layer connected in series. In other words, the first programmable resistive random access memory layer 31 The second programmable resistive random access memory layer 320 is connected in series, and the second programmable resistive random access memory layer 320 is connected in series with the third programmable resistive random access memory layer 1010, ... 'the (n-Dth can The program resistive random access memory layer 1020 is connected in series with the nth programmable resistive random access memory layer 1〇3〇. In one embodiment, the first, second, third, ... (n_1)th, The nth programmable resistive random access memory layers 310, 320, 1010, 1 20, 1030 provide the ability to store two logic states. In additional embodiments, the first, second, third, ... (n_l) The thth, nth programmable resistive random access memory layers 310, 320, 1010, 1020, 1030 all provide the ability to store more than 31 200820257 round two bits of data. In other embodiments, the first and second Third, the (nl)th, nth programmable resistive random access memory layer 310,

320, 1010, 1020, 1030 all provide the ability to store two or more bits of data, each of which has the ability to store multiple levels of data. The total number of logic states of the bistable programmable resistive random access memory is determined by the number of X bits of each programmable resistive random access memory layer and the y bits of each bit. The number of bits. The mathematical expression is Zx〃, where the symbol Z represents the total number of programmable resistive random access memory layers. For example, if the bistable programmable resistive random access memory 100 has eight private resistive random access memory layers, each of the private resistive random access memory layers can be stored. The data of one bit and each bit stores two logic states or current levels, then the total number of logic states can be calculated as 8&quot;2 or 64 logic states. The first, first, second, ... (nl)th, first, programmable resistive random access memory layers 310, 320, 1010, Li), 103Q may have the same or different materials 'or specific The program random access memory layer has the same material' while the remaining programmable resistor access memory layer has a combination of the same material. In addition, the first, the _th, the second (n-1)th, the nth programmable resistive random access memory layer, 1010, 1020, 1030 may have the same or different thickness, or a specific program resistive random The access memory layer has the same thickness, and the port α-type resistive random access memory layer has another group of the same thickness. [1, 2, 3, ... (nKnth programmable resistor) Random access memory layers 310, 320, 1010, 1020, 1〇3〇 have an example of corpse 32

TW2957PA 200820257 degrees, ranging from 1 nm to 200 legs. Each programmable resistive random access memory layer is interconnected with a conductive layer. In addition to the above mentioned first and second conductive layers, the third conductive layer is occluded in the third programmable electric (four), the program resistive random storage memory recalls! 〇 32 the 11th picture shows the first, the first - w &amp; a 电阻-type resistive random access device 410, 51〇 and the first and second dielectric sidewalls, the bistable programmable resistance random access memory of a stream (4) ^ The machine access memory member 410, 510_etched 43 (3, lm system is formed. _ spear can be further implemented in the continuation of the first and second programmable motor access § the memory components 410, 51 Can be 10 + 4 current reed, such as 篦 - π 妒 private private resistance random access:: Resistive random access memory layer 1_. In this case is _ third programmable resistance random access _ Layer ι_ _ _. The corresponding dielectric sidewalls may also be deposited between the conductive layer and the programmable resistive access memory layer - in the embodiment 'second shouting resistive random access The area of the memory structure 510 is determined in advance by the thickness of the first dielectric sidewall 汕. The screen y also, the third programmable resistive random access memory member 121 The surface is also determined in advance by the thickness of the second dielectric sidewall 111. Therefore, the four programmable resistive random access memory layers have the meaning of the dielectric sidewall 33 200820257 - one ... one u TW2957PA ^First &amp; individual area' makes each programmable resistive random access layer have individual resistance values.

Figure 12 depicts a plurality of possible removable sidewalls. A flowchart of the bistable resistive random access memory 12 (10) of the resistive Ik machine accessing 5&amp; The bistable programmable resistive random access memory 1200 includes a first conductive member 412 located on the first programmable resistive random access memory member 41. The first programmable memory access device 41 is located on the second conductive member 512. The second conductive member 512 is located on the second programmable resistive random access memory member 510. The second programmable resistive random access memory member 51 is located on the third conductive member 1220. The third conductive member 122 is located on the second programmable resistive random access memory device 1210. The first conductive member 1040 is located on the nth programmable resistive random access memory layer. In one embodiment, the first conductive member 412 has the same width as the first programmable resistive random access memory member 410, and the width is smaller than the second conductive member 512 and the second programmable resistive random access memory member. Width of 510. The second conductive member 512 has the same width as the second programmable resistive random access memory member 510, and the width is smaller than the width of the third conductive member 1220 and the second programmable resistive random access memory member. The width of the nth conductive member 1040 and the first programmable resistive random access memory layer 1030 is typically wider than the width of the above-mentioned programmable resistive random access memory member and conductive member. As illustrated in Figures 12 and 13, the bit line voltage is supplied to the bistable programmable resistive random access memory 600 to achieve different logic.

rW2957PA 200820257

Evil. The bistable programmable resist random access memory 5 (10) in Fig. 5 can be represented by the equivalent circuit system of Fig. 13. In this example, two programmable resistive random access memory layers are described, and the additional memory layers and corresponding bit line voltages are also increased. The circuit system 1300 has a first resistor Ri 1310 representing the resistance of the first programmable resistive random access memory component 410, and a second resistor h 1312 representing the second programmable resistive random access memory component. 51 〇 resistor. The second resistor 匕 1312 is connected between the first bit line voltage Vm 132 〇 and the second bit line voltage Vm 1330. The first bit line voltage Vbi 132 is connected to the first bit line BL1 1340. The second bit line voltage - 133 is connected to the second bit line Bu 1342. The first bit line voltage Vbi 132 is connected to the top surface of the first conductive member 412, and the second bit line voltage l 133 is connected to the bottom surface of the second programmable resistive random access memory member. In this embodiment, the bistable programmable resistive random access memory 5 includes two and first programmable resistive random access memory components 41 and a second programmable resistive random access memory component. 51 〇 related voltage. The two voltages are represented by the symbol VlR_&amp; VmAM 1314 to respectively correspond to the first voltage associated with the first programmable resistive random access memory component 41 and to the second programmable resistive random access memory component 51. Two voltages. The first programmable resistive random access memory voltage Virram 1313 has a first endpoint and a second endpoint. The first end point is coupled to the first conductive member 412. The second endpoint is coupled to the first programmable resistive random access memory component 410. The second programmable resistive random access memory voltage 1314 has a first end point and a second end point. The first endpoint is usually associated with the first executable 35

The 200820257rW2957PA resistive random access memory component 410 is connected to the first programmable resistive random access memory voltage Vi_m1313. The second endpoint is coupled to the second programmable resistive random access memory component 510. An additional programmable resistive random access memory can be applied to successive programmable resistive random access memory and memory components, such as a third programmable resistive random access memory voltage V3R_1316 system and a second removable type The random access resistive memory member 121 is connected. When the bistable sorrowable resistive random access memory 5 is reset, that is, when the reset state is reached, the bistable programmable resist random access memory 10 starts at a logic state. 〇" (or logic state "00"). The bistable programmable resist random access memory 6 (10) can be programmed from a logic state of "0" to a logic state "1" (or logic state "01"). Or from the logic state "〇" to the logic state "2" (or the logic state "1〇"). Or from the logic "0" to the logic state "3" (or logic state "11"). The bistable sorcerer resistive random access memory 500 is programmed from the logic state "00" to the logic state "10", supplying the first voltage to the first bit line 'to become the first bit line voltage 1320, and supplying the second voltage to the second bit line to become the second bit line voltage Vb2 1330. The supply to the first 兀 line voltage Vbl 132 可 can be a negative voltage of 〇 or small. The first 70-wire power ^ ^ 1320 and the second bit line voltage Vb2 1330 are the same as the first programmable resistance random access memory voltage. Virram1313 and the second programmable resistance random access memory voltage _ of V2R_ 1314. In mathematical expressions, the system is

Vb2-Vm^e_+V2RRAfVi()w. The first programmable resistive random access memory structure 36

The initials of 200820257TW2957PA and the first programmable resistive random access memory component are reset, which is the low resistance state. In this embodiment, the resistive type I random access memory member 41 has a smaller area than the second: programmable resistive random access memory member 510. Therefore, the first-programmable resistive random access memory member 41 has a larger resistance than the second programmable resistive random access memory member 510. This indicates that the value of the first programmable resistive random access memory voltage Virram 1313 is greater than the second programmable resistive random access memory voltage v_ 1314. In mathematical expressions • System 4 W &gt; V_. If the value of the first programmable resistive random access memory voltage Vi_1313 is greater than a set voltage (Vi_&gt;VsET), the first programmable resistive random access memory component 410 transitions from the reset state to the set state (in other words) In other words, it is a high resistance state). If the value of the second programmable resistance return memory access voltage VmAM 1314 is less than a set voltage (VmMasn), the second programmable resistive random access memory device 510 remains in the reset state. The resistance in the first programmable resistive random access memory block 410 is changed from a logic state of "0" (or a logic state "(10)") to a logic state of "2" (or a logic state of "10"). The logic state "〇" has a resistance of (1 + ί) and the logic state of "2" has a resistance of (ι + Ώ /). For example, if the variable /=2 and the variable /1=10, the reset resistance of the second programmable resistive random access memory member 510 is equal to and the total resistance value will change from 3i? to 21. The bistable programmable resistive random access memory β〇〇 is supplied by the logic state “〇” (or logic state “00”) to the logic state “3” (or logic state “11”). Voltage to the first bit line to become 37

200820257rW2957PA is the first bit line voltage vbl 1320, and supplies the second voltage to the second bit line to become the second bit line voltage V, 2 1330. The supply to the first bit line voltage 1320 can be a negative voltage of 0 volts or less. The first programmable resistance type - the random access memory component 410 and the second programmable resistive random access memory = the initial state of the component 510 are all in a reset state, in other words, in a low resistance state. The voltage difference between the first bit line voltage 132 () and the second bit line voltage Vb2 133 足够 is sufficiently high (vhigh) that the first programmable resistance random access memory member 410 has the first programmable resistance random The second programmable resistance random access memory voltage V2RRAM 1314 of the access memory voltage _ν·ΑΜ1313 and the second programmable resistive random access memory unit 51 is higher than Vset. The resistance states of the first programmable resistive random access memory means and the second programmable resistive random access memory means 51 are changed from the reset state to the set state. The resistances of the first and second programmable resistive random access memory components 410, 510 are changed from a logic state "〇" (or a logic state "〇〇") to a logic state "3" (or a logic state "11"). The logic state "0" has a resistance of + and a logic state of "2" has a resistance of &lt;1 + /). For example, if the variable and the variable /2 = 10, the reset resistance of the second programmable resistive random access memory member 510 is equivalent to J, and the total resistance value will be changed to 30i?. The bistable programmable resistive access memory 600 is stable by a logic state "〇" (or logic state "00") to a logic state "1" (salty logic state "01"). The state programmable resistive random access memory 600 first sequentially changes the logic state "〇" to the logic state "3" (or the logic state "11"). First and second programmable resistive random access codes 38

TW2957PA 200820257 The components 410, 510 are changed from the reset state to the set state. The voltage supplied to the second bit line voltage ^ 1330 is a negative voltage that can be crouched or small, the mathematical expression of which is. The voltage supplied to the first bit line -Vm 1320 is - positive voltage. In the set state, the first programmable resistive random access memory component 410 has an area smaller than the second programmable resistive random access memory component 510 such that the first programmable resistive random access memory component 410 has a Greater than the resistance of the second programmable resistive random access § memory component 510. This represents a situation in which a higher voltage is passed through the first programmable _ resistive random access memory member 410. Its mathematical form is 丨VlOAM | &gt;丨VmAM |. If the absolute value of the first programmable resistive random access memory voltage VimMl313 is greater than the reset voltage (|VimM|&gt;VmET), the first programmable resistive random access memory component, 410 is switched to the reset state ( Low resistance state). If the absolute value of the second programmable resistive random access memory voltage V2RRAM 1314 is less than the reset voltage (丨V2RRAM丨<VresET), the second programmable resistive random access memory device 510 remains in the set state. The first and second programmable resistive random access _ memory elements 410, 510 are switched from logic state "3" (or logic state "11") to logic state "1" (or logic state "〇1" ). The logic state "3" has a resistance system of + logic state "〗". The resistance system is, for example, if the variable /=2 and the variable ', then the logic state changes from "0" to "3", the second programmable resistance The reset resistance of the random access memory component 510. is equivalent to the allowable, and the total resistance value changes V from 3i? to 30i?. When the logic state is changed from "3" to "1", the reset resistance of the second programmable resistive random access memory member 510 is equivalent to 39.

2〇〇82〇257rW2957PA i?, and the total resistance value will change from 30i? to 12i?. The resistors Ri 1310 and R2 1312 are placed in series between the two bit lines BL· 1340 and BL2 1342. The voltages supplied to the respective bit lines are represented by Vm 1320 and Vb2 1330. The voltage drop across the two resistors is Vu· - and V2RRAM, so the voltage drop across the two power lines is equivalent to ViRRAM + V^AM. As shown in the figure, the area of the first programmable resistive random access memory member 410 is smaller than the area of the second programmable resistive random access memory member 510. Therefore, the resistance R! is larger than the resistance R2. • Table 1 Status/Value Reset Setting 1 (01) Setting Reset 2 (10) Reset Setting 3 (11) The state of the RRAM and the resulting cell value are shown in Table 1. The cell value corresponds to the relative resistance value. It is worth noting that the embodiment of Table 1 is represented by a small-endian structure. That is to say, the last component is the least significant digit (MSD) and the most significant digit. Other embodiments follow a big-endian module in which the numerator is saved and the following procedure is the same procedure, but two memory elements are saved. As shown in Figures 8A through 8D, it is used to explain the source of each cell state to describe the relationship exhibited by each cell state. Figure 8A

200820257TW2957PA describes the cell body of the first memory element Mi and the second memory element M2. The first memory element Mi includes a first programmable resistive random access memory member 410 and a first conductive member 420. The second memory element M2 includes a second programmable resistive random access memory member 510 and a second conductive member 520. The two components are here - a reset state with low resistance. If the i? is the resistance of the second second programmable resistive random access memory component 510, the other first programmable resistive random access memory component 410 has a random stored memory relative to the second programmable resistive memory. The resistance value of the memory member 510 is taken as a constant value /. 10 In the embodiment, the first programmable resistive random access memory component 410 has a higher resistance than the second programmable resistive random access memory component 510, so the constant f is greater than one. However, other embodiments are inversely related to semantics. As described above, the resistance difference of the embodiments of Figs. 8A to 8D is caused by the difference in size between the two programmable resistive random access memory members. Smaller programmable resistive random access memory components have higher resistance. In other embodiments (not shown in the figure), it is possible to achieve the same operation mode by using two components of different materials, but the resistance is different. The different structures of the two examples do not affect the way in which the relationship is expressed. However, the difference here can still be known by constants. In this embodiment, the two programmable resistive random access memory components are approximately the same thickness, but the widths of the two programmable resistive random access memory components are different (as described in more detail below). ), and the difference in width produces a difference in resistance. Two programmable resistive random access memory components are connected in series

2〇〇820257rW2957PA is arranged, so the total resistance of the cell body can be expressed as a group or (l+/)i?. Convert the low-order component m2 to the set state as shown in the δΒ diagram. Converting low-order components has a higher resistance level to ground. The resistance level is boosted by an equal ratio to the constant of the constant J2. Different materials will exhibit different constants - depending on the specific compound or the characteristics of the choice. However, if a specific material is given, the relationship between the reset and the set state can be expressed as shown in the first figure, hi?. Therefore, the state interpolated in Fig. 8B can be described by the expression or U+iOi?. • Similarly, Figure 8C depicts the result of a RRAM component I transitioning to the set state Μ' and Μι remaining reset. In the embodiment, when the materials of the two members are the same, the constant/3 system describes the difference between the set state and the reset state, and the ili?/ is used to describe the resistance value, and the electrical value of the cell body of this part is (l+i2/)i? Description. Finally, Figure 8D illustrates the conversion of two programmable resistive random access memory components Μι and M2 to the ruined dimension to produce the allowable pi? (M2) and (Μ!). This status can be expressed as stun or nG + iOi?. The semantic relationship excerpts related to the four cell values are as shown in the second table. 'The second table cell value relationship cell value (l+/)i? 0(00) (niOR 1(01) 2(10 ) n(l+〇R 3(11) 42

An example of the 200820257 TW2957PA sensing window can be achieved by setting the parameters /2, / and . If ?? = 104 Ω, with 10 and /= 2, the resistance of the four states can be 3 χΐ〇 4 Ω, L 2 χ 1 〇 5 Ω, 2 · 1 χ 1 〇 5 Ω, and 3 χ 105 Ω. With an induced voltage of -120 mv (reading the electric house), the induced currents of the four states are 4) A, 1 // A 0. 6 # a and 〇. 4 # A. The partial voltage of the multi-layer operation can be set to 2.5 #A, 0.8, and 〇.5 #A. It has a higher resistance than 2, and the lowest resistance state can be defined as "0" state (or state 〇 &amp; 〇). When the induction current is lower than 5·5 # A, the highest resistance ^ can be defined as the "3" state (or state "11"). When the current is low, the low resistance state can be set to "1" state (or state "01"). When the induction current is higher than 0 5 but lower than t8, the high resistance state can be defined as "2". 4 The change in current should be changed in the process of the mosquito. The wide yield (4) changes in the heart. For example, the thickness of the dielectric sidewall is equal to or greater than the thickness of the surface of the two-dimensional resistive random access memory device. Tianshi, = resistive random access memory component, and a wide The operation window is used to execute high-quality multi-bits, and the value of Tian Qiao _ number is higher, for wider = _ thus avoiding the state of product failure. BL memory cell to f evaluation is provided by - Cross-bit line 虬 and all possible values. It is understandable in the technique shown in the table of the syllabus + Chengdi 1 that many possibilities exist in the direct _ _ use two positive voltages (including Zhengdi 43

200820257rw2957PA is based on Vb2 vs. Vm) and two negative voltages. The resulting voltage is represented by Vhigh, Vlow, -Vhigh and -Vlow. The absolute value of the voltage supplied depends on the characteristics of the memory component, including the materials and dimensions used. In the embodiment - the high voltage value of 3.3 volts and the low voltage value of 1.5 volts are proved to be ... effective values. The first process is a general reset process in which the first process drives the programmable resistive random access memory device to a reset state such that the cell value is zero. This procedure is shown in Table 3 below. _ 3rd table all reset transition process V2-Vl = ~Yhigh component state cell body action component state cell body Μι 1 3 | Vl | &gt;VsET 0 0 M2 1 1 V2 1 &gt;Yreset 0 Appropriate for this transition process The voltage value is shown as -Vhigh, so that the absolute value of the voltage drop of each VlRRAM and V2RRAM exceeds the reset value. When both of the resistive random access memory components are reset, the total cell value is 0 〇 The reset condition is the starting point for all further operations. Since the unpredictable results may occur in the intermediate state of the transition, it is desirable to reduce the unit to reset condition as the first step of any state change operation. On the contrary, the cell value is 3, as shown in the fourth table below. Transition Process 44 of Table 4 0-3 200820257 Erlang Myanmar TW2957PA Vb2*'Vbl==Vhigh Component Status Cell Body Action Element State Cell Μι 0 0 Vi&gt;Yset 1 3 M2 0 V2&gt;VsET 1 Here, The supply voltage Vhigh is such that the two components are sufficient to cause a voltage drop above VSET. When both components are in the set state, the cell value is 11 or 3 of the two bits. The process of generating a memory cell value of 2 is shown in Table 5 below. Conversion process of Table 5-2 (Yb2-Vbl)-Vlow Element state Cell body action element state cell body 0 0 0 Vl&gt;VsET 1 2 M2 0 V2&lt;VsET 0 In this setting, the voltage drop Vi is greater than required The value of the set condition is generated, so Rl is set as the setting, but the voltage drop V2 is less than the value required for setting, so that the component is reset. The Ri system is set and the R2 system is reset, and the cell value is the result of 01 or 2 of the two bits. The cell value yielding 1 is shown in Table 6 below. The process of achieving a value of 1 is more difficult than the other embodiments. Intuitive observation shows that when both components start to be reset, a voltage sufficient to cause V2 to generate a set state must be provided, and V! is also the same. This will result in a cytometry of 3, not 1. The solution to this situation is to first transform the cell body into a complete setting. 45 200820257

Second violation _ arc. TW2957PA sad, as shown in the third table above. Next, starting from the cell value system 3, a voltage -V_ is supplied to generate a reset state of Ri but not 匕 so that the cell value produces two bits 01 or 1. Transition process of Table 6 3-1 (Yb2-Vbl) = - Vibw Component state Cell body action element state Cell body Μ 1 1 〇 J1H &gt; Vset 0 M2 1 0 v2 丨 &lt;vSET 1 1 Figure 14 shows bistable The programmable resistive random access memory 600 is programmed from the logic state "〇〇" to the flow chart 14 of the other three logic states "〇1", "10" and "11". In step 1410, the bistable programmable resistive random access memory 600 is in a logic state "00". If the bistable programmable resistive random access memory 600 is programmed from the logic state "00" to the logic state "01", first, in step H20, the bistable programmable resistive random access memory 600 Transition from logic state "00" to logic state "11". In step 1430, the second stylized step transitions from a logic state "11" to a logic state "〇1". In step 1420, the bistable programmable resistive random access memory 600 is programmed from a logic state "00" to a logic state "11". The voltage difference between the first bit line voltage Vm 1320 and the second bit line voltage Vb2 1330 is equivalent to a high voltage Vh_, which is represented by a mathematical expression Vbl_Vb2 = Vhigh. The second programmable resistive random access memory voltage V2RMM 1314 is larger than the voltage Vset, and the first programmable resistive random access memory voltage VimM1313 is larger than the voltage VSET. Step 46 200820257

—• 迁目 m . TW2957PA In step 1430, the bistable programmable resistive random access memory 6 is programmed from the logic state "11" to the logic state "〇1". The first bit line is Vbi 1320 and the other one line voltage Vb2 1330 is equal to the difference, and a negative low voltage -Vuw is expressed in mathematical expression Vb2-Vbl=-v^. - The absolute value of the second programmable resistive random access memory voltage VmM 1314 is smaller than the absolute value of the voltage Vreset, and the absolute value of the first programmable resistive random access memory voltage Virram 1313 is larger than the absolute value of the voltage vRESST. In step 1440, the bistable programmable resistive random access memory _600 is programmed from a logic state "〇〇" to a logic state "1". The voltage difference between the first bit line voltage Vbi 1320 and the one bit line voltage Vb2 1330 is equivalent to a low voltage V-, expressed in mathematical expressions Vb2 - Vbl =: Vh5w. The second programmable resistance is random The access memory voltage VmAM 1314 is smaller than the voltage ySET, and the first programmable resistive random access memory voltage V1RRAm1 313 is larger than the voltage Vset. In step 1450, the bistable programmable resistive random access memory 600 is logic The state "00" is programmed to the logic state "11". The voltage difference between the first bit line voltage Vw 1320 and the second bit line voltage Vm 1330 is equivalent to a high voltage Vhigh, which is represented by a mathematical expression Vbi-Vb2 = Vh handsome. The second programmable resistive random access memory voltage V2RRAM 1314 is larger than the voltage Vsn, and the first programmable resistive random access memory voltage Vi_1313 is larger than the voltage Vset. Figure 15 is a flow chart showing the bistable programmable resistive random access memory 600 programmed from the logic state "01" to the other three logic states "〇〇", "10" and "11". . In step 1510, the bistable programmable resistive random access memory 6 〇 0 is in a logic state "〇1". Step 47 200820257

In the TW2957PA 1520, the bistable programmable resistive random access memory 6 is programmed from the logic state "01" to the logic state "〇 〇". The voltage difference between the first bit line voltage Vbi 1320 and the bit line voltage Vb2 1330 is equivalent to a negative high voltage -Vhuh, which is expressed in mathematical expression Vm-Vb2&gt;Vhigh. The absolute value of the second programmable resistive random access memory voltage y2RRM 1314 is larger than the voltage Vmn, and the absolute value of the first programmable resistive random access memory voltage Virram 1313 is larger than the voltage VRESET. If the bistable programmable resistive random access memory 600 is programmed from the logic state "01" to the logic state "10", the bistable programmable resistive random access memory 600 is first in step 1530. Stylized from logic state "〇1" to logic state "00". Next, in step 1540:, the logic state "〇〇" is programmed to the logic state "10". In step 1530, the bistable programmable resistive random access memory 600 is programmed from a logic state "〇1" to a logic state "00". The voltage difference between the first bit line voltage ^ 132 〇 and the second bit line voltage Vm 1330 is equivalent to a negative high singular voltage, expressed in mathematical expressions Vbl-VbF-Vhigh. The absolute value of the second programmable resistive random access memory voltage VmAM 1314 is larger than the voltage yRESST, and the absolute value of the first programmable resistive random access memory voltage Vi_1313 is larger than the voltage Vreset. In step 1540, the bistable programmable resist random access memory 600 is programmed from the logic state "00" to a logical state - evil "10". The voltage difference between the first bit line voltage Vbi 1320 and the second bit line voltage '1330 is equivalent to a low voltage Vlc&gt;w, expressed in mathematical expressions Vm-Vb^ViQW. The second programmable resistive random access memory voltage 1314 is larger than the voltage VREsn, and the first programmable resistive random access memory 48 200820257

Second 遂 Burmese. TW2957PA voltage Vl_13l3 is smaller than voltage V to make T small. In step 1550, the bistable programmable resistive random access memory 600 is programmed from a logic state "01" to a logic state "11". The voltage difference between the first 'yuan line voltage Vw 1320 and the second bit line voltage Vt&gt; 2 1330 is equivalent to a high voltage Vhw, expressed as a mathematical expression VM-Vb2 = Vhigh. The second programmable resistive random access memory voltage y2_ 1314 is larger than the voltage Vset, and the first programmable resistive random access memory voltage ViRRAM1313 is larger than the voltage VsET. _ Figure 16 shows a flow chart 1600 of the bistable programmable resistive random access memory 600 programmed from the logic state "1" to the other three logic states "〇〇", "01" and "11" . In step 1610, the bistable programmable resistive random access memory 600 is in a logic state "10". In step 1620, the bistable programmable resistive random access memory 6 is programmed from the logic state "10" to the logic state "〇〇". The voltage difference between the first bit line voltage Vw 1320 and the second bit line voltage vb2 1330 is equivalent to a negative high voltage -Vhigh, expressed in mathematical expressions vbl - vb2 - Vhigh. The absolute value of the first programmable resistive random access memory voltage V2RRAM 1 3 1 4 is larger than the voltage Vmn, and the first programmable resistive random access memory voltage ViRRAm1313 has a large Vrese. If the bistable programmable resistive random access memory 600 is programmed from the logic state "10" to the logic state "01", the bistable programmable resistive random access memory 600 is first in step 1630. Stylized from logic state "10" to logic state "11". Then, in step 164, the logic state "11" is programmed to the logic state "01". Step 1630 49 200820257

In the TW2957PA, the bistable programmable resistive random access memory 6 state "10" is programmed to the logic state "11". The voltage difference between the first bit line voltage v= and the second bit line voltage Vb2 1330 is recognized

Vhish, expressed in mathematical expression, is Vbi_Vb2=Vhigh. :回宅压禾-式音* Resistive Be machine access § 丨思思V2RRAM 1314 voltage vi V SET y 3 versatile programmable random access memory voltage Virram1313 is greater than voltage % step 1640 in 'stable State programmable resistance random access

It is programmed from the logic state "11" to the logic state "1〇.^ _ , ". The electric line difference between the first line voltage Vm 1320 and the second bit line voltage vb2 133〇 is equal to a negative low voltage -viC)W ’ mathematical expression of the formula ' 〆 , clothing is not

Vbi-Vb2=-Vi〇w. The absolute value of the second programmable resistance random access memory voltage v 1314 is larger than the absolute value of the voltage Vreset, and the absolute value of the first light gas resistive random access memory voltage VimMl313 is greater than the absolute value of the electric house. small. In step 1650, the bistable programmable resistive random access memory 6 is programmed from a logic state "10" to a logic state "11". The voltage difference between the first bit line voltage Vw 1320 and the second bit line voltage Vm 1330 is equivalent to a high voltage Vhigh, expressed as a mathematical expression Vbl~Vb2 = Vhigh. The second programmable resistive random access memory voltage V2_1314 is larger than the voltage VSET, and the first programmable resistive random access memory voltage Vi_1313 is larger than the voltage Vset. Figure 17 is a flow chart Π 00 of the bistable programmable resistive random access memory 600 programmed from the logic state "11" to the other three logic states "〇〇", "〇1" and "10". In step 1710, the bistable state can be 50 200820257

1W2957PA Program Resistive Random Access Memory 600 Logic State 1720, bistable programmable resistive random access memory = set state "11" is programmed to logic state "00. The first 'thinking

Vbi 1320 and the first bit line electric waste Vb2 1330 voltage difference is equal to the negative electric waste -Vhigh, expressed in mathematical expression is ~ ~; The second programmable resistance random access memory voltage V2rram 13l4b ^gh^h° is more electric than v_* 'and the first programmable resistance random access memory

The absolute value of Virram I313 is larger than the voltage vRESET. ^ In step 1730, the bistable programmable resistive random access memory 600 is programmed from a logic state "11" to a logic state "〇1". The voltage difference between the first bit line voltage Vm 1320 and the second bit line voltage Vb2 133 系 is equivalent to a negative low voltage, expressed as a mathematical expression Vbl - Vb2 = -Vi〇W. The first programmable resistive random access memory voltage 1314 has a larger absolute value than the voltage Vreset, and the absolute value of the first programmable resistive memory voltage V1RRAM is smaller than the absolute value of the voltage VRmT. If the bistable programmable resistive random access memory 6 is programmed from the logic state "11" to the logic state "10", the bistable program can be programmed. * ' · Resistive random access sibling The 600 system first transitions from a logic state "11" to a logic state "00" in step 1740. In step 1750, the logic state "(9)" is second programmed to the logic state "1". In step 1740, the bistable programmable resistive random access memory 6 is programmed from a logic state "11" to a logic state "〇〇". The voltage difference between the first bit line voltage Vbi 1320 and the second bit line voltage Vb2 1330 is equivalent to a negative high voltage in a mathematical expression for the system Vbl-Vf_Vhigh. The 51st 200820257

The absolute value of the first programmable resistance random access memory voltage VlRRAIi 313 is larger than the voltage VrESET. In step 1750, the bistable ^ programmable resistive random access memory 600 is programmed from a logic state "00" to a logic state "10". The voltage difference between the first bit line voltage Vh 1320 and the second bit line voltage Vm 1330 is equivalent to a low voltage Vh, expressed in mathematical expression for the system VM-Vb2 = Vlow. The second programmable resistance random access memory voltage V2RRAM 1314 is larger than the voltage VsET, and the first programmable resistance _ random access memory voltage Vi_l 313 is lower than the voltage VseH. For additional information on the fabrication, material composition, use, and operation of phase change memory devices, reference is made to US Patent No. n/155,067, π ΤΜ Film Fuse Phase Change RAM and Manufacturing Method (June 17, 2005). The present invention is incorporated by reference to the assignee of the present disclosure. The scope of the invention is defined by the scope of the appended claims.

Erda Number: TW2957PA [Simplified Schematic] FIG. 1 is a schematic diagram of a bistable programmable resistance random access memory array according to the present invention. 2 is a simplified block diagram of an integrated circuit of an RRAM structure in accordance with an embodiment of the present invention. 3 is a simplified flow chart showing a reference step of fabricating a bistable programmable resistive random access memory according to the present invention. The bistable programmable resistive random access memory system is fabricated by deposition and lithography. _ Two programmable resistive random access memory layers. 4 is a flow chart showing a step of manufacturing a bistable programmable resistive random access memory in accordance with the present invention, the step of performing an etching process to a second conductive layer having deposited dielectric sidewalls. The dielectric sidewall sub-system is adjacent to the first conductive member and the first programmable resistive random access memory device. Figure 5 is a flow chart showing a step of fabricating a bistable programmable resistive random access memory layer in accordance with the present invention, the step of etching through a second programmable resistive random access memory layer. Figure 6 is a simplified flow chart showing the programmable resistive memory cell structure of the bistable programmable resistive random access memory according to the present invention. Figure 7 is a diagram showing an example of current-voltage curves of a bistable programmable resistive random access memory having a programmable resistive random access memory layer in accordance with the present invention. * FIG. 8A is a diagram showing a bistable programmable resistor having two programmable resistive random access memory members in a reset state according to the present invention 53 200820257

A simplified flow chart of the TW2957PA type random access memory. Figure 8B is a simplified flow diagram of a bistable 'programmable resistive random access memory with a programmable resistive random access memory device in a set state and a reset state in accordance with the present invention. Figure 8C is a simplified flow diagram of a bistable programmable resistive random access memory having two programmable resistive random access memory devices in a set state and a reset state in accordance with the present invention. Figure 8D is a simplified flow diagram of a bistable programmable resistive random access memory having two programmable resistive random access memory components in a set state in accordance with the present invention. Figure 9 is a diagram showing the mathematics of four logic states of four logic states provided by two bistable programmable resistive random access memories having two programmable resistors in series with each other in accordance with the present invention. Relationship. FIG. 10 is a flowchart showing a process flow of a bistable programmable resistive random access memory having a plurality of bit-programmable random access memory modules connected in series to each other to provide a plurality of bits in each memory cell according to the present invention. Figure. 11 is a diagram showing steps of a bistable programmable resistive random access memory including an etching step of a first and a second programmable resistive random access memory layer and a deposition step of a dielectric sidewall according to the present invention. flow chart. 12 is a flow chart showing a process of bistable programmable resistive random access memory having a plurality of programmable resistive random access memory members and conductive members after removing dielectric sidewalls according to the present invention. . Figure 13 is a diagram showing the supply voltage according to the present invention to have two 54 200820257

Sanda number: TW2957PA Circuit diagram of a bistable programmable resistive random access memory of a programmable resistive random access memory device. ... Figure 4 shows that the bistable programmable resistance random access 5 according to the present invention is programmed from the logic state "〇〇" to the other three logic state factories 01"'"10" and " Flow chart of 11". Figure 15 is a flowchart showing the flow of the bistable programmable resistive random access memory according to the present invention from the logic state "01" to the other three logic states _ "00", "1" and "11" Figure. The figure shows that the bistable programmable resistance type random 1 1 2 3 4 memory is programmed from the logic state "10" to the other three logic states ^ 〇 ", 〇 1" and "u" according to the present invention. Flow chart. Figure 17 is a flow chart showing the bistable programmable resistance type random access memory according to the present invention programmed from the logic state "11" to the other three logic states (10), "01" and "10". 55 1 [Description of main component symbols] 2 10〇, 260: Memory array 123, 124, 262: Word line 128: Common source line 132 133 • Lower electrode member 3 ▲ 134: Upper electrode member 4 - 135: Side wall connection Foot memory cells 141, 142, 264: bit lines U5, 146, 266: block 200820257

Erda number: TW2957PA 150, 151, 152, 153: transistor 200, 275: integrated circuit 261: column decoder 263: pin decoder '265: bus bar 267: data sink drain 268: bias arrangement supply Voltage 269: biased state machine

• 271: data input line 272: data output line 274: other circuit 300: bistable RRAM 310: first programmable resistive random access memory layer 312: first conductive layer 320: second programmable resistive random memory Taking memory layer 322: second conductive layer • 330: mask 410: first programmable resistive random access memory member 412, 420: first conductive member 430: first dielectric sidewall sub-500: bistable Program resistive random access memory 510: second programmable resistive random access memory component 512, 520: second conductive member 600: bistable programmable resistive random access memory 56 200820257 建建鱿· TW2957PA 610: bottom layer 620: contact hole 630: intermediate dielectric layer 700: current-voltage curve example diagram 710: voltage 720: current 730: reset state 740: set state 750: read voltage 752: dashed line 810, 820, 830, 850, 860, 870, 880: Resistor 910: Logic state "0 920: Logic state "1 930: Logic state "2 940: Logic state "3 1000 1012 1010 1020 1022 1030 1032

Bi-stable programmable resistive random access memory third conductive layer third programmable resistive random access memory layer (η -1) 1 h programmable resistive random access memory layer (nl)th conductive Layer nth programmable resistive random access memory layer nth conductive layer 1040: nth conductive member 1110: second dielectric sidewall 57 200820257

A class of face fox TW2957PA 1200: bistable programmable resistance random access memory 1210: third programmable resistance random access memory component 1220: third conductive member '1300: circuit system - 1310: first resistance 1312: second resistor 1313: first programmable resistive random access memory voltage 1314: second programmable resistive random access memory voltage • 1316 · third programmable resistive random access memory voltage 1320: First bit line voltage 1330: second bit line voltage 1340: first bit line 1342: second bit line 1400, 1500, 1600, 1700: flowchart 58

Claims (1)

TW2957PA 200820257 X. Patent Application Range: 1. A memory device comprising: a first conductive member located in a first programmable resistance random access memory member (first programmable resistance random access memory member) The first programmable resistive random access memory device has an area representing a first resistance value, and the first conductive member and the first programmable resistive random access memory member each have a plurality of sides ;and a second conductive member is disposed on a second programmable resistive random access memory member, the first programmable resistive random access memory member Positioned on the second component, the first programmable resistive random access memory component and the second programmable resistive random access memory component are connected in series, and the second programmable resistive random access memory The member has an area representing a second resistance value. The second programmable resistance type access memory member has an area larger than an area of the first programmable resistance random access memory device. 2. The device of claim 2, wherein the second programmable, resistive random access memory component has a large area "double the area of the first programmable resistive random access memory component" 3. The device of claim 19, wherein the picking device further comprises a first dielectric spacer (fim spacer) disposed on the first conductive member and the first a circuit array 59 200820257 rW2957PA type random access memory member on the side of the 'and the first dielectric sidewall is also placed on the top surface of the second conductive member, wherein the second programmable resistance random The area of the access memory member is a function of the first dielectric state; the sub-t-degree. 4. The device of claim 1, wherein the device further comprises a third conductive member. (thini ^ndueii = flieinbei·) is located on a third programmable resistance random access memory member (third programmable resistance random access memory member), the second programmable resistive random access memory component is located On the third conductive member, The second programmable resistive random access memory component is connected in series with the third programmable resistive random access memory component, and the second programmable resistive random access memory component has a third resistance value. The area of the third programmable resistive random access memory device is greater than the area of the second programmable resistive random access memory device. 5. The device of claim 4, The memory device includes a second dielectric sidewall disposed on a side of the second conductive member and the first flexible resistive random access memory device, wherein the third programmable resistor The area of the random access memory device is a function of the thickness of the second dielectric sidewall. The apparatus of claim 1, wherein the first and second programmable resistance are random The access memory component provides two logic states (log two states) 'the serial combination of the first programmable resistive random access memory component and the second programmable resistive random access memory component 200820257 The TW2957PA system provides four logic states. 7. The device of claim 4, wherein the first, the second, and the third programmable resistance random access memory components respectively provide a logic state, the first programmable resistive random access memory component and the serial combination of the second programmable resistive random access memory component and the third programmable resistive random access memory component provide eight logics 8. The device of claim 1, wherein the first programmable resistive random access memory component and the second programmable resistive random access memory component have the same material characteristics. 9. The device of claim 1, wherein the programmable resistive random access memory component and the second programmable resistive random access memory component have different material characteristics. 10. The device of claim 1, wherein the first programmable resistive random access memory component and the second programmable resistive random access memory component have the same thickness. The device of claim 1, wherein the first programmable resistive random access memory component and the second programmable resistive random access memory component have different thicknesses. 12. The device of claim 1, wherein the first programmable resistive random access memory component has a thickness between 1 and 200 awake. The device of claim 1, wherein the first programmable resistive random access memory device comprises a metal oxide, and the gold 61 TW2957PA 200820257 is an oxide system of nickel oxide (Ni〇x) ), titanium oxide (Ti〇x), oxidized crane (w〇x), alumina (Al〇x), oxidized hammer (Zr〇x), zinc telluride (211〇〇 or copper oxide (CuOx) ° 14· The device of claim 1, wherein the first programmable resistive random access memory device comprises a giant magnetoresistance material, the giant magnetoresistive material being fin-calcium-manganese oxide (PrCaMn) 〇 3) or 镨-lithium-manganese oxide (prSrMn〇3). The device of claim 1, wherein the first programmable resistive random access memory member comprises a three-element compound (three-e 1 ement c (10) pound), the ternary compound being doped Cr-doped SrTi〇3 (Cr) or Nb-doped SrTiCh doped with sharp ((4)). 16. The device of claim 1, wherein the first programmable resistive random access memory device comprises a polymer (p〇lymer) which is a copper-tetracyano-p-butadiene (Cu-TCNQ (tetracyquinodimethane)) or TCNQ/phenyl C61-butyric acid methyl ester (PCBM). 17. The device of claim 1, wherein the first programmable resistive random access memory component is selected from the group consisting of two or more materials of a group of materials. ), recorded (Sb), bismuth (Te), sillimanite (Se), indium (In), titanium (Ti), gallium (Ga), secret (Bi), tin (Sn), copper (Cu), le ( Pd), (Pb), silver (Ag), sulfur (S), gold (Au) or a combination thereof. The apparatus of claim 1, wherein the second programmable resistive random access memory member comprises a metal oxide, the metal oxide is nickel oxide (Ni0x) , titanium oxide (Ti0x), tungsten oxide (w0x), alumina (A10x), oxidized hammer (Zr〇x), zinc oxide (Zn〇x) or copper oxide (CuOx) 〇19· as claimed in the scope of the article The device, wherein the second sturdy resistive random access memory member comprises a giant magnetoresistive material system as a spectrum-dance-dye oxide (PrCaMn〇3) or a spectrum-Ming-Meng oxide (PrSrMn〇) 3). The device of claim 1, wherein the second programmable resistive random access memory device comprises a ternary compound which is Cr-doped SrTi〇3 or doped Nb srTi〇3. The device of claim 2, wherein the second private resistive access memory member comprises a polymer, the polymer being Cu-TCNQ or TCNQ/PCBM. The device of claim 1, wherein the second private-type refractory tunnel access memory component is selected from the group consisting of two or more materials of a group of materials, the group material comprising Ge, %, &amp;, ^, ΙΠ ^ Tl ^ ^ M ' Sn / Cu ^ Pd ^ Pb ^ Ag ^ S ^ Au 〇 23 · The device according to claim 1, wherein the first electricity The member has the same thickness as the second conductive member. The device of claim 7, wherein the first conductive member and the second conductive member have different thicknesses. ,. The device of claim 1, wherein the first conductive member has a thickness of between 1 nm and 200 nm. The apparatus of claim 1, wherein the first conductive member comprises titanium nitride (TiN), TiN/W/TiN, TiN/Ti/Al/TiN or n+ double crystal slab (n+ polysilicon). The device of claim 1, wherein the memory device further includes a bottom layer deposited under the second programmable resistive random access memory device to form a plug connection. 28. A method for fabricating a programmable resistive random access memory, comprising: 10 forming a first conductive layer on a first programmable resistive random access memory layer; forming a second conductive layer The first programmable resistive random access memory layer is located on the second conductive layer on the second programmable resistive random access memory layer, and the first programmable resistive random access memory layer is The second programmable resistive random access memory layer is connected in series; a mask is placed on a top surface of the first conductive layer to etch the first conductive layer and the first programmable resistive memory Taking a side of the memory layer to form a first conductive member and a first programmable resistive random access memory member, the first programmable resistive random access memory member has a first resistance value And forming a first dielectric sidewall on a side of the first conductive member and the first programmable resistor: and a top surface of the second conductive layer ·, 'where the second can Resistive Random Access Memory function layer having a thickness that one surface of the product line of the first dielectric sidewall spacers. The method of claim 28, wherein the second conductive layer is a function of the thickness of the first dielectric sidewall. 30. The method of claim 28, wherein the mask comprises a photo resist or a hard mask, the hard mask comprising yttrium oxide (SiOx) ), tantalum nitride (SiNx) or bismuth oxynitride (SiOxNy). 31. The method of claim 30, wherein if the mask is the photoresist, the photoresist is based on chlorine (C12) or based on boronic acid (HB2). The reactive ion etcher is trimmed. 32. The method of claim 30, wherein if the mask is the hard mask, the hard mask is removed by wet trimming. 33. The method of claim 32, wherein the hard mask is trimmed by distilling hydrofluoric acid (di lute HF) if the hard mask comprises SiOx. The method of claim 32, wherein if the hard mask comprises the material SiNx, the hard mask is trimmed by hot phosphoric acid. 35. The method of claim 28, wherein the method further comprises: forming a third conductive layer on a third programmable resistive random access memory layer, the second programmable resistive memory Taking a memory layer on the third conductive layer, the second programmable resistive random access memory layer and the 65 200820257 —* TW2957PA third programmable resistance random access. 36. as claimed in the patent scope:: ^ It is connected in series. The method further includes the method of: wherein the side places a second dielectric sidewall on the first programmable resistive random access memory member X, a conductive member and the second sidewall are also disposed On the side of the third conductive layer, the second dielectric etches the second conductive layer and the %. a side of the '· and the memory layer to form a second guide: a lightly resistive random access resistive random access memory member, the second, the second and the second programmable electronic component have One represents a second resistor and can be long-resistance random access memory. 37. The method of claim 3, the third conductive layer, and the third programmable resistance type, wherein the first area is the second dielectric side/random access memory layer .38·If you apply for patent scope item 28: 2. The first conductive layer and the method of etching the side, wherein the material of the side is etched, and the electrical layer of the packaged resistive random access memory layer: the edge surname and the engraving step are by the -th chemical Etching the first-guided, sputum-engraving step is performed by a second chemical etched by the first programmable resistor controller (4). The method of claim 38, wherein if the first conductive layer is TiN and the first side light resistive random access k layer is Al〇x, The first etch etch includes a etch step based on ch, the second etch step comprising/being a BC13 based rudder step. 66