TW200810162A - Method of fabricating flip chip substrate connecting with multi chips and having anti electrostatic destruction property and the device thereof - Google Patents

Method of fabricating flip chip substrate connecting with multi chips and having anti electrostatic destruction property and the device thereof Download PDF

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TW200810162A
TW200810162A TW96134578A TW96134578A TW200810162A TW 200810162 A TW200810162 A TW 200810162A TW 96134578 A TW96134578 A TW 96134578A TW 96134578 A TW96134578 A TW 96134578A TW 200810162 A TW200810162 A TW 200810162A
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layer
flip
conductive layer
chip substrate
substrate
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TW96134578A
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Chinese (zh)
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TWI347689B (en
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lian-bi Zhang
Xin-Yi Zhang
Guo-Ling Jiang
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Univ Chang Gung
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Abstract

The invention provides a method of fabricating flip chip substrate connecting with multi chips and having anti electrostatic destruction property and the device thereof. The flip chip substrate with conductive layer, insulation layer, and conductive layer capacity (CIC) is patterned by photo mask so that plural light emitting devices can connect with the flip chip substrate with CIC capacitor. The flip chip substrate with CIC capacity is composed of semiconductor layer, insulation layer, and semiconductor substrate. The semiconductor substrate is formed by high heat dissipation material. The insulation layer is formed by material of high dielectric or high break down voltage. Therefore, not only it can protect the plural light emitting devices to avoid the destruction by the electrostatic discharge but also save the cost and reduce the space of assembled plural light emitting devices. The effect of high heat dissipation is achieved by the semiconductor substrate.

Description

200810162 九、發明說明, 【發明所屬之技術領域】 : 本發明係提供一種可連接多顆晶片及具有防靜電破 :壞之覆晶基板的製造方法及其裝置,尤指—種將多顆發光 板導體元件連結於一覆晶基板上的製造方法,可保護發光 二極體半導體元件免於靜電放電破壞’且具有散熱佳、體 積小及價袼便宜之優點。 • 【先前技術】 有關於保護發光二極體半導體元件免於靜電放電破壞 的方法,請參閱證書號第⑺⑴4號「一種保護一化合物 半導體免於靜電放電破壞的方法及具靜電保護能力之覆晶 半導體元件」之發明專利,其中該步驟為: (a )形成該發光二極體半導體於一 光二極體半導體具有-多層結構及一第一與—第電中= (b)形成一導電層絕緣層導電層(CIC)電容覆晶基 _板,其中該導電層絕緣層導電層(CIC)基板上具有一第一及 一第二電極; (c )分別電性連結該發光二極體半導體元件之第一 及第二電極至該導電層絕緣層導電層(CIC)電容覆晶基板 之第一及第二電極。 其中該導電層絕緣層導電層(CiC)電容包括··半導體層 /、&緣層/半導體基板(SIS);或者是金屬層/絕緣層/半導體 基板(MIS);或是金屬層/絕緣層/金屬層等結構。 由於忒覆日日封装半導體結構,係以導電層絕緣層導電 5 200810162 層(C I C )作為覆晶半導體的基板,在正常工作時漏電流小, 同時在直流工作電壓時不會有導通之慮,因此可保護化合 物半導體免於靜電放電破壞。 然而,此種導電層絕緣層導電層(c I c)電容覆晶半導體 的基板’只有電容結構,若將其絕緣層以高介電係數材料 完成使其電容加大將有利於洩放靜電,或是過電壓材料平 時是電容,過電壓時便成短路電阻也能增進洩放功能;200810162 IX. Description of the Invention, Technical Field of the Invention: The present invention provides a manufacturing method and a device for connecting a plurality of wafers and an antistatic cracking: a flip chip substrate, in particular, a plurality of light emitting materials The manufacturing method of connecting the plate conductor element to a flip-chip substrate can protect the light-emitting diode semiconductor element from electrostatic discharge damage and has the advantages of good heat dissipation, small volume, and low cost. • [Prior Art] For the method of protecting the LED component from electrostatic discharge damage, please refer to Certificate No. (7)(1) No. 4 "A method for protecting a compound semiconductor from electrostatic discharge damage and flip chip with electrostatic protection capability. The invention patent of the semiconductor device, wherein the step is: (a) forming the light-emitting diode semiconductor in a photodiode semiconductor having a multi-layer structure and a first and a second electricity = (b) forming a conductive layer insulation a conductive layer (CIC) capacitor flip-chip layer, wherein the conductive layer insulating layer (CIC) substrate has a first electrode and a second electrode; (c) electrically connecting the light emitting diode semiconductor component The first and second electrodes are connected to the first and second electrodes of the conductive layer insulating layer (CIC) capacitor flip chip. Wherein the conductive layer insulating layer conductive layer (CiC) capacitor comprises: · semiconductor layer /, & edge layer / semiconductor substrate (SIS); or metal layer / insulating layer / semiconductor substrate (MIS); or metal layer / insulation Structure such as layer/metal layer. Since the semiconductor structure is packaged on a daily basis, the conductive layer insulating layer 5200810162 layer (CIC) is used as the substrate of the flip-chip semiconductor, and the leakage current is small during normal operation, and there is no conduction during the DC operating voltage. Therefore, the compound semiconductor can be protected from electrostatic discharge damage. However, such a conductive layer insulating layer conductive layer (c I c) capacitor flip-chip semiconductor substrate only has a capacitor structure, and if the insulating layer is made of a high dielectric constant material to increase its capacitance, it will facilitate the discharge of static electricity. Or the overvoltage material is usually a capacitor, and when it is overvoltage, the short circuit resistance can also improve the bleed function;

此外,鈾案之導電層絕緣層導電層(d c)電容覆晶半導 體的電容結構,只能連接一顆發光二極體半導體元件,因 此一顆發光二極體半導體元件就要有一導電層絕緣層導電 層((310¾谷覆日日半導體的基板,而多顆發光二極體半導體 元件就要有多個導電層絕緣層導電層(CIC)電容覆晶半導 體的基板,如此不僅成本高,且多顆發光二極體半導體元 Μ 什、々;夕干攸爭相 域之研究開發與設計經驗,努力研發如何降低發光二 半導體元件之散熱、體積及價格,經詳加設計與審慎 後’終得一確具實用性之可連接多顆晶片及具有防靜 壞之覆晶基板的製造方法及其裝置。 【發明内容】 欲解決之技術問題點, (CIC)電容覆晶半導體的基板, 導體元件,其具有下列缺點: 習知的導電層絕緣層導電層 、月b連接一顆發光二極體半 一、如要使用多顆發光二極^ 從體+導體元件就要 導電層絕緣層導電層(CIC)電容 夕1 旻日日半導體的基板,且多顆 6 200810162 發光二極體半導體元件連結後,成本非常高。 二、 如要使用多顆發光二極體半導體元件就要有多個 :導電層絕緣層導電層(CIC)電容覆晶半導體的基板,多顆發 :光二極體半導體元件連結後,體積會較大。 三、 現有導電層絕緣層導電層(CIC)電容覆晶結構, 其絕緣層以一般介電係數材料完成,錢放功能有限; 本發明解決問題之技術特點,係提供一種可連接多顆 籲晶片及具有防靜電破壞之覆晶基板的製造方法,包括有: 步驟一:係製作多顆發光二極體半導體元件,並使每 一顆發光二極體半導體元件形成有一第一電極及一第二電 極; 步驟一.係製作導電層絕緣層導電層(C 1C)電容覆晶基 板,該導電層絕緣層導電層(CIC)電容覆晶基板為半導體 層、絕緣層、半導體基板組合而成;該半導體基板為高散 熱材λ所形成;該絕緣層為介電材料所形成;若將其絕緣 鲁層以高介電係數材料完成使其電容加大將有利於洩放靜 電’或是過電壓材料平時是電容,過電壓時便成短路電阻 也能增進洩放功能。 步驟三:係將導電層絕緣層導電層(CIC)電容覆晶基板 之半導體層圖形化以製作光罩,並形成有數組之第一電極 及第二電極; 步驟四:將各顆發光二極體半導體元件之第一電極及 第二電極,分別與該導電層絕緣層導電層(CIC)電容覆晶久 板的各第一電極及第二電極電性連接。 200810162 藉由此方法,本發明另提供一種可連接多顆晶片及具 有防靜電破壞之覆晶基板的裝置’其係包括: -至少一發光二極體半導體元件,各發光二極體半導體 :兀件係在一基板上依序設有一晶核層、一導電緩衝層、主 動層、一上束缚層一下束缚層、一接觸層、一第一電極及 一第二電極; 一導電層絕緣層導電層(CIC)電容覆晶基板,該導電層 絕緣層導電層(C 1C)電容覆晶基板,為半導體層、絕緣層、 半V體基板組合而成,該導電層絕緣層導電層(CIC)電容覆 晶基板上之_冑體層_化形,並形成有數組之 第一電極及第二電極;該導電層絕緣層導電層(CIC)電容覆 晶基板的各第-電極及第二電極可分別藉由焊料球與各顆 發光二極體半導體元件之第一電極及第二電極電性連結。 本發明除了藉由導電層絕緣層導電層⑹c)電容覆晶 基板保護發光二極料導體元件免於靜電放電破壞外,同 時也可於-個導電層絕緣層導電層(CIC)電容覆晶基板可 接多顆發光二極體半導體元件形成陣列結構。 對照先前技術之功效,係提供—種可連接多顆晶片及 具有防靜電破壞之“基板的製造方法及其裝置,本發明 除了可保護發光二極體半導體元件免於靜電放電破壞外, 由於其加人了將導電層絕緣層導電層(ΠΟ電容覆晶基板 …體層圖形化之步驟’ @此—個導電層絕緣層導電層 :)電容覆晶基板可接多顆發光二極體半導體元件陣列 結構’不僅可節省成本’亦可減小多顆發光二極體半導體 8 200810162 元件串接後之體積。 有關本發明所搡 ‘ 休用之技術、手段及其功效 : 佳實施例並配合圖式^ 口式砰細祝明於后,相信本發 : 的、構造及特徵,當可ώ今〜 田可由之得一深入而具體的 【實施方式】 本發明餘提出—σΓ ^ * 種可連接多顆晶片及具有 之覆晶基板的製造方法及其裝置。 請參閱第一圖至箆匹 ❿ 口王乐四圖所不’其係方法為 步驟一(S 1 ):係製作多顆發光二極體丰 每一顆發光二極體半導體元件(如第二圖所示 板(1 0 )上依序設有一晶核層(丄丄)、一導電 2)、主動層(1 3)、一上束缚層(1 3丄 3 2)、一接觸層(1 4)、一第一電極(1 5 ) 極(1 6 ); 其中該第一電極(1 5 )上可鍍銀作為反 _使發光二極體半導體元件之發光效果更好; 步驟一(S 2 ):係製作導電層絕緣層導^ 容覆晶基板,該導電層絕緣層導電層(c丨c)電$ (2 0 )(如第三圖所示),為半導體層、絕緣 基板組合而成; 其中該半導體基板為高散熱材質所形成, 紹(A 1N ),可達到高散熱且價格便宜之優點; 其中該絕緣層為介電材料,高介電材料, 潰材料所形成,包括為二氡化砍(Si〇2)、氮化 .,兹舉-較 明上述之目 瞭解。 防靜電破壞 •導體元件, )係在一基 緩衝層(1 7束缚層(工 及~第二電 射層,藉以 1層(CIC)電 &覆晶基板 層、半導體 包括為氮化 與過電壓崩 矽(Si3N4), 9 200810162 _ »ί 一氧化給(Hf〇2)、一氧化鍅(Zr〇2)、及稀土氧化物等等· 步驟三(S 3 ):係將導電層絕緣層導電層(c丨◦電容 -覆晶基板(2 0 )之半導體層圖形化,以製作光罩(2 4 ) :(如第四圖所示),並形成有數組之第一電極(2 1)及第 二電極(22)(如第三圖所示); 步驟四(S 4 ):將各顆發光二極體半導體元件之第一 電極(1 5 )及第二電極(1 6 ),經由焊料球(2 3 )分 鲁別與該導電層絕緣層導電層(CIC)電容覆晶基板(2 0 )的 各第一電極(2 1 )及第二電極(22)電性連接。 其中’請參閱第四圖所示,係本發明導電層絕緣層導 電層(CIC)電容覆晶基板(2 0 )之半導體層圖形化製作光 罩佈局示意圖,由於發光二極體所發出的光,光的照射會 有不均勻的現象,例如,發光二極體的路燈,光不會往側 邊照射,因此本發明導電層絕緣層導電層(CIc)電容覆晶基 板(2 0 )於半導體層圖形化製作光罩(2 4 )時,光罩 肇(2 4 )佈局可經過設計,使數顆發光二極體與導電層絕 緣層導電層(C 1C)電容覆晶基板(2 〇 )連結時,藉由光罩 (2 4 )佈局去達成所需之光場,使光場分布也可經由晶 粒在子基板上由不同圖案化植晶而達成。 另外’本發明導電層絕緣層導電層(C 1C)電容覆晶基 板(2 0 )上可進一步形成數反光凹洞,每一凹洞可供至 少一顆發光二極體放置,如此當發光二極體發光時,可藉 由凹洞達到聚光效果,並讓光線朝上發射時,所照射之距 離可以更遠且更亮。 10 200810162 藉由上述之設計,本發明在正常操作下,當順向偏壓 施加於V+與V-之間時,一電流從第—電極(1 5 )流過半導 :體部份,而使所產生的光(3 〇)經由基板(1 〇)發出;當 :有異常電壓或靜電產生時,放電路徑便會轉至導電層絕緣 層導電層⑹〇電容覆晶基板(2 Q)上,而不會通過半導體 部份,此時本發明所形成的保護機制便纟2,時開始啟動 保護,最佳例可以承受人體模式耐壓到8κν。 φ 本發明除了可保護發光二極體半導體元件免於靜電 放電破壞外,由於其加入了將導電層絕緣層導電層(cic) 電容覆晶基板(20)《半導體層圖形化之步驟,因此一 個導電層絕緣層導電層(CIC)電容覆晶基板(2 〇 )可接多 顆發光二極體半導體元件形成陣列結構,改良習知一個導 電層絕緣層導電層(CIC)電容覆晶半導體基板,只能接一顆 發光二極體半導體元件之缺點;如此不僅可節省成本,亦 可減小多顆發光二極體半導體元件串接後之體積。 Φ 本發明之發光二極體半導體元件為多顆,發光所產生 的熱度非常的高,導電層絕緣層導電層(CIC)電容覆晶基板 (2 0 )必須有良好的散熱,才能將多顆發光二極體半導 體元件連結於一導電層絕緣層導電層(CIC)電容覆晶基板 (2 0 )上;因此本發明導電層絕緣層導電層(CIC)電容覆 曰曰基板(2 0 )之半導體基板可為石夕(si)或是氮化銘 (A1N),可使發光二極體半導體元件具有高散熱之效果, 且價格便宜,可降低成本。 藉由上述之方法,本發明另提供一種可連接多顆晶片 11 200810162 及具有防靜電破壞之覆晶基板的裝置,參閱第二圖至第三 圖所示,其係包括: 至少一發光二極體半導體元件,各發光二極體半導體 元件(如第二圖所示)係在一基板(1 〇 )上依序設有一晶 核層(1 1)、一導電緩衝層(1 2)、主動層(1 3)、一上 束缚層(1 3 1 )—下束缚層(1 3 2)、一接觸層(1 4)、 一第一電極(1 5)及一第二電極(1 6); 其中該第一電極(1 5 )上可鍍銀作為反射層,藉以 使發光二極體半導體元件之發光效果更好; 一導電層絕緣層導電層(CIC)電容覆晶基板,該導電層 絕緣層導電層(CIC)電容覆晶基板(2 〇 )(如第三圖所 示),為半導體層、絕緣層、半導體基板組合而成,該導電 層絕緣層導電層(CIC)電容覆晶基板(2 〇 )上之半導體層 圖形化形成有光罩(2 4)(如第四圖所示),並形成有數 組之第一電極(2 1 )及第二電極(2 2 )(如第三圖所示); 且該導電層絕緣層導電層(CIC)電容覆晶基板(2 〇 )的各 第-電極(2 1 ) A第二電極(2 2 )可分別藉由焊料球 (23)與各顆發光二極體半導體元件之第一電極(15) 及第二電極(1 6 )電性連結; 可達到高散熱且價袼便宜之優點 其中該導電層絕緣層導電層 上之絕緣層為介電材料,古 其中该導電層絕緣層導 〇)上之半導體基板為高散 (A1N)In addition, the conductive structure of the conductive layer insulating layer (dc) capacitor flip-chip semiconductor of the uranium case can only be connected to one light-emitting diode semiconductor component, so that one light-emitting diode semiconductor component has a conductive layer insulating layer. Conductive layer ((3103⁄4 valleys cover the substrate of the Japanese semiconductor, and multiple light-emitting diode semiconductor components have a plurality of conductive layer insulating layer conductive layer (CIC) capacitor flip-chip semiconductor substrate, so not only costly, but also The light-emitting diode semiconductor element Μ 々 々; 夕 攸 攸 之 之 之 之 之 之 之 之 之 之 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕 夕A practical method and apparatus for connecting a plurality of wafers and a chip-backed substrate having anti-static properties. SUMMARY OF THE INVENTION PROBLEM TO BE SOLVED BY THE INVENTION A substrate of a (CIC) capacitor flip-chip semiconductor, a conductor element It has the following disadvantages: a conventional conductive layer insulating layer conductive layer, a monthly b-connected one light-emitting diode half, if multiple light-emitting diodes are to be used ^ slave + conductor The conductive layer insulation layer (CIC) capacitor is required to be used on the substrate of the Japanese semiconductor, and the plurality of 6 200810162 LED semiconductor components are connected, and the cost is very high. 2. If multiple light-emitting diodes are to be used There are a plurality of bulk semiconductor components: a conductive layer insulating layer conductive layer (CIC) capacitor flip chip semiconductor substrate, a plurality of hair: the photodiode semiconductor element is connected, the volume will be larger. 3. The existing conductive layer insulating layer is conductive The layer (CIC) capacitor flip-chip structure, the insulating layer is completed by a general dielectric coefficient material, and the money release function is limited; the technical feature of the invention solves the problem is to provide a flip chip capable of connecting a plurality of wafers and having anti-static damage The manufacturing method of the substrate includes the following steps: Step 1: fabricating a plurality of light emitting diode semiconductor components, and forming a first electrode and a second electrode for each of the light emitting diode semiconductor components; Layer insulating layer conductive layer (C 1C) capacitor flip-chip substrate, the conductive layer insulating layer conductive layer (CIC) capacitor flip-chip substrate is a semiconductor layer, an insulating layer, a semiconductor substrate combination The semiconductor substrate is formed by a high heat dissipation material λ; the insulating layer is formed of a dielectric material; if the insulating layer is made of a high dielectric constant material, the capacitance is increased to facilitate the discharge of static electricity' or The over-voltage material is usually a capacitor, and the short-circuit resistance can also improve the bleed function when the voltage is over-voltage. Step 3: pattern the semiconductor layer of the conductive layer of the conductive layer (CIC) capacitor flip-chip to form a reticle, and Forming the first electrode and the second electrode of the array; Step 4: respectively, the first electrode and the second electrode of each of the light-emitting diode semiconductor elements are respectively laminated with the conductive layer of the conductive layer (CIC) Each of the first electrode and the second electrode is electrically connected. 200810162 By the method, the present invention further provides a device capable of connecting a plurality of wafers and a flip-chip substrate having anti-static damage, which comprises: - at least one light-emitting diode The body semiconductor device, each of the light-emitting diode semiconductors: the germanium member is sequentially provided with a crystal core layer, a conductive buffer layer, an active layer, an upper binding layer, a binding layer and a contact layer on a substrate. a first electrode and a second electrode; a conductive layer insulating layer conductive layer (CIC) capacitor flip chip substrate, the conductive layer insulating layer conductive layer (C 1C) capacitor flip chip substrate, is a semiconductor layer, an insulating layer, a half V The conductive substrate is formed by combining the body substrate, the conductive layer of the conductive layer (CIC) on the flip chip substrate, and the first electrode and the second electrode are formed; and the conductive layer is conductive layer ( Each of the first electrode and the second electrode of the CIC) capacitor flip-chip substrate can be electrically connected to the first electrode and the second electrode of each of the light-emitting diode semiconductor elements by solder balls. In addition to the conductive layer of the conductive layer insulating layer (6) c), the capacitor flip-chip substrate protects the light-emitting diode material component from electrostatic discharge damage, and can also be used in a conductive layer insulating layer conductive layer (CIC) capacitor flip-chip substrate. A plurality of light emitting diode semiconductor elements can be connected to form an array structure. In view of the efficacy of the prior art, a method for manufacturing a substrate capable of connecting a plurality of wafers and having antistatic damage and a device thereof are provided, and the present invention can protect the light emitting diode semiconductor device from electrostatic discharge damage due to its Adding a conductive layer of a conductive layer insulating layer (a step of patterning the body layer of the tantalum capacitor flip-chip layer] - this conductive layer of the conductive layer: a capacitor flip chip substrate can be connected to a plurality of light-emitting diode semiconductor device arrays The structure 'not only saves cost' but also reduces the volume of a plurality of light-emitting diode semiconductors 8 200810162 after being connected in series. The technology, means and functions of the invention are related to the use of the invention: ^ 口 砰 祝 祝 , , , , , , , , , , , , 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 相信 田 田 田 田 田 田 田 田 田 田A method for manufacturing a wafer and a flip chip substrate, and a device therefor. Please refer to the first figure to the 箆 ❿ 王 王 乐 乐 乐 四 四 ' ' ' ' ' ' ' ' ' ( ( ( ( ( ( ( ( ( ( ( ( ( ( ( Each body of a light-emitting diode semiconductor device (such as a nucleation layer (丄丄), a conductive 2), an active layer (1 3), a An upper tie layer (1 3丄3 2), a contact layer (14), and a first electrode (15) pole (16); wherein the first electrode (15) can be plated with silver as an anti- The illuminating effect of the illuminating diode semiconductor component is better; Step 1 (S 2 ): fabricating a conductive layer insulating layer to guide the flip chip substrate, the conductive layer insulating layer conductive layer (c 丨 c) electricity $ (2 0 ) (As shown in the third figure), the semiconductor layer and the insulating substrate are combined; wherein the semiconductor substrate is formed by a high heat dissipating material, and the (A 1N ) can achieve the advantages of high heat dissipation and low cost; wherein the insulating layer It is formed by dielectric materials, high dielectric materials, and collapsed materials, including bismuth bismuth (Si〇2), nitriding, and the above-mentioned items. Anti-static damage • Conductor components, ) In a base buffer layer (1 7 tie layer (work and ~ second electrode layer, by 1 layer (CIC) electricity & flip-chip substrate layer, semiconductor including nitriding With overvoltage collapse (Si3N4), 9 200810162 _ »ί oxidized (Hf〇2), cerium oxide (Zr〇2), and rare earth oxides, etc. Step 3 (S 3 ): Conductive layer The conductive layer of the insulating layer (the semiconductor layer of the c-capacitor-clad substrate (20) is patterned to form a photomask (2 4 ): (as shown in the fourth figure), and an array of first electrodes is formed ( 2 1) and the second electrode (22) (as shown in the third figure); Step 4 (S 4 ): the first electrode (15) and the second electrode (1 6) of each of the LED components And electrically connecting each of the first electrode (2 1 ) and the second electrode (22) of the conductive layer insulating layer (CIC) capacitor flip-chip substrate (20) via the solder ball (23) . Wherein, please refer to the fourth figure, which is a schematic diagram of the semiconductor layer patterning of the conductive layer insulating layer (CIC) capacitor flip-chip substrate (20) of the present invention, due to the light emitted by the light-emitting diode The illumination of the light may be uneven. For example, the street lamp of the light-emitting diode does not illuminate the side. Therefore, the conductive layer of the conductive layer of the present invention (CIc) and the flip-chip substrate (20) are used in the semiconductor. When the layer is patterned to produce the mask (2 4 ), the mask 肇 (2 4 ) layout can be designed to make several LEDs and conductive layer insulating layer conductive layer (C 1C) capacitor flip-chip substrate (2 〇) When connected, the reticle (24) layout is used to achieve the desired light field, so that the light field distribution can also be achieved by different patterned crystallization on the sub-substrate via the dies. In addition, the conductive layer insulating layer (C 1C) capacitor flip-chip substrate (20 ) of the present invention can further form a plurality of reflective recesses, and each recess can be placed for at least one light emitting diode, so that when the light is emitted When the polar body emits light, the concentrating effect can be achieved by the concave hole, and when the light is emitted upward, the distance irradiated can be farther and brighter. 10 200810162 With the above design, the present invention, under normal operation, when a forward bias is applied between V+ and V-, a current flows from the first electrode (15) through the semiconductor portion: The generated light (3 〇) is emitted through the substrate (1 〇); when: abnormal voltage or static electricity is generated, the discharge path is transferred to the conductive layer insulating layer conductive layer (6) tantalum capacitor flip-chip substrate (2 Q), However, the semiconductor portion is not passed. At this time, the protection mechanism formed by the present invention is 纟2, and the protection is started. The best example can withstand the human body mode withstand voltage to 8 κν. φ In addition to protecting the light-emitting diode semiconductor component from electrostatic discharge damage, the present invention incorporates a conductive layer (cic) capacitor-clad substrate (20) "the semiconductor layer patterning step, so a Conductive layer insulating layer conductive layer (CIC) capacitor flip-chip substrate (2 〇) can be connected to a plurality of light-emitting diode semiconductor elements to form an array structure, and a conductive layer insulating layer conductive layer (CIC) capacitor flip-chip semiconductor substrate is improved. The disadvantage of only one light-emitting diode semiconductor component can be connected; this not only saves cost, but also reduces the volume of a plurality of light-emitting diode semiconductor components after being connected in series. Φ The plurality of light-emitting diode semiconductor components of the present invention are high in heat generation, and the conductive layer insulating layer (CIC) capacitor flip-chip substrate (20) must have good heat dissipation to be able to have multiple particles. The light emitting diode semiconductor component is coupled to a conductive layer insulating layer conductive layer (CIC) capacitor flip chip substrate (20); therefore, the conductive layer insulating layer conductive layer (CIC) capacitor of the present invention covers the substrate (20) The semiconductor substrate can be Si Xi (Si) or Niobium (A1N), which can make the LED semiconductor element have a high heat dissipation effect, and is inexpensive, and can reduce the cost. According to the above method, the present invention further provides a device for connecting a plurality of wafers 11 200810162 and a flip-chip substrate having anti-static damage. Referring to the second to third figures, the method includes: at least one light-emitting diode The body semiconductor device, each of the light emitting diode semiconductor devices (as shown in the second figure) is provided with a nucleation layer (1 1), a conductive buffer layer (1 2), and an active layer on a substrate (1 〇). a layer (1 3), an upper binding layer (1 3 1 ) - a lower binding layer (1 3 2), a contact layer (14), a first electrode (15), and a second electrode (16) The first electrode (15) can be plated with silver as a reflective layer, so that the light emitting effect of the light emitting diode semiconductor component is better; a conductive layer insulating layer conductive layer (CIC) capacitor flip chip substrate, the conductive layer Insulating layer conductive layer (CIC) capacitor flip-chip substrate (2 〇) (as shown in the third figure), which is a combination of a semiconductor layer, an insulating layer and a semiconductor substrate, and the conductive layer insulating layer conductive layer (CIC) capacitor flip chip The semiconductor layer on the substrate (2 〇) is patterned to form a photomask (24) (as shown in the fourth figure), and Forming an array of a first electrode (2 1 ) and a second electrode (2 2 ) (as shown in the third figure); and the conductive layer insulating layer conductive layer (CIC) capacitor flip chip substrate (2 〇) - Electrode (2 1 ) A second electrode (2 2 ) can be electrically connected to the first electrode (15) and the second electrode (16) of each of the LED components by solder balls (23) The invention can achieve the advantages of high heat dissipation and low price, wherein the insulating layer on the conductive layer of the conductive layer is a dielectric material, and the semiconductor substrate on the conductive layer of the conductive layer is high dispersion (A1N)

電層(CIC)電容覆晶基板(2 熱材質所形成,包括為氮化鋁 (CIC)電容覆晶基板(2 介電材料,與過電壓崩潰 12 200810162 材料所形成r 氧化铪(Hf〇2) 包括為二氧化矽(Si〇2)、氮化矽(SiD,二 '二氧化锆(Zr〇2)、及稀土氧化物等等; 其中該導電層絕緣層導電層(C 1C)電容覆晶基板(2 0 )上可進步形成數反光凹洞,每一凹洞可供至少一顆 I光-極體放置,^此當發光二極體發光時,可藉由凹洞 達〗XK光效果並讓光線朝上發射時,所照射之距離可以 更遠且更亮。 , 唯以上所述者,僅為本發明之較佳實施例,當不能以 制本毛月的範圍。即大凡依本發明申請專利範圍所作 ,均等變化及修飾,仍將不失本發明之要義所纟,亦不脫 離本發明之精神和範圍,故都應視為本發明的進一步實施 狀況。 、 【圖式簡單說明】 第一圖係本發明之流程示意圖。 第二圖係本發明發光二極體半導體元件之示意圖。 鲁第_圖係本發明發光二極體半導體元件與導電層絕緣層導 笔層(CIC)電容覆晶基板之結合示意圖。 第四圖係本發明半導體層圖形化製作之光罩佈局示意圖。 【主要元件符號說明】 (s 1 )步驟一 (S 2 )步驟二 (S 3 )步驟三 (s 4 )步驟四 (1 〇 )基板 13 200810162 (11)晶核層 (1 2 )導電緩衝層 : (1 3 )主動層 : (131)上束缚層 (1 3 2 )下束缚層 (1 4 )接觸層 (15)第一電極 (1 6 )第二電極 • ( 2 0 )導電層絕緣層導電層(CIC)電容覆晶基板 (21)第一電極 (2 2 )第二電極 (2 3 )焊料球 (2 4 )光罩 (3 0 )光 14Electrical layer (CIC) capacitor flip-chip substrate (2 thermal material formed, including aluminum nitride (CIC) capacitor flip-chip substrate (2 dielectric material, with overvoltage collapse 12 200810162 material formed r yttrium oxide (Hf 〇 2 Included as cerium oxide (Si 〇 2), cerium nitride (SiD, bis-zirconia (Zr 〇 2), and rare earth oxides, etc.; wherein the conductive layer insulating layer conductive layer (C 1C) capacitor covering On the crystal substrate (20), several reflective concave holes can be formed, and each concave hole can be placed for at least one I light-polar body. When the light-emitting diode emits light, the concave hole can reach XK light. When the effect is made and the light is emitted upwards, the distance irradiated can be farther and brighter. Only the above description is only a preferred embodiment of the present invention, and the range of the gross month cannot be used. The invention is not limited to the spirit and scope of the present invention, and should be considered as a further implementation of the present invention. Description of the Invention The first diagram is a schematic diagram of the flow of the present invention. Schematic diagram of a polar semiconductor device. Ludi-picture is a schematic diagram of the combination of a light-emitting diode semiconductor device and a conductive layer insulating layer conductive layer (CIC) capacitor flip-chip substrate. The fourth figure is a graphic design of the semiconductor layer of the present invention. Schematic diagram of reticle layout. [Main component symbol description] (s 1) Step 1 (S 2 ) Step 2 (S 3 ) Step 3 (s 4 ) Step 4 (1 〇) Substrate 13 200810162 (11) Nucleation layer ( 1 2) Conductive buffer layer: (1 3 ) Active layer: (131) Upper tie layer (1 3 2 ) Lower tie layer (1 4 ) Contact layer (15) First electrode (1 6 ) Second electrode • ( 2 0) Conductive layer insulating layer conductive layer (CIC) capacitor flip-chip substrate (21) first electrode (2 2 ) second electrode (2 3 ) solder ball (2 4 ) reticle (30) light 14

Claims (1)

200810162 十、申請專利範圍, 種可連接多顆晶片及具有防靜電破壞之霜晶美 板的製造方法,其步驟包括: 步驟.係製作多顆發光二極體半導體元件,並使每 -顆發光二極體半導體元件形成有一第一電極&一第二電 步驟一 ·係製作導電層絕緣層導電層(C 1C)電容覆晶基 春板’ ^導電層絕緣層I電層(CIC)電容覆晶基板為半導體 f系巴緣層、半導體基板組合而成;該半導體基板為高散 熱材質所形成; …步驟二:係將導電層絕緣層導電層(C 1C)電容覆晶基板 ;體層圖形化以製作光罩,並形成有數組之第一電極 第一電極及 電容覆晶基200810162 X. Patent application scope, a manufacturing method for connecting a plurality of wafers and a frosted crystal board having antistatic damage, the steps comprising the steps of: manufacturing a plurality of light emitting diode semiconductor components and making each of the two light emitting diodes The polar semiconductor component is formed with a first electrode & a second electrical step - a conductive layer insulating layer conductive layer (C 1C) capacitor flip-chip spring plate ^ ^ conductive layer insulating layer I electrical layer (CIC) capacitor cover The crystal substrate is formed by combining a semiconductor f-bar layer and a semiconductor substrate; the semiconductor substrate is formed by a high heat dissipation material; and the second step is: conducting a conductive layer insulating layer conductive layer (C 1C) capacitor flip-chip substrate; To fabricate a photomask, and form an array of first electrode first electrode and capacitor flip chip ^步私四·將各顆發光二極體半導體元件之 弟二電極,分別與該導電層絕緣層導電層(CIC) 板的各第一電極及第二電極電性連接。 2:如申請專利範圍第i項所述之可連接多顆晶片及 杏々知電破壞之覆晶基板的製造方法,其中,每一顆發 九-極體半導體元件係在—基板上' 導雷短# 曰日核層、一 ¥電緩衝層、主動層、一上束缚層一 一筮 9 r术、、寻層、一接觸層、 電極及一第二電極。 .具有防靜 極體半導 如申請專利範圍第1項所述之可連接多顆晶片及 包破壞之覆晶基板的製造方法, . /、甲,该發光二 體元件之第一電極上可鍍銀作為反射層。 15 200810162 4 ·如申請專利範圍第1項所述之可連接多顆 具有防靜電破壞之覆晶基板的製造方法,其中,該 '基板包括為氮化鋁(A 1 N )所形成。 ’ 5 ·如申請專利範圍第1項所述之可連接多顆 具有防靜電破壞之覆晶基板的製造方法,其中,該 為介電材料所形成。 6 ·如申請專利範圍第1項所述之可連接多賴 φ具有防靜電破壞之覆晶基板的製造方法,其中,讀 為高介電材料所形成。 7 ·如申請專利範圍第1項所述之可連接多 具有防靜電破壞之覆晶基板的製造方法,其中, 為過電壓崩潰材料所形成。 8如申請專利範圍第1項所述之可連接多 /、有防靜书破壞之覆晶基板的製造方法,其中, g括為一氧化铪(Ηf 〇2)所形成。 如申明專利範圍第1項所述之可連接多 /、有防靜電破壞之覆晶基板的製造方法,其中, i括為氧化鍅(Zr〇2 )所形成。 |〜祀固弟1項所述之可 及具有防靜電破壞之覆晶基板的製造方法, 層包括為二氧化石夕(Si 〇2)所形成。 ".如’請專利範圍第】項所述之可 及/、有防靜電破壞之覆晶基板的製造 層包括為氦化矽(Si3N4)所形成。 ’: 晶片及 半導體 晶片及 絕緣層 晶片及 絕緣層 晶片及 絕緣層 晶片及 絕緣層 晶片及 絕緣層 顆晶片 該絕緣 黃晶片 I絕緣 16 200810162 丄匕·如申請專利範圍第1項所述之可連接多顆晶片 及具有防靜電破壞之覆晶基板的製造方法,其中,該絕緣 層包括為稀土氧化物所形成。 ' : 1 3 ·如申請專利範圍第1項所述之可連接多顆晶片 及具有防靜電破壞之覆晶基板的製造方法,其中,該導電 層絶緣層導電層(CI〇電容覆晶基板於製作光罩時,先罩佈 局可經過設計,使數顆發光二極體與導電層絕緣層導電層 _ )電各覆日日基板連結時,藉由光罩佈局去改善光場不约 勻之現象。 ~ 1 4 ·如申請專利範圍第1項所述之可連接多顆晶片 及具有防靜電破壞之覆晶基板的製造方法,其中,該導電 層絕緣層導電層(CIC)電容覆晶基板上可進一步形成數反 光凹洞,每一凹洞可供至少一顆發光二極體放置,藉由凹 洞達到聚光效果。 ^ 1 5 · —種可連接多顆晶片及具有防靜電破壞之 1文日日 _基板的裝置,其係包括: 至少一發光二極體半導體元件,各發光二極體半導體 元件包括有一第一電極及一第二電極; 一導電層絕緣層導電層(Cic)電容覆晶基板,該導電層 、、-ε、、象層導電層(CIC )電容覆晶基板為半導體層、絕緣層、半 導體基板組合而成,該導電層絕緣層導電層(CIC)電容覆晶 基板上之半導體層圖形化形成有光罩,並形成有數組之第 一電極及第二電極,且該導電層絕緣層導電層(CIC)電容覆 晶基板的各帛一電極及第。電極彳分別#由焊#球與各顆 17 200810162 發光二極體半導If开/生斤 千V體疋件之第一電極及第二電極電性連結。 1 6 .如申請專利範圍第1 5項所述之可連接:。 片及具有防靜電破壞之覆晶基板的裝置,丨 極體半導體元件係在1板上依序設有-晶核層、 緩衝層、主動&、-上束缚層一下束缚層、—接觸Z電 第-電極及-第二電極。 拱觸層、〜 1 7 .如申請專利範圍第i 5項所述之可連 曰 片及具有防靜電破壞之覆晶基板的 日曰 極體半導體元件之第〜電極上可…^ 發光二 包極上T鍍銀作為反射層。 1 8 .如申請專利範圍第丄5項所述之可: 片及具有防靜電破壞之覆晶基板的裝置 …顆晶 絕緣層導電層(CIC)電容覆晶基板上之半導體其:亥導▲電層 熱材質所形成。 、-.土板為向散 1 9 .如申請專利範圍第i 5項所述之可 片及具有防靜電破壞之覆晶基板的裝置,其中,^曾、晶 絕緣層導電層(CIC)電容覆晶基板上 X導電層 化銘(A1N)所形成。 ^體基板為為氣 2 〇 .如申請專利範圍第i 5項所述 片及具有防靜電破壞之覆晶基板的裝 夕晶 異中,該逡Φ B 絕緣層導電層(CIC)電容覆晶基板上 寺苯層 所形成。 、'巴緣層為介電材料 21 .如中請專利範圍第15項所述之可連接多顆晶 片及具有防靜電破壞之覆晶基板的裝置, 曰曰 ’、中’該導雷局 絕緣層導電層(C 1C)電容覆晶基板上之奶祕 曰 、"巴緣層為高介電材 18 200810162 料所形成。 2 2 ·如申請專利範圍第1 5項所述之可連接多顆晶 片及具有防靜電破壞之覆晶基板的裝置,其中,該導電層 絕緣層導電層(CIC)電容覆晶基板上之絕緣層為過電 潰材料所形成。 m 匕d ·如申請專利範圍第i 5項所述之可連接多顆晶 及〃有防靜電破壞之覆晶基板的裝置,其中,該導電層 鲁絕緣層導電層(CIC)電容覆晶基板上之絕緣層包括為二 化石夕(S i 〇 2)所形成。 2 4 ·如申請專利範圍第i 5項所述之可連接多顆晶 /、有防靜電破壞之覆晶基板的裝置,其中,該導電層 絕緣層導電層(CIC)電容覆晶基板上之絕緣層包括為曰 化鈴(Hf〇2)所形成。 2 5 ·如申請專利範圍第i 5項所述之可連接多顆晶 2及/、有防靜電破壞之覆晶基板的裝置,其中,該導電層 春緣層導電層(C1C)電容覆晶基板上之絕緣層包括為二氧 化錯(Zr〇2)所形成。 如申明專利範圍第1 5項所述之可連接多顆晶 π -有防靜电破壞之覆晶基板的裝置,纟中,該導電層 絕緣層導電;& 9 )電各覆晶基板上之絕緣層包括為稀土 軋化物所形成。 如申明專利範圍第1 5項所述之可連接多顆晶 /、有防靜電破壞之 甘士 既 π 、復日日基板的裝置,其中,該導電層 、、、巴緣層導電厣^ Γ τ Γ、 ^ 9 ”各覆晶基板上可進一步形成數反光 19 200810162 凹洞,每一凹洞可供至少一顆發光二極體放置。 : Η 、圖式 ; 如次頁Step 4: The second electrode of each of the light-emitting diode semiconductor elements is electrically connected to each of the first electrode and the second electrode of the conductive layer of the conductive layer (CIC). 2: A method for manufacturing a flip-chip substrate capable of connecting a plurality of wafers and apricots and electric breaks as described in claim i, wherein each of the nine-polar semiconductor components is on the substrate Lei short # 曰 核 nuclear layer, a power buffer layer, active layer, an upper binding layer one by one 9 r surgery, stratification, a contact layer, an electrode and a second electrode. A method for manufacturing a flip-chip substrate capable of connecting a plurality of wafers and a package destruction as described in claim 1 of the patent application scope, wherein the first electrode of the light-emitting two-body element is Silver plating is used as a reflective layer. 15 200810162 4 - A method of manufacturing a plurality of flip-chip substrates having antistatic breakdown as described in claim 1, wherein the 'substrate comprises aluminum nitride (A 1 N ). The manufacturing method of a plurality of flip-chip substrates having antistatic breakdown as described in claim 1, wherein the dielectric material is formed. 6. A method of manufacturing a flip-chip substrate having an antistatic breakdown as described in claim 1, wherein the method is a high dielectric material. 7. A method of manufacturing a flip chip substrate having an antistatic breakdown as described in claim 1, wherein the overvoltage collapse material is formed. [8] The method for producing a flip-chip substrate which can be connected to a multi-layer/destroyed book according to the first aspect of the patent application, wherein g is formed by cerium oxide (Ηf 〇 2). A method for producing a flip-chip substrate which can be connected to a plurality of / and has an antistatic breakdown as described in the first aspect of the invention, wherein i is formed by yttrium oxide (Zr〇2). The method for producing a flip-chip substrate having antistatic breakdown as described in Item 1 of the sturdy body, wherein the layer is formed of SiO 2 (Si 〇 2). ". The manufacturing layer of the flip-chip substrate with/or antistatic damage as described in the 'Required Patent Range】 includes the formation of antimony telluride (Si3N4). ': wafer and semiconductor wafer and insulating layer wafer and insulating layer wafer and insulating layer wafer and insulating layer wafer and insulating layer wafer. Insulating yellow wafer I insulating 16 200810162 可 · Connectable as described in claim 1 A method of manufacturing a plurality of wafers and a flip chip substrate having antistatic breakdown, wherein the insulating layer is formed of a rare earth oxide. ' : 1 3 · A manufacturing method for connecting a plurality of wafers and a flip-chip substrate having antistatic breakdown as described in claim 1, wherein the conductive layer insulating layer conductive layer (CI tantalum capacitor flip chip substrate) When the reticle is made, the layout of the hood can be designed so that the light-emitting diodes and the conductive layer of the conductive layer are electrically connected to each other. phenomenon. ~ 1 4 · The method for manufacturing a flip-chip substrate capable of connecting a plurality of wafers and having anti-static damage as described in claim 1, wherein the conductive layer insulating layer (CIC) capacitor flip-chip substrate is Further, a plurality of reflective dimples are formed, each of the cavities being disposed for at least one of the light emitting diodes, and the concavity effect is achieved by the concave holes. ^ 1 5 · A device capable of connecting a plurality of wafers and a substrate having an antistatic breakdown, comprising: at least one light emitting diode semiconductor component, each of the light emitting diode semiconductor components including a first Electrode and a second electrode; a conductive layer insulating layer conductive layer (Cic) capacitor flip-chip substrate, the conductive layer, - ε, and a layer conductive layer (CIC) capacitor flip-chip substrate is a semiconductor layer, an insulating layer, a semiconductor Forming a substrate, the conductive layer conductive layer (CIC) capacitor on the flip-chip substrate is patterned to form a photomask, and an array of first electrodes and second electrodes are formed, and the conductive layer insulating layer is electrically conductive Each layer of the layer (CIC) capacitor flip-chip substrate and the first. Electrode 彳################################################################################## 1 6 . Connectable as described in item 15 of the patent application scope: A device for a chip and a flip-chip substrate having an antistatic breakdown, the gate semiconductor device is sequentially provided on the first plate - a nucleation layer, a buffer layer, an active &, an upper binding layer, a binding layer, and a contact Z Electrode-electrode and -second electrode. The arch contact layer, 〜1 7 . The galvanic sheet of the ytterbium sheet and the flip-chip substrate with antistatic breakdown as described in the scope of claim 5 can be ... On the pole, T is plated with silver as a reflective layer. 1 8 . As described in item 5 of the patent application, there are: a device for a chip and a flip chip substrate with antistatic breakdown... a crystalline insulating layer (CIC) capacitor on a flip chip substrate: The electric layer is formed by a thermal material. - The earth plate is a dispersion of the film according to the scope of the patent application, and the device having the anti-static damage of the flip chip substrate, wherein the conductive layer (CIC) capacitor Formed on the flip-chip substrate by X conductive layering (A1N). The bulk substrate is gas 2 〇. The 逡Φ B insulating layer conductive layer (CIC) capacitor flip chip is as described in the patent document scope i i 5 and the flip-chip substrate with antistatic damage. The benzene layer is formed on the substrate. The 'bar edge layer is a dielectric material. 21. The apparatus for connecting a plurality of wafers and a flip-chip substrate having anti-static damage as described in claim 15 of the patent scope, 曰曰', the middle' The layer of conductive layer (C 1C) capacitor on the flip-chip substrate is made of milk, and the edge layer is formed of high dielectric material 18 200810162. 2 2 · A device capable of connecting a plurality of wafers and a flip-chip substrate having antistatic breakdown as described in claim 15 wherein the conductive layer insulating layer (CIC) is electrically insulated on the flip chip substrate The layer is formed by over-crushing the material. m 匕d · A device capable of connecting a plurality of crystals and a flip-chip substrate having an antistatic breakdown as described in the scope of claim 5, wherein the conductive layer of a conductive insulating layer (CIC) capacitor flip-chip substrate The insulating layer on the upper layer is formed by the second fossil (S i 〇 2). 2 4 · A device capable of connecting a plurality of crystal/antistatically damaged flip-chip substrates as described in the scope of claim 5, wherein the conductive layer insulating layer (CIC) capacitor is on the flip chip substrate The insulating layer is formed of a halogenated bell (Hf〇2). 2 5 · A device capable of connecting a plurality of crystal 2 and/or an antistatically damaged flip-chip substrate as described in claim i. 5, wherein the conductive layer spring layer conductive layer (C1C) capacitor flip chip The insulating layer on the substrate is formed of dioxins (Zr〇2). For example, in the device of claim 15, the device capable of connecting a plurality of crystal π-anti-statically damaged flip-chip substrates, wherein the conductive layer insulating layer is electrically conductive; & 9) on the respective flip-chip substrates The insulating layer is formed of a rare earth rolled product. The device of claim 1, wherein the conductive layer, the rim layer is electrically conductive, and the device is capable of connecting a plurality of crystals/antistatically destroyed sinter and slabs. τ Γ, ^ 9 ” can further form a number of reflective 19 200810162 recesses on each of the flip-chip substrates, each recess can be placed for at least one light-emitting diode. : Η , pattern; 2020
TW96134578A 2007-09-14 2007-09-14 Method of fabricating flip chip substrate connecting with multi chips and having anti electrostatic destruction property and the device thereof TW200810162A (en)

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