KR101239857B1 - Semiconductor light emitting device and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a light emitting device and a method of manufacturing the same. The semiconductor light emitting device according to the present invention includes a substrate, a first semiconductor layer formed on the substrate, an active layer formed on the first semiconductor layer, a second semiconductor layer formed on the active layer, and a first semiconductor layer formed on the first semiconductor layer. And an insulating layer formed on at least one of an electrode, a second electrode formed on the second semiconductor layer, a part of the second semiconductor layer, and a part of the second electrode, and a metal layer formed on the insulating layer, wherein the insulating layer is A capacitor region is formed by surrounding at least one of a portion of the second semiconductor layer and a portion of the second electrode with a metal layer, and at least one of the second electrode, the insulating layer, and the metal layer is a mirror.

Semiconductor, Light Emitting, Capacitor, Reflective Film, Mirror

Description

Semiconductor light emitting device and method for manufacturing the same

1A-1B are cross-sectional views and equivalent circuit diagrams schematically showing the configuration of a flip chip LED in which a zener diode is formed in a submount to prevent ESD damage in the related art.

2A and 2B are cross-sectional views schematically showing the configuration of a semiconductor light emitting device according to a first embodiment of the present invention and an equivalent circuit thereof.

3A to 3F are views illustrating a manufacturing process of a semiconductor light emitting device according to a first embodiment of the present invention.

4 is a cross-sectional view schematically showing the configuration of a semiconductor light emitting device according to a second embodiment of the present invention.

5 is a cross-sectional view schematically illustrating flip chip bonding of a semiconductor light emitting device according to a second exemplary embodiment of the present invention.

6A is a schematic cross-sectional view of a portion of a semiconductor light emitting device according to the third embodiment;

6B is a top view schematically illustrating a portion of the semiconductor light emitting device corresponding to FIG. 6A.

7 is a schematic cross-sectional view of a portion of a semiconductor light emitting device according to the fourth embodiment of the present invention.

The present invention relates to a light emitting device using a semiconductor film formed on a substrate and a method of manufacturing the same.

Semiconductor light emitting devices, for example, light emitting diodes (LEDs) have a long life and low power consumption, and thus are widely used in the electric and electronic fields as well as in the advertising field. Attempts have recently been made to use LEDs as, for example, backlight units of liquid crystal displays. In addition, LED is expected to be widely used in daily life as indoor lighting in the future.

Semiconductor light emitting devices such as LEDs that are showing explosive growth are evolving to smaller and lower power according to the demand of the application field. However, in response to this evolution process, input capacitance is inevitably reduced at the terminals for input and output to the outside, which causes semiconductor light emitting devices such as LEDs to have a sudden surge voltage or electrostatic discharge (ESD) ( Hereinafter, the vulnerability is exposed to external surge voltage, ESD, and the like applied to a semiconductor light emitting device. That is, semiconductor light emitting devices, such as LEDs, can be damaged by breaking internal junctions due to unexpected ESDs that exceed the input capacitance.

In order to improve the reliability of semiconductor light emitting devices while overcoming the weaknesses of ESD, several methods have been proposed. One of them is a method of protecting a semiconductor light emitting device by connecting a zener diode in parallel and bypassing unexpected ESD to the zener diode in a packaging process for the semiconductor light emitting device. However, the above method of packaging Zener diodes in parallel reduces the light extraction efficiency by 10% to 15% as semiconductor light emitting devices such as LEDs are spaced apart from the lamp center, and added Zener diodes and additional wire bonding. Due to the need for such, there is a problem that the cost and process time increases. In order to overcome the problem of a method of packaging Zener diodes in parallel, there is a method of protecting a semiconductor light emitting device from ESD by forming a Zener diode in a sub-mount as a flip chip semiconductor light emitting device.

FIG. 1A is a cross-sectional view schematically showing a configuration of a flip chip LED in which a Zener diode is formed in a submount to prevent ESD damage, and an equivalent circuit diagram thereof is shown in FIG. 1B. 1A and 1B, the semiconductor light emitting device includes an LED 125 and a Zener diode 155 formed in the sub-mount 151 while being connected in parallel with the LED 125. The LED 125 is an n-type semiconductor layer (eg, n-GaN) 103, an active layer 105, and a p-type semiconductor layer (eg, p-GaN) sequentially stacked on the sapphire substrate 101. 107, an n-type electrode 111 stacked on the n-type semiconductor layer 103, and a p-type electrode 109 stacked on the p-type semiconductor layer 107. The zener diode 155 may be formed by implanting, for example, p-type ions into a portion of the submount 151 such as an n-type silicon substrate to form the p-type silicon region 153. The n-type electrode 111 of the LED 125 is connected to the p-type silicon region 153 through the first conductive bump 113 and the p-type electrode 109 is connected to the n-type electrode 111 via the second conductive bump 115. [ And is connected to the submount 151 such as a silicon substrate to be flip chip bonded. When an ESD voltage is applied through an input / output terminal (not shown) of the semiconductor light emitting device shown in FIG. 1A, most of the discharge current flows through a Zener diode 155 connected in parallel to the LED 125. This structure allows the LED 125 to be protected from unexpected application of ESD voltage.

In the case of the semiconductor light emitting device shown in FIG. 1A, an expensive ion implantation process is performed to fabricate a zener diode in the submount, or a diffusion process having difficulty in control is performed, so that the submount manufacturing process is complicated However, there is a problem that the cost is increased.

The present invention forms a capacitor region surrounded by a metal or a conductive semiconductor with an insulating layer, which is a dielectric, to prevent ESD damage without additionally using a conventional zener diode, and also emits semiconductor light to maximize light extraction efficiency with a mirror structure. It is an object to provide an element and a method of manufacturing the same.

Another object of the present invention is to provide a semiconductor light emitting device capable of securing a larger capacitor capacity and a method of manufacturing the same.

Still another object of the present invention is to provide a semiconductor light emitting device for forming a mirror structure capable of maximizing reflectance and a method of manufacturing the same.

Still another object of the present invention is to provide a semiconductor light emitting device and a method for manufacturing the same, which can improve current dispersion of a p-type electrode.

Still another object of the present invention is to provide a semiconductor light emitting device and a method of manufacturing the same, which can effectively release heat generated from a chip.

Still another object of the present invention is to provide a semiconductor light emitting device and a method of manufacturing the same, which are easy to bond when fabricating flip chips.

In order to achieve the above objects, according to an aspect of the present invention, a substrate, a first semiconductor layer formed on the substrate, an active layer formed on the first semiconductor layer, a second semiconductor layer formed on the active layer A first electrode formed on the exposed first semiconductor layer, a second electrode corresponding to the second semiconductor layer formed on the second semiconductor layer, a part of the second semiconductor layer, and a part of the second electrode An insulating layer formed on at least one of the metal layer and the metal layer formed on the insulating layer, wherein the metal layer is insulated by the second semiconductor layer, the second electrode and the active layer, and electrically connected to the first electrode, The insulating layer is surrounded by at least one of a part of the second semiconductor layer and a part of the second electrode and the metal layer to form a capacitor region, and at least one of the second electrode, the insulating layer, and the metal layer. I can provide a semiconductor light-emitting device formed a mirror (mirror) structure for reflecting the light generated from the active layer.

In the light emitting device connected in parallel with the capacitor, the capacitor is not current through the DC voltage, but only through the current when there is a voltage change. Therefore, when a normal forward voltage is applied to the light emitting device, light is generated from the active layer. When the reverse or forward overvoltage (ESD) is instantaneously applied to the light emitting device, the capacitor is energized to protect the light emitting device from the sudden overvoltage.

In a preferred embodiment, the refractive index of the second semiconductor layer and the insulating layer is relatively higher than the refractive index of the second electrode and the metal layer. The substrate is sapphire, the first semiconductor layer is n-type GaN, the second semiconductor layer is p-type GaN, the first electrode is an n-type electrode, the second electrode is a p-type electrode, the metal layer Is connected to the first electrode. In addition, the p-type electrode is characterized in that any one or a combination of two or more selected from the group containing Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. In addition, the insulating layer is characterized in that any one or a combination of two or more selected from the group containing SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN. In addition, the metal layer is characterized in that any one or a combination of two or more selected from the group containing Ag, Al, Au, Pt, Ti, Ni and W. In addition, the thickness (t) of the p-type electrode, the insulating layer and the metal layer corresponds to Equation 1, wherein Equation 1 is t = [λ / 4n] * k (where t is the thickness of the stack and λ is The wavelength of light generated in the light emitting device, n is the refractive index of the laminated material and k is a natural number). In addition, the semiconductor light emitting device may further include a p-type pad formed on a portion of the p-type electrode. In addition, the p-type pad may be configured in plurality. The semiconductor light emitting device may further include a sub-mount, an insulating film and an electrode plate formed on a portion of the sub-mount, a first bump to allow the n-type electrode to be connected to the electrode plate, and a p-type pad to be connected to the sub-mount. It may further include two bumps.

According to another aspect of the invention, preparing a substrate, forming a first semiconductor layer on the substrate, forming an active layer on the first semiconductor layer, forming a second semiconductor layer on the active layer Etching a portion of the first semiconductor layer, a portion of the active layer, or a portion of the second semiconductor layer, forming a first electrode on an exposed area of the first semiconductor layer, and forming the second semiconductor layer. Forming a second electrode on the second electrode, forming a p-pad on the second electrode, etching by at least one of the portion of the second semiconductor layer and the portion of the second electrode and the etching step It can provide a method for manufacturing a semiconductor light emitting device comprising forming an insulating layer on the surface and forming a metal layer on the insulating layer.

In an exemplary embodiment, the etching surface is an inclined etching surface, and the inclined etching surface is formed by a reflow method of a photoresist. In addition, the method of manufacturing a semiconductor light emitting device may further include performing a plasma treatment on the inclined etching surface before forming the insulating layer. In addition, the refractive index of the second semiconductor layer and the insulating layer is characterized in that it is relatively higher than the refractive index of the second electrode and the metal layer. The substrate is sapphire, the first semiconductor layer is n-type GaN, the second semiconductor layer is p-type GaN, the first electrode is an n-type electrode, the second electrode is a p-type electrode, the metal layer Is connected to the n-type electrode. In addition, the p-type electrode is characterized in that any one or a combination of two or more selected from the group containing Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. In addition, the insulating layer is characterized in that any one or a combination of two or more selected from the group containing SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN. In addition, the metal layer is characterized in that any one or a combination of two or more selected from the group containing Ag, Al, Au, Pt, Ti, Ni and W. In addition, the thickness (t) of the p-type electrode and the insulating layer corresponds to Equation 1, wherein Equation 1 is t = [λ / 4n] * k (where t is a thickness of a stack and λ is a light emitting device). Wavelength of the generated light, n is the refractive index of the laminated material and k is the natural number).

In addition, the method of manufacturing a semiconductor light emitting device may further include forming a p-type pad on a portion of the p-type electrode. In addition, the p-type pad is characterized in that a plurality. The method of manufacturing a semiconductor light emitting device may include sequentially forming an insulating film and an electrode plate on a portion of the sub-mount, connecting the n-type electrode to the electrode plate by a first bump, and connecting the p-type pad to the second bump. The method may further include flip chip bonding by connecting to the sub mount.

According to another aspect of the invention, the substrate, the first semiconductor layer formed on the substrate, the active layer formed on the first semiconductor layer, the second semiconductor layer formed on the active layer, on the first semiconductor layer At least one of a first electrode formed on the second electrode, a second electrode formed on the second semiconductor layer, a p-pad formed on the second electrode, a portion of the second semiconductor layer, and a portion of the second electrode And a first insulating layer formed on the first insulating layer, a first metal layer formed on the first insulating layer, a second insulating layer formed on the first metal layer, and a second metal layer formed on the second insulating layer. And the first insulating layer is surrounded by at least one of a part of the second semiconductor layer and a part of the second electrode and the first metal layer to form a first capacitor region, and the second insulating layer includes the first metal layer and Surrounded by the second metal layer A second capacitor region is formed, the first metal layer is electrically connected to the first electrode, the second metal layer is connected to the p-pad and electrically connected to the second electrode, and the second electrode and the first insulating layer are In some embodiments, at least one of the first metal layer, the second insulating layer, and the second metal layer may be a mirror.

In a preferred embodiment, at least one capacitor region is further formed on the second capacitor region. In addition, the refractive indexes of the second semiconductor layer, the first insulating layer, and the second insulating layer may be relatively higher than that of the second electrode, the first metal layer, and the second metal layer. The substrate is sapphire, the first semiconductor layer is n-type GaN, the second semiconductor layer is p-type GaN, the first electrode is an n-type electrode, the second electrode is a p-type electrode, The first metal layer is formed on the first insulating layer and is electrically connected to the first electrode, and the second metal layer is formed on the second insulating layer and is connected to the p pad and electrically connected to the second electrode. . In addition, the second electrode is characterized in that any one or a combination of two or more selected from the group containing Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. At least one of the first and second insulating layers may be any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN. It is characterized by one or a combination of two or more. At least one of the first metal layer and the second metal layer may be any one selected from the group consisting of Ag, Al, Au, Pt, Ti, Ni, W, and ITO, or a combination of two or more. In addition, the thickness t of the second electrode, the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer corresponds to Equation 1, where Equation 1 is t = [λ / 4n] * k, where t is the thickness of the lamination, λ is the wavelength of light generated in the light emitting element, n is the refractive index of the lamination material, and k is a natural number. In addition, the semiconductor light emitting device may further include a p-type pad formed on a portion of the p-type electrode. In addition, the p-type pad is characterized in that a plurality. The semiconductor light emitting device may further include a sub-mount, an insulating film and an electrode plate formed on a portion of the sub-mount, a first bump to allow the n-type electrode to be connected to the electrode plate, and a p-type pad to be connected to the sub-mount. It may further include two bumps.

Next, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

FIG. 2A is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device according to a first exemplary embodiment of the present invention, and an equivalent circuit thereof is illustrated in FIG. 2B. Hereinafter, the technical idea of the present invention is not limited to a specific semiconductor light emitting device. Hereinafter, for convenience of description, the semiconductor light emitting device is an LED, and in particular, an LED made of group III nitride.

2A and 2B, the semiconductor light emitting device may include a capacitor unit for bypassing an unexpected ESD voltage to an LED element unit 225 emitting light on a sapphire substrate 201 and simultaneously forming a mirror structure ( 257 are connected in parallel. The LED element unit 225 is a nitride series LED. In more detail, the n-type semiconductor layer 203, the active layer 205, and the p-type semiconductor layer 207 are sequentially stacked on the sapphire substrate 201. Thereafter, after an etching process is performed to form an inclined etching surface in a predetermined region, the n-type electrode 211 corresponding to the n-type semiconductor layer 203 and the p-type electrode corresponding to the p-type semiconductor layer 207 ( 209 and p-type pad 213 are formed. Next, as illustrated, the insulating layer 219 and the first metal layer 229 are sequentially stacked.

In FIG. 2A, since the dielectric insulating layer 219 is between a portion of the p-type semiconductor layer 207 and / or a portion of the p-type electrode 209 and the first metal layer 229, the region A in FIG. It functions as a capacitor and corresponds to the capacitor portion 257 on the equivalent circuit. Here, a part of the p-type semiconductor layer 207 and / or a part of the p-type electrode 209 correspond to the lower electrode of the capacitor, and a part of the first metal layer 229 corresponds to the upper electrode of the capacitor, and the insulating layer 219 corresponds to the dielectric.

Since the first metal layer 229 constituting the upper electrode of the capacitor is connected to the n-type electrode 211 of the LED, the LED is electrically connected in parallel with the capacitor, so that when a normal forward voltage is applied to the LED, no current flows through the capacitor. LED will operate normally and emit light. However, when an instantaneous overvoltage, such as reverse or forward ESD, is applied to the LED, current flows through the capacitor to block the current flowing into the LED, protecting the LED.

In the first embodiment, at least one of the p-type electrode 209, the insulating layer 219, and the first metal layer 229 is implemented as a mirror structure that reflects the light generated from the active layer 205, and more preferably, the p-type electrode The electrode 209, the insulating layer 219, and the first metal layer 229 may be implemented as a mirror having a complex structure having a difference in refractive index. For convenience of description, the p-type electrode 209, the insulating layer 219, and the first metal layer 229 are implemented as a composite mirror having a refractive index difference.

FIG. 2A illustrates an LED structure up to the step of flip chip bonding. The semiconductor light emitting device according to the first embodiment includes a capacitor having a dielectric structure surrounded by a metal and a metal (or semiconductor layer) and a mirror structure simultaneously. It is a flip chip LED that not only prevents ESD damage but also optimizes light extraction efficiency toward the sapphire substrate. A manufacturing process of the semiconductor light emitting device according to the first embodiment, which is schematically described with reference to FIG. 2, will be described in detail with reference to FIGS. 3A to 3F.

3A to 3F are views illustrating a manufacturing process of a semiconductor light emitting device according to a first embodiment of the present invention. First, as shown in FIG. 3A, a sapphire substrate 201 is prepared. After that, as shown in FIG. 3B, the n-type semiconductor layer 203, the active layer 205, and the p-type semiconductor layer 207 are sequentially stacked on the sapphire substrate 201. A process of epitaxially growing the n-type semiconductor layer 203, the active layer 205, and the p-type semiconductor layer 207 on the sapphire substrate 201 and the n-type semiconductor layer 203, the active layer 205, and the p-type Since the semiconductor layer 207 is well known, a detailed description thereof will be omitted.

Subsequently, as shown in FIG. 3C, an etching process is performed. A portion of the p-type semiconductor layer 207, a portion of the active layer 205, and a portion of the n-type semiconductor layer 203 are etched by an etching process to expose a portion of the n-type semiconductor layer 203. In this case, the side surface may be vertical, but it is more preferable that the side surface is an inclined surface instead of vertical. The etching process for forming the inclined surface will be described in more detail. First, an etch mask such as a photoresist is applied on the n-type semiconductor layer 203, the active layer 205, and the p-type semiconductor layer 207 sequentially stacked on the sapphire substrate 201. Thereafter, heat is applied to the applied photoresist to reflow. That is, the photoresist applied on the p-type semiconductor layer 207 is preferably reflowed by heating to a temperature between 100 degrees Celsius and 200 degrees Celsius, and the reflowed photoresist gradually increases in thickness from the center to the edge direction. It has a hemispherical inclined structure that becomes thinner. In the first embodiment of the present invention, the degree of inclination of the photoresist may be adjusted by changing conditions such as heating time and temperature. Subsequently, the etching process is performed by dry etching while the photoresist is reflowed. Since the reflowed photoresist has an inclined structure, a difference in the degree of etching due to the thickness difference of the reflowed photoresist occurs. Due to this difference in etching degree, a semiconductor layer (n-type semiconductor layer 203, active layer 205, and p-type semiconductor layer 207) having an inclined etching surface is formed. The etching process may be performed to have an inclined etch surface, thereby preventing generation of step coverage for the thin film to be subsequently deposited.

Subsequently, an insulating layer may be formed by exposing the plasma to the inclined etching surface. The plasma preferably corresponds to any one of N ₂ , N ₂ O, NH ₃ , He, Ne, and Ar. In addition, the plasma is preferably exposed to a small power of 1W to 100W. The plasma treatment process for forming the insulating layer according to the first embodiment is optional, but as shown in FIG. 3E, the insulating layer is stacked over the semiconductor layer including the inclined etching surface, and thus the thickness of the laminated insulating layer is increased. Since the thickness is thin and there is a possibility that pinholes or the like are generated in the insulating film, it is preferable that the plasma treatment process is performed to sufficiently secure the insulation.

Thereafter, as shown in FIG. 3D, the n-type electrode 211 is formed on the exposed region of the n-type semiconductor layer 203, and the p-type electrode 209 is formed on one side of the p-type semiconductor layer 207. The p-type pad 213 is formed on the p-type electrode 209. Heat treatment may be performed on the formed p-type electrode 209. As shown in FIG. 3D, the p-type electrode 209 may be formed to cover almost the entire region of the p-type semiconductor layer 207 or may be formed only in a predetermined region of the p-type semiconductor layer 207. The p-type electrode 209 according to the first embodiment may be any one selected from the group consisting of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu, and HfN, or a combination of two or more thereof. . Since the electrode forming process is well known, a detailed description thereof will be omitted.

Subsequently, as shown in FIG. 3E, a capacitor and a mirror structure are formed. As illustrated in FIG. 3D, the insulating layer 219 is formed on the etched semiconductor layer while the electrode is formed. The insulating layer 219 covers the p-type electrode 209 and the p-type semiconductor layer 207 and the inclined surface etched. The insulating layer 219 may be any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO, and AlN, or a combination of two or more thereof. Thereafter, a first metal layer 229 is formed on the insulating layer 219 as shown in FIG. 3E. In this case, the first metal layer 229 is formed to be electrically connected to the n-type electrode 211. The first metal layer 229 may be any one or a combination of two or more metal layers selected from the group consisting of Ag, Al, Au, Pt, Ti, Ni, and W. Subsequently, an Au layer (not shown) may be further deposited on the first metal layer 229 to prevent oxidation of the air contact surface. Deposition of the Au layer is optional.

An insulating layer 219 is formed between a portion of the p-type semiconductor layer 207 and / or between the p-type electrode 209 and the first metal layer 229 to function as a capacitor, the capacitor on the equivalent circuit shown in FIG. Corresponds to part 257. As described above, the p-type electrode 209 is formed to cover almost most of the region of the p-type semiconductor layer 207 as shown in FIG. 3D, or is formed only in a predetermined region of the p-type semiconductor layer 207. The portion of the p-type semiconductor layer 207 and the portion of the p-type electrode 209, the portion of the p-type semiconductor layer 207, or the portion of the p-type electrode 209 correspond to the lower electrode of the capacitor. A portion of the first metal layer 229 corresponds to an upper electrode of the capacitor, and the insulating layer 219 corresponds to a dielectric disposed between the upper electrode and the lower electrode.

In the first embodiment, at least one of the p-type electrode 209, the insulating layer 219, and the first metal layer 229 is implemented as a mirror structure that reflects the light generated from the active layer 205, and more preferably, the p-type electrode It may be implemented as a composite mirror of the electrode 209, the insulating layer 219, and the first metal layer 229. High refractive index (GaN layer) / low refractive index (p-type electrode) / high refractive index (insulation layer) when the p-type electrode 209, the insulating layer 219, and the first metal layer 229 are implemented as a composite mirror. The structure of the low refractive index (first metal layer) can maximize the reflectance, thereby maximizing the light extraction efficiency of the semiconductor light emitting device. That is, when the refractive index of the GaN layer and the insulating layer is formed to be relatively higher than that of the p-type electrode and the first metal layer, the reflectance may be maximized.

In particular, the p-type semiconductor layer 207 / p-type electrode 209 / insulating layer 219 / the first metal layer 229 has a high refractive index / low refractive index / high refractive index / low refractive index, the p-type When the electrode 209, the insulating layer 219, and the first metal layer 229 each have a thickness t corresponding to Equation 1 below, the reflectance may be maximized, and thus light extraction of the semiconductor light emitting device may be performed. Efficiency is maximized.

t = [λ / 4n] * k

(Where t is the thickness of the lamination, λ is the wavelength of light generated in the light emitting element, n is the refractive index of the lamination material and k is the natural number)

The p-type electrode 209 is a combination of two or more of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu, and HfN, or the insulating layer 219 is formed of SiO ₂ , Si ₃ N ₄ , In the case of a combination of two or more of Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN or the first metal layer 229 includes Ag, Al, Au, Pt, Ti, Ni and W In the case of any one or a combination of two or more metal layers selected from the above, the thickness at which the reflectance can be maximized may be determined by the refractive index of the material to be combined.

As shown in FIG. 3E, the semiconductor light emitting device according to the first embodiment may not only prevent ESD damage by implementing a capacitor having a dielectric structure surrounded by a metal and a metal (or semiconductor layer) and a mirror structure as an integral structure. The light extraction efficiency toward the sapphire substrate can be optimized.

Subsequently, as illustrated in FIG. 3F, flip chip bonding is performed on the sub-mount 301 of the semiconductor light emitting device having the capacitor region and the mirror structure integrally formed thereon. First, the insulating film 311 and the electrode plate 313 are sequentially stacked on a portion of the sub mount 301. Thereafter, the n-type electrode 211 is connected to the electrode plate 313 through the first conductive bump 351, and the p-type electrode 209 is connected to the submount 301 through the second conductive bump 353. do. The submount 301 may be a conductive substrate (eg, a heavily doped Si substrate) or a metal plate. Subsequently, in the semiconductor light emitting device according to the first embodiment of the flip chip bonding, a bias terminal may be connected to the sub-mount 301 and the electrode plate 313 during the packaging process.

Second Embodiment

4 is a cross-sectional view schematically illustrating a configuration of a semiconductor light emitting device according to a second exemplary embodiment of the present invention. Description of the same or similar parts as in the first embodiment will be omitted.

In the semiconductor light emitting device according to the first embodiment, an insulating layer, which is a dielectric, is deposited once to form a capacitor region. However, the semiconductor light emitting device according to the second embodiment increases the capacitor capacity as shown in FIG. 4 to effectively prevent ESD damage. In order to prevent this, a plurality of dielectric insulating layer structures including the first insulating layer 219 and the second insulating layer 239 are formed. The effective area of the dielectric insulating layer of the capacitor is enlarged to increase the charging capacity of the capacitor, thereby effectively preventing ESD damage and forming a composite mirror composed of a plurality of mirror layers, thereby increasing the light reflectance toward the sapphire substrate. It is possible to increase the light extraction efficiency.

The p-type electrode 209 may be any one or a combination of two or more selected from the group consisting of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu, and HfN, and the insulating layer 219, 239) may be any one or a combination of two or more selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO, and AlN, and may include a first metal layer ( 229 or the second metal layer 249 may be any one selected from the group consisting of Ag, Al, Au, Pt, Ti, Ni, W, and ITO, or a combination of two or more thereof. In this case, the first metal layer 229 formed on the first insulating layer 219 is electrically connected to the n-type electrode 211, and the second metal layer 249 formed on the second insulating layer 239 is p-type. It is connected to the pad 213 and electrically connected to the p-type electrode 209.

As in the case of the first embodiment, the p-type electrode 209, the first insulating layer 219, the first metal layer 229, the second insulating layer 239, and the second type of the semiconductor light emitting device according to the second embodiment. At least one of the metal layers 249 is implemented as a mirror structure that reflects light generated from the active layer 205, and more preferably, the p-type electrode 209, the first insulating layer 219, the first metal layer 229, It may be implemented as a composite mirror of the second insulating layer 239 and the second metal layer 249. A p-type electrode 209, a first insulating layer 219, a first metal layer 229, a second insulating layer 239, and a second structure of the second metal layer 249 are formed on the p-type semiconductor 207. In this case, the high refractive index / low refractive index / high refractive index / low refractive index / high refractive index / low refractive index structure (ie, the refractive index of the p-type semiconductor, the first insulating layer and the second insulating layer may be the p-type electrode, the first metal layer and the 2) the structure having a structure higher than the refractive index of the second metal layer) may maximize the reflectance, thereby maximizing the light extraction efficiency of the semiconductor light emitting device. In particular, the p-type semiconductor layer 207 / the p-type electrode 209 / the first insulating layer 219 / the first metal layer 229 / the second insulating layer 239 / the second metal layer 249 has a high refractive index / low The p-type electrode 209 / the first insulating layer 219 / the first metal layer 229 / the second insulating layer 239 while maintaining the relationship of refractive index / high refractive index / low refractive index / high refractive index / low refractive index When each of the second metal layers 249 has a thickness t corresponding to Equation 1, the reflectance may be maximized, thereby maximizing light extraction efficiency of the semiconductor light emitting device.

In the semiconductor light emitting device shown in FIG. 4, a plurality of capacitor regions and a plurality of mirror layers are formed corresponding to two insulating layers 219 and 239, but a plurality of capacitor regions corresponding to more than two insulating layers are provided. It will be apparent to those skilled in the art that the present invention may be formed of a plurality of mirror layers based on the technical idea of the present invention. Since the semiconductor light emitting device according to the second embodiment forms a plurality of capacitor regions and a plurality of mirror layers by increasing the area of the dielectric film, as described above, it is possible to increase the capacitance of the capacitor to more effectively prevent ESD damage. As a result, the reflectance of the mirror is increased to increase the light extraction efficiency.

In addition, in the semiconductor light emitting device according to the second embodiment, as shown in FIG. 4, since the second metal layer 249 covers most of the upper region of the light emitting device, flip chip bonding is convenient. This will be described in detail with reference to FIG. 5.

5 is a cross-sectional view schematically illustrating flip chip bonding of a semiconductor light emitting device according to a second exemplary embodiment of the present invention. Referring to FIG. 5, in a state where the insulating film 311 and the electrode plate 313 are sequentially stacked on a portion of the sub-mount 301, the n-type electrode 211 passes through the first conductive bump 351. The second metal layer 249 is connected to the sub mount 301 through the second conductive bump 353. In this case, since the uppermost part of the semiconductor light emitting device according to the second embodiment is formed of the second metal layer 249 connected to the p-type electrode 209, the large area contact with the second conductive bump 353 is easy. have.

Third Embodiment

6A is a cross-sectional view schematically illustrating a portion of the semiconductor light emitting device according to the third embodiment, and FIG. 6B is a top view schematically illustrating a portion of the semiconductor light emitting device corresponding to FIG. 6A. In the semiconductor light emitting device according to the third embodiment, similarly to the case of the first embodiment, a capacitor region in which an insulating layer 269 as a dielectric is surrounded by a p-type electrode 209 as a metal or a conductive semiconductor and a first metal layer 279 as a metal is used. Has However, in the semiconductor light emitting device according to the first embodiment, only one p-type pad 213 is formed, so that a local current crowding effect may occur when the electrical conductivity of the p-type electrode 209 is not good. In addition, only one pad may be installed, which may make it difficult to effectively release heat generated from the semiconductor light emitting device. In order to overcome this problem, in the semiconductor light emitting device according to the third embodiment, as shown in FIGS. 6A and 6B, the first metal layer 279 corresponding to the upper electrode of the capacitor is formed through the dielectric insulating layer 269. A plurality of p-type pads 263 connected to the n-type electrode (not shown) of the light emitting device and connected to the p-type electrode 209 which is the lower electrode of the capacitor are the openings of the insulating layer 269 and the first metal layer 279. The upper part of the device also has a protruding structure through the protruded region, which prevents ESD damage through a capacitor connected in parallel with the light emitting device. Good current dispersion in 209 can be achieved.

Fourth Example

7 is a schematic cross-sectional view of a portion of a semiconductor light emitting device according to a fourth exemplary embodiment of the present invention. The fourth embodiment combines the second embodiment with a plurality of capacitor regions formed by the plurality of insulating layers and the third embodiment with a plurality of p-type pads. As illustrated in FIG. 7, the semiconductor light emitting device according to the fourth exemplary embodiment includes a p-type electrode in which at least two insulating layers 269 and 289 are metal or conductive semiconductors, respectively. 209 and the capacitor region surrounded by the metal first metal layer 279 and the capacitor region surrounded by the metal first metal layer 279 and the metal second metal layer 299, thereby increasing the area of the effective dielectric layer to charge the capacitor. Capacity increases. This effectively prevents ESD damage.

The first metal layer 279 provided on the first insulating layer 269 is electrically connected to the n-type electrode, and the second metal layer 299 provided on the second insulating layer 289 is connected to the p-type pad 263. They are connected and electrically connected to the p-type electrode 209 to form a light emitting element in which capacitors are connected in parallel.

In addition, since the semiconductor light emitting device according to the fourth embodiment forms a plurality of mirror layers as described in the case of the second embodiment, the reflectance of the mirror is increased to increase the light extraction efficiency. In addition, in the semiconductor light emitting device according to the fourth exemplary embodiment, as illustrated in FIG. 7, a plurality of p-type pads 263 are formed to improve current dispersion between the p-type electrodes 209, and semiconductor light emission. The heat generated in the device can be effectively released. In addition, as described in the second embodiment, the semiconductor light emitting device according to the fourth embodiment is formed of the second metal layer 299 having the uppermost part connected to the p-type electrode 209, so that the semiconductor light emitting device has a conductive bump during flip chip fabrication. Large area contact is easy.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

According to the present invention, by forming a capacitor region surrounded by a metal or a conductive semiconductor as the dielectric layer, it is possible to effectively prevent ESD damage without adding a separate zener diode, and maximize the light extraction efficiency with a mirror structure fabricated simultaneously with the capacitor. The semiconductor light emitting element which can be performed, and its manufacturing method can be provided.

In addition, according to the present invention, it is possible to provide a semiconductor light emitting device and a method for manufacturing the same, which can effectively prevent ESD damage by securing a larger capacitor capacity without using a zener diode. In addition, according to the present invention, it is possible to provide a semiconductor light emitting device for forming a mirror structure capable of maximizing reflectance and a method of manufacturing the same. Moreover, according to this invention, the semiconductor light emitting element which can make current dispersion | distribution between a p-type electrode and a p-type pad favorable can be provided, and its manufacturing method can be provided. In addition, according to the present invention, it is possible to provide a semiconductor light emitting device capable of effectively dissipating heat generated from a chip and a method of manufacturing the same. According to the present invention, it is possible to provide a semiconductor light emitting device and a method of manufacturing the same, which are easy to bond when fabricating a flip chip.

Claims (34)

Board; A first semiconductor layer formed on the substrate; An active layer formed on the first semiconductor layer; A second semiconductor layer formed on the active layer; A second electrode formed on the second semiconductor layer; An insulating layer formed on at least one of a portion of the second semiconductor layer and a portion of the second electrode; And Including; a metal layer formed on the insulating layer; The insulating layer is surrounded by at least one of a part of the second semiconductor layer and a part of the second electrode and the metal layer to form a capacitor region, and at least one of the second electrode, the insulating layer, and the metal layer is formed in the active layer. A semiconductor light emitting device formed of a mirror structure that reflects generated light. The method of claim 1, And a first electrode formed on the exposed region of the first semiconductor layer. 3. The method of claim 2, The refractive index of the second semiconductor layer and the insulating layer is a semiconductor light emitting device, characterized in that relatively higher than the refractive index of the second electrode and the metal layer. The method of claim 3, The substrate is sapphire, the first semiconductor layer is an n-type nitride semiconductor, the second semiconductor layer is a p-type nitride semiconductor, the first electrode is an n-type electrode, the second electrode is a p-type electrode A semiconductor light emitting element. 5. The method of claim 4, The p-type electrode is any one or a combination of two or more selected from the group consisting of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. 5. The method of claim 4, The insulating layer is any one or a combination of two or more selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN device. 5. The method of claim 4, The metal layer is a semiconductor light emitting device, characterized in that any one or a combination of two or more selected from the group containing Ag, Al, Au, Pt, Ti, Ni and W. 8. The method according to any one of claims 5 to 7, The thickness t of the p-type electrode, the insulating layer and the metal layer corresponds to Equation 1, where Equation 1 is t = [λ / 4n] * k (Where t is the thickness of the lamination, λ is the wavelength of light generated in the light emitting element, n is the refractive index of the lamination material, and k is a natural number). 5. The method of claim 4, And a p-type pad formed on at least a portion of the p-type electrode. 10. The method of claim 9, The p-type pad is a plurality, each p-type pad is a semiconductor light emitting device, characterized in that disposed to be spaced apart from each other. 11. The method according to claim 9 or 10, Submount; An insulating film and an electrode plate formed on a portion of the sub-mount; A first bump to allow the n-type electrode to be connected to the electrode plate; And And a second bump to allow the p-type pad to be connected to the sub-mount. Preparing a substrate; Forming a first semiconductor layer on the substrate; Forming an active layer on the first semiconductor layer; Forming a second semiconductor layer on the active layer; Etching a portion of the first semiconductor layer, a portion of the active layer, and a portion of the second semiconductor layer; Forming a first electrode on the exposed region of the first semiconductor layer and forming a second electrode on the second semiconductor layer; Forming an insulating layer on a portion of the second electrode, a portion of the second semiconductor layer, and an etching surface by the etching step; And Forming a metal layer on the insulating layer; The insulating layer is surrounded by at least one of a part of the second semiconductor layer and a part of the second electrode and the metal layer to form a capacitor region, and at least one of the second electrode, the insulating layer, and the metal layer is formed in the active layer. A method of manufacturing a semiconductor light emitting device, which is formed of a mirror structure that reflects generated light. The method of claim 12, The etching surface is an inclined etching surface, the inclined etching surface is a semiconductor light emitting device manufacturing method, characterized in that formed by the reflow method of the photoresist. The method of claim 12, And forming a plasma treatment on the etching surface before forming the insulating layer. 14. The method of claim 13, The refractive index of the second semiconductor layer and the insulating layer is relatively higher than the refractive index of the second electrode and the metal layer. 16. The method of claim 15, The substrate is sapphire, the first semiconductor layer is an n-type nitride semiconductor, the second semiconductor layer is a p-type nitride semiconductor, the first electrode is an n-type electrode, the second electrode is a p-type electrode A semiconductor light emitting device manufacturing method. 17. The method of claim 16, The p-type electrode is any one or a combination of two or more selected from the group consisting of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. 17. The method of claim 16, The insulating layer is any one or a combination of two or more selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN Device manufacturing method. 17. The method of claim 16, The metal layer is a semiconductor light emitting device manufacturing method, characterized in that any one or a combination of two or more selected from the group containing Ag, Al, Au, Pt, Ti, Ni and W. The method according to any one of claims 17 to 19, The thickness t of the p-type electrode, the insulating layer and the metal layer corresponds to Equation 1, where Equation 1 is t = [λ / 4n] * k Where t is the thickness of the lamination, λ is the wavelength of light generated in the light emitting element, n is the refractive index of the lamination material, and k is the natural number. A method of manufacturing a semiconductor light emitting device, characterized in that. 17. The method of claim 16, And forming a p-type pad on a portion of the p-type electrode. 22. The method of claim 21, The p-type pad is a plurality of semiconductor light emitting device manufacturing method characterized in that. 23. The method of claim 21 or 22, Sequentially forming an insulating film and an electrode plate on a portion of the sub-mount; Connecting the n-type electrode to the electrode plate by a first bump, and connecting the p-type pad to the sub-mount by a second bump to flip chip bonding the semiconductor light emitting device. Board; A first semiconductor layer formed on the substrate; An active layer formed on the first semiconductor layer; A second semiconductor layer formed on the active layer; A first electrode formed on the exposed region of the first semiconductor layer; A second electrode formed on the second semiconductor layer; A first insulating layer formed on at least one of a portion of the second semiconductor layer and a portion of the second electrode; A first metal layer formed on the first insulating layer; A second insulating layer formed on the first metal layer; And Including a second metal layer formed on the second insulating layer; The first insulating layer is surrounded by at least one of a part of the second semiconductor layer and a part of the second electrode and the first metal layer to form a first capacitor region, and the second insulating layer includes the first metal layer and the A second capacitor region is surrounded by a second metal layer, and at least one of the second electrode, the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer reflects light generated from the active layer. A semiconductor light emitting element formed of a mirror structure. 25. The method of claim 24, At least one capacitor region is further formed on the second capacitor region. 25. The method of claim 24, The refractive index of the second semiconductor layer, the first insulating layer and the second insulating layer is higher than the refractive index of the second electrode, the first metal layer and the second metal layer. The method of claim 26, The substrate is sapphire, the first semiconductor layer is an n-type nitride semiconductor, the second semiconductor layer is a p-type nitride semiconductor, the first electrode is an n-type electrode, the second electrode is a p-type electrode A semiconductor light emitting element characterized by the above-mentioned. 28. The method of claim 27, The p-type electrode is any one or a combination of two or more selected from the group consisting of Pt, W, RuO ₂ , ITO, Pd, Cr, Ag, Ni, Au, Cu and HfN. 28. The method of claim 27, At least one of the first insulating layer and the second insulating layer is any one selected from the group consisting of SiO ₂ , Si ₃ N ₄ , Al ₂ O ₃ , TiO ₂ , HfO ₂ , Y ₂ O ₃ , MgO and AlN Or a combination of two or more thereof. 28. The method of claim 27, At least one of the first metal layer and the second metal layer is any one or a combination of two or more selected from the group consisting of Ag, Al, Au, Pt, Ti, Ni, W and ITO. The method according to any one of claims 28 to 30, The thickness t of the second electrode, the first insulating layer, the first metal layer, the second insulating layer, and the second metal layer corresponds to Equation 1, wherein Equation 1 is t = [λ / 4n] * k (Where t is the thickness of the lamination, λ is the wavelength of light generated in the light emitting element, n is the refractive index of the lamination material, and k is a natural number). 28. The method of claim 27, And a p-type pad formed on at least a portion of the p-type electrode. 33. The method of claim 32, The p-type pad is a plurality, each p-type pad is a semiconductor light emitting device, characterized in that disposed to be spaced apart from each other. 34. The method of claim 32 or 33, Submount; An insulating film and an electrode plate formed on a portion of the sub-mount; A first bump to allow the n-type electrode to be connected to the electrode plate; And And a second bump to allow the p-type pad to be connected to the sub-mount.

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