200810116 . 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種薄膜電晶體（thin film transistor， 簡稱TFT)裝置，特別是指一種具非揮發性記憶（nonvolatile memory)功能的薄膜電晶體裝置。 【先前技術】 近年來由於液晶顯示器（liquid crystal display，簡稱 LCD)與非揮發性記憶體大量地應用於可攜式電子產品上， • 其相關的研究也越來越受到重視。 在液晶顯示器方面，多晶矽（poly-Si)薄膜電晶體因具備 有較大的電子傳導率而擁有較高的導通電流，因此，可作 成週邊電路之驅動元件。但多晶矽薄膜裡因存在許多晶界 (grain boundary)而具有較大的缺陷密度，使得薄膜電晶體於 關閉狀態會產生嚴重的漏電流現象，此外，因為晶界之.缺 陷，使得導通時會有較差之次臨界電流（subthreshold current)特性，因此啟始電壓變大，而此缺點亦將導致無法 ^ 應用於低消耗功率與低操作電壓之產品上。 _ 在非揮發性記憶體方面，以現階段最常見的結構為半 導體-氧化物（oxide)-氮化物（nitride)-氧化物-半導體（SONOS) 結構之非揮發性記憶體。 參閱圖1，——種具有SONOS結構的非揮發性記憶體1 ，包含：一矽基材11，及複數設置於該矽基材11的記憶元 件12。 每一記憶元件12具有一設置於該石夕基材11的没極121 5 200810116 、一與該没極121相間隔設置的源極122、一介於該汲極 121與源極122之間的電荷儲存膜123、一形成於該電荷儲 存膜123上的閘極124、一覆蓋該汲極121、源極122、電 荷儲存膜123與閘極124並包括複數分別與該汲極121、源 極122與閘極123相通的連通孔126的保護膜125，及複數 分別對應填置於該等連通孔126的接點插塞（c〇ntact Plug)127 〇 母一電荷儲存膜123包括：一疊置於石夕基材上的穿 遂氧化層128、一形成於該穿遂氧化層128上的阻絕氧化層 (Mocking oxide layer)129,及一夾置於該穿遂氧化層128與 阻絕氧化層129之間且是由氮化矽（SixNy)所構成的電荷儲存 層 130 〇 般ό亥具有S0N0S結構的非揮發性記憶體1在記憶操 作時，主要的電荷寫入（program)方式有較為耗電的熱電子 注入法與穿隧效率較差的福勒諾罕穿隧（f〇wler_n的 tunneling)效應兩種。在電荷抹除（erase)的操作上，則是有 熱電洞注入法與反向福勒諾罕穿隧效應兩種方式。然而， 利用熱％洞注入法所完成的記憶抹除方式，仍存在有該穿 遂氧化層128受損及可靠度下降等問題，而經由反向福勒 諾罕穿遂效應所構成的記憶抹除方式也面臨有抹除效率不 佳的問題。 於近年來系統整合的技術日趨成熟的發展下，在同一 基板上整合前揭具有SONOS結構的非揮發性記憶體丨與薄 膜電晶體亦成為現階段熱門的研發主題。 6 200810116 然而，由前述說明可知，傳統TFT因多晶矽疒 曰 界缺陷的問題而導致起始電壓過高子在有晶 门力邊具有SOKfCK么士 構的非揮發性記憶m，其在該等閑極124施加電 $ 跨於此電荷儲存膜電場仍存在有電場不足的問/ 因此，亦嚴重地影響非揮發性記憶體的寫入及抹除效率。、 由上述可知，在一基板上整合顯示器用之 :⑼發性記憶元件以同時達到整合晝素電晶體二二 性記憶體的功能時，解決起始電壓過高並維持優里的: ^入/抹除效率，是目前研究開發元件整合相_域: 克服的難題。 汀倚 【發明内容】 <發明概要> 百先，本發明是以傳統非揮發性記憶體的電荷儲存膜 即，ΟΝΟ膜層結構的介電膜）來取代傳統了打中所使用的閑 極’I包膜（一般為氧化矽，即，Si〇 、 化物修補傳統TFT中多 I '何儲存膜之氮 夕日日矽通迢（channel)的表面缺陷，並 解決傳統ΊΤΤ起始電壓過高的問題。 太、，另’針對—般寬度大於1GG nm之多晶石夕通道與多晶石夕 矛、米線—GWire)通道之幾何結構所能提供的電性相比較， 當閑極施加電塵時，其聚集於通道表面處的電力線密度， 將，多晶⑦奈米線之通道寬度較小㈣對寬度大於⑽⑽ 高。由前述說明可知’多晶石夕奈米線通道經 由此種尖端效應的影響’其電場也會較大。因此，當原本 連接源極# 極之域A於⑽㈣的多晶料道，被前述 7 200810116 多晶矽奈米線取而代之時，將使得横跨於閘極介電膜的電 場變大，如此，不但可增加非揮發性記憶體之記憶寫入/抹 除的效率，亦可進一步地降低元件的起始電壓值。 <發明目的〉 因此，本發明之目的，即在提供一種具非揮發性記 功能之薄膜電晶體裝置。 於是，本發明具非揮發性記憶功能之薄膜電晶體裝置 ，包含：-基板，及複數呈陣列式排列並相互電性隔絕地 设置於該基板的薄膜電晶體。 每一薄膜電晶體具有一形成於該基板的主動膜、一閘 極介電膜、一閘極、一保護膜及複數接點掃塞。 每一薄膜電晶體的主動膜具有一源極區、一盥嗲 區相間隔設置的汲極區、複數 參 後數相間隔汉置且連接該源極區 與没極區並界定出複數狹長間隙的奈米線區。 每—薄膜電晶體的閘極介電膜具有一覆蓋該等夺米線 區及狹長間隙的穿遂氧化層、一 ^ t + 形成於忒牙逐乳化層的阻 ㈢一 ^置於該穿遂氧化層與阻絕氧化層之間且 由氮化物所構成的電荷儲 ^ 對應於其夺乎線^ ^存層。母一㈣電晶體之閘極相 —、:未、、泉&並豐置於該閘極介電膜。 母薄膜電晶體的該^早罐胳_ #甘、、75 k 、， ’、Q又膜覆皿，、源極區、没極區、 /、甲]極’並包括複數分、 的連通孔。 ^、汲極區、源極區與閘極相通 母一薄膜電晶I#的# Μ , 連通孔。 、以寺接點挿塞分別對應填置於該等 8 200810116 本發明之功效在於，可回性、去本,击女人土 士 J π ¥達到整合畫素電晶體與非 揮發性記憶體的功能，亦呈 J /、備有低起始電壓、優異的記憶 寫入/抹除效率等特點。 【實施方式】 <發明詳細說明> >閱圖2目3及圖4 ’本發明具非揮發性記憶功能之 溥膜電晶體裝置的-較佳實施例，包含：_基板2，及複數 呈陣列式排列並相互電性隔絕地設置於該基板2的薄膜電 晶體3。 ' 每一薄膜電晶體3具有一形成於該基板2的主動膜31 、-閘極介電膜32、一閘極33、一保護膜34及複數接點 挿塞35。 每一薄膜電晶體3的主動膜31具有一源極區311、一 與該源極區311相間隔設置的汲極區312、複數相間隔設置 且連接該源極區311與汲極區312並界定出複數狹長間隙 314的奈米線區313。 每一薄膜電晶體3的閘極介電膜32具有一覆蓋該等奈 米線區313及狹長間隙314的穿遂氧化層321、一形成於該 穿遂氧化層321的阻絕氧化層322，及一夹置於該穿遂氧化 層321與阻絕氧化層322之間且由氮化物所構成的電荷儲 存層323。每一薄膜電晶體3之閘極33相對應於其奈米線 區313並疊置於該閘極介電膜32。 每一薄膜電晶體3的保護膜34覆蓋其源極區3 11、及 極區312、與閘極32，並包括複數分別與其汲極區312、振 200810116 極區311與閘極32相通的連通孔341。 每-薄膜電晶體3的該等接點挿塞35分㈣應填置於 該等連通孔341。 雖然當該等奈米線區313 #寬度越小時，將因更明顯 的尖端效應而產生更大的電場，進而降低該等薄膜電晶體3 的起始電壓值並增加記憶寫入/抹除效率。然而，當該等奈 米線區3i3的寬度小& 10 nm時，將因量子偈限效應200810116. IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor (TFT) device, and more particularly to a thin film device having a nonvolatile memory function. Crystal device. [Prior Art] In recent years, liquid crystal display (LCD) and non-volatile memory have been widely used in portable electronic products, and their related research has received more and more attention. In the case of a liquid crystal display, a poly-Si thin film transistor has a high on-state current because of its large electron conductivity, and thus can be used as a driving element of a peripheral circuit. However, in the polycrystalline germanium film, there are many grain boundaries and a large defect density, so that the thin film transistor will have a serious leakage current in the off state, and in addition, due to the defects of the grain boundary, there will be a turn-on time. Poor subthreshold current characteristics, so the starting voltage becomes large, and this disadvantage will also result in failure to apply to products with low power consumption and low operating voltage. _ In terms of non-volatile memory, the most common structure at this stage is a non-volatile memory of a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) structure. Referring to Fig. 1, a non-volatile memory 1 having a SONOS structure includes: a substrate 11 and a plurality of memory elements 12 disposed on the substrate 11. Each of the memory elements 12 has a non-polarity 121 5 200810116 disposed on the base material 11 , a source 122 spaced apart from the gate 121 , and a charge between the drain 121 and the source 122 . The storage film 123, a gate 124 formed on the charge storage film 123, a gate 112, a source 122, a charge storage film 123 and a gate 124 are included and include a plurality of gates 121 and 122 respectively. a protective film 125 of the communication hole 126 communicating with the gate 123, and a plurality of contact plugs 127 correspondingly filled in the communication holes 126, the first charge storage film 123 includes: a stack a passivation oxide layer 128 on the shixi substrate, a Mocking oxide layer 129 formed on the ruthenium oxide layer 128, and a pinch-through oxide layer 128 and a resistive oxide layer 129 The charge storage layer 130 composed of tantalum nitride (SixNy) is similar to the non-volatile memory 1 having the S0N0S structure. In the memory operation, the main charge writing method has a relatively high power consumption. Hot electron injection method and Fowlerhan tunneling with poor tunneling efficiency (f〇wler_n tunneling) effect of the two. In the operation of charge erasing, there are two ways of thermal hole injection and reverse Fowlerham tunneling. However, in the memory erasing method by the hot % hole injection method, there is still a problem that the through oxide layer 128 is damaged and the reliability is lowered, and the memory wipe formed by the reverse Fowlerham penetrating effect is formed. In addition to the method, there is also the problem of poor efficiency in erasing. With the development of system integration technology in recent years, the integration of non-volatile memory devices and thin film transistors with SONOS structure on the same substrate has become a hot research topic at this stage. 6 200810116 However, as can be seen from the foregoing description, the conventional TFT has a non-volatile memory m with SOKfCK structure in the presence of a gated force due to the problem of polysilicon boundary defects, which is in the idle pole. 124 Applying electricity $ across the charge storage film, there is still an electric field shortage in the electric field. Therefore, the writing and erasing efficiency of the non-volatile memory is also seriously affected. It can be seen from the above that when the display is integrated on a substrate: (9) the hair-receiving element simultaneously achieves the function of integrating the halogen crystal transistor, and solves the problem that the starting voltage is too high and maintains excellent: Erasing efficiency is the current research and development component integration phase _ domain: overcome the problem. Ting Yi [Invention] [Summary of the Invention] The invention is based on the conventional non-volatile memory charge storage film, that is, the dielectric film of the ruthenium film structure, instead of the traditional use of the hit. The extremely 'I-coated film (usually yttrium oxide, ie, Si 〇, the compound repairs the surface defects of the nitrogen in the conventional TFT, and solves the problem of the conventional ΊΤΤ initial voltage is too high) The problem is too, and the other 'special width is greater than 1GG nm polycrystalline litter channel and polycrystalline stone spear, rice line - GWire) channel geometry compared to the electrical properties, when the idle pole is applied In the case of electric dust, the density of power lines concentrated at the surface of the channel will be smaller, and the width of the channel of the polycrystalline 7 nanowire is smaller (four) and the width is greater than (10) (10). From the foregoing description, it can be seen that the 'polycrystalline celite channel is affected by such tip effect' and its electric field is also large. Therefore, when the polycrystalline channel originally connected to the source A pole in the domain A (10) (4) is replaced by the above-mentioned 7 200810116 polycrystalline silicon nanowire, the electric field across the gate dielectric film will be increased, so that not only Increasing the efficiency of memory write/erase of non-volatile memory can further reduce the initial voltage value of the component. <Objectives of the Invention Accordingly, it is an object of the present invention to provide a thin film transistor device having a non-volatile recording function. Accordingly, the thin film transistor device of the present invention having a non-volatile memory function comprises: a substrate, and a plurality of thin film transistors arranged in an array and electrically isolated from each other. Each of the thin film transistors has an active film formed on the substrate, a gate dielectric film, a gate, a protective film, and a plurality of contact plugs. The active film of each of the thin film transistors has a source region, a drain region spaced apart from each other, a plurality of phase intervals, and a source region and a gate region are connected to define a plurality of narrow gaps Nano line area. Each of the gate dielectric films of the thin film transistor has a pass-through oxide layer covering the rice-capture regions and the narrow gaps, and a resist formed on the dentate-emulsion layer (3) The charge storage between the oxide layer and the resistive oxide layer and composed of the nitride corresponds to the memory layer. The gate phase of the mother-one (four) transistor -, :, , spring & and is placed on the gate dielectric film. The mother film transistor of the mother film _ #甘,, 75 k,, ', Q and film, the source region, the immersion region, /, A] pole 'and includes a plurality of connected holes . ^, the drain region, the source region and the gate are connected to each other. The mother-film electro-crystal I## Μ , the communication hole. The function of the present invention is to replace the pixel and the non-volatile memory with the help of the woman. It is also J /, has a low starting voltage, excellent memory writing / erasing efficiency and so on. [Embodiment] <Detailed Description of the Invention>> FIG. 2 and FIG. 4 'Best Embodiment of the present invention having a non-volatile memory function 溥 film transistor device, comprising: _ substrate 2, and The plurality of thin film transistors 3 of the substrate 2 are arranged in an array and electrically isolated from each other. Each of the thin film transistors 3 has an active film 31, a gate dielectric film 32, a gate 33, a protective film 34, and a plurality of contact plugs 35 formed on the substrate 2. The active film 31 of each of the thin film transistors 3 has a source region 311, a drain region 312 spaced apart from the source region 311, and a plurality of phase intervals and connecting the source region 311 and the drain region 312. A nanowire region 313 defining a plurality of narrow gaps 314 is defined. The gate dielectric film 32 of each of the thin film transistors 3 has a through oxide layer 321 covering the nanowire regions 313 and the elongated gaps 314, and a resistive oxide layer 322 formed on the through oxide layer 321 , and A charge storage layer 323 is sandwiched between the passivation oxide layer 321 and the resistive oxide layer 322 and composed of nitride. The gate 33 of each of the thin film transistors 3 corresponds to the nanowire region 313 and is stacked on the gate dielectric film 32. The protective film 34 of each of the thin film transistors 3 covers the source region 3 11 , the polar region 312 , and the gate 32 , and includes a plurality of interconnections respectively with the drain region 312 , the vibration of the 200810116 pole region 311 and the gate 32 . Hole 341. The contact plugs 35 (4) of each of the thin film transistors 3 should be placed in the communication holes 341. Although the smaller the width of the nanowire regions 313 #, a larger electric field will be generated due to the more pronounced tip effect, thereby lowering the initial voltage value of the thin film transistors 3 and increasing the memory writing/erasing efficiency. . However, when the width of these nanowire regions 3i3 is small & 10 nm, the quantum threshold effect will be
(quantum confinement effect)而產生能階分裂使得該等薄 膜電晶體3因起始電壓變大而影響該等薄膜電晶體/於實 施非揮發性記憶功料的記憶效應。此外，當該等奈米線 區313的寬度過大時’將因聚集於該等奈米線區313表面 之電力線密度變小而使得其料也相對應地下降並降低尖 端效應的貢獻度。如此將增加料薄膜電晶體3的起始電 壓並影響於實施非揮發性記憶功能時的記憶寫人/抹除效應 。因此’較佳地’每-奈米線區313的寬度是介於ι。細〜 100 nm之間。 再者，當該等奈⑽區313的厚度越大時將可使得 載子於奈米㈣313内移動的有效面積增加。因此’於實 施定電流之操作條件所取得的驅動電壓值將可相對下降。、 然=當㈣奈米線區313的厚度過大時，將使得每一薄 膜電晶體3的結構因類似一二 、 —向閘極（b-gate)結構而增加該 專示未線區313表面之♦士地 电力線的7刀佈區域，並抑制該等奈 未線區3 13的尖端六f t 的m 即使減少該等奈米線區313 見 法改4該等薄膜電晶體3之驅動電塵特性與記 10 200810116 抹除效率另：考量該等奈米線區3i3可提供適度 妓區二又以維持该等缚膜電晶體3的元件特性，該等奈米 mV'的厚度不可過小。因此’較佳地，每-奈米線區 的厚度是介於15nm〜1〇〇nm之間。 另’值得一提的是’考慮當該等薄膜電晶體3僅需要 =的操作電壓（如：12 V)及較快的寫人/抹除效率時，則 母一間極介電膜32的穿遂氧化層321、電荷儲存層功及 氧化層322的厚度可分別維持約3 nm、4 nm及6 nm。 而“亥等薄膜電晶體3是同時被用來當 =記憶體使用時，為避免因電子直接穿遂至該等電： 子θ 323而導致起始電塵飄移’該等電荷儲存層323及 阻絕氧化層322的厚度分別是不可小於4nm及7nm。因此 丄車乂佳地，每-閘極介電膜32的穿遂氧化層321之厚度是 二於3 Γ:15 nm之間；每—閘極介電膜32的電荷健存層 之尽度是介於4 nm〜25 _之間；每一間極介電膜” 的阻絕乳化層322之厚度是介於6nm〜3()nm之間。 此外，為使得每-薄膜電晶體3的閘極33可覆罢盆太 米^區313及狹長間隙314,以維持其閑極33的控制能I ^牛低起始電壓與增加記憶寫入/抹除效率，本發明該等狹 :間隙314的見度至少需比其兩倍厚度的間極介電膜μ再 夕出20 nm。而由前揭备.一 ^ 褐母牙逐虱化層321、電荷儲存層 及阻絕氧化層322的厚度範圍可知，該等閘極介電膜 32的厚度是介於13nm〜7〇nm之間，因此，較佳地每一 狹長間隙3U的寬度是至少大於4“m以上。 11 200810116 適用於本發明之每-主動膜31是—多晶碎層；較佳地 ，每一源極區311與汲極區312的多晶矽是摻雜有n型摻質 。此外，在-具體射’本發明之基板2具有—⑪晶圓Η 及-覆蓋該石夕晶圓的氧化膜[例如：氧化石夕（Si〇2)]22。另 ，值得-提的是’本發明亦可❹玻璃基板以取代該石夕晶 圓21。 有關本發明之前述及其他技術内容、特點與功效，在The energy level splitting is caused by the quantum confinement effect, so that the thin film transistors 3 affect the memory effect of the thin film transistors/implementing non-volatile memory materials due to the increase of the starting voltage. Further, when the width of the nanowire regions 313 is too large, the density of power lines concentrated on the surface of the nanowire regions 313 becomes small, so that the materials are correspondingly lowered and the contribution of the tip effect is lowered. This will increase the initial voltage of the thin film transistor 3 and affect the memory write/erase effect when the non-volatile memory function is implemented. Thus the width of the 'better' per-nanoline region 313 is therefore between ι. Fine ~ 100 nm between. Furthermore, the greater the thickness of the na[10] regions 313, the greater the effective area of movement of the carriers within the nano (tetra) 313. Therefore, the value of the driving voltage obtained by operating the constant current will be relatively decreased. However, when the thickness of the (4) nanowire region 313 is too large, the structure of each of the thin film transistors 3 is increased by the similarity to the b-gate structure. ♦ The area of the 7-knife area of the power line of the Shidi, and suppressing the tip of the line of the Nai line area 3 13 by six ft. Even if the nano-line area 313 is reduced, see the driving electric dust of the thin-film transistor 3 Characteristics and Recording 10 200810116 Erasing Efficiency Another: Considering that the nanowire region 3i3 can provide a moderate 妓 zone 2 to maintain the component characteristics of the lining transistor 3, the thickness of the nanometer mV' should not be too small. Therefore, preferably, the thickness per nano-line region is between 15 nm and 1 〇〇 nm. Another 'it is worth mentioning' is that when the thin film transistor 3 only needs the operating voltage of = (12 V) and the faster writing/erasing efficiency, the mother-electrode dielectric film 32 The thickness of the tantalum oxide layer 321, the charge storage layer, and the oxide layer 322 can be maintained at about 3 nm, 4 nm, and 6 nm, respectively. "Hei and other thin film transistors 3 are used simultaneously when the memory is used, in order to avoid direct penetration of the electrons to the electricity: the sub-theta 323 causes the initial dust to drift" the charge storage layer 323 and The thickness of the resistive oxide layer 322 is not less than 4 nm and 7 nm, respectively. Therefore, the thickness of the passivation oxide layer 321 of each gate dielectric film 32 is preferably between 2 Γ: 15 nm; The thickness of the charge storage layer of the gate dielectric film 32 is between 4 nm and 25 _; the thickness of the barrier dielectric layer 322 of each of the pole dielectric films is between 6 nm and 3 () nm. between. In addition, in order to make the gate 33 of each of the thin film transistors 3 can cover the basin 313 and the narrow gap 314 to maintain the controllability of the idle pole 33, the initial voltage is increased and the memory write is increased. The erase efficiency, the narrowness of the present invention: the gap 314 must be at least 20 nm more than the double-thickness interlayer dielectric film μ. The thickness range of the gate dielectric film 32, the charge storage layer and the resistive oxide layer 322 is disclosed in the foregoing. The thickness of the gate dielectric film 32 is between 13 nm and 7 nm. Therefore, preferably, the width of each of the elongated gaps 3U is at least greater than 4"m. 11 200810116 Each of the active films 31 suitable for use in the present invention is a polycrystalline fracture layer; preferably, each source region 311 The polycrystalline germanium with the drain region 312 is doped with an n-type dopant. Further, the substrate 2 of the present invention has -11 wafers and an oxide film covering the day wafer [for example: an oxidized stone.夕(Si〇2)]22. In addition, it is worth mentioning that 'the present invention can also replace the glass substrate 21 with a glass substrate. The foregoing and other technical contents, features and effects of the present invention are
以下配合參考圖式之一具體例的詳細說明中，將可清楚的 呈現。 <具體例> 再參閱圖2、圖3與圖4,在本發明具非揮發性記憶功 能之薄膜電晶體裝置的一具體例中，每一薄膜電晶體3之 :動,31是多晶矽層；每一源極區3ιι與汲極區η:的多 日日石夕疋摻雜有n型摻質；每一奈米線區313的厚度約為Μ η二每一奈米線區313的寬度為65 ;每一狹長間隙… 的^度約為280 nm;每一閘極介電膜32的穿遂氧化層321 之=度約為10 nm ;每一閘極介電膜32的電荷儲存層⑵ 之=度約為20 nm ;每一閘極介電膜32的阻絕氧化層⑶ 2厗度約為2〇議；每-薄膜電晶體3的閘極33之厚度約 為 150 nm。 本發明該具體例的製作方法，是簡單地說明於下。 先’對切晶圓21施予氧化處理以在該⑦晶圓21 广形成該厚度約為500 nm的氧化膜（si〇2)22;另，於一低 壓化學氣相沉積（LPCVD)系、统中，卩工作壓力$ 1〇5心抓 12 200810116 - 、反應氣體為碎烧（SiH4)、氣體流量為85 seem及反應溫度 為550 t：等製程條件，於該氧化膜22上形成一厚度約為 50 nm的多晶石夕層，並配合實施微影製程（photolithography process)以定義出每一薄膜電晶體3之主動膜31。 進一步地，於該沉積系統中以工作壓力為300 mTorr、 反應氣體為四乙基矽[Si(OC2H5)4]、氣體流量為100 seem及 反應溫度為700 °C等製程條件，於該等主動膜31上形成一 厚度約為10 nm的第一 Si02層；另，以工作壓力為350 mTorr、氣體流量分別為30 seem及130 seem的二氯石夕曱烧 (SiH2Cl2)及氨氣（NH3)、反應溫度為780 °C等製程條件，於 該第一 Si02層上形成厚度約為20 nm的氮化矽（SixNY)層； 又，以相同於該第一 Si02層的製程條件於該氮化矽層上形 戒一厚度約為20 nm的第二Si02層。 於完成該第二Si02層之後，在該沉積系統中以工作壓 力為600 mTorr、氣體流量分別為1 slm、200 seem及1〜5 slm的SiH4、氫化磷（PH3)及氮氣（N2)、反應溫度為550 °C ® 等製程條件，於該第二Si02層且與該等奈米線區313相對 應處上形成該等厚度約為150 nm的閘極33(為η型摻雜之 多晶矽層）；另，對該等主動膜31施予磷（Ρ)的離子佈植（ion implantation)及活化製程進而定義出該等源極區3 11與沒極 區 312。 以相同於該第一 Si02層的製程條件於該第二Si02層及 該等閘極33上形成一第三Si02層；另，對該第一、二、三 Si02層及氮化矽層施予微影製程，以定義出每一薄膜電晶 13 200810116 體3的穿遂氧化層3U、電荷儲存層313、阻絕氧化層3i2 、保護膜34及該等連通孔341。最後，利用一賤鐘系統， 以2〜4 mT⑽的工作壓力對一由銘[A1Si(1%)Cu(〇 5%)]所構 成的靶材施予8 kW的輸出功率，進而在該等連通孔341中 填置該等接點插塞35。 <電性分析>The detailed description of one specific example with reference to the drawings will be clearly described below. <Specific Example> Referring again to Figs. 2, 3 and 4, in a specific example of the thin film transistor device having a non-volatile memory function of the present invention, each of the thin film transistors 3 is moved, and 31 is polycrystalline germanium. The layer; each source region 3 ιι and the bungee region η: the multi-day day shi 疋 is doped with n-type dopant; each nano-line region 313 has a thickness of about Μ η 2 per nano-line region 313 The width of each slit is about 280 nm; the passivation oxide layer 321 of each gate dielectric film 32 has a degree of about 10 nm; the charge of each gate dielectric film 32 The storage layer (2) has a degree of about 20 nm; the barrier oxide layer (3) of each of the gate dielectric films 32 has a thickness of about 2; and the thickness of the gate 33 of each of the thin film transistors 3 is about 150 nm. The production method of this specific example of the present invention will be briefly described below. First, the dicing wafer 21 is subjected to an oxidation treatment to form an oxide film (si〇2) 22 having a thickness of about 500 nm on the 7 wafer 21; and, in a low pressure chemical vapor deposition (LPCVD) system, In the system, the working pressure is $1〇5心1212, the reaction gas is calcined (SiH4), the gas flow is 85 seem, and the reaction temperature is 550 t: the process conditions, a thickness is formed on the oxide film 22. A polycrystalline layer of about 50 nm is used in conjunction with a photolithography process to define the active film 31 of each thin film transistor 3. Further, in the deposition system, the working pressure is 300 mTorr, the reaction gas is tetraethyl hydrazine [Si(OC2H5)4], the gas flow rate is 100 seem, and the reaction temperature is 700 °C, and the like, A first SiO 2 layer having a thickness of about 10 nm is formed on the film 31; in addition, a chlorine gas having a working pressure of 350 mTorr and a gas flow rate of 30 seem and 130 seem, SiH2Cl2 and ammonia (NH3) a reaction temperature of 780 ° C and the like, forming a layer of tantalum nitride (SixNY) having a thickness of about 20 nm on the first SiO 2 layer; and nitriding the same under the same processing conditions as the first SiO 2 layer The second layer of SiO 2 having a thickness of about 20 nm is formed on the ruthenium layer. After completion of the second SiO 2 layer, SiH 4 , hydrogen hydride (PH 3 ) and nitrogen (N 2 ) react at a working pressure of 600 mTorr and a gas flow rate of 1 slm, 200 seem and 1 to 5 slm, respectively. The process is performed at a temperature of 550 ° C ® , and the gate 33 having a thickness of about 150 nm is formed on the second SiO 2 layer and corresponding to the nanowire regions 313 (is an n-type doped polysilicon layer). In addition, ion implantation and activation processes for applying phosphorus (Ρ) to the active film 31 further define the source regions 31 and the non-polar regions 312. Forming a third SiO 2 layer on the second SiO 2 layer and the gates 33 in the same manner as the first SiO 2 layer; and applying the first, second, and third SiO 2 layers and the tantalum nitride layer The lithography process defines a passivation oxide layer 3U, a charge storage layer 313, a resistive oxide layer 3i2, a protective film 34, and the via holes 341 of each of the thin film transistors 13 200810116. Finally, using a one-clock system, an output of 8 kW is applied to a target consisting of Ming [A1Si (1%) Cu (〇5%)] at a working pressure of 2 to 4 mT (10), and then The contact plugs 35 are filled in the communication holes 341. <Electrical Analysis>
>閱圖5，由，及極電流對閘極電壓（Id_Vg)曲線圖顯示可 矣以氧化石夕（Si〇2)作為閘極介電膜的傳統TF丁具有較低的 導通電流值’反觀以本發明所提及之「利用〇N〇膜層結構 取代氧化⑦以作為TFT之閘極介電膜」的發明㈣，使得 ΟΝΟ結構之TFT具備有較大的導通電流。此外，由於咖 膜層結構中的氮原子可修補多晶石夕表面的缺陷，因此，有 m I界^巾s (subthreshGld swing)，且驅動電壓及漏電 流亦較低。 >閱圖6，由圮憶視窗（memory window)對寫入時間之. 曲線圖顯示可知’傳統s_s結構之非揮發性記憶體在Μ V及20 乂的測試條件下，於i秒鐘的寫人時間所 憶視窗分別約為2.3vwv;反觀本發明該具體例在 條件下，於1秒鐘的寫入時間所取得的記 φ 達3.8 V及6.5 ν。本發明該具體例因具 較大的記憶視窗·判別字U或字元！時可更為料確 此外，亦具備有較高的記憶寫人效率。 確’ 參閱圖7， 傳統SONOS結 由記憶視窗對抹除時間之曲線圖顯示可知， 構之非揮發性記憶體在_15 V及·2G 乂的測試 14 200810116 條件下，⑨！秒鐘的抹除時間所取得的記憶視窗分別 〇.75 V及].33 V;反觀本發明該具體例在-15 v及,v的 測試條件下，⑨1秒鐘的抹除時間所取得的記憶視窗分別 可達1·1 vu.65 V。同樣地，本發明該具體例因具備有較 大的記憶視窗而於判別字元0或字元1時可更為精確，因 此’記憶寫入效率較高。 本毛月具非揮發性§己憶功能之薄膜電晶體裝置，可同> Read Figure 5, by, and the pole current vs. gate voltage (Id_Vg) graph shows that the conventional TF with osmium oxide (Si〇2) as the gate dielectric film has a lower on-current value' In contrast, the invention (4), which uses the 〇N〇 film layer structure instead of oxidizing 7 as a gate dielectric film of a TFT, which is referred to in the present invention, allows the TFT of the ruthenium structure to have a large on-current. In addition, since the nitrogen atoms in the structure of the coffee film layer can repair the defects of the surface of the polycrystalline stone, there is a mth boundary s (subthreshGld swing), and the driving voltage and the leakage current are also low. > Read Figure 6, from the memory window to the write time. The graph shows that the 'traditional s_s structure of non-volatile memory under 测试 V and 20 乂 test conditions, in i seconds The window recalled by the time of writing is about 2.3 vwv, respectively. In contrast, the specific example of the present invention has a record φ of 3.8 V and 6.5 ν at a write time of 1 second. This specific example of the present invention has a large memory window, a discriminating word U or a character! It can be more reasonable. In addition, it also has a high efficiency in memory writing. Indeed, referring to Figure 7, the traditional SONOS node shows the graph of the erasing time of the memory window. The non-volatile memory is tested in _15 V and · 2G 14 14 200810116, 9! The memory window obtained by the erasing time of the second is 75.75 V and ].33 V; in contrast, the specific example of the present invention is obtained under the test conditions of -15 v and v, the erasure time of 91 seconds. The memory window can reach 1·1 vu.65 V respectively. Similarly, this specific example of the present invention is more accurate in discriminating character 0 or character 1 because it has a larger memory window, so the memory writing efficiency is higher. The film has a non-volatile § recall function of the thin film transistor device, which can be the same
¥達到整合畫素電晶體與非揮發性記憶體的功能，亦且備 有低起始電壓、優異的記憶寫人/抹除效率等特點，確實 到本發明之目的。 ' 惟以上所述者，僅為本發明之較佳實施例而已，當不 =以此限定本發明實施之範圍，即大凡依本發明中請專利 辄圍及發明說明内容所作之簡單的等效變化與㈣，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】¥Achieves the function of integrating the pixel and non-volatile memory, and also has the characteristics of low initial voltage, excellent memory writing/erasing efficiency, etc., which is indeed the object of the present invention. The above is only the preferred embodiment of the present invention, and does not limit the scope of the implementation of the present invention, that is, the simple equivalent of the patent scope and the description of the invention in the present invention. Changes and (4) are still within the scope of the invention patent. [Simple description of the map]
圖1是一正視示意圖，說明一種具有 揮發性記憶體； SONOS結構的非 〃圖2是一俯視示意圖，說明本發明具非揮發性記憶功 旎之薄膜電晶體裝置的一較佳實施例； ;、圖3是沿圖2之直線3_3户斤取得的一局部剖視示意圖， 說明該較佳實施例的細部結構； 圖4是沿圖2之直線4·4所取得的_局部剖視示意圖， 說明該較佳實施例的細部結構； 圖5是一汲極電流對閘極電壓（Id_Vg)之曲線圖； 15 200810116 圖6是一電壓對時間之曲線圖，說明本發明具非揮發 性記憶功能之薄膜電晶體裝置的一具體例之寫入記憶視窗 特性；及 圖7是一電壓對時間之曲線圖，說明本發明該具體例 之抹除記憶視窗特性。1 is a front view showing a volatile memory; SONOS structure is a top view showing a preferred embodiment of the thin film transistor device with non-volatile memory function of the present invention; 3 is a partial cross-sectional view taken along line 3_3 of FIG. 2, illustrating a detailed structure of the preferred embodiment; FIG. 4 is a partial cross-sectional view taken along line 4·4 of FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT; FIG. 5 is a graph of a gate current versus gate voltage (Id_Vg); 15 200810116 FIG. 6 is a graph of voltage vs. time, illustrating the non-volatile memory function of the present invention. A write memory window characteristic of a specific example of the thin film transistor device; and FIG. 7 is a voltage vs. time graph illustrating the erase memory window characteristic of the specific example of the present invention.
16 200810116 - 【主要元件符號說明】 X -S- a + μ + i …基板 閘極介電膜 2 1 " " μ …。$夕晶圓 321 -- …5穿遂氧化層 2 2…… …^氧化膜 3 2 2… 7…阻絕氧化層 3…… ……薄膜電晶體 323… …1電荷儲存層 1夺尹夺分今 …主動膜 3 3…… 閘極 311 - :…源極區 3 4…" ……保護膜 3 12… …没極區 3 4 1… …5連通孔 313- …奈米線區 3 5…… …接點插塞 3 14… …狹長間隙 1716 200810116 - [Main component symbol description] X -S- a + μ + i ... substrate gate dielectric film 2 1 "" μ .... $夕半导体321 -- ... 5 through the oxide layer 2 2 ... ... ^ oxide film 3 2 2... 7... blocking oxide layer 3 ... ... thin film transistor 323 ... 1 charge storage layer 1 wins the score Today... active membrane 3 3... gate 311 - :... source region 3 4..." ...... protective film 3 12... no pole region 3 4 1... 5 communication hole 313- ... nanowire region 3 5 ... ... contact plug 3 14... narrow gap 17