TW200807896A - Sigma-delta modulation with offset - Google Patents

Abstract

Techniques for performing ΣΔ modulation with offset in order to reduce out-of-band quantization noise are described. In an exemplary oversampling DAC that implements ΣΔ modulation with offset, an interpolation filter performs upsampling and interpolation filtering on data samples to generate input samples. A summer adds an offset to the input samples to generate intermediate samples. The offset alters the characteristics of the quantization noise from a ΣΔ modulator and may be selected to obtain the desired quantization noise characteristics, to retain as much dynamic range as possible, and to simplify the removal of the offset. The ΣΔ modulator performs upsampling and noise shaping on the intermediate samples and provides output samples. An offset removal unit removes at least a portion of the offset from the output samples in the digital or analog domain. A DAC converts the output samples to analog.

Description

200807896 IX. INSTRUCTIONS: [Technical field to which the invention pertains] and more particularly to the present disclosure relates generally to electronic device incremental delta (ΣΔ) modulators. [Prior Art]

/△ Tuning (4) Widely used in two applications such as oversampling audio digital analog conversion crying (MC), oversampling analog-to-digital converter (ADC), instrument DAc, etc. The ΣΔ modulator receives a digital input with a resolution of many bits (eg, 16 bits) at a lower input sample rate and outputs the sample at a higher resolution: produces one or a few bits with the same resolution The number is round. The modulator can use a quantizer with one or a few bits of resolution to produce a digital output and thus achieve good linearity. In addition, the ΣΔ modulator can spectrally refine the noise so that most of the noise is pushed away from the desired signal band toward a higher frequency. A simple analog filter can be used to more easily filter out out-of-band noise at higher frequencies. However, high frequency out-of-band noise from the ΣΔ modulator can cause certain problems even in the presence of analog filtering. For example, out-of-band noise may be mixed with other signals and folded back into the desired signal band before filtering, thus raising the bottom of the noise in the band. A high noise floor can cause the ΣΔ modulator to fail to meet the signal-to-noise ratio (SNR) and/or other regulations. In addition, out-of-band noise can be handled by digital circuitry located on the analog integrated circuit (IC) die. The quantization noise is directly converted into the activity rate of the digital circuit during the sensitive period of operation and can deteriorate the analog circuit block of the adjacent positioning, thereby raising the noise floor of the analog circuit blocks. This is due to the out-of-band noise from the ςδ 117836.doc 200807896 modulator. These four adverse effects are undesirable and may be even less necessary in the art to reduce the technology from the communication. . The extra-band of the Zhou dynasty [Abstract] The description herein is for performing the compensation edge...

Techniques for quantifying noise. A further reduction in the out-of-band one is applied with a compensated ΣΔ modulated oversampling DAC that is inserted and produces a wheeled sample. Add ==: frequency = and endogenous intermediate samples. The compensation changes the characteristics of the noise from £:;; complements the production of _ Π夂 ^ and can be selected to obtain the desired quantification only to remove the singularity, so as to maintain as much dynamic as possible as described below Range and simplify the removal of compensation. ς △ 变 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 对 中间 中间 中间 对 中间 中间 中间 中间 中间 对 中间 中间 中间 中间 中间 对 对 对 对 对 对 对兀 inverting) and / or analog domain (for example, # by adding compensation in the analog circuit)

At least a portion of the compensation is removed from the output sample. Dac uses multiple DACs to convert output samples to analog samples. Dynamic Component Matching (1) Decisions Where the different ones of the DAC components are selected based on the output samples. The low pass filter filters the analog signal from the DAC to remove out-of-band noise. The amplifier amplifies and/or buffers the filtered signal to produce an output signal. Various aspects and embodiments of the invention are described in more detail below. [Embodiment] The term "exemplary" is used herein to mean, ". Any of the "exemplary" described herein as an example, example, or embodiment or design is not necessarily 117836.doc 200807896 shall be constructed to be superior to the Gan + t design. A preferred or advantageous embodiment of the example or design, or a square of the oversampling of one of the compensated ΣΔ modulations. ... can be used for oversampling audios. Others = t embodiment shown in Fig. 1 'digital processor 110," sample 112... has a desired number (N) of bits of data samples W. memory sub-. The data and code of the processor 110. The adder 120 adds compensation to each data sample of the Y. U〇 and provides an intermediate sample: the compensation system can select a static value as described below. The temporary memory (not only For the ΣΔ modulator 130 part) perform combined up-sampling and zero-order hold interpolation for the intermediate sample. 4 △ modulator (1) clearing upsampled ''executive helium reforming and taking the sample rate of 乂^ Provide a round-out sample χ〇υτ with one or a few (M) bits of 7L. The sample rate is usually many times higher than the input sample rate. For example, Ν can be equal to 16, Μ can be equal to 2 or 4, and = The sampling ratio (OSR) can be equal to 32 or 256. In detail, the age of the foot spleen, the basin / (four) is the bandwidth of the signal being processed, and Λ is the sampling rate. For the digital processing benefit no, because (10) is Therefore, the increase in the sampling rate of the factor κ causes the OSR to increase by a factor of κ. For Ν, Μ, and 〇 sR, other The value (4) is possible. An exemplary design of the ΣΔ modulator 130 is described below. The ΣΔ modulator 130 has a specific noise transfer function determined by the design of the ΣΔ modulator, which is added via adder 120 to Compensation of the data samples results in quantization noise being attenuated at a higher frequency. The compensation removal unit 140 removes all of the compensation or compensation 117836.doc 200807896 in the output samples and provides a corrected sample x(10). In the digital domain (eg Compensating removal is performed in the _ field or in the analog domain (in item 1 + not shown). m : tlDAC 150 converts the digitized digital sample into an analog sample and provides an analog signal. Low pass filter 16 〇 filter The analog signal is used to remove the out-of-band impurity 2 and provide a signal through the chirp. The low-pass filter '10' can also be called post-filter, wave, reconstruction filter, etc. Amplifier (Amp) m amplification and / or buffer The filtered signal provides the output signal to, for example, a speaker or some other output circuit. Figure 2 shows a block diagram of another embodiment of implementing an oversampled DAC 200 with compensated ΣΔ modulation. The DAC can also be used ultra Sample audio DM and other applications. For the embodiment shown in Figure 2, the digital processor 2 generates a data sample 'T with N-bit resolution' at a sample rate of 乂. Memory bank storage for the processor 1 1 〇之慎祖^ A ^ Becco and private code. Interpolation filter 2 i 4 upsamples the data samples by a factor of 8, performs an interpolation transition and provides N bits at a sample rate of 8/ί The meta-resolution input sample XiNm22 adds compensation to each input sample from the filtered state 214 and provides an intermediate XINT. The single-pass 226 performs up-sampling and noise reforming. Within the cell, the zero-order hold (fine) cell 228 performs upsampling at a factor of 32 by maintaining each of the intermediate samples for 32 clock cycles of the ςΔ modulator (4). ς△ 调器 (4) Quantify the sample from ΖΟΗ早凡228 to job$, perform noise re-formation, and provide the output sample χ〇υτ with difficult elements at a sample rate of two 々. Compensation Private 7L 240 removes any compensation or compensation portion of the output sample 117836.doc 200807896 and provides a corrected sample Xc〇R. Dynamic Component Matching (DEM) unit 242 receives the calibrated samples and dynamically selects different components within Dac 25A to improve the adverse effects of mismatches in such DAC components. Hey. It is said that the samples of the two positives are converted into analog samples and the analog signals are provided. The low pass filter 210 filters the analog signal to remove out of band noise and provide a filtered signal. Amplifier 270 amplifies and/or buffers the filtered signal and provides an output signal. Figure 2 also shows an embodiment for implementing an oversampling DAC. For this embodiment, the digital processor 210 to the compensation removal unit 24 are constructed on the digital 1C die 202, and the DEM cell 242 to the amplifier 27 are constructed on the analog 1C die 204. For this embodiment, even though the DEM unit 242 is a digital circuit, it is constructed on the analog IC die to reduce the number of signal lines passing between the digital IC die 202 and the analog 1C die 204. The M-bit modulator can be interfaced to the dem unit 242 via only one signal line. The DEm unit 242 performs a thermometer code translation that changes the data so that the data contains 2M levels. These levels are directly related to analog hardware. The DEM unit 242 can introduce a relatively large amount of digital noise into the power supply of the substrate and/or analog 1C die. This digital noise can degrade the performance of adjacent analog circuits. This digital noise can be determined by the characteristics of the quantized noise from the ΣΔ modulator. By using the added compensation to change the quantization noise characteristics, the digital noise from the DEM unit 242 can be mitigated and the performance of the adjacent analog circuit can be improved. The ΣΔ modulator 130 of Fig. 1 and the ΣΔ modulator 230 of Fig. 2 can be constructed in various designs 117836.doc 200807896. In addition, chirp modulators 130 and 230 can receive samples having any number of bits and can provide output samples having any number of bits. An exemplary chirp modulator design is described below. 3 is a block diagram showing an embodiment of a second-order Σ Σ Δ modulator 3 可 that can be used for each of the ςα modulator ι3 图 of FIG. 1 and the Σ δ modulator 230 of FIG. 2, respectively. . For the embodiment shown in FIG. 3, the ςα modulator 3〇〇 includes an input gain element 308, two-level noise reforming, and a one-bit quantizer hurricane element 308 that receives the intermediate sample χΙΝΤ and gains Αι Scale up the intermediate sample XINT. The intermediate sample has a resolution of N bits, where "may be 16 or some other value." For the first noise reforming stage, the adder 3 "0" is subtracted from the output of the gain element 3 〇 8 by the gain element 318 The difference is supplied to the filter portion 312. The filter benefit portion 3 12 includes an adder 314 and a delay element 316. The adder 314 adds the output of the adder 31 and the output of the delay element 316. 316 receives the output of adder 314 and provides a delay of the -clock cycle. For the second noise reforming stage, adder 32 subtracts the output of delay element 316 from the output of delay element 328 and provides to chopper portion 322. In the waver portion 322, the adder 324 adds the output of the output disk delay element 326 of the adder 320. The delay element appears to receive the adder-like output and provide a delay of one clock period. The inner component can be designed to have a dislocation greater than n bits: the refinement quantizes the rotation of the delay 70 pieces 326 and provides the M 兀 rain out sample X0UT. Quantizer 3 quantizer, ~ can be ! (4) Reading one for multiple yuan yuan for 1 person For the modulator, it is possible that 117836.doc 200807896 is ambiguous. Gain element 3 1 8 scales up the wheel with gain A2 and gain element 328 scales up the output sample with gain As. Filter sections 312 and 322 The transfer function ❻2) of each of them can be expressed as · 2 - 1 G(z) = - Specialized (1) One of the clock cycles U, where z-1 is indicated by delay elements 316 and 3 26 Every delay.

For Σ Δ modulator 3 〇〇, it is expressed as: The total transfer function of the desired signal is (2) Α ΑΓ ΑΓ — — — — _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 2) In the two sides, the '(four) transfer function has two zeros at the object 纟~Ό

It has two complex poles' whose center is dominated by the gain Α2 Ή 疋. The k-th transfer function ff(z) has a low-pass shape. Q is expressed as ΣΔ modulator 300: and the total transfer function of the mouth noise is u \厶)· In the ζ plane, the noise transfer function equation (3) is right at a+/b (5) There are two zeros at the "*7·0 and - plague /, there are two complex poles. Shape. The chowder transfer private function has a high-pass graph 3 exhibits the △ Δ modulator can be exemplified with any number ...10. The technical turn-out bits described in this article, any order, any number of parts, and various ΣΔ modulators of the U7836.doc 200807896 class, etc. For clarity, some parts of the description below Used in the ΣΔ modulator 3〇〇 in Figure 3. The ΣΔ modulator can implement any of the various quantization mechanisms known in the art. In the first mechanism, in the 16-bit domain The range of ", 〇,, to "4〇95" is mapped to "〇" in the 4-bit field, and in the 16-bit field, the range of ·ι" to -4096" is mapped to The "_i' mechanism in the 4-bit field (for example) allows simple quantization of the number (four) towel by lowering the bit. In the second mechanism 'at 16 bits The "2()47" to "_2G48„ range in the meta-domain maps to "0" in the 4-bit domain. Different quantization mechanisms can have different noise characteristics. For smaller input signals, The output of the second filter portion 322 can be & 〇 徘徊 徘徊 徘徊 徘徊 徘徊 徘徊 徘徊 徘徊 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 量化 ' ' ' ' ' ' ' ' ' Because of the threshold, the system is close to this. In the first mechanism, the quantizer output can jump very frequently between 1 " and 1, because the threshold 2〇47 is different from 々θα. The activity rate will be lower at far m. The techniques described herein can be used for all quantization mechanisms and are especially beneficial for the first mechanism. μ Adding compensation to the input samples affects the quantization noise from the 2 delta modulator, The rumor 'can reduce the high frequency out-of-band noise by applying appropriate compensation. The reduction of out-of-band noise is explained below. Figure 4Α shows the ΣΔ modulator from Figure 3 There is no curve 2 for the quantized noise of the initial mechanism) and from (5)-ς△ The 冉" of the transformer" has a _4929 complement applied to the 16-bit input sample. π, ρ complements the mussel (which is called the compensation machine into the curve 420 of the noise. For this example 'ΝΑ, heart, The input rate is Λ, khz, and the output sample rate is w88 ϊ I7836.doc 200807896 MHz. Quantization noise is traced to the logarithm of the logarithm of frequency. Figure 4A shows the smaller input signal The feature is because the signal-to-noise ratio is high for a small input heart, so this is an important situation. The quantized noise characteristics can be different for larger input signals. In the absence of any compensation, τ, as for the order ςΔ modulator, is expected to increase the noise amplitude at a rate of 4 〇 decibels per ten frequencies. ° As indicated by Qu. 41, the amplitude of the noise is flattened at approximately 2 points. In the case of full compensation, the amplitude of the noise is chosen to be large at a rate of 4 每 every ten frequencies but lower at a higher frequency. As shown in Figure 4A and also as follows (4): No, for the two mechanisms, the subject of the quantized noise from the 2 Δ modulator appears at a higher frequency from about i MHz to slightly over 6 MHz, two The latter of the frequencies indicates the half of the output sample rate. "And, as indicated by curve (4) and curve 420, the noise amplitude with compensation is lower at higher frequencies than the noise amplitude without any compensation. Figure 4B shows a more detailed plot of quantized noise at higher frequencies. The quantized noise from the ΣΔ modulator 3〇〇 without any compensation is shown by curve 412, and the compensated quantization noise from the same ΣΔ modulator is shown by curve 422. Curve 412 and curve 422 indicate that out-of-band noise is reduced by up to 1 dB at higher frequencies by adding compensation. This amount of noise reduction translates into a mechanism that has signal variations that are more than nine times smaller than the original mechanism. Figures 4A and 4B show the reduction in out-of-band noise for a particular 4-bit ΣΔ modulator with a particular compensation -4929 applied to a singular input sample. This specific compensation offers several advantages. First, the application to the 16-bit input sample complements 117836.doc • ]3· 200807896 The compensation -4929 results in a compensation of approximately -I in the 4-bit output sample from the ΣΔ modulator. As described below, since the round-off compensation is close to one of the least significant bits (LSB) of the 4-bit round, most of this compensation can be easily digitally removed. Second, the 16-bit compensation of _4929 avoids the input signal being limited by the ΣΔ modulator. The ΣΔ modulator has a 4-bit range of +7 to -8. In the absence of compensation, the output of the ΣΔ modulator is in the range of +7 to _7. In the case of compensation, the output of the ΣΔ modulator is in the range of +6 to the slave: However, if the compensation of +4929 is used, the output of the modulator is in the range of +8 to _6. Since the +8 system is not available, this range is invalid. Therefore, for very large signals, the ΣΔ modulator will be limited using compensation +4929, and the input signal will have a reduced dynamic range from the top. Figures 4A and 4B show quantified noise for an exemplary ΣΔ modulator design with no specific compensation applied to the input sample. In general, compensation can result in a statistic that allows the feedback within the ΣΔ modulator to attenuate the magnitude of the internal state more quickly, thus reducing the variation in the output signal. Different (four) △ modulation Μ: two different compensation can obtain different noise characteristics. For a given _ k benefit, various compensations can be used to make the frequency band σ 化 5 5f low. For Σ△调...... Hunting is chosen by choosing the appropriate compensation. This suitable compensation can be based on a computer simulation m-hole test, etc., to confirm that the laboratory test may need to be removed by the adder 22G, and the effective dynamic range of the system can be lowered. Thunder 铋 + ^ r .虓 No longer between the power rails. Therefore, the collision with one of the Fanyuan 诘丨^ table source before the collision is reduced. Secondly, the turn-off signal can be, for example, a direct current (DC) coupled to a speaker in the audio system, for example, from a power amplifier. Any DC compensation introduced and not removed in the digital domain will result in a DC offset from the nominal center voltage at the power amplifier output. If the DC offset is quite large, in addition to consuming more standby power, significant DC power can flow through the speaker coil and can damage the speaker. In one embodiment, the compensation added prior to the ΣΑ modulator is removed digitally by, for example, the compensation removal unit 140 of Figure 1 or the unit 240 of Figure 2 after the ΣΑ modulator. The compensation can be removed by subtracting • compensation from the output samples produced by the free chirp modulator. If the output sample is represented in a two's complement format and if the compensation in the output sample is about -1, the compensation can be removed by simply inverting each of the bits in the output sample. Table 1 shows the output of the 4-bit ΣΑ modulator in binary and decimal formats and the inverted output of the binary and decimal formats. Table 1

ΣΑ modulator output (binary) Σ △ modulator output (decimal) 反相 Δ Δ modulator output (binary) 反相 Δ Δ modulator output (decimal) 0111 +7 1000 -8 0110 +6 1001 -7 0101 +5 1010 -6 0100 +4 1011 -5 0011 +3 1100 -4 0010 +2 1101 -3 0001 +1 1110 -2 0000 0 1111 -1 1111 -1 0000 0 1110 - 2 0001 +1 117836.doc -15- 200807896 —---— __1101 11----- -3 _J100 '—| One ~ -4 —_J011 , ------ -5 _1010 '-6 ~1001 -7 _1000 - _-8

+7_ reaches 1, ΣΔ 调 调 之 & & 经 经 经 经 经 经 & & & & & & X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X As shown in equation (4), the resulting phase of each of the four bits in the output sample of the 4-bit 兀ΣΔ modulator has the following effect: (1) The output sample adds +1 compensation and (2) reverses the resulting sample. The corrected sample Xc〇R of the bit inversion j is inverted with respect to the data sample XDAT from the digital processor of FIG. 2 and the input sample Xm from the interpolation chopper 2 14 for the 曰5 hole application, # The phase inversion does not affect the output sound and does not require the correction signal to be inverted. Even if the signal needs to be inverted, there are different paths within the analog circuit that can be swapped to reverse the signal without additional circuitry. For applications where signal polarity is important, the data sample Xdat or the input sample (7) can be inverted to resolve the signal inversion caused by the bit inversion. In another embodiment, the compensation added prior to the ΣΔ modulator is removed after 斋α: after fasting, for example, by D A C 2 5 0 in Fig. 2 in the analog domain. Specific embodiments for removing compensation in the analog domain are described below.

FIG. 5 shows a schematic diagram of one embodiment of the DAC 250 of FIG. 2. For this embodiment, the DAC 250 is constructed as a 4-bit capacitive switched DAC. DAC 117836.doc -16- 200807896 2 5 0 includes 16 DAC elements 51〇a to 510p for 16 possible levels of four bits. Each DAC component 510 includes a capacitor 512 and switches 514 516 and 518. The electric valley § 512 has a horse connected to one end of the node a and a horse connected to the other end of one of the switches 514, 516 and 5 18 . The other end of the switch 514 is connected to the high reference voltage VREF_HI. The other end of the switch 516 is coupled to a low reference voltage VREF-L0. The other end of the switch 5 1 8 | Ma is connected to medium or input pong mode voltage VICM. 16 intrusions (: elements 510 & to 51 (^ receive from) ^) ^ 16 control signals of unit 242, a control signal for a DAC component. Each control signal is controlled in the associated DAC component 510 Switches 514 and 516. During clock phase contrast, the control signal of DAC component 510i / (where 仏 ..., ... turns switch 514 on to couple capacitor 512 to Vref_hi or switch 516 to couple capacitor 512 Connected to VREF-L0. Capacitor 512 is thus coupled to Vref_-Vref_L〇 depending on the logic value of the control signal. During the clock phase, there are 16 DAC components 51〇3 to 51〇1) 518 is turned on, and capacitor 512 of all components is coupled to VlCM. Clock phase 0 and 0 can respectively correspond to logic high level and logic low level of clock for DAC 250. If no compensation is added to input sample , the output sample will be uncompensated. In this case, the average of 8 DAC components will be coupled to Vref-hi, and the average ^ DAC components will be coupled to Vref if the target is 7 - REFJD. The net average input of the pass filter 260 can be expressed as: 8 ' Cunii · + 8 · Cunit · 乂赃-(1)=〇 The capacitance in each of equations (5) where Cunit is the capacitance of 117836.doc -17·200807896 5 1 2 in DAC components 5i〇a to 51〇p. However, if the compensation of -4929 is added to For a 16-bit input sample, the 4-bit output sample will have a compensation of about ―! In this case, an average of 7 DACtl pieces will be coupled to vREF_HI, and an average of 9 DAC elements will be coupled to Vref_L0. If ν^ΗΙ = -Vrefl〇, the net average input provided to the low pass filter 26〇 can be expressed as: Equation (6)

.C— . VreF_hi + 9. Cunit. I L〇 = -2 · Q

Referring to Figure 5, two DAC elements 520a and 520b can be used to compensate for the compensation shown in equation (6). Each DAC component 520 includes a capacitor 522 and switches 524 and 528 that operate in the same manner as the guillotine 512 and switches 514 and 518 in DAC component 510, respectively. The actuators 522 of DAC components 520a and 520b are directly coupled to vREF_HI and result in a net average input of approximately zero to the low pass filter 26A. If the -4929 16-bit compensation is added to the 16-bit input sample and the 4-bit is removed from the 4-bit output sample - the 4-bit compensation (which corresponds to the 16-bit complement of 4〇96)' assumes Σ△ Modulator 230 has a gain of 1.0, then the remaining 16 bits of -833 are compensated (which corresponds to the remaining 4 bit compensation of 0.20) remaining in the analog signal from the DAC. If the ΣΔ modulator 230 has a gain different from 1.1, the remaining compensation may be different. In any event, this residual compensation can be removed in the low pass filter 260 or can be left in the analog signal. Figure 5 also shows an embodiment of the low pass filter 26A of Figure 2. For this practical example 'low pass filter 260 is constructed from a capacitively switched two quad filter having two quad portions 530a and 530b. In each quad portion 117836.doc 200807896 530, capacitor 534 has a terminal that is lightly coupled to the output of the amplifier and to the other end of one of switches 536 and 538. The other end of switch 536 is coupled to the inverting input of amplifier 532. Switch 538 and 74 are coupled to the input of the quad portion. Capacitor 540 is coupled between the inverting input of amplifier 532 and the input of the quad portion. Switch 542 is coupled between the input of the quad portion and the circuit ground. The switch 550 has a terminal coupled to the output of the amplifier 532& and the other end of the capacitor 554. Switch = the other end is coupled to the circuit ground. The other end of the capacitor 554 is coupled to the input of the quad portion 530b. The capacitor 56A has one end coupled to the input of the quad portion 530b and the other end coupled to one of the switches 562 and 564 and coupled to the input of the inverting buffer 570. The inverting buffer 57 can be constructed by simply cross-coupling the wires of different signals in different circuit designs. The other end of the switch 562 is coupled to the circuit ground, and the other end of the switch 564 is coupled to the output of the quad portion 530b. Capacitor 572 is coupled between the input of quad block portion 530a and the output of inverting buffer 57A. The switches 53 8a, 53 6b, 542b, 5 50 and 5 62 are turned on during the clock phase y. Switches 536a, 53 8b, 542a, 552 and 564 are turned "on" during clock phase furnace 2. Figure 5 shows an exemplary design of DAC 250 and low pass filter 26A. In general, 5, DAC 250 and low pass filter 260 can be constructed in a variety of designs. For example, the low pass filter 260 can be constructed by passive filters and/or active filters and filters. The DEM single 7 242 selects different DAC components in the dac 250 in a predetermined or pseudo-random manner to mitigate the adverse effects of component mismatch in the DAC. 117836.doc -19- 200807896 For the DAC embodiment shown in Figure 5, component mismatch may be caused by the different capacitances of capacitor 512 in DAC components 510a through 510p. By choosing different DAC components, the error due to mismatch in the DAC component can be reformed and out of band, without a priori understanding of how the components are mismatched. FIG. 6 shows an embodiment of the DEM unit 242 of FIG. 2. For this embodiment, DEM unit 242 implements a data weighted average (DWA) mechanism. The corrected sample XC0R from the compensation removal unit 240 is zero-mean • represents a conversion to have a representation of the average value of 8. The converted sample XDEM has a range of 1 to 16. Each converted sample enables the number of DAC elements indicated by the value of the converted sample. The DAC component is selected in a round-robin fashion (starting with a DAC component adjacent to the last selected DAC component). For the example shown in Figure 6, DEM unit 242 receives the corrected sample sequence of -5, -3, +1, 0, -2, ... and produces a converted 3, 5, 9, 8, 6, ... Sample sequence. For the first converted sample 3, the DEM unit 242 selects the DAC elements 1 to 3; then for the second converted sample 5, the DEM unit 242 selects the DAC elements 4 to 8; then _ for the third converted sample 9, the DEM unit 242 DAC elements 9 to 16 and DAC element 1 are selected; then for fourth converted sample 8, DEM unit 242 selects DAC elements 2 to 9; then for fifth converted sample 6, DEM unit 242 selects DAC elements 10 to 15 and so on . FIG. 6 shows a particular embodiment of a DEM unit 242. The DEM unit 242 can also implement other dynamic component matching algorithms known in the art. Figure 7 shows an embodiment of a process 700 for performing oversampling and noise reforming. Perform up-sampling and interpolation filtering on the data samples to generate input samples 117836.doc -20- 200807896 (step 712). A compensation is added to the input samples to produce an intermediate sample (step 714). Upsampling and noise reforming are performed on the intermediate samples to produce a rounded sample (step 716). At least a portion of the compensation is removed from the output sample (step 718). The compensation can be removed in the digital domain (e.g., by inverting all of the bits of each output sample) or in the analog domain (e.g., by adding compensation to the DAC). Compensation removal in the digital domain is generally preferred because it typically does not add noise or loss or cause other adverse effects. The output samples are converted to analog samples using a plurality of DAC components (step 720). Different DAC elements are selected based on the output samples, for example, using a DWA mechanism or some other D]gM mechanism (step 722). The analog signal from the DAC is filtered to remove out of band noise (step 724). The filtered signal is amplified and/or buffered to produce an output signal (step 726). The compensation techniques and oversampling DAC 22 delta modulators described herein can be used in, for example, wireless communication devices (eg, cellular phones, terminals, etc.), consumer electronic devices (eg, stereo players, televisions, cd*s) Machines, etc.), various electronic devices and other devices of computers. The oversampling DAC can be built into one or more special application integrated circuits (ASICs), digital signal processors (Dsp), digital signal processing devices (DSPDs), programmable logic devices (pLDs), field programmable gate arrays. (FPGA) processor, control state, microcontroller, microprocessor, and/or other electronic unit. The oversampling DAC can be constructed on one or more 1s (on the die and/or on multiple 1Cs. For example, all circuit constructions can be performed on the digital 2〇2 in Figure 2) On an Ic die, and all the circuits shown in analog 1 (^ die 204 can be constructed on another _IC die. As another 117836.doc -21 - 200807896 circuit can construct various examples of BJT, etc. 'Oversampling DAC 100 or all or most of it on 1C die. Oversampling DACs can also be fabricated by techniques such as CMOS, NMOS, and redundancy. Some parts of the sample can be built into software and/or In the object, the compensation can be added by the software/blade body. The software/blade body can be used in the memory (for example, the picture in the picture 29 1 匕, the body 112 or the memory 212 in FIG. 2) )

Rough... (for example, processor 110 or 21〇) to execute. Memory can be built inside or outside the processor. The previous description of the disclosed embodiments is made to enable those skilled in the art to: make or use the invention. A person skilled in the art will be able to understand the various modifications of the invention, and the general principles defined herein may be applied to other embodiments without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is in accord with the broadest scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 shows an oversampling DAC implementing a compensated ΣΔ modulation. Figure 2 shows another oversampling DAC implementing a compensated ΣΔ modulation. Figure 3 shows a block diagram of a second-order 4-bit Σ A modulator. 4A and 4B show uncompensated and compensated quantization noise. Figure 5 shows a block diagram of the DAC and low pass filter. Figure 6 shows the operation of the DEM unit. Figure 7 shows the process for performing oversampling and noise reforming. [Main component symbol description] 117836.doc -22- 200807896

100 Oversampling DAC no Digital Processor 112 Memory 120 Adder 130 ΣΔ Modulator 140 Compensation Removal Unit 150 Μ Bit DAC 160 Low Pass Filter 170 Amplifier 200 Oversampling DAC 202 Digital 1C Grain 204 Analog IC Die 210 Digital Processor 212 Memory 214 Interpolation Filter 220 Adder 226 Port 0 Early 228 228 Zero Order Hold Unit 230 ΣΑ Modulator 240 Compensation Removal Unit 242 Dynamic Component Matching Unit 250 DAC 260 Low Pass Filter 270 Amplifier - 23- I17836.doc 200807896 ❿ 300 ΣΔ modulator 308 input gain element 310 adder 312 filter section 314 adder 316 delay element 318 gain element 320 adder 322 filter part 324 adder 326 delay element 328 gain element 330 Μ Bit Quantizer 410 Curve 412 Curve 420 Curve 422 Curve 510 a DAC Element 510b DAC Element 51 Op DAC Element 512 Capacitor 514 Switch 516 Switch 518 Switch 117836.doc _24· 200807896 520 a DAC Element 52〇b DAC Element 522 Capacitor 524 Switch 528 switch 530a quad portion 53 0 b quaternion portion 532a amplifier 532b amplifier 534a capacitor 534b capacitor 536a switch 536b switch 538a switch 5 38b switch 540a capacitor 540b capacitor 542a switch 542b switch 550 switch 552 switch 554 capacitor 560 capacitor 562 switch 117836.doc -25- 200807896 564 switch 570 Inverting Buffer 572 Capacitor 117836.doc -26-

Claims (1)

200807896 X. Patent application scope: 1 · A device comprising: an adder, an intermediate sample; and configured to add a compensation to the input sample to generate ', add a transformer, the group of bears Reconstruction and provide output samples,: intermediate sample execution 2 · such as: the impact of item 1, the further steps include: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , At least part of it. The apparatus of claim 1 further comprising: a remove:::: divide unit that is configured to divide at least a portion of the compensation from the output samples. 4. The device of the request, wherein each output sample 5. The device of claim 4, further comprising: a bit 疋 彳 移除 移除 移除 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Each of the retention ports is inverted to remove at least a portion of the compensation. 6. The apparatus of claim 1, further comprising: an interpolation filter, wave H' configured to perform up-sampling and interpolation filtering on the data samples and providing the input samples. The apparatus of claim 1, further comprising: a digital analog converter (DAC) comprising a plurality of DAC elements and, two sets of evils to convert the output samples into analog samples; and a dynamic component matching (DEM) A unit configured to select a different one of the plurality of DAC elements based on the output samples. 117836.doc 200807896 The apparatus of the monthly term 7, wherein the DAC is a capacitive switching DAC, and wherein the plurality of DAC components comprise a plurality of switchable capacitors. 9. The apparatus of claim 7, wherein the DEM unit is configured to select the plurality of DAC elements based on a data weighted average (DWA) mechanism. 10. The device of claim 7, further comprising: • a low pass filter configured to filter an analogy from the dac • filter I: item 1 of the device 'where the low pass chopping The device is a capacitor-switched guide: two devices: wherein the output samples are added to the compensation of the input samples. 13 ·If the Qing 求^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ And the accumulative incremental modulation piano is part of an oversampling DAC. Limen Wenyi 15·If the dream of the request item 1, the number, the input samples are used for an audio message 10· An integrated circuit comprising: a two-stage device and its "sample addition-compensation"-accumulation incremental modulator configured to perform noise reforming and provide round-robin samples.彳+Between Samples 聋 17. As requested in Item 、6, the integrated circuit, the further step includes: a compensation removal unit configured to shift from the rounds of samples 117836.doc 200807896 At least part of it. 18. The integrated circuit of claim 16, further comprising: - an interpolation filter, a wave H, configured to perform and interpolate the data samples and provide the input samples. 19. A method </ RTI> comprising: adding - compensation to an input sample to produce an intermediate sample; and performing a noise reforming on an intermediate sample such as 5 hai to generate an output sample. 20. The method of claim 19, further comprising: removing at least a portion of the compensation from the output samples. 21. The method of claim 19, further comprising: performing a 弁 sample on the data sample. Sampling and interpolating the enthalpy to generate the input 22. The method of claim 19, further comprising: the present == conversion 11 (DAC) component: the output sample:: the output sample is selected to select the complex number A different device of the DAC components, comprising: means for generating an intermediate sample by using = two additions - compensation; and inter-component samples performing noise reforming to produce an output sample. The device of 23, the step of the step comprises: for drawing the article from the wheel. 7 私 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The components. The apparatus of claim 23, further comprising: means for converting the output samples into analog samples using a plurality of digital analog converter elements; and for selecting the plurality of samples based on the samples of the rim media A component of a different DAC component in a DAC component. 117836.doc