JP2001332973A - Method and device for digital/analog conversion using common weight generating element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital/analog(D/A) converting method for generating an analog output signal, while using a common weight generating element which has the set of prescribed weights. SOLUTION: A combined weight generation control digital signal 180 is generated by receiving plural weight generation control digital signals (13-1, 13-2,..., 13-K) for controlling a common weight generating element circuit 2A, and combining these signals in digital manner. By controlling the common weight generating element circuit 2A in response to the signal 180, an analog output signal/corresponding to the combination of plural weight generation control digital signals is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to digital-to-analog conversion for converting a digital input signal into an analog output signal, and more particularly to a method and apparatus for implementing digital-to-analog conversion using a plurality of conversion methods. .

[0002]

2. Description of the Related Art Various digital-analog conversion techniques have been proposed. For example, such a method includes a so-called multi-bit method in which a binary-weighted M-bit digital signal input is converted into an analog input by using a conversion element having a binary-weighted weight. Since the digital signal processing speed has been improved due to the development of circuit technology, a 1-bit system using a delta-sigma modulator, which has spread rapidly, is included. These methods are based on differences in the method of connecting the conversion elements in the form of electric circuits, or differences in the types of conversion elements.
Although further subdivided, basically, the digital-analog conversion method is roughly classified into these two methods. The feature of the multi-bit method is that a high SN ratio is easily obtained because there is no special digital circuit. On the other hand, if the conversion element configured by the semiconductor integrated circuit does not provide sufficient relative accuracy of the conversion element, the linearity of the level becomes a problem in the multi-bit system, and there is a concern that the distortion may deteriorate. It is necessary to increase the precision by a trimming method, which leads to a disadvantage that the cost is likely to be high.

On the other hand, the 1-bit method oversamples a digital signal at a signal processing frequency higher than a signal band and moves quantization noise of the 1-bit signal out of a necessary band, thereby obtaining a high linearity. Sex can be obtained. However, since a digital signal is processed at such a high frequency, it has been difficult to obtain a high SN ratio when the present method is realized by a semiconductor integrated circuit.

To overcome the disadvantages of both systems, a digital-analog converter called a multi-bit and 1-bit composite type advanced 1-bit system has been proposed. This converter separates a 16-bit binary digital signal into two groups of upper bits and lower bits. A high-order bit uses a resistance ladder type multi-bit converter using a trimmed resistance conversion element, a low-order bit uses a 1-bit signal converter using a delta-sigma method, and a final analog output section. The method of synthesizing the analog output of the converter is adopted. In the digital-to-analog converter for PCM audio realized by the advanced 1-bit method, the SN ratio is 110 dB.
High performance has been obtained.

[0005]

However, a disadvantage of the advanced one-bit method is that the reference level of the analog output in each converter is slightly different due to an error generated in the manufacture of the integrated circuit. Therefore, when the analog outputs of the respective converters are combined, distortion occurs at the combining point due to the relative error of the reference level, and the overall analog output characteristics deteriorate.

[0006] In the digital-analog converter composed of a plurality of converters as described above, a relative error between the converters becomes a problem. Accordingly, an object of the present invention is to provide a digital-to-digital converter capable of reducing the above-mentioned relative error between the analog output of the advanced 1-bit multi-bit converter and the analog output of the 1-bit converter to obtain highly accurate analog output characteristics. It is to provide an analog converter.

Another object of the present invention is to provide a digital-to-analog converter that includes two or more separate digital-to-analog (D
/ A) To provide a method and an apparatus for realizing high-precision digital-analog conversion using a conversion type digital signal processing method.

Another object of the present invention is to provide a method and apparatus that can reduce the relative error between the outputs of each conversion method when using two or more different D / A conversion methods. is there.

[0009]

According to the present invention, there is provided a digital-to-analog conversion method for generating an analog output signal representing a received digital input signal comprising a plurality of bits according to the present invention. Forming a plurality of bit groups from the plurality of bits of the signal; and b) processing each of the plurality of bit groups using at least one predetermined digital-to-analog conversion digital signal processing method. Generating a plurality of weight generation control outputs for the plurality of bit groups by generating a weight generation control output; and c) digitally adding the plurality of weight generation control outputs to generate combined weight generation control. Generating an output; and d) responding to the composite weight generation control output with a plurality of weight generation elements corresponding to the weight generation element. Generating an analog output signal representative of said digital input signal by controlling said combination switch. According to the invention, the conversion method comprises:
By digitally processing the synthesized weight generation control output by encoding logic,
A digital processing step of performing dynamic element averaging for generating the control output may be included.

A digital-to-analog converter for generating an analog output signal from a received digital input signal comprising a plurality of bits according to the present invention comprises: a) a plurality of bit groups from the plurality of bits of the digital input signal. B) a plurality of bit group weight generation control means respectively receiving the plurality of bit groups, wherein each of the plurality of weight generation control means A plurality of weight generation control means for generating a plurality of weight generation control outputs by processing using a predetermined digital-analog conversion type digital signal processing method to generate weight generation control outputs; c) Adding means for digitally adding the plurality of weight generation control outputs to generate a combined weight generation control output,
D) weight generating means including a plurality of weight generating elements, and controlling the plurality of weight generating elements in response to the composite weight generating control output to generate an analog output signal representing the digital input signal; Consisting of

Further, according to the present invention, the conversion device includes:
Digital signal processing means for digitally performing signal processing on the composite weight generation control output may be included. In addition, the digital-analog converter according to the present invention separates a digital signal input sequence weighted by a digit by at least one or more arbitrary digits to obtain a K
A first digital signal processing unit (for example, a serial digital signal input weighted by a digit (column)) separated by at least one or more arbitrary digits to generate K digital signal input strings; Generate a serial digital signal input (eg, if K = 4, 100011110000111110000001
1000 1111 0000111 110000
001)) and a second digital signal processing unit including a plurality of means, wherein the plurality of means digitally processes the separated K digital signal input strings, The second digital signal converting the separated K digital signal input streams into a K type of second digital signal group representing the level of the associated separated K digital signal input streams. A processing unit; a third digital signal processing unit that converts the K kinds of second digital signal group into one kind of third digital signal group representing a level; and a third digital signal group representing the level Is converted into an analog signal by a digital-analog conversion element group composed of a plurality of N substantially equivalent weight generation elements.

According to the present invention, the digital-analog conversion element group composed of substantially equivalent weight generation elements is:
For the M-bit output of the third digital signal group, M
Or more than M conversion elements can be included. Further, according to the present invention, the third digital signal processing unit can have a function of performing an averaging process of the digital-analog conversion element on the time axis.

Further, according to the present invention, the second digital signal processing section for converting into the K kinds of second digital signal groups can have at least one kind of sigma-delta modulated digital signal processor.

[0014]

FIG. 1 shows the basic concept of a digital-analog converter (D / A converter), which will be described after FIG.

FIG. 2 shows a digital-analog converter (D / A converter) for receiving a digital signal composed of a plurality of bits.
100 is shown, which receives a digital signal 9 consisting of a plurality of bits. The illustrated converter comprises a digital circuit section 1 for performing digital processing, ie, “weight generation control”, and an analog circuit section 2 for performing analog processing, ie, “weight generation”. The digital circuit 1 receives a plurality of bit groups by dividing a plurality of bits of the received digital signal 9 into a plurality of bit groups (possibly having overlapping portions). A digital signal processing unit 12 including a plurality of bit group digital signal processors 12A and 12B. (Some implementations of the divider 10 for parallel input mode operation and serial input mode operation are shown in FIGS. 3, 4, and 5 and will be described in sequence).

A plurality of digital signal processors 12A, 12B
Uses the same or different digital-to-analog conversion type digital signal processing methods, thereby generating a plurality of digital signal processing outputs 13A, 13B.
The digital circuit section 1 also includes an adder section 14 for digitally adding the plurality of digital signal processing outputs 13A and 13B to generate a combined or combined digital signal processing output 140. The digital signal processing section 16 digitally performs signal processing on the composite digital signal processing output 140.

The “average processing circuit” 16 A included in the digital signal processing section 16 has a digital output 140
, A dynamic element matching (DEM) is performed. An output generated by the averaging circuit 16A on the conductor 160 is a weight generation element 20 included in the weight generation unit 2 for generating an analog output 22 corresponding to the digital input 9.
Supply to FIG. 6, which will be described later, shows the weight generation element 2
0, weight generator 2 and any additional control signals generated in the weight generator controller 1 for controlling the weight generator 2 are shown.

In the digital-to-analog converter 100 of FIG. 2, the upper (most significant) 6 bits 11A are processed in a segment conversion (SDAC) digital signal processor 12A to provide a total of 64 levels, and The remaining lower bits 11B are processed by the 5-level ΔΣ conversion type digital signal processor 12B.

The digital-to-analog converter 100 also includes this 5-level ΔΣ-converted digital signal processor 12B for the MSB of the 24-bit digital input word 9 and the lower 18 bits. In audio data, the term "MSB" indicates a plus or minus (+/-) sign, so this MSB bit is also required for a ΣΔ-converting digital signal processor.

FIGS. 7 and 8 show the output 13A of the thermometer decoder 12A and the 5-level ΔΣ signal modulator 12B.
The output value of the output signal 140 obtained by taking the sum of the output 13B of FIG.

The five-level ΔΣ modulator 12B outputs “100d
A-3V, 22mW multi-bit current mode DS DAC with B dynamic range (A-3V, 22mW Multibit Current
Mode DS DAC with 100dB Dynamic Range ", IEEE J. of
Solid State Circuits, Volume 31, Number 12, pp. 1
888-1894, 1996), which is hereby incorporated by reference herein. To match the "relative levels" of the SDAC digital signal processor and the ΔΣ digital signal processor, the Δ 信号 digital signal Set the processor's feedback gain to 2 (ie, run amplitude is 50%).

The analog circuit or weight generator 2 of FIG. 2 controls a plurality of built-in weight generators 20 in response to the composite digital signal processed as described above, thereby providing an analog representation of the digital input signal. Generate an output signal. The output 160 of the DEM circuit 16A provides on a plurality of conductors, which are coupled to the inputs of the weighting element switch of the weighting element if the weighting element switch is included in the weighting element 20. . Alternatively,
The conductor 160 is connected to the DEM circuit 16
If it is included in, it can be an input to the weight generation element. (FIG. 3, FIG. 4, FIG. 5, and FIG. 6, described below, illustrate the weighting element switches described).

In FIG. 2, as an example, a segment conversion type digital signal processing method including a segment digital-to-analog converter (SDAC) 12A and a ΔΣ conversion type digital signal processing method including a five-level ΔΣ digital-analog converter 12B are shown. 1 shows a configuration of a digital-analog converter 100 that combines the two conversion digital signal processing methods. The example shown in FIG. 2 includes a segment-converted digital signal processor 12A for the upper 6 bits 11A (including the MSB) of a 24-bit digital input word. The SDAC 11A is a “segment conversion type digital decoder”, which is a kind of “thermometer decoder”.

The segment conversion is a conversion method for preparing an analog output level by preparing a number of segments represented by an input subword and selecting the number of segments according to the value of the input subword. This segment conversion has a simple configuration, and averaging between segments can be performed relatively easily, so that a highly accurate output can be obtained. However, on the other hand, as the number of bits in the input subword increases, the number of segments increases exponentially, which makes it impractical for a certain number of "high" input bits.

On the other hand, in the ΔΣ conversion, the output signal can be reduced to a serial data stream having a width of 1 bit. However, this ΔΣ conversion has a disadvantage that the noise level in a high frequency region increases and is weak against jitter.

According to the present invention, by combining these two conversion methods, a configuration utilizing each of the advantages can be realized. That is, the upper bits 11A are converted by the segment conversion SDAC 12A that does not generate extra noise. The lower bits that cannot be processed by the segment conversion method are simultaneously converted by the 5-level ΔΣ digital-analog converter 12B.

For comparison with the present invention, for example, in a 20-bit digital-to-analog converter, the case of the prior art system in which the upper 5 bits are input to the segment converter and the lower bits are input to the Δ 器 converter think of. In this case, the number of segments of the segment converter may be 30. In addition, each segment is processed by an appropriate averaging process (for example, “data weighted av method”).
eraging method), so that a highly accurate output can be obtained from the segment system converter. (The 5-bit accuracy of the input is sufficiently obtained.) A ΔΣ converter also requires a plurality of segments. Also in this case, an output close to the ideal is obtained by using the averaging process, and since the upper 5 bits are processed by the segment conversion method, the accuracy of the ΔΣ converter may be 16 bits.
In this way, both converters can obtain an output with an accuracy close to the ideal. By combining these two outputs, an output close to the ideal can be obtained for a 20-bit input.

However, such a highly accurate output cannot be actually obtained. Segment converter 12A and Δ
Although it is possible for each of the Σ converters 12B to obtain an output close to the ideal, it is because a problem arises when combining them. The cause is that each converter 12A and 12A
This is because there is a difference in the reference level of B. In a conventional DAC that includes two different conversion DAC units, each DAC has a respective "reference level" for the DAC conversion element. Since these reference levels are generated in the respective conversion circuits, the characteristics of the reference levels are strongly affected by electrical properties of the circuit topology, such as stability against power supply voltage changes and temperature dependence. Here, the term "reference level" refers to a weight set when the input digital signal 9 is divided into the inputs of the respective converters 12A and 12B, and refers not to an absolute value but to a relative relationship. Therefore, since the upper bits of the digital input 9 are converted by the segment converter 12A and the lower bits by the ΔΣ converter 12B, the 1LSB of the segment converter 12A and the full scale value of the ΔΣ converter 12B (in the case of plus, Must be exactly equal to the analog output level of (full scale + 1 LSB).

However, in practice, manufacturing errors are extremely large with respect to the required accuracy. Therefore, in the present invention, the segment type DAC element includes an equivalent circuit element shared between different conversion methods.

An important point of the present invention is that the relative accuracy between the converted output processed by the multi-bit thermometer decoder SDAC 12A of FIG. 2 and the converted output generated by the multi-level ΔΣ modulator 12B is determined. It is to provide a way to improve. As described above, each converter has one or more analog conversion segments (or weight generation elements), as described above. The segments 20 in each of the converters 12A and 12B have the same weight and are averaged by an appropriate averaging process.

An important aspect of this architecture is that in the digital-to-analog conversion stage 20, two different conversion decoders, namely thermometer decoders 12A and 12A, are used.
The effect is to effectively "share" the same transform element, ie, the weighting element, for the level ΔΣ modulator 12B. This effective "sharing" of the same transform element is achieved by the method of producing a signal on conductor 140 when the outputs of thermometer decoder 12A and .DELTA..SIGMA. Modulator 12B are generated and summed by summer 14. You. This efficient sharing of the transform elements results in a reduction in errors caused by different reference levels or by the same or different transform methods.

Various techniques have been considered and implemented for averaging a plurality of segments having the same weight. For example, if the segments 20 used by the two converters 12A and 12B are configured with one weight, the averaging process can be easily performed, and as a result, the relative accuracy between the converters can be improved. It is. In the embodiment shown in FIG. 1, one common weight generating element 20
Is composed of 30 identical segments for the segment converter, so that the weight generating element for the ΔΣ converter can be composed of those segments. (Note that different weights can be used if they can be averaged.) A very well-known technique, dynamic element matching (DEM), is a DEM circuit 16A of the digital signal processing unit 16. Is the preferred technique to use in
eighted Averaging (DWA)) is also a very well known technique, but is also a particularly preferred technique.
The DWA technique is effective because the resulting error is suppressed by a first-order noise shaping method.

The implementation of the dividing unit 10 is simple. FIGS. 3, 4 and 5 show logic diagrams for various parallel and serial input mode implementations for the divider 10 of FIG.

Referring to FIG. 3, the digital-to-analog converter 101 corresponds to the digital-to-analog converter 100 of FIG.
Is an example of realizing the parallel input mode. Digital input 9
Is shown as a parallel 24-bit word,
Then, the data dividing circuit 10 outputs the upper 6 bits 11A,
It generates the MSB and the lower 18 bits 11B and has a parallel word. The SDAC 12A in FIG. 2 is shown as a thermometer decoder 12A in FIG. Thermometer decoder output 13A is shown as producing 63 discrete levels 0-62 encoded as binary signals carried by six conductors. The digital adder 14 has 67 discrete level 0
-66 (which is encoded as the first signal conducted by the seven conductors 140). The output signal generated by the dynamic element matching encoder 16A is generated on a suitable number of conductors 160 as an input to the weighting element switch 18, thereby selectively selecting the dynamic weighting element for the thermometer.
Connected to decoder 12A and ΔΣ modulator 12B, and current segment DAC 20A generally follows the dynamic element matching technique described above.

FIG. 4 shows a modification 102 of the digital-to-analog converter 101 of FIG. 3, ie, the input word is a 24-bit serial digital input word and the serial-to-parallel converter 10A This serial input word is converted into a 24-bit parallel word,
Then, this parallel word is applied to the input terminal of the parallel data divider 10. In another variation shown in FIG. 5, a serial digital input word is applied to the input of a serial data divider circuit 10C, and the
C divides the serial digital input word into six high order serial bits 111A and a low order serial word (consisting of the MSB indicated by reference numeral 111B and the low order 18 bits). These upper and lower serial words 111A and 111B are serial-
By applying to the inputs of the parallel converters 10D, 10E, a parallel upper word 11A and a parallel lower word 11B are generated and these are
The signals are applied to the inputs of the decoder 12A and the ΔΣ modulator 12B.

Next, referring to FIG.
Shown is a C topology 20A, in which the input of the weighting element switch 18 receives a signal generated by the dynamic element matching encoder circuit 16. Conductors 181, 182, 1
83, 184 represent the terminals of the particular weighting element selected by the current state of the dynamic element matching encoder 16. In FIG. 6, the output signal 160 generated by the dynamic element matching encoder 16A is output from the weighting element switch 18-1 of the weighting element switch circuit 18,
18-2,..., 18-M. Each weighting element switch has one terminal connected to the reference data conductor 44 and another terminal connected to the first terminal of the corresponding current segment current source 45 of the current segment circuit 19. Each of the preferably substantially equal current sources 45 has a second terminal, which is coupled to the output conductor 22 where the analog output is generated.

FIG. 9 shows an alternative arrangement in which the input word 9 is divided into K groups 11-1, 11-2,... 11-K by a data dividing circuit 10 in a 24-bit parallel manner. To K decoders 12-1, 12-
2,... 12-K digital inputs are shown. Decoders 12-1, 12-2 ... 12
The outputs of -K are summed by digital summing circuit 14 to generate signal 140, which is applied to dynamic element matching encoder 16A.

Referring now to FIG. 1, a more generalized implementation of the present invention is disclosed, in which the data conductor groups 11-1 and 1 generated by the data divider 10 are shown.
.., K in FIG. 9 or the SDA in FIG.
Apply to the inputs of a converter such as C12A and a five-level ΔΣ modulator 12B, which in FIG.
Call them "weight controllers" 1, 2,... K, which perform data processing functions. The encoded outputs of the weight controllers 1, 2,... K are “weight combination / encoding unit” 1
6, 18 corresponding inputs are applied, and these add and process the data. The output 180 of the weight combination and encoding units 16 and 18 is output from the weight generation unit 2A.
And the weight generator generates an analog output 22.

[0039]

As described above, according to the present invention,
A high-performance digital-to-analog converter can be realized without requiring high cost such as trimming.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital-analog converter according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a digital-analog converter according to a second embodiment of the present invention.

FIG. 3 is a block diagram of an implementation example of a parallel input mode of the digital-analog converter of FIG. 2;

FIG. 4 is a block diagram of an example of realizing a serial input mode of the digital-analog converter of FIG. 2;

FIG. 5 is a block diagram of an implementation example of a serial input mode of the digital-to-analog converter of FIG. 2;

FIG. 6 is a block diagram of a segment type DAC used in the implementation examples of FIGS. 2, 3, 4, and 5;

FIG. 7 is a graph showing the operation of the digital-analog converter of the present invention.

FIG. 8 is a graph showing the operation of the digital-to-analog converter of the present invention.

FIG. 9 is one implementation of the digital-to-analog converter of FIG. 2 having a parallel input mode topology, wherein a data divider groups parallel digital input words into K groups; K decoders have their K
FIG. 3 is a block diagram showing a configuration in which each group is decoded.

Claims (18)

[Claims] 1. A digital-to-analog conversion method for generating an analog output signal using a common weight generating element circuit having a predetermined weight set, the method comprising: a) controlling the common weight generating element circuit Receiving a plurality of weight generation control digital signals for generating a composite weight generation control digital signal by digitally combining the plurality of weight generation control digital signals; and c) generating the composite weight generation control digital signal. Generating an analog output signal corresponding to the combination of the plurality of weight generation control digital signals by controlling the common weight generation element circuit in response to the control digital signal. 2. The method according to claim 1, further comprising: generating each of the plurality of weight generation control digital signals from a plurality of digital signals represented by a weight set different from the predetermined weight set. A digital-analog conversion method. 3. The method of claim 2, further comprising: receiving a digital input signal comprising a plurality of bits; and forming a plurality of bit groups from the plurality of bits of the digital input signal. And using the plurality of bit groups as the plurality of digital signals. 4. The method of claim 2, wherein said step of generating said plurality of weight generation control digital signals comprises the step of generating said plurality of weight generation control digital signals from said plurality of digital signals. A digital-to-analog conversion type digital signal processing method. 5. The method of claim 1, wherein said digitally combining step comprises digitally adding said plurality of weight generation control digital signals. -Analog conversion method. 6. A digital-to-analog converter for generating an analog output signal using a common weight generating element circuit having a predetermined weight set, the method comprising: a) controlling the common weight generating element circuit; A combination circuit that receives a plurality of weight generation control digital signals to generate a composite weight generation control digital signal by digitally combining the plurality of weight generation control digital signals; And connected to receive the composite weight generation control digital signal from the combinational circuit, and by controlling the common weight generation element circuit in response to the composite weight generation control digital signal, A weight generation circuit for generating an analog output signal corresponding to a combination of the plurality of weight generation control digital signals. - analog converter. 7. The apparatus according to claim 6, further comprising: generating each of the plurality of weight generation control digital signals from a plurality of digital signals represented by a weight set different from the predetermined weight set. A digital-to-analog conversion device, comprising: a plurality of weight generation control circuits. 8. The apparatus according to claim 7, further comprising: forming a plurality of bit groups from a digital input signal consisting of a plurality of bits; and using the plurality of bit groups as the plurality of digital signals. Splitting means,
A digital-to-analog converter characterized by the above-mentioned. 9. The apparatus according to claim 7, wherein said plurality of weight generation control circuits are adapted to generate a plurality of different digital-analog conversions for generating said plurality of weight generation control digital signals from said plurality of digital signals. A digital-to-analog conversion device characterized by using a digital signal processing method. 10. The digital-to-analog converter according to claim 6, wherein the combination circuit performs digital addition as the digital combination. 11. A digital-to-analog conversion method for generating an analog output signal representing a received digital input signal comprising a plurality of bits, the method comprising the steps of: a) converting a plurality of bit groups from the plurality of bits of the digital input signal; And b) processing each of said plurality of bit groups using a predetermined digital-to-analog conversion digital signal processing method to generate a weight generation control output, thereby forming said plurality of bit groups. Generating a plurality of weight generation control outputs with respect to: c) digitally adding the plurality of weight generation control outputs to generate a composite weight generation control output; d) generating a composite weight generation control output Generating an analog output signal representative of said digital input signal by controlling a plurality of weight generating elements in response And a digital-analog conversion method. 12. The digital-to-analog conversion method according to claim 11, further comprising the step of digitally processing the composite weight generation control output. 13. A digital-to-analog converter for generating an analog output signal from a received digital input signal comprising a plurality of bits, the method comprising: a) forming a plurality of bit groups from the plurality of bits of the digital input signal. B) a plurality of bit group weight generation control circuits respectively receiving the plurality of bit groups, wherein each of the plurality of weight generation control circuits converts the associated bit group into a predetermined bit group. A plurality of weight generation control circuits for generating a plurality of weight generation control outputs by processing using a digital-analog conversion type digital signal processing method to generate weight generation control outputs; An addition circuit for digitally adding the weight generation control outputs of the above to generate a composite weight generation control output; and d) including a plurality of weight generation elements A weight generation circuit that generates an analog output signal representing the digital input signal by controlling the plurality of weight generation elements in response to the composite weight generation control output.
Analog converter. 14. The digital-to-analog converter according to claim 13, further comprising a digital signal processing circuit that digitally processes the composite weight generation control output. 15. A digital-to-analog converter for converting a digital signal into an analog signal, comprising: a) a digital signal input sequence weighted by digits;
Separated by at least one arbitrary digit,
B) a first digital signal processing unit for generating a plurality of digital signal input strings; and b) a second digital signal processing unit including a plurality of converters, wherein the plurality of converters includes the separated K number of converters. By digitally processing the digital signal input sequence,
The second digital signal converting the separated K digital signal input streams into a K type of second digital signal group representing the level of the associated separated K digital signal input streams. A processing unit; c) a third digital signal processing unit that converts the K kinds of second digital signal groups into one type of third digital signal group representing a level; and d) a third digital signal group representing the level. A digital-analog conversion element group composed of a plurality of N substantially equivalent weight generating elements with respect to the M-bit output of the digital signal group. 16. The converter according to claim 15, wherein said digital-to-analog conversion element group composed of substantially equivalent weight generating elements outputs M-bit output of said third digital signal group. A digital-to-analog converter comprising N or more than M conversion elements. 17. The converter according to claim 16, wherein said third digital signal processing section has a function of performing averaging processing of said digital-analog conversion element on a time axis. Digital to analog converter. 18. The converter according to claim 16, wherein K
A digital-to-analog converter, wherein the second digital signal processing unit for converting into a second kind of digital signal group includes at least one kind of sigma-delta modulation digital signal processor.