TW200801977A - Processor - Google Patents

Processor

Info

Publication number
TW200801977A
TW200801977A TW095143962A TW95143962A TW200801977A TW 200801977 A TW200801977 A TW 200801977A TW 095143962 A TW095143962 A TW 095143962A TW 95143962 A TW95143962 A TW 95143962A TW 200801977 A TW200801977 A TW 200801977A
Authority
TW
Taiwan
Prior art keywords
processor
circuit board
electrical contacts
memory
memory device
Prior art date
Application number
TW095143962A
Other languages
English (en)
Inventor
Henry T Verheyen
Raj Kumar Mathur
William Watt
Original Assignee
Liga Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Liga Systems Inc filed Critical Liga Systems Inc
Publication of TW200801977A publication Critical patent/TW200801977A/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7832Architectures of general purpose stored program computers comprising a single central processing unit without memory on one IC chip (single chip microprocessors)
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Sources (AREA)
TW095143962A 2005-12-23 2006-11-28 Processor TW200801977A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/318,042 US20070150702A1 (en) 2005-12-23 2005-12-23 Processor

Publications (1)

Publication Number Publication Date
TW200801977A true TW200801977A (en) 2008-01-01

Family

ID=38195290

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095143962A TW200801977A (en) 2005-12-23 2006-11-28 Processor

Country Status (3)

Country Link
US (1) US20070150702A1 (zh)
TW (1) TW200801977A (zh)
WO (1) WO2007078484A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489341B1 (en) 2018-06-25 2019-11-26 Quanta Computer Inc. Flexible interconnect port connection

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070239906A1 (en) * 2006-03-13 2007-10-11 Vakil Kersi H Input/output agent having multiple secondary ports
WO2009118731A2 (en) 2008-03-27 2009-10-01 Rocketick Technologies Ltd Design simulation using parallel processors
US9032377B2 (en) 2008-07-10 2015-05-12 Rocketick Technologies Ltd. Efficient parallel computation of dependency problems
WO2010004474A2 (en) * 2008-07-10 2010-01-14 Rocketic Technologies Ltd Efficient parallel computation of dependency problems
US8966292B2 (en) * 2011-01-03 2015-02-24 Qualcomm Incorporated Performance improvements in a wireless client terminal using assistance from a proxy device
US9128748B2 (en) * 2011-04-12 2015-09-08 Rocketick Technologies Ltd. Parallel simulation using multiple co-simulators
CN104048658B (zh) * 2013-03-15 2019-03-01 应美盛股份有限公司 一种使用基于姿态生成的设备来降低数据速率和功率消耗的方法
CN113217827B (zh) 2016-04-22 2023-08-08 纳米格有限公司 用于连接和控制可配置照明单元的系统和方法
CN107638178B (zh) * 2016-07-22 2021-03-12 西门子(深圳)磁共振有限公司 一种磁共振成像系统的控制系统和控制板
CN106371807B (zh) * 2016-08-30 2019-03-19 华为技术有限公司 一种扩展处理器指令集的方法及装置

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4736663A (en) * 1984-10-19 1988-04-12 California Institute Of Technology Electronic system for synthesizing and combining voices of musical instruments
US5093920A (en) * 1987-06-25 1992-03-03 At&T Bell Laboratories Programmable processing elements interconnected by a communication network including field operation unit for performing field operations
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
JP2746502B2 (ja) * 1992-08-20 1998-05-06 三菱電機株式会社 半導体集積回路装置の製造装置及び製造方法並びに電子回路装置
US5572710A (en) * 1992-09-11 1996-11-05 Kabushiki Kaisha Toshiba High speed logic simulation system using time division emulation suitable for large scale logic circuits
US5347428A (en) * 1992-12-03 1994-09-13 Irvine Sensors Corporation Module comprising IC memory stack dedicated to and structurally combined with an IC microprocessor chip
US5663900A (en) * 1993-09-10 1997-09-02 Vasona Systems, Inc. Electronic simulation and emulation system
DE69518403T2 (de) * 1994-01-10 2001-03-29 Dow Chemical Co Ein massiv multiplexierter, superskalarer prozessor mit harvard-architektur
US5737631A (en) * 1995-04-05 1998-04-07 Xilinx Inc Reprogrammable instruction set accelerator
US5956518A (en) * 1996-04-11 1999-09-21 Massachusetts Institute Of Technology Intermediate-grain reconfigurable processing device
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US6530014B2 (en) * 1997-09-08 2003-03-04 Agere Systems Inc. Near-orthogonal dual-MAC instruction set architecture with minimal encoding bits
US5915123A (en) * 1997-10-31 1999-06-22 Silicon Spice Method and apparatus for controlling configuration memory contexts of processing elements in a network of multiple context processing elements
DE69927075T2 (de) * 1998-02-04 2006-06-14 Texas Instruments Inc Rekonfigurierbarer Koprozessor mit mehreren Multiplizier-Akkumulier-Einheiten
US6097886A (en) * 1998-02-17 2000-08-01 Lucent Technologies Inc. Cluster-based hardware-software co-synthesis of heterogeneous distributed embedded systems
US6523055B1 (en) * 1999-01-20 2003-02-18 Lsi Logic Corporation Circuit and method for multiplying and accumulating the sum of two products in a single cycle
US6745317B1 (en) * 1999-07-30 2004-06-01 Broadcom Corporation Three level direct communication connections between neighboring multiple context processing elements
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation
US6678646B1 (en) * 1999-12-14 2004-01-13 Atmel Corporation Method for implementing a physical design for a dynamically reconfigurable logic circuit
US6668308B2 (en) * 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
US6576494B1 (en) * 2000-06-28 2003-06-10 Micron Technology, Inc. Recessed encapsulated microelectronic devices and methods for formation
US7953588B2 (en) * 2002-09-17 2011-05-31 International Business Machines Corporation Method and system for efficient emulation of multiprocessor address translation on a multiprocessor host
US7984268B2 (en) * 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US7103823B2 (en) * 2003-08-05 2006-09-05 Newisys, Inc. Communication between multi-processor clusters of multi-cluster computer systems
US7480611B2 (en) * 2004-05-13 2009-01-20 International Business Machines Corporation Method and apparatus to increase the usable memory capacity of a logic simulation hardware emulator/accelerator
US20060089829A1 (en) * 2004-10-21 2006-04-27 International Business Machines Corporation Method and apparatus to efficiently access modeled memory in a logic simulation hardware emulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10489341B1 (en) 2018-06-25 2019-11-26 Quanta Computer Inc. Flexible interconnect port connection
TWI706324B (zh) * 2018-06-25 2020-10-01 廣達電腦股份有限公司 具互連埠彈性連接方式之運算裝置

Also Published As

Publication number Publication date
WO2007078484A2 (en) 2007-07-12
US20070150702A1 (en) 2007-06-28
WO2007078484A3 (en) 2009-05-07

Similar Documents

Publication Publication Date Title
TW200801977A (en) Processor
AU2003240534A1 (en) Memory buffer arrangement
MXPA03006691A (es) Conector de energia en microplaqueta.
FR2792803B1 (fr) Dispositif a semiconducteur monte sur une carte
TW200613970A (en) On board performance monitor and power control system
SG140467A1 (en) Data processing method and its apparatus
EP1312091B8 (en) Memory device and method having data path with multiple prefetch i/o configurations
AU2003268967A1 (en) A memory circuit comprising a non-volatile ram and a ram
TW200620857A (en) Method and system for reducing power consumption of IrDA enabled handsets by turning ON/OFF an IrDA port dynamically
WO2007001505A3 (en) Die module system and method
WO2010080444A3 (en) Methods and systems for power consumption management of a pattern-recognition processor
WO2002039490A3 (en) A power distribution printed circuit board for a semiconductor processing system
TW200712841A (en) Processor configuration architecture of multi-processor system
WO2002063421A3 (en) System level applications of adaptive computing (slaac) technology
ES2169687A1 (es) Unidad electronica de control con elemento de activacion y elemento detratamiento de control.
WO2004040357A3 (en) Power management for spatial power combiners
AU2003222411A8 (en) Access to a wide memory
EP1422948A3 (de) Verteilereinrichtung einer Datensignal-Verarbeitungsanlage und Datensignal-Verarbeitungsanlage
WO2007050429A3 (en) Array interconnect for improved directivity
TW200610268A (en) Level shifter and method thereof
TW200745874A (en) Computer and main circuit board thereof
TW200731066A (en) Memory systems with memory chips down and up
TW200721418A (en) Semiconductor device, manufacturing method for semiconductor device, electronic component, circuit board, and electronlc device
TWI263318B (en) An electronic assembly having a more dense arrangement of contacts that allows for routing of traces to the contacts
PL1775769T3 (pl) Półprzewodnikowy moduł mocy