TW200745852A - Method and system for symmetric allocation for a shared L2 mapping cache - Google Patents

Method and system for symmetric allocation for a shared L2 mapping cache

Info

Publication number
TW200745852A
TW200745852A TW095147153A TW95147153A TW200745852A TW 200745852 A TW200745852 A TW 200745852A TW 095147153 A TW095147153 A TW 095147153A TW 95147153 A TW95147153 A TW 95147153A TW 200745852 A TW200745852 A TW 200745852A
Authority
TW
Taiwan
Prior art keywords
shared
mapping cache
tiled
symmetric allocation
cache
Prior art date
Application number
TW095147153A
Other languages
English (en)
Other versions
TWI405081B (zh
Inventor
Mark A Sabol
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of TW200745852A publication Critical patent/TW200745852A/zh
Application granted granted Critical
Publication of TWI405081B publication Critical patent/TWI405081B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0886—Variable-length word access
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
TW095147153A 2005-12-30 2006-12-15 對共享第二層對映快取記憶體對稱配置之方法與系統 TWI405081B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/322,922 US8593474B2 (en) 2005-12-30 2005-12-30 Method and system for symmetric allocation for a shared L2 mapping cache

Publications (2)

Publication Number Publication Date
TW200745852A true TW200745852A (en) 2007-12-16
TWI405081B TWI405081B (zh) 2013-08-11

Family

ID=37964978

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147153A TWI405081B (zh) 2005-12-30 2006-12-15 對共享第二層對映快取記憶體對稱配置之方法與系統

Country Status (6)

Country Link
US (1) US8593474B2 (zh)
EP (1) EP1966704A1 (zh)
JP (2) JP2009521766A (zh)
CN (1) CN101310259B (zh)
TW (1) TWI405081B (zh)
WO (1) WO2007078703A1 (zh)

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US9659343B2 (en) * 2011-12-29 2017-05-23 Intel Corporation Transpose of image data between a linear and a Y-tiled storage format
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US9558120B2 (en) 2014-03-27 2017-01-31 Intel Corporation Method, apparatus and system to cache sets of tags of an off-die cache memory
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CN104317361B (zh) * 2014-10-27 2017-08-04 杭州中天微系统有限公司 一种基于指针延迟更新的循环缓冲器
WO2016097810A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon mode
JP6209689B2 (ja) * 2014-12-14 2017-10-04 ヴィア アライアンス セミコンダクター カンパニー リミテッド モードに応じてウェイの全部又はサブセットに選択的に割り当てるように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ
WO2016097808A1 (en) 2014-12-14 2016-06-23 Via Alliance Semiconductor Co., Ltd. Dynamic cache replacement way selection based on address tag bits
US10176096B2 (en) * 2016-02-22 2019-01-08 Qualcomm Incorporated Providing scalable dynamic random access memory (DRAM) cache management using DRAM cache indicator caches
CN113282524B (zh) * 2021-05-08 2022-08-16 重庆大学 一种缓存分片的配置方法、装置以及存储介质
CN116561020B (zh) * 2023-05-15 2024-04-09 合芯科技(苏州)有限公司 一种混合缓存粒度下的请求处理方法、设备及存储介质
CN117130663A (zh) * 2023-09-19 2023-11-28 摩尔线程智能科技(北京)有限责任公司 一种指令读取方法及l2指令缓存、电子设备和存储介质

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Also Published As

Publication number Publication date
CN101310259A (zh) 2008-11-19
CN101310259B (zh) 2011-12-14
WO2007078703A1 (en) 2007-07-12
EP1966704A1 (en) 2008-09-10
JP2009521766A (ja) 2009-06-04
TWI405081B (zh) 2013-08-11
US8593474B2 (en) 2013-11-26
JP2012108930A (ja) 2012-06-07
US20070153014A1 (en) 2007-07-05

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Legal Events

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MM4A Annulment or lapse of patent due to non-payment of fees