TW200742058A - Semiconductor device including a strained superlattice and overlying stress layer and related methods - Google Patents

Semiconductor device including a strained superlattice and overlying stress layer and related methods

Info

Publication number
TW200742058A
TW200742058A TW095125959A TW95125959A TW200742058A TW 200742058 A TW200742058 A TW 200742058A TW 095125959 A TW095125959 A TW 095125959A TW 95125959 A TW95125959 A TW 95125959A TW 200742058 A TW200742058 A TW 200742058A
Authority
TW
Taiwan
Prior art keywords
strained superlattice
semiconductor device
stress layer
device including
related methods
Prior art date
Application number
TW095125959A
Other languages
English (en)
Inventor
Robert J Mears
Scott A Kreps
Original Assignee
Mears R J Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/457,286 external-priority patent/US7598515B2/en
Priority claimed from US11/457,293 external-priority patent/US20070020860A1/en
Application filed by Mears R J Llc filed Critical Mears R J Llc
Publication of TW200742058A publication Critical patent/TW200742058A/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151Compositional structures
    • H01L29/152Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7849Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being provided under the channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
TW095125959A 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice and overlying stress layer and related methods TW200742058A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US69994905P 2005-07-15 2005-07-15
US11/457,286 US7598515B2 (en) 2003-06-26 2006-07-13 Semiconductor device including a strained superlattice and overlying stress layer and related methods
US11/457,293 US20070020860A1 (en) 2003-06-26 2006-07-13 Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related Methods

Publications (1)

Publication Number Publication Date
TW200742058A true TW200742058A (en) 2007-11-01

Family

ID=37057155

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125959A TW200742058A (en) 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice and overlying stress layer and related methods

Country Status (6)

Country Link
EP (1) EP1905091A1 (zh)
JP (1) JP2009500871A (zh)
AU (1) AU2006270324A1 (zh)
CA (1) CA2612123A1 (zh)
TW (1) TW200742058A (zh)
WO (1) WO2007011628A1 (zh)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005057301A (ja) * 2000-12-08 2005-03-03 Renesas Technology Corp 半導体装置及びその製造方法
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
US6573172B1 (en) * 2002-09-16 2003-06-03 Advanced Micro Devices, Inc. Methods for improving carrier mobility of PMOS and NMOS devices
US6830964B1 (en) * 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
WO2005018005A1 (en) * 2003-06-26 2005-02-24 Rj Mears, Llc Semiconductor device including mosfet having band-engineered superlattice

Also Published As

Publication number Publication date
CA2612123A1 (en) 2007-01-25
JP2009500871A (ja) 2009-01-08
AU2006270324A1 (en) 2007-01-25
EP1905091A1 (en) 2008-04-02
WO2007011628A1 (en) 2007-01-25

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