TW200746263A - Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods - Google Patents

Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods

Info

Publication number
TW200746263A
TW200746263A TW095125961A TW95125961A TW200746263A TW 200746263 A TW200746263 A TW 200746263A TW 095125961 A TW095125961 A TW 095125961A TW 95125961 A TW95125961 A TW 95125961A TW 200746263 A TW200746263 A TW 200746263A
Authority
TW
Taiwan
Prior art keywords
pair
spaced apart
stress regions
semiconductor device
strained superlattice
Prior art date
Application number
TW095125961A
Other languages
Chinese (zh)
Inventor
Robert J Mears
Scott A Kreps
Original Assignee
Mears R J Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/457,269 external-priority patent/US7531828B2/en
Priority claimed from US11/457,276 external-priority patent/US20070015344A1/en
Application filed by Mears R J Llc filed Critical Mears R J Llc
Publication of TW200746263A publication Critical patent/TW200746263A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/151—Compositional structures
    • H01L29/152—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation
    • H01L29/154—Compositional structures with quantum effects only in vertical direction, i.e. layered structures with quantum effects solely resulting from vertical potential variation comprising at least one long range structurally disordered material, e.g. one-dimensional vertical amorphous superlattices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Abstract

A semiconductor device may include at least one pair of spaced apart stress regions, and a strained superlattice layer between the at least one pair of spaced apart stress regions and including a plurality of stacked groups of layers. Each group of layers of the strained superlattice layer may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
TW095125961A 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods TW200746263A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US69994905P 2005-07-15 2005-07-15
US11/457,269 US7531828B2 (en) 2003-06-26 2006-07-13 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions
US11/457,276 US20070015344A1 (en) 2003-06-26 2006-07-13 Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress Regions

Publications (1)

Publication Number Publication Date
TW200746263A true TW200746263A (en) 2007-12-16

Family

ID=37070665

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125961A TW200746263A (en) 2005-07-15 2006-07-14 Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regions and associated methods

Country Status (6)

Country Link
EP (1) EP1905092A1 (en)
JP (1) JP2009500873A (en)
AU (1) AU2006270125A1 (en)
CA (1) CA2612127A1 (en)
TW (1) TW200746263A (en)
WO (1) WO2007011789A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685514B2 (en) 2012-05-09 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having dopant layer and method of making the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8524562B2 (en) * 2008-09-16 2013-09-03 Imec Method for reducing Fermi-Level-Pinning in a non-silicon channel MOS device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
US6830964B1 (en) * 2003-06-26 2004-12-14 Rj Mears, Llc Method for making semiconductor device including band-engineered superlattice
US20040262683A1 (en) * 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6946350B2 (en) * 2003-12-31 2005-09-20 Intel Corporation Controlled faceting of source/drain regions

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9685514B2 (en) 2012-05-09 2017-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. III-V compound semiconductor device having dopant layer and method of making the same

Also Published As

Publication number Publication date
AU2006270125A1 (en) 2007-01-25
JP2009500873A (en) 2009-01-08
EP1905092A1 (en) 2008-04-02
CA2612127A1 (en) 2007-01-25
WO2007011789A1 (en) 2007-01-25

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